AMD Advanced Micro Devices AM79C976KCWV, AM79C976KIW Datasheet

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you ev aluate this produc t. AMD reserves the right to chang e or discontinu e work on this proposed product without notice.

Publication# 22929 Rev: C Amendment/0 Issue Date: August 2000

Refer to AMD’s Website (www.amd.com) for the latest information.



Am79C976

PCnet-PRO™ 10/100 Mbps PCI Ethernet Controller

DISTINCTIVE CHARACTERISTICS

■ Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus — 32-bit gluele ss PCI hos t interf ace — Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization

— PCI specification revision 2.2 compliant — Supports PCI Subsystem/Subvendor

ID/Vendor ID programming through the EEPROM interface

— Supports both PCI 3.3-V and 5.0-V signaling

environments

— Plug and Play compatible — Uses advanced PCI commands (MWI, MRL,

MRM)

— Optionally supports PCI bursts aligned to

cache line boundaries

— Supports big endian and little endian byte

alignments

— Implements optional PCI power management

event (PME

) pin

— Supports 40-bit addressing (using PCI Dual

Address Cycles)

■ Media Independent Interface (MII) for

connecting external 10/100 megabit per second (Mbps) transceivers

— IEEE 802.3-compliant MII — Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non auto-

negotiable external PHYs

— Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3compliant MII PHYs at full- or half-duplex

■ Full-duplex operation supported with

independent Transmit (TX) and Receive (RX) channels

■ Includes support for IEEE 802.1Q VLANs

— Automatically inserts, deletes, or modifies

VLAN tag

— Optionally filters untagged frames

■ Provides optional flow control features

— Recognizes and transmits IEEE 802.3x MAC

flow control frames

— Asserts collision-based back pressure in

half-duplex mode

■ Provides internal Management Information

Base (MIB) counters for network statistics

■ Supports PC97, PC98, PC99, and Net PC

requirements — Implements full OnNow features including

pattern matching and link status wake-up

— Implements Magic Packet™ mode — Magic Packet mode and the physical address

loaded from EEPROM at power up without requiring PCI clock

— Supports PCI Bus Power Management

Interface Specification Version 1.1

— Supports Advanced Configuration and

Power Interface (ACPI) Specification Version

1.0

— Supports Network Device Class Power

Management Specification Version 1.0

■ Large independent external TX and RX FIFOs

— Supports up to 4 megabytes (Mbytes)

external SSRAM for RX and TX frame storage

— Programmable FIFO watermarks for both

transmit and receive operations

— Receive frame queuing for high latency PCI

bus host operation

— Programmable allocation of buffer space

between transmit and receive queues

2 Am79C976 8/01/00

PRELIMINARY

■ Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards

■ Programmable internal/external loopback

capabilities

■ Supports patented External Address Detection

Interface (EADI) with receive frame tagging support for internetworking applications

■ EEPROM interface supports jumperless design

and provides through-chip programming — Supports full programmability of all internal

registers through EEPROM mapping

■ Programmable PHY reset output pin capab le of

resetting external PHY without needing buffering

■ Integrated oscillator circuit is controlled by

external crystal

■ Extensive programmable LED status support

■ Supports up to 16 Mbyte optional Boot PR OM or

Flash for diskless node application

■ Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame

■ Optional delayed interrupt feature reduces CPU

overhead

■ Programmable Inter Packet Gap (IPG) to

address less aggressive network MAC controllers

■ Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

■ Optionally sends and receives non-standard

frames of up to 64K octets in length

■ IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface for board-level production connectivity test

■ Provides built-in self test (MBIST) for the

external SSRAM

■ Software compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor architecture

■ Compatible with the existing PCnet Family

driver and diagnostic software (except for statistics)

■ Available in 208-pin PQFP package

■ +3.3-V power supply with 5-V tolerant I/Os

enables broad system compatibility

■ Support for operation in Industrial temperature

range (-40° C to +85

 C) available.

8/01/00 Am79C976 3

PRELIMINARY

GENERAL DESCRIPTION

The Am79C976 controll er is a highly-integrated 32- bit full-duplex, 10/100-Megabit per second (Mbp s) Ethernet controller solution, designed to address highperformance system application requirements. It is a flexible bus mastering device that ca n be used in any application, including network-ready PCs and bridge/ router designs. The bus master architecture provides high data throughput and low CPU and system bus utilization. The Am79C976 controller is fabricated with advanced low-power 3.3-V CMOS p rocess to provid e low operating current for power sensitive applications.

The Am79C976 controller also has several enhancements over its predecessor, the Am79C971 PCnet-FAST d evice. In addi tion t o providing acc ess t o a larger SSRAM, it fur ther reduces s ystem implementation cost by the addition of a new EEPROM programmable pin (PHY_RST) and the integration of the PAL function needed for Magic Packet application. The PHY_RST pin is i mplemented to reset the external PHY without increasing the load to the PCI bus and t o block RST

to the PHY when PG input is LOW.

The 32-bit multiplexed bus interface unit provides a d irect interface to the P CI local bus, simplif ying the design of an Ethernet node in a PC system. The Am79C976 contr oller provides the complet e interface to an Expansion ROM or Flash device allowing add-on card designs with onl y a single lo ad per PCI bus interface pin. With its built-in suppor t for both little and big endian byte alignment, this controller also addresses non-PC applications. The A m79C976 controller’s advanced CMOS design allows the bus interface to be connected to eithe r a +5-V o r a +3.3-V signalin g environment. An IEEE 1149.1-compliant JTAG test interface for board-level testing is also provided.

The Am79C976 controller is also compliant with the PC97, PC98, PC99, and Network PC (Net PC) specifications. It includes the full implementation of the Microsoft OnNow and ACPI specifications, which are backward compatible with the Magic Packet technology, and it is compliant with the PCI Bus Power Management Interface Specifica tio n by sup porting the four power management states ( D0, D1, D2, and D3), th e optional PME

pin, and the necessary configuration and

data registers. The Am79C976 control ler is ideal ly suited for Net PC,

motherboard, net work interface card (N IC), and embedded designs. It is available in a 208-pin Plastic Quad Flat Pack (PQFP) package.

The Am79C976 controller contains a bus interface unit, a DMA Buffer Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller (MAC), and an IEEE 802.3-compliant MII. An i nter face to an external RAM of up to 4 Mbytes is provided for frame storage. The MII supports IEEE 802.3-compliant full-duplex and half-duplex operations at 10 Mbps or 100 Mbps. The MII TX an d RX clock signals can be stopped independently for home networking applications.

The Am79C976 controller is register compatible with the LANCE™ (Am7990) and C-LANCE™ (Am79C 90) Ethernet controllers, and all Et hernet contro ll ers in the PCnet Family except ILACC™ (Am79C900), including the PCnet™-ISA controller (Am79C960), PCnet™-ISA+ (Am79C961), PCnet™-ISA II (Am79C961A), P Cnet™-32 (Am79C965) , PCnet™PCI (Am79C970), PCn et™-PCI II (Am79C970A), and the PCnet™-FAST (Am79C971).

The Buffer Management Unit supports the LANCE and PCnet descriptor software models.

The Am79C976 controll er suppor ts auto- configuration in the PCI configu ration space. Additional Am79C976 controller configuration parameters, including the unique IEEE physical address, can be read from an external nonvolatile memory (EEPROM) immediately following system reset.

In addition, the device provides programmable on-chip LED drivers f or tr ansmit, re ceiv e, coll ision, lin k integrity, Magic Packet status, activit y, addre ss match, fullduplex, or 100 Mbps status. The Am79C976 controller also provides an EADI to al low external hardware address filtering in interne tworking applications and a receive frame tagging feature.

With the rise of embedded networking applications operating in harsh environments where temperatures may exceed the normal commercial temperature (0

 C

to +70

 C) window, an industrial temperature (-40 C to

+85

 C) version is available. This industrial temperature

version of the PCnet-PRO Ethernet co ntroller is characterized across the industrial temperature range (-40



C to +85 C) within the published power supply specification (4.75V to 5.25V;

±5% Vcc). Thus, conformance

of the PCnet-PRO performance over this temperature range is guaranteed by a design and character i zatio n monitor.

4 Am79C976 8/01/00

PRELIMINARY

BLOCK DIAGRAM

CLK

RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT PERR SERR

INTA

PCI Bus

Interface

Unit

93CXX

EEPROM

Interface

Expansion Bus

Interface

MIB

Counters

JTAG

Port

Control

OnNow

Power

Management

Unit

802.3 MAC Core

MII

Port

EADI

Port

ERADV/FLOE ERADSP/ICEN ERCLK ERD[31:0]/FLD[7:0]/FLA[23.20] ERA[19:0]/FLA[19:0] ERCE EROE ERWE FLCS

PME

RWU

WUMI

PHY_RST

TXD[3:0] TX_EN TX_CLK COL RXD[3:0] RX_ER RX_CLK RX_DV CRS

SFBD EAR RXFRTGD RXFRTGE

EECS EESK

EEDI

EEDO

LED0 LED1 LED2 LED3

Network Port

Manager

MDC MDIO

Memory Control

Unit

and Status Unit

Descriptor

Management Unit

LED

Control

VAUX_SENSE

Clock

Generator

XTAL1 XTAL2 XCLK CLKSEL0 CLKSEL1 CLKSEL2

TCK

TMS

TDI

TDO

TEST

22929B1

8/01/00 Am79C976 5

PRELIMINARY

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LIST OF FIGURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CONNECTION DIAGRAM (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PIN DESIGNATIONS (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Network Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disconnect When Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Disconnect Of Burst T ransfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Parity Error Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Basic Non-Burst Read Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Basic Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Basic Non-Burst Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

DMA Burst Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Disconnect Without Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Preemption During Burst Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Parity Error Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Descriptor Management Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

TABLE OF CONTENTS

6 Am79C976 8/01/00

PRELIMINARY

Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Run and Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Descriptor Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Transmit Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Receive Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Look Ahead Packet Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Destination Address Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Medium Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Signal Quality Error (SQE) Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Transmit Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Transmit FIFO Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Receive Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Statistics Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Receive Statistics Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Transmit Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

VLAN Frame Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Admit Only VLAN Frames Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

VLAN Tags in Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Miscellaneous Loopback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Full-Duplex Link Status LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

MII Receive Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

MII Network Status Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

MII Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

MII Management Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Host CPU Access to External PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Auto-Poll State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Auto-Negotiation With Multiple PHY Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Operation Without MMI Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Regulating Network Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

MAC Control Pause Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Back Pressure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

8/01/00 Am79C976 7

PRELIMINARY

Enabling Traffic Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Hardware Control of Traffic Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Software Control of Traffic Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Programming the Pause Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

PAUSE Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Delayed Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

External Address Detection Interface: Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . .91

External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Expansion ROM - Boot Device Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Direct Flash Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Flash/EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

EEPROM Auto-Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Direct Access to the Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

EEPROM CRC Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Power Management Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

OnNow Wake-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

RWU Wake-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Link Change Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

OnNow Pattern Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Pattern Match RAM (PMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

TAP Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Other Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

EE_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

STOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Power on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

External PHY Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Address PROM Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Double Word I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

PCI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

PCI Revision ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

PCI Programming Interface Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

PCI Base-Class Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

8 Am79C976 8/01/00

PRELIMINARY

PCI Cache Line Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

PCI Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PCI I/O Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

PCI Memory Mapped I/O Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

PCI Subsystem ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

PCI Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

PCI Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

PCI MIN_GNT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

PCI MAX_LAT Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Power Management Capabilities Register (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

PCI Power Management Control/Status Register (PMCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . .120

PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

MIB Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

AP_VALUE0: Auto-Poll Value0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

AP_VALUE1: Auto-Poll Value1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

AP_VALUE2: Auto-Poll Value2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

AP_VALUE3: Auto-Poll Value3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

AP_VALUE4: Auto-Poll Value4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

AP_VALUE5: Auto-Poll Value5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

AUTOPOLL0: Auto-Poll0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

AUTOPOLL1: Auto-Poll1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

AUTOPOLL2: Auto-Poll2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

AUTOPOLL3: Auto-Poll3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

AUTOPOLL4: Auto-Poll4 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

AUTOPOLL5: Auto-Poll5 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

BADR: Receive Ring Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

BADX: Transmit Ring Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CHIPID: Chip ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CHPOLLTIME: Chain Poll Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CMD0: Command0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

CMD2: Command2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

CMD3: Command3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

CMD7: Command7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

CTRL0: Control0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

CTRL1: Control1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

CTRL2: Control2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

CTRL3: Control3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

DATAMBIST: Memory Built-in Self-Test Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

DELAYED_INT: Delayed Interrupts Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

EEPROM_ACC: EEPROM Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

FLASH_ADDR: Flash Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

FLASH_DATA: Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

FLOW: Flow Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

IFS1: Inter-Frame Spacing Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

INT0: Interrupt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

INTEN0: Interrupt0 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

IPG: Inter-Packet Gap Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

LADRF: Logical Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

LED0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

LED1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

8/01/00 Am79C976 9

PRELIMINARY

LED2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

LED3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

MAX_LAT_A: PCI Maximum Latency Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

MIN_GNT_A: PCI Minimum Grant Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

PADR: Physical Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Pause Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

PCIDATA0: PCI DATA Register Zero Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

PCIDATA1: PCI DATA Register One Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

PCIDATA2: PCI DATA Register Two Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

PCIDATA3: PCI DATA Register Three Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

PCIDATA4: PCI DATA Register Four Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

PCIDATA5: PCI DATA Register Five Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

PCIDATA6: PCI DATA Register Six Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

PCIDATA7: PCI DATA Register Seven Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

PHY Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

PMAT0: OnNow Pattern Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

PMAT1: OnNow Pattern Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

PMC_A: PCI Power Management Capabilities Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Receive Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

RCV_RING_LEN: Receive Ring Length Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

ROM_CFG: ROM Base Address Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

SID_A: PCI Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

SRAM Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

STAT0: Status0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Software Timer Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

SVID_A: PCI Subsystem Vendor ID Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

VID_A: PCI Vendor ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

XMT_RING_LEN: Transmit Ring Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

XMTPOLLTIME: Transmit Poll Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

CSR0: Am79C976 Controller Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

CSR1: Initialization Block Address 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

CSR2: Initialization Block Address 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

CSR3: Interrupt Masks and Deferral Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

CSR5: Extended Control and Interrupt 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

CSR6: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

CSR7: Extended Control and Interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

CSR12: Physical Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

CSR13: Physical Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

CSR14: Physical Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

CSR15: Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

CSR16-23: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

CSR26-29: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

CSR32-46: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

CSR48: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

10 Am79C976 8/01/00

PRELIMINARY

CSR49: Chain Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

CSR50-57: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

CSR58: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

CSR59-75: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR77: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR78: Transmit Ring Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR79: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . .191

CSR81-87: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR88: Chip ID Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR89: Chip ID Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR90-99: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR100: Bus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR101-111: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR113: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR114: Receive Collision Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR115: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

CSR117-121: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

CSR122: Advanced Feature Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

CSR123: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

CSR124: Test Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

CSR125: MAC Enhanced Configuration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

BCR1: Master Mode Write Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

BCR2: Miscellaneous Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

BCR4: LED0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

BCR5: LED1 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

BCR6: LED2 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

BCR7: LED3 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

BCR9: Full-Duplex Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

BCR16: I/O Base Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

BCR17: I/O Base Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

BCR20: Software Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

BCR22: PCI Latency Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

BCR23: PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

BCR24: PCI Subsystem ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

BCR25: SRAM Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

BCR26: SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

BCR27: SRAM Interface Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

BCR28: Expansion Bus Port Address Lower (Used for Flash/EPROM and SRAM Accesses). . 216

BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses) . . . . . . . . . . . . . . 216

BCR30: Expansion Bus Data Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

BCR31: Software Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

BCR32: MII Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

BCR33: MII Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

BCR34: MII Management Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . . . . . . . . . . . . . . .220

BCR37: PCI DAT A Register Zero (DATA0) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

BCR38: PCI DATA Register One (DATA1) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

BCR39: PCI DATA Register Two (DATA2) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

BCR40: PCI DATA Register Three (DATA3) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

8/01/00 Am79C976 11

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BCR41: PCI DATA Register Four (DATA4) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

BCR42: PCI DAT A Register Five (DATA5) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

BCR43: PCI DAT A Register Six (DATA6) Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

BCR44: PCI DATA Register Seven (DATA7) Alias Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

RDRA and TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

LADRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

PADR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

REGISTER BIT CROSS REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . 267

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

SWITCHING WAVEFORMS: SYSTEM BUS INTERFA CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

SWITCHING CHARACTERISTICS: EEPROM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

SWITCHING CHARACTERISTICS: JTAG TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . 278

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . .281

SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

SWITCHING WAVEFORMS: EXTERNAL MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

PQFP208. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Plastic Quad Flat Pack Trimmed and Formed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

APPENDIX A: LOOK-AHEAD PACKET PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

APPENDIX B: MII MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Technology Ability Field Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Auto-Negotiation Link Partner Ability Register (Register 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .INDEX-1

12 Am79C976 7/25/00

PRELIMINARY

LIST OF FIGURES

Figure 1: Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 2: Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 3: Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4: Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5: Disconnect Of Slave Cycle When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 6: Disconnect Of Slave Burst Transfer - No Host Wait States . . . . . . . . . . . . 38

Figure 7: Disconnect Of Slave Burst Transfer - Host Inserts Wait States . . . . . . . . . 39

Figure 8: Address Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 9: Slave Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10: Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 11: Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12: Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13: Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 14: Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 15: Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16: Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17: Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 18: Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19: Preemption During Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20: Master Abor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21: Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22: Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23: Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 24: Descriptor Ring Write In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 25: Descriptor Ring Write In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 26: FIFO Burst Write At Start Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . 58

Figure 27: FIFO Burst Write At End Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . 59

Figure 28: 16-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 29: 32-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 30: ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 31: IEEE 802.3 Frame and Length Field Transmission Order . . . . . . . . . . . . . 73

Figure 32: VLAN-Tagged Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 33: Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 34: Frame Format at the MII Interface Connection . . . . . . . . . . . . . . . . . . . . . 83

Figure 35: MII Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 36: External SSRAM and Flash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 37: Expansion ROM Bus Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 38: Flash Read from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 39: Flash Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 40: EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 41: EEPROM Entry Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 42: CRC Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 43: LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 44: OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 45: Pattern Match RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 46: PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . 117

Figure 47: Address Match Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 27

Figure 48: Normal and Tri-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

7/25/00 Am79C976 13

PRELIMINARY

Figure 49: CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 50: CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 51: Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 52: Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 53: Output Tri-State Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 54: EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 55: Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Figure 56: JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling . . . . . . . . . . . . . . 276

Figure 57: JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . 277

Figure 58: Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 59: Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 60: MDC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

Figure 61: Management Data Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . .280

Figure 62: Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . 280

Figure 63: Reject Timing - External PHY MII @ 25 MHz . . . . . . . . . . . . . . . . . . . . . 281

Figure 64: Reject Timing - External PHY MII @ 2.5 MHz . . . . . . . . . . . . . . . . . . . . . 282

Figure 65: Receive Frame Tag Timing with Media Independent Interface . . . . . . . .283

Figure 66: External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Figure A-1: LAPP Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

Figure A-2: LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

Figure A-3: LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . A-9

Figure A-4: LAPP 3 Buffer Grouping for Two-Interrupt Method . . . . . . . . . . . . . . . . A-10

14 Am79C976 7/25/00

PRELIMINARY

LIST OF TABLES

Table 1: System Clock Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2: Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 3: PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 4: Descriptor Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 5: Descriptor Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 6: Receive Address Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 7: Receive Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 8: Transmit Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 9: VLAN Tag Control Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 10: VLAN Tag Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 11: Auto-Negotiation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 12: MAC Control Pause Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 13: FC Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 14: FCCMD Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 15: SRAM_TYPE Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 16: LED Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 17: IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . 104

Table 18: BSR Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 19: Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 20: PCI Configuration Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 21: Address PROM Space Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 22: I/O Map In Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 23: Legal I/O Accesses in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . 109

Table 24: I/O Map In DWord I/O Mode (DWIO = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 25: Legal I/O Accesses in Double Word I/O Mode (DWIO =1) . . . . . . . . . . . . 109

Table 26: AP_VALUE0: Auto-Poll Value0 Register . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 27: AP_VALUE1: Auto-Poll Value1 Register . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 28: AP_VALUE2: Auto-Poll Value2 Register . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 29: AP_VALUE3: Auto-Poll Value3 Register . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 30: AP_VALUE4: Auto-Poll Value4 Register . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 31: AP_VALUE5: Auto-Poll Value5 Register . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 32: AUTOPOLL0: Auto-Poll0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 33: AUTOPOLL1: Auto-Poll1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 34: AUTOPOLL2: Auto-Poll2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 35: AUTOPOLL3: Auto-Poll3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 36: AUTOPOLL4: Auto-Poll4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 37: AUTOPOLL5: Auto-Poll5 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 38: Receive Ring Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 39: Transmit Ring Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 40: CHIPID: Chip ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 41: CHPOLLTIME: Chain Polling Interval Register . . . . . . . . . . . . . . . . . . . . 129

Table 42: CMD0: Command0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 43: CMD2: Command2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 44: CMD3: Command3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 45: CMD7: Command7 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 46: CTRL0: Control0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 47: CTRL1: Control1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 48: CTRL2: Control2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7/25/00 Am79C976 15

PRELIMINARY

Table 49: CTRL3: Control3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 50: Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 51: DATAMBIST: Memory Built-in Self-Test Access Register . . . . . . . . . . . . 145

Table 52: DELAYED_INT: Delayed Interrupts Register . . . . . . . . . . . . . . . . . . . . . . 147

Table 53: EEPROM_ACC: EEPROM Access Register . . . . . . . . . . . . . . . . . . . . . .148

Table 54: Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 55: FLASH_ADDR: Flash Address Register . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 56: FLASH_DATA: Flash Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 57: FLOW: Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 58: IFS1: Inter-Frame Spacing Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . 152

Table 59: INT0: Interrupt0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Table 60: INTEN0: Interrupt0 Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 61: IPG: Inter-Packet Gap Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 62: Logical Address Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 63: LED0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 64: MAX_LAT_A: PCI Maximum Latency Alias Register . . . . . . . . . . . . . . . . 160

Table 65: MIN_GNT_A: PCI Minimum Grant Alias Register . . . . . . . . . . . . . . . . . . 160

Table 66: PADR: Physical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 67: PAUSE_CNT: Pause Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 68: PCIDATA0: PCI DATA Register Zero Alias Register . . . . . . . . . . . . . . . . 161

Table 69: PHY_ACCESS: PHY Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 70: PMAT0: OnNow Pattern Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 71: PMAT1: OnNow Pattern Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 72: Receive Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Table 73: RCV_RING_LEN: Receive Ring Length Register . . . . . . . . . . . . . . . . . . 165

Table 74: ROM_CFG: ROM Base Address Configuration Register . . . . . . . . . . . . .166

Table 75: SID_A: PCI Subsystem ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 76: SRAM Boundary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 77: SRAM Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Table 78: STAT0: Status0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 79: Software Timer Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 80: SVID: PCI Subsystem Vendor ID Shadow Register . . . . . . . . . . . . . . . . . 170

Table 81: TEST0: Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 82: VID_A: PCI Vendor ID Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 83: XMT_RING_LEN: Transmit Ring Length Register . . . . . . . . . . . . . . . . . . 171

Table 84: XMTPOLLTIME: Transmit Polling Interval Register . . . . . . . . . . . . . . . . . 172

Table 85: Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 86: Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 87: Transmit Start Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 88: Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 89: BCR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 90: EEDET Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 91: Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 92: Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 93: SRAM_BND Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 94: FMDC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 95: APDW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 96: Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 97: Initialization Block (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

16 Am79C976 7/25/00

PRELIMINARY

Table 98: R/TLEN Decoding (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Table 99: R/TLEN Decoding (SSIZE32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Table 100: Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 101: Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 102: Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 103: Receive Descriptor (SWSTYLE = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 104: Receive Descriptor (SWSTYLE = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 105: Receive Descriptor, SWSTYLE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 106: Receive Descriptor, SWSTYLE = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 107: Receive Descriptor, SWSTYLE = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 108: Receive Descriptor, SWSTYLE = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 109: Receive Descriptor, SWSTYLE = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 110: Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 111: Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 112: Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 113: Transmit Descriptor (SWSTYLE = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 114: Transmit Descriptor (SWSTYLE = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 115: Transmit Descriptor, SWSTYLE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 116: Transmit Descriptor, SWSTYLE = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 117: Transmit Descriptor, SWSTYLE = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 118: Transmit Descriptor, SWSTYLE = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 119: Transmit Descriptor, SWSTYLE = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 120: Register Bit Cross Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Table 121: Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 122: Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table B-1: MII Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Table B-2: MII Management Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . B-1

Table B-3: MII Management Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . B-2

Table B-4: Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . B-3

Table B-5: Technology Ability Field Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Table B-6: Auto-Negotiation Link Partner Ability Re gister (Register 5)

- Base Page Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

8/01/00 Am79C976 17

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard produc ts are av ailable in sev eral pac kages and operating r anges. T he order number (Valid Combination) is f ormed by a combination of the elements below.

AM79C976

TEMPERATURE RANGE

C = Commercial (0 C to +70 C) I = Industrial (–40 C to 85 C

SPEED OPTION

PACKAGE TYPE

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Not applicable

K = Plastic Quad Flat Pack (PQR208)

Am79C976 PCnet-Pro 10/100 Mb ps PCI Ethernet Controller

Valid Combinations

AM79C976

KC\WV,

KI\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

18 Am79C976 8/01/00

PRELIMINARY

CONNECTION DIAGRAM (PQR208)

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

171

170

169

168

167

166

165

164

163

162

161

172

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129

127 126 125 124 123 122 121 120 119 118 117

128

6162636465666768697071727374757677787980818283848586878890919293949596979899100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

30 31 32 33 34 35 36 37 38 39 40

ERD3/FLD3

ERD17 VDD ERD18 ERD19

VSSB

TX_EN

TXD2

ERD0/FLD0 ERD1/FLD1

TXD1

TXD0

VSSB

CRS

VDD

ERD2/FLD2 VDD

ERD4/FLD4 ERD5/FLD5 ERD6/FLD6 VSS

ERD7/FLD7 VDD ERD8/FLA20

ERD10/FLA22 ERD11/FLA23 VSSB

VDD ERD13 ERD14 ERD15 ERD16 VSS

ERD12

ERD9/FLA21

VSSB

TXD3 COL

ERD20

VSSB

IRDY

VDD

TRDY STOP

VSSB

PERR

VSS

SERR

PAR VDD

C/BE1

AD15 AD14

AD30 AD29

VDD AD28 AD27 AD26

VSSB

AD25 AD24

C/BE3

VDD

IDSEL

AD23 AD22

VSSB

AD21

AD20

AD19

VDD AD18

AD17 AD16

VSSB

C/BE2

FRAME

DEVSEL

VSS

ERCE

VDD

EROE

VSSB

ERWE/FLWE

ERADV/FLOE

ERADSP/CEN

VSS

VSSB

ERA13/FLA13

ERA3/FLA3

ERA4/FLA4

VDD

ERA5/FLA5

ERA6/FLA6

ERA8/FLA8

ERA9/FLA9

VDD

VSS

VSSB

ERA11/FLA11

ERA12/FLA12

ERA14/FLA14

VDD

VSSB

ERA15/FLA15

VDD

ERA18/FLA18

ERA17/FLA17

VDD

FLCS

VSSB

ERA1/FLA1

ERA7/FLA7

ERA16/FLA16

ERD31

ERA0/FLA0

ERA10/FLA10

ERA2/FLA2

ERA19/FLA19

VDD

VSS

AVDD

VSSB

XTAL1

EAR

VDD

LED0/EEDI

LED2/RXFRTGE

XTAL2

LED3/EEDO/RXFRTGD

VSS

VSSB

CLKSEL0

TEST

VAUX_SENSE

PHY_RST

MDC

RXD3

VSSB

VDD

RXD0

EECS

PME

WUMI

RWU

TCK

TMS

TDO

VSSB

TDI

XCLK

CLKSEL1

MDIO

RXD2

RXD1

LED1/EESK

CLKSEL2

Am79C976

PCnet-PRO

INTA

RST

VDD

CLK

GNT

AD31

VSSB

REQ

41 42 43 44 45 46 47 48

VSSB

AD13 AD12 AD11

VDD AD10

AD9 AD8

53545556575859

AD5

VDD

AD4

AD3

VSSB

AD2

AD1

AD0

116 115 114 113 112 111 110 109

VDD ERD23 ERD24 ERD25

ERD22

ERD21 VSSB

ERCLK

49 50 51 52

VSSB

C/BE0

AD7 AD6

108 107 106 105

VSSB ERD26 VDD ERD27

101

102

103

104

ERD29

VSSB

ERD28

ERD30

160

159

158

157

RX_DV

RX_ER

TX_CLK

RX_CLK

208

207

206

205

204

203

202

201

22929B2

8/01/00 Am79C976 19

PRELIMINARY

PIN DESIGNATIONS (PQR208)

Listed By Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 AD30 53 AD5 105 ERD27 157 TX_CLK 2 AD29 54 VDD 106 VDD 158 RX_ER 3 VDD 55 AD4 107 ERD26 159 RX_CLK 4 AD28 56 AD3 108 VSSB 160 RX_DV 5 AD27 57 VSSB 109 ERCLK 161 RXD0 6 AD26 58 AD2 110 ERD25 162 VDD 7 VSSB 59 AD1 111 ERD24 163 RXD1 8 AD25 60 AD0 112 ERD23 164 VSSB 9 AD24 61 ERCE 113 VDD 165 RXD2 10 C/BE3 62 VDD 114 ERD22 166 RXD3 11 VDD 63 EROE 115 VSSB 167 MDC 12 IDSEL 64 VSSB 116 ERD21 168 MDIO 13 AD23 65 ERWE/FLWE 117 ERD20 169 PHY_RST 14 AD22 66 ERADV/FLOE 118 ERD19 170 VAUX_SENSE 15 VSSB 67 ERADSP/CEN 119 ERD18 171 TEST 16 AD21 68 VSS 120 VDD 172 CLKSEL0 17 VSS 69 FLCS 121 ERD17 173 CLKSEL1 18 AD20 70 VDD 122 VSSB 174 VSSB 19 AD19 71 ERA0/FLA0 123 VSS 175 CLKSEL2 20 VDD 72 VSSB 124 ERD16 176 VSS 21 AD18 73 ERA1/FLA1 125 ERD15 177 XTAL2 22 AD17 74 ERA2/FLA2 126 ERD14 178 XTAL1 23 AD16 75 ERA3/FLA3 127 ERD13 179 AVDD 24 VSSB 76 ERA4/FLA4 128 VDD 180 XCLK 25 C/BE2 77 VDD 129 ERD12 181 VDD

26 FRAME

78 ERA5/FLA5 130 VSSB 182

LED3

/EEDO/

RXFRTGD

27 IRDY

79 VSSB 131 ERD11/FLA23 183 LED2/RXFRTGE 28 VDD 80 ERA6/FLA6 132 ERD10/FLA22 184 LED1/EESK 29 TRDY 81 ERA7/FLA7 133 ERD9/FLA21 185 LED0/EEDI 30 DEVSEL 82 ERA8/FLA8 134 ERD8/FLA20 186 EECS 31 STOP 83 ERA9/FLA9 135 VDD 187 EAR 32 VSSB 84 VDD 136 ERD7/FLD7 188 VSSB 33 PERR 85 ERA10/FLA10 137 VSSB 189 VSS 34 VSS 86 VSS 138 VSS 190 FC

20 Am79C976 8/01/00

PRELIMINARY

35 SERR 87 VSSB 139 ERD6/FLD6 191 VDD 36 PAR 88 ERA11/FLA11 140 ERD5/FLD5 192 PME 37 VDD 89 ERA12/FLA12 141 ERD4/FLD4 193 WUMI 38 C/BE1 90 ERA13/FLA13 142 ERD3/FLD3 194 RWU 39 AD15 91 ERA14/FLA14 143 VDD 195 TCK 40 AD14 92 VDD 144 ERD2/FLD2 196 TMS 41 VSSB 93 ERA15/FLA15 145 VSSB 197 TDO 42 AD13 94 VSSB 146 ERD1/FLD1 198 TDI 43 AD12 95 ERA16/FLA16 147 ERD0/FLD0 199 VSSB 44 AD11 96 ERA17/FLA17 148 CRS 200 PG 45 VDD 97 ERA18/FLA18 149 COL 201 INTA 46 AD10 98 ERA19/FLA19 150 VDD 202 RST 47 AD9 99 VDD 151 TXD3 203 VDD 48 AD8 100 ERD31 152 TXD2 204 CLK 49 VSSB 101 VSSB 153 VSSB 205 GNT 50 C/BE0 102 ERD30 154 TXD1 206 REQ 51 AD7 103 ERD29 155 TXD0 207 VSSB 52 AD6 104 ERD28 156 TX_EN 208 AD31

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

8/01/00 Am79C976 21

PRELIMINARY

PIN DESIGNATIONS

Listed By Group

Pin Name Pin Function Signal Type1Pin Type1No. of Pins Clock Interface

XTAL1 Crystal I I 1 XTAL2 Crystal O O 1 XCLK External Clock I I 1 CLKSEL0 Clock Select I I 1 CLKSEL1 Clock Select I I 1 CLKSEL2 Clock Select I I 1 TEST Test Select I I 1

PCI Bus Interface

AD[31:0] Address/Data Bus IO IO 32 C/BE[3:0] Bus Command/Byte Enable IO IO 4 CLK Bus Clock I I 1 DEVSEL Device Select IO IO 1 FRAME Cycle Frame IO IO 1 GNT Bus Grant I I 1 IDSEL Initialization Device Select I I 1 INTA Interrupt O TSO 1 IRDY Initiator Ready IO IO 1 PAR Parity IO IO 1 PERR Parity Error IO IO 1 REQ Bus Requ es t O TSO 1 RST Reset I I 1 SERR System Error IO IO 1 STOP Stop IO IO 1 TRDY Target Ready IO IO 1

Board Interface

LED0 LED0 O TSO 1 LED1 LED1 O TSO 1 LED2 LED2 O IO 1 LED3 LED3 O IO 1 PHY_RST Reset to PHY O O 1 FC Flow Control I I 1

EEPROM Interface

22 Am79C976 8/01/00

PRELIMINARY

EECS Serial EEPROM Chip Select O O 1 EEDI Serial EEPROM Data In O TSO 1 EEDO Serial EEPROM Data Out I IO 1 EESK Serial EEPROM Clock IO TSO 1

External Memory Interface

ERCLK External Memory Clock O O 1 ERA[19:0]/FLA[19:0] External Memory Address[19:0] O O 20

ERD[31:0] / FLA[23:20] / FLD[7:0]

External Memory Data [31:0]/Flash Address[23:20]/Flash Data[7:0]

IO IO 32

ERADV

/FLOE Extern al Memory Advance O O 1 ERADSP/CEN External Memory Address Strobe O O 1 EROE External Memory Output Enable O O 1 ERWE/FLWE External Memor y Write En able O O 1 ERCE SSRAM Chip Enable O O 1 FLCS Flash Memory Chip Select O O 1

Media Independent Interface (MII)

COL Collision I I 1 CRS Carrier Sense I I 1 FC Hardware Flow Control I I 1 MDC Management Data Clock O O 1 MDIO Management Data I/O IO IO 1 RX_CLK Receive Clock I I 1 RXD[3:0] Receive Data I I 4 RX_DV Receive Data Valid I I 1 RX_ER Receive Error I I 1 TX_CLK Transmit Clock I I 1 TXD[3:0] Transmit Data O O 4 TX_EN Transmit Data Enable O O 1

External Address Detection Interface (EADI)

EAR External Address Reject I I 1 SFBD Start Frame Byte Delimiter Note 2 Note 2 1 RXFRTGD Receive Frame Tag Data I IO 1 RXFRTGE Receive Frame Tag Enable I IO 1

Power Management Interface

RWU Remote Wake Up O TSO 1 PME Power Management Event O OD 1 WUMI Wake-Up Mode Indicator O OD 1 PG Power Good I I 1

Pin Name Pin Function Signal Type

Pin Type1No. of Pins

8/01/00 Am79C976 23

PRELIMINARY

Notes:

1. Since some pins provide more than one signal, the pin type for a signal may differ from the signal type.

2. The SFBD signal can be programmed to appear on any of the LED pins.

Table Legend:

VAUX_SENSE Vaux Sense I I 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I I 1 TDI Test Data In I I 1 TDO Test Data Out O O 1 TMS Test Mode Select I I 1

Power Supplies

VDD Digital and I/O Buffer Power P P 24 VSS Digital Ground P P 8 A VDD Analog VDD for PLL and OSC P P 1 VSSB I/O Buffer Ground P P 25

Pin Name Pin Function Signal Type1Pin Type1No. of Pins

Name Pin Type

IO Input/Output

I Input

O Output

TSO Three-State Output

OD Open Drain

24 Am79C976 8/01/00

PRELIMINARY

PIN DESCRIPTIONS

PCI Interface

AD[31:0]

Address and Data Input/Output

Address and data ar e multi pl exed on the same bus interface pins. During the firs t clock of a transaction, AD[31:0] contain a physical address (32 bits). During the subsequent clocks, AD[31:0] contain data. Byte ordering is L ittle Endian by de fault. AD[7:0] are de fined as the least significant byte (LSB) and AD[31:24] are defined as the most significant byte (MSB). For FIFO data transfers, the Am79C976 controller can be programmed for Big Endian byte ordering. See Control 0 Register, bit 24 (BSWP) for more details.

During the address phase of the transaction, when the Am79C976 controller is a bus master, AD[31:2] will address the active Double Word (DWord). The Am79C976 controller always drives AD[1:0] to “00” during the address phase indicating linear burst order. When the Am79C976 controller is not a bus master, the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transf ers.

During the data phase of the transaction, AD[31:0] are driven by the Am79C976 controller wh en performing bus master write and slave read operations. Data on AD[31:0] is latched by the Am79C976 co ntroller when performing bus master read and slave write operations.

The Am79C976 device suppor ts Dual A ddress Cy cles (DAC) for systems with 64-bit addressing. As a bus master the Am79C976 d evice wil l gene rate add re ss es of up to 40 bits in length. If the value of the C/BE

[3:0] bus during the PCI addres s phase is 1101b, the address phase is extended to two clock cycles. T he low order address bits appear on the AD[31:0] bus during the first clock cycle, and the high order bits appear during the second clock cycle. In dual address cycles the PCI bus command (memory read, I/O write, etc.) appears on the C/BE

pins during the second clock cycle.

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the same bus interface pins. During the a ddress phase o f the transaction, C /BE

[3:0] define the bus command.

During the data phase, C/BE

[3:0] are us ed as byte enables. The byte enables define which physical byte lanes carry meaningful data. C/BE

0 applies to byte 0

(AD[7:0]) and C/BE

3 applies to byte 3 (AD[31:24]). The function of the byte enables is indepe nden t of the byte ordering mode (BSWP, CSR3, bit 2).

CLK

Clock Input

This cloc k is us e d to d rive the system b u s i n te rface. All bus signals are sampled on the rising edge of CLK and all parameters are defined with respect to this edge. The Am79C976 controller normally operates over a frequency range of 15 MHz to 33 MHz on the PCI bus due to networking demands. The Am79C976 controller will support a c lock frequency of 0 MHz after cer tain pr ecautions are taken to ens ure data integr ity. This clock or a derivation is not used to drive any network functions.

DEVSEL

Device Select Input/Output

The Am79C976 controller dr ives DEVSEL when it detects a transaction that selects the device as a tar get. The device samples DEVSEL

to detect if a target claims a transaction that the Am79C976 controller has initiated.

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79 C976 controll er when it is the bus master to indicate the beginning and duration of a transaction. FRAME

is asser ted to indica te a bus

transaction is be ginning. FRAME

is asserted while

data transfers continue. FRAME

is deasserted before the final data phase o f a transaction. When the Am79C976 controller is in slave mode, it samples FRAME

to determ ine the ad dress phas e of a tran sac-

tion.

GNT

Bus Grant Input

This signal indicates that the access to the bus has been granted to the Am79C976 controller.

The Am79C976 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNT without an active REQ from the Am79C976 controller, the device will drive the AD[31:0], C/BE

[3:0], and PA R

lines.

IDSEL

Initialization Device Select Input

This signal is used as a chi p sele ct for the Am7 9C97 6 controller duri ng configurat ion read a nd write transactions.

INTA

Interrupt Request Output

An attention signal which indicates that one or more enabled interrupt flag bits are set. See the descriptions of the INT and INTEN registers for details.

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PRELIMINARY

By default INTA

is an open-drain output. For applications that need an a ctive-high edge-sens itive interrup t signal, the INTA

pin can be configured for this mode by

setting INTLEVEL (CMD3, bit 13 or BCR2, bit 7) to 1.

IRDY

Initiator Ready Input/Output

IRDY indicates the ability of the initiato r of the transac tion to complete the current data phase. IRDY

is used

in conjunc ti o n w i th TRDY

. Wait states are inserted until

both IRDY

and TRDY are asser ted simultaneously. A data phase is completed on any clock when both IRDY and TRDY are asserted.

When the Am79C976 c ontroll er is a bus mas ter, it asserts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. Dur ing all read dat a phases, the device asserts IRDY

to indicate that it is

ready to accept the data. When the Am79C976 controller is the target of a trans-

action, it checks IRDY

during all wr ite data phas es to determine if valid data is presen t on AD[31:0]. During all read data phases, the device checks IRDY

to deter-

mine if the initiator is ready to accept the data.

PAR

Parity Input/Output

Parity is even parity across AD[31:0 ] and C/BE[3:0]. When the Am79C976 controller is a bus master, it generates parity during the address and write data phases. It checks parity during read data phases. When the Am79C976 controller operates in slave mode, it checks parity during every address phase. When it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases.

PERR

Parity Error Input/Output

During any slave write transaction and any master read transaction, the Am79C976 contro ller asserts PE RR when it detects a dat a pa rity error and repo rting of th e error is enabled by setting PERREN (PCI Command register, bit 6) to 1. During any master write transaction, the Am79C976 controlle r monit ors PERR

to see if the

target reports a data parity error.

REQ

Bus Request Input/Output

The Am79C976 controller asserts REQ pin as a signal that it wishes to become a bus mas ter. REQ

is driven high when the Am79C976 control ler does not request the bus.

RST

Reset Input

When RST is asser ted LOW and the PG pin is HIGH, then the Am79C976 controller performs an internal system reset of the type H_RESET (HARDWARE_RESET, see section on RESET). Immediately after the initial power up, RST

must be held low

for 26µs. At any other time RST

must be held low for a minimum of 30 clock periods to gu arant ee t hat the device is properly reset. While in the H_RESET state, the Am79C976 controller will disable or deassert all outputs. RST

may be asynchronous to clock when as-

serted or deasserted. Asserting RS T disables all of the PCI pins except the

PME

pin.

SERR

System Error Output

During any slave transaction, the Am79C976 controller assert s S ER R

when it detects an address par i ty error, and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1.

By default SERR

is an open-drain out put. For component test, it can be programmed to be an active-high totem-pole output.

STOP

Stop Input/Output

In slave mode, the Am79C976 controller drives the STOP

signal to inform the bus mas ter to stop the current transaction. In bus master mode, the Am 79C976 controller checks STOP

to determine if the target wants

to disconnect the current transaction.

TRDY

Target Ready Input/Output

TRDY indicates the ability of the target of the tran saction to complete the current data phase. Wait states are inserted until both IRD Y

and TRDY are asserted simultaneously. A data phase is comple ted on any clock when both IRDY

and TRDY are asserted.

When the Am79C976 controller is a bus master, it checks TRD Y during all read data phases to determine if vali d data is present on AD[31: 0]. During all write data phases, the device checks TRDY

to determine if the

target is ready to accept the data. When the Am79C976 controller is the target of a trans-

action, it asser ts TRDY

during all read data pha ses to indicate that valid data is present on AD[31 :0]. Durin g all write data phases, the device asserts TR DY

to indi-

cate that it is ready to accept the data.

26 Am79C976 8/01/00

PRELIMINARY

PME

Power Management Event Output, Open Drain

PME is an output that can be used to indicate that a power management event (a Magic Pack et, an OnNow pattern match, or a ch ange in link state) has been detected. The PME

pin is asserted when either:

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1. The PME

signal is asynchronous with respect to the

PCI clock.

Board Interface

Note: Before programmin g the LE D pins, see th e description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By default, LED0

indicates an active link connection. This pin can also be programmed to indicate other network status (see BCR4). The LED0

pin polarity is programma-

ble, but by default it is active LOW. When the LED0

pin polarity is programmed to active LOW, the output is an open drain dri ver. When the LED0

pin polarity is programmed to active HIGH, the output is a totem pole driver.

Note: The LED0

pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By default, LED1

indicates receive or transmit activity on the network. This pin can also be programm ed to indic ate other network status (see BCR5). The LED1

pin polarity is programmable, but by default, it is active LOW. When the LED1

pin polarity is programmed to active LOW, the output is an o pen drain driver. When the LED1

pin polar ity is programm ed to acti ve HIGH, the

output is a totem pole driver.

Note: The LED1 pin is multiplexed with the EESK pin.

LED2

LED2 Output

This output is designed to directly drive an LED. By default, LED2

indicates that the network bit rate is 100 Mb/s. This pin can also be programmed to indicate various network status (see BCR6). The LED2

pin polarity is programmable, but by default it is active LOW. When the LED2

pin polarity is programmed to active LOW , the

output is an open d rain driver. When the LED2

pin polarity is pr ogrammed to active HIGH, th e output is a totem pole driver.

Note: The LED2

pin is multiplexed with the RXFRTGE

pin.

LED3

LED3 Output

This output is designed to directly drive an LED. By default, LED3

indicates that a collision has occurred. This pin can also be programmed to indicate o ther ne twork status (see BCR7). The LED3

pin polarity i s programmable, but by default it is active LOW. When the LED 3 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED3

pin polarity is programmed to active HIGH, the output is a totem pole driver.

Special attention must be given to the external circuitry attached to this pin. When thi s pin is used to drive an LED while an EEPROM is used in the system, then buffering may be required between the LED3

pin and the LED circuit. If an LED circuit were directly attached to this pin, it may create an I

OL requirement that could

not be met by the serial EEPROM attached to this pin. If no EEPROM is included i n the system design or l ow current LEDs are used, then the LE D3

signal may be directly connecte d to an LED without buffering. In any case, if an EEPROM is present, there must be a pull-up resistor connected to this pin (10 k

W should be ade-

quate). For more details regarding LED connection, see the section on LED Support.

Note: The LED3

pin is multiplexed with the EEDO and

RXFRTGD pins.

Power Good Input

The PG pin has two functions: (1) it puts the device into Magic Packet mode, and (2) it blocks any resets when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is set to 1, the device enters the Magic Packet mode.

When PG is LOW, a LO W assertion of the PCI RST

will only cause the PCI interface pins (except for PME

) to be put in the high impedance state. The internal logic will ignore the assertion of RST

When PG is HIGH, assertion of the PCI RST

pin causes the controller logic to be reset and the configuration information to be loaded from the EEPROM.

RWU

Remote Wake Up Output

RWU is an output that is asserted either when the controller is in the Magic Packet mode and a Magic Packet frame has been detected, or the controller is in the Link Change Detect mode and a Link Change has been detected.

8/01/00 Am79C976 27

PRELIMINARY

This pin can dr ive the external system mana gement logic that causes the CP U to get out of a low power mode of operation. This pin is implemented for designs that do not support the PME

function.

Three bits that are loaded from the EEPROM into CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the RWU signal.

2. If RWU_GATE bit is set, RWU is forced to the hig h impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is open drain or totem pole.

The internal power-on-reset signal forces this output into the high impedance state until after the polarity and drive type have been determined.

WUMI

Wake-Up Mode Indicator Output, Open Drain

This output, which is cap able of drivi ng an LED, is asserted when the device is in Magic Packet mode. It can be used to drive external logic that switches the device power source from the main power supp ly to an auxi liary power suppl y.

VAUX_SENSE

3.3 Vaux Presence Sense Input

The signal on this pin is logically anded with bit 15 of the PCI PMC register when the PMC regist er is read. This pin should norm ally be connected to the PCI

3.3 Vaux pin. This allows the PMC register to indicat e

that the device is capable of suppor ting PME

from the

cold

state only when the 3.3 Vaux pin is supplying

power.

CLKSEL0

Clock Select 0 Input

The Am79C976 system clock can either be driven by an external clock generator connected to the XCLK pin or by an internal clock generator timed by a 25-MHz crystal connected between the XT AL1 and XTAL2 pins. The CLKSEL0 and CLKSEL1 pins select the source of the system clock and the frequency at which the external clock generator must run. In addition, CLKSEL0 and CLKSEL1 determine the frequency of ERCLK, the external SSRAM clock. Table 1 shows the possible combinations.

CLKSEL1

Clock Select 1 Input

the system clock and the frequency at which the external clock generator must run. In addition CLKSEL0 and CLKSEL1 determin e the frequenc y of ERCLK, the external SSRAM clock. Table 1 shows the possible combinations.

CLKSEL2

Clock Select 2 Input

The CLKSEL2 pin must be hel d low dur i ng no rmal operation.

TEST

Test Reset Input

The TEST pin must b e held low dur ing nor mal operation.

XCLK

External Clock Input Input

The Am79C976 system clock can either be driven by an external clock generator connect ed to this pin or by a 25-MHz crystal connected between the XTAL1 and XTAL2 pins, depending on the state of the CLKSEL0 and CLKSEL1 pins. When either CLKSEL0 or CLKSEL1 or both are held high, a 20-, 25-, or

-MHz clock signal must be applied to XCLK as

shown in Table 1. When CLKSEL0 and C LKSEL1 ar e both held low, the XCLK pin should be connected to either VSS or VDD.

Table 1. System Clock Selections

XTAL1

Crystal Input

If the CLKSEL0 and CLKSEL 1 pins are both he ld low, a 25-MHz crystal should be connected between the XTAL1 pin and the XTAL2 pin. This crystal controls the frequency of the internal clock-generator circuit.

If the CLKSEL0 and CLKSEL1 pins ar e not both held low, a 20-, 25-, or

-MHz clock source must be con-

CLKSEL2 CLKSEL1 CLKSEL0

CLOCK

SOURCE

ERCLK

(MHz)

1XX

Design Factory

Test Only.

000

25-MHz

Crystal,

XTAL1,XT

AL2

87.5

001

XCLK, 20

MHz

010

XCLK, 25

MHz

87.5

011

XCLK,

MHz

82.5

28 Am79C976 8/01/00

PRELIMINARY

nected to the XCLK pin, and the XTAL1 and XTAL2 pins should be connected to VSS.

XTAL1 and XTAL2 are not 5-volt tolerant pins.

XTAL2

Crystal Output

If the CLKSEL0 and CLKSEL 1 pins are both he ld low, a 25 MHz crystal should be connected between the XTAL1 pin and the XT AL2 pin. This crystal controls the frequency of the internal clock generator circuit.

If either the CLKSEL0 or the CLKS EL1 pin or both ar e held high, a 20-, 25-, or

-MHz clock source must be

connected to the XCLK pin, and the XTAL1 and XTAL2 pins should be connected to VSS.

XTAL1 and XTAL2 are not 5-volt tolerant pins.

PHY_RST

PHY Reset Output

PHY_RST is an output pin that is used to reset the external PHY. This output eliminates the need for a fan-out buffer for the PCI RST signal, provides polarity for the specific PHY used, and prevents the resetting of the PHY when the PG input is LOW. The output polarity is determined by the PHY_RST_POL bit (CMD3, bit0), which can be loaded from the EEPROM.

The length of time for which the PHY_RST pin is asserted depends on the number of registers that are loaded from the EEP ROM and the order in whi ch the registers are loaded. Immediately after the PHY_RST_POL bit is loaded from the EEPROM, the PHY_RST pin is asser ted. When the la st register has been loaded from the EEPROM, the PHY_RST pin is deasserted. Each register loaded after the PHY_RST_POL bit is loaded adds about 240 µs to the time that PHY_RST is asserted. If the PHY_RST pin is used to reset an external PHY, the us er should prog ram the EEPROM to make sure that PHY_RST is asserted long enough to meet the requirements of the PHY. The user can in sert d ummy writes to offset 28h to extend the reset period.

Flow Control Input

The Flow Control input signal controls when MAC Control Pause Frames are sent or when half-duplex back pressure is asserted.

EEPROM Interface

EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EEPROM that uses the 93Cxx EE PROM interface protocol. EECS is connected to the EEPROM ’s chip select pin. It is controll ed by either the Am7 9C976 controll er

during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial EEPROM that uses the 93Cxx EEP ROM interface protocol. EEDI is co nnected to the EE PROM’s data input pin. It is control led by either the Am7 9C976 controll er during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0

pin.

EEDO

EEPROM Data Out Input

This pin is designed to directly interface to a serial EEPROM that uses the 93Cxx EEP ROM interface protocol. EEDO is con nected to the EEPROM’s data output pin. It is control led by either the Am7 9C976 controll er during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3

and

RXFRTGD pins.

EESK

EEPROM Serial Clock Output

This pin is designed to directly interface to a serial EEPROM that uses the 93Cxx EEP ROM interface protocol. EESK is connected to the EEPROM’s clock pin. It is controlled by either the Am79C976 controller directly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1

pin.

External Memory Interface

ERA[19:0]/FLA[19:0]

External Memory Address [19:0] Output

The ERA[19:0] pins provide addresses for both the external SSRAM and the external boot ROM device.

All ERA[19:0] pin outputs are forced to a constant level to conserve power while no access on the External Memory Bus is being performed.

FLA[23:20]

Boot ROM (Flash) Address [23:20] Output

The FLA[23:20] pins provide the 4 most significant bits of the address for the external boot ROM device.

All FLA[23:20] pin outputs are forced to a constant level to conserve power while no access on the External Memory Bus is being performed.

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PRELIMINARY

Note: The FLA[23:20] pins are multiplexed with the ERD[11:8] pins.

ERD[31:0]/FLD[7:0]

External Memory Data [31:0] Input/Output

The ERD[7:0] pins provide data bits [7:0] for boot ROM accesses. The ERD[31: 0] p ins provid e data bits [ 31:0] for external SSRAM accesses. The ERD[31:0] signals are forced to a constant l evel to conser ve power while no access on the Exter nal Memor y Bus is b eing performed.

Note: The FLA[23:20] pins are multiplexed with the ERD[11:8] pins.

ERCE

External SSRAM Chip Enable Output

ERCE

serves as the chip enable for the external SSRAM. It is asser t ed low when the SSRAM add ress o n the ERA[19:0] pins is valid.

FLCS

Boot ROM Chip Select Output

FLCS serves as the chip select for the boot device. It is asserted low when the boot ROM address on the FLA[23:20] and ERA[19:0] pins is valid.

EROE

External SSRAM Output Enable Output

EROE is asserted active LOW during SS RAM device read operations to allow the SSRAM device to drive the ERD[31:0] data bus. It is deasserted at all other times.

FLOE

Expansion ROM Output Enable Out put

FLOE

is asserted active LOW during boot ROM read operations to allow the boot ROM to drive the ERD[7:0] data bus. It is deasserted at all other times.

Note: The FLOE

pin is multiplexed with the ERADV

pin.

ERWE/FLWE

External Memory Write Enable Output

ERWE provides the write enable for write acc esses to the external SSRAM and the Flash (boot ROM) device.

ERADSP/CEN

External Memory Address Strobe Output

ERADSP provides the address strobe signal to load the address into the external SSRAM.

ERADV

External Memory Address Advance Output

ERADV provides the address advance signal to the external SSRAM. Th is signal is asser ted low during a

burst access to increment the addres s counter in the SSRAM.

Note: The FLOE

pin is multiplexed with the ERADV

pin.

ERCLK

External Memory Clock Output

ERCLK is the reference clock for all synchronous SRAM accesses.

Media Independent Interface

TX_CLK

Transmit Clock Input

TX_CLK is a conti nuous clock input th at provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals out of the Am79C976 device. TX_CLK must provide a nibble rate clock (25% of th e network data rate). Hence, an MII transceiver operating at 10 Mbps must provide a TX_CLK f requency of 2.5 MHz and an MII transceiver operating at 100 Mbps must provide a TX_CLK frequency of 25 MHz.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. V alid data is generated on TXD[3:0] on every TX_CLK rising edge while TX_EN is asser te d. While TX_EN is deasserted, TXD[3:0] values are driven to a 0. TXD[3:0] transitions synchronous to TX_CLK rising edges.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C976 device is presenting valid transmit nibbles on the MII. While TX_EN is asserted, the Am79C976 device generates TXD[3:0] on TX_CLK risin g edges. TX_EN is as serted with the first nibble of preamble and remains asserted throughout the duration of a packet until it i s deasser ted pr ior to the first TX_CLK following the final nibble of the frame. TX_EN transitions synchron ous to T X_CLK rising edges.

COL

Collision Input

COL is an input that indicates that a collision has been detected on the network medium.

CRS

Carrier Sense Input

CRS is an input that indicates that a non-idl e medium , due either to transmit or receive activity, has been detected.

30 Am79C976 8/01/00

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RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and RX_ER signals into the Am79C976 device. RX_CLK must provide a nibble rate clo ck (25% of the network data rate). Hence, an MII transceiver operating at 10 Mbps must provide an RX_ CLK freq uency of 2 .5 MHz and an MII transceiver operating at 100 Mbps must provide an RX_CLK frequency of 25 MHz. When the external PHY switches the RX_CLK and TX_CLK, it must provide glitch-free clock pulses.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII recei ve data bus. Data on RXD[3:0] is sampled on every rising edge of RX_CLK while RX_DV is asserted. RXD[3:0] is ignored while RX_DV is de-asserted.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that valid, received data is being presented o n the RXD[3:0] pins and RX_CLK is sync hronous to the re ceive data. In order for a frame to be fully received by the Am79C976 device on the MII, RX_DV must be asser ted prior to the RX_CLK rising edge, when the first nibble of the Startof-Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted pri or to the RX _CLK rising edge which follows this final nibble. RX_DV transitions are synchronous to RX_CLK rising edges.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receive frame currently being transferred on the RXD[3:0] pins. When RX_ER is asser ted whi le RX_DV is assert ed, a CRC error will be indicated in the receive descriptor for the incoming receive frame. RX_ER is ignored while RX_DV is deasserted. Spec i al co de group s gen erate d on RXD while RX_DV is deasserted are ignor ed (e.g., Bad SSD in TX and IDLE in T4). RX_ER transitions are synchronous to RX_CLK rising edges.

MDC

Management Data Clock Output

MDC is a non-continuous clock output t hat provides a timing referenc e for bits on the MDIO p in. Duri ng MII management por t operations, MDC runs at a nominal frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW.

If the MII Management p ort is not use d, the MDC pin can be left floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional M II management port data pin. MDIO is an output during the header portion of the management frame transfers and dur ing the dat a portions of write transfers. MDIO is an input during the data portions of read data transfers. When an operation is not in progress on the management port, MDIO is not driven. M DIO tr ansiti ons fr om the Am79C976 contro ller are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connector, then the MDIO pin should be externally pulled down to VSS with a 10-k

W ±5% resistor. If the PHY is perma-

nently connected, the n the MDIO pin should be externally pulled up to VCC with a 10-k

W ±5% resistor.

External Address Detection Interface

EAR

External Address Reject Input

The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR’d with the value on the EAR pin. The EAR pin acts as an exter nal address ac cept function. The pin value is OR’d with the intern al address detection result to determine if the current frame should be accepted. If EAR

remains high while a frame is being received, the frame will be accepted regardless of the state of the internal address matching logic.

The EAR

pin must not be left unconnecte d. If it is no t

used, it should be tied to VSS through a 10-k

W ±5% re-

sistor.

SFBD

Start Frame-Byte Delimiter Output

An initial rising edge on the SFBD signal indicates that a start of valid data is present on the RXD[3:0] pins. SFBD will go high for one nibble time (400 ns when operating at 10 Mbps and 40 ns when operating at 100 Mbps) one RX_CLK perio d after RX_DV has been asserted and RX _ER is deas serted, and there is the detection of the S FD (Start of Frame Delimiter ) of a received frame.

Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nibble time (1.25 MHz frequency when operating at 10 Mbps and 12.5 MHz fr equency when o peratin g at 10 0 Mbps), indicating the first nibble of each subsequent byte of the received nibble stream. The RX_CLK should be used in conjunction with t he SFBD to latch the correct data for external addre ss matching. SFBD will be active only during frame reception.

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