AMD Advanced Micro Devices AM79C974KCW Datasheet

PRELIMINARY

Am79C974

PCnetTM-SCSI Combination Ethernet and SCSI Controller
for PCI Systems

DISTINCTIVE CHARACTERISTICS
PCI Features

■ Direct glueless interface to 33 MHz, 32-bit PCI

local bus

■ 132 Mbyte/s burst DMA transfer rate

■ Compliant to PCI local bus Specification

Revision 2.0

Ethernet Features

■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and

Ethernet Standards

■ High-performance Bus Master architecture with

integrated DMA Buffer Management Unit for
low CPU and bus utilization

■ Individual 136-byte transmit and 128-byte

receive FIFOs provide frame buffering for
increased system latency

■ Microwire

jumperless design

■ Integrated Manchester Encoder/Decoder

■ Provides integrated Attachment Unit Interface

(AUI) and 10BASE-T transceiver with automatic
port selection

■ Automatic Twisted-Pair receive polarity detec-

tion and automatic correction of the receive
polarity

■ Dynamic transmit FCS generation programma-

ble on a frame-by-frame basis

■ Internal/external loopback capabilities

■ Supports the following types of network

interfaces:

— AUI to external 10BASE2, 10BASE5,

10BASE-T or 10BASE-F MAU

— Internal 10BASE-T transceiver with Smart

Squelch to Twisted-Pair medium

TM

EEPROM interface supports

SCSI Features

■ Compliant to ANSI standards X3.131 – 1986

(SCSI-1) and X3.131 – 199X (SCSI-2)

■ Fast 8-bit SCSI-2 10 Mbyte/s synchronous or

7Mbyte/s asynchronous data transfer rate

■ SCSI specific Bus Mastering DMA engine

(32-bit address/data)

■ 96-byte DMA FIFO for low bus latency

■ On-chip state machine to control the SCSI

sequences in hardware

■ Integrated industry standard Fast SCSI-2 core

■ Single-Ended 48 mA outputs to drive the SCSI

bus directly

■ Support for Scatter-Gather DMA data transfers

■ Hooks in silicon and software to enable disk

drive spin down for power savings

General Features

■ Software compatible with AMD’s Am79C960

PCnet-ISA, Am79C961 PCnet-ISA+, Am79C965
PCnet-32, Am79C970 PCnet-PCI register and
descriptor architecture

■ Plug-in and software compatible with AMD’s

PC

SCSI family of SCSI controllers for PCI

■ NAND Tree test mode for connectivity testing

on printed circuit boards

■ Single +5 V power supply operation

■ Low-power, CMOS design with sleep modes for

both Ethernet and SCSI controllers allows re­duced power consumption for critical battery
powered applications and ‘Green PCs’

■ Fully static design for low frequency and

power operation

■ 132-pin PQFP package

Advanced

Micro

Devices

GENERAL DESCRIPTION

The PCnet-SCSI combination Ethernet and 8-bit Fast
SCSI controller with a 32-bit PCI bus interface is a highly
integrated Ethernet-Fast SCSI system solution de­signed to address high-performance system application
requirements. This single-chip is a flexible bus-master­ing device that can be used in many applications, includ­ing network- and SCSI-ready PCs, printers, fax

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

modems, and bridge/router designs. The bus-master
architecture provides high data throughput in the sys­tem and low CPU and system bus utilization. The
PCnet-SCSI controller is fabricated with AMD’s ad­vanced low-power CMOS process to provide low oper­ating and standby current for power sensitive
applications.

Publication# 18681 Rev. B Amendment/1
Issue Date: October 1994

AMD

P R E L I M I N A R Y

The PCnet-SCSI is part of AMD’s PCI product family of
plug-in and software compatible SCSI and Ethernet
controllers. This product compatibility ensures a low
cost system upgrade path and lower motherboard
manufacturing costs.

Ethernet Specific

The PCnet-SCSI controller includes a complete Ether­net node integrated into a single VLSI device. It contains
a bus interface unit, a DMA buffer management unit, an
IEEE 802.3-defined Media Access Control (MAC) func­tion, individual 136-byte transmit and 128-byte receive
FIFOs, an IEEE 802.3-defined Attachment Unit Inter­face (AUI) and Twisted-Pair Transceiver Media Attach­ment Unit (10BASE-T MAU), and a Microwire EEPROM
interface. The PCnet-SCSI controller is also register
compatible with the LANCE (Am7990) Ethernet control­ler, the C-LANCE (Am79C90) Ethernet controller, the
ILACC (Am79C900) Ethernet controller, and all Ether­net controllers in the PCnet Family, including the PCnet­ISA controller (Am79C960), the PCnet-ISA+ controller
(Am79C961), and the PCnet-32 controller
(Am79C965). The buffer management unit supports the
LANCE, ILACC, and PCnet descriptor software models.
The PCnet-SCSI controller is software compatible with
the Novell NE2100 and NE1500 Ethernet adapter card
architectures. In addition, a Sleep function has been in­corporated to provide low standby current, excellent for
notebooks and Green PCs.

The 32-bit multiplexed bus interface unit provides a di­rect interface to the PCI local bus applications, simplify­ing the design of an Ethernet node in a PC system. With
its built-in support for both little and big endian byte
alignment, this controller also addresses proprietary
non-PC applications.

The PCnet-SCSI controller supports auto configuration
in the PCI configuration space. Additional PCnet-SCSI
controller configuration parameters, including the
unique IEEE physical address, can be read from an ex­ternal non-volatile memory (serial EEPROM) immedi­ately following system RESET.

The controller also has the capability to automatically
select either the AUI port or the Twisted-Pair trans­ceiver. Only one interface is active at any one time. The
individual transmit and receive FIFOs optimize system

overhead, providing sufficient latency during frame
transmission and reception, and minimizing intervention
during normal network error recovery. The integrated
Manchester encoder/decoder (MENDEC) eliminates
the need for an external Serial Interface Adapter (SIA) in
the system. In addition, the device provides program­mable on-chip LED drivers for transmit, receive, colli­sion, receive polarity, link integrity or jabber status.

SCSI Specific

The PCnet-SCSI controller also includes a high­performance Fast SCSI controller with a glueless inter­face to the PCI local bus. The PCnet-SCSI integrates its
own 32-bit bus mastering DMA engine with an industry
standard Fast SCSI-2 block. The DMA engine and ac­companying 96 byte DMA FIFO allow 32-bit burst data
transfers across the high bandwidth PCI bus at speeds
of up to 132 Mbyte/s. Full support for scatter-gather
DMA transfers optimize performance in multi-tasking
system applications.

The PCnet-SCSI’s on-chip state machine controls SCSI
bus sequences in hardware and is coupled with the bus
mastering DMA engine to eliminate the need for an on­chip RISC processor. This results in a smaller die size
giving the Am79C974 superior price/performance ver­sus competitive offerings.

AMD supports the Am79C974 with a total system solu­tion which includes:

A full suite of licensable SCSI drivers and utilities
fully tested under the following operating system
environments:

— DOS 5.0 – 6.0
— Windows 3.1
— Windows NT
— OS/2 2.x
— Netware 3.x, 4.x
— SCO UNIX 3.2.4, ODT 2.0
An INT13h Compatible SCSI ROM BIOS
ASPI Compatibility
Complete hardware reference design kit

For more detailed information on the PCnet-SCSI refer
to the technical manual, PID #18738A.

2

Am79C974

HIGH LEVEL BLOCK DIAGRAM

SCSI Data SCSI Control 10Base-T, AUI Ports

SCSI Sequences,
SCSI Control,
SCSI Registers

P R E L I M I N A R Y

AMD

802.3 MAC Core

SCSI FIFO DMA Registers

DMA
FIFO

96 Bytes

PCI Data/Address PCI Host Control

FIFO &
DMA Control

PCI Host Control and Interface

RCV

FIFO

FIFO

Control

DMA Registers
DMA Control

XMT

FIFO

18681A-1

3Am79C974

AMD

CPU

Cache
SRAM

Control

Address

Data

P R E L I M I N A R Y

DRAM

Memory

Core

Logic

PC-AT ISA Bus

PCnet-SCSI

(Am79C974)

PCI Bus

Video

Control

PCI

to

ISA

Super I/O

IDE/Floppy

Ser/Par

Am79C974 in a PCI System

Keyboard

Control

18681A-2

4

Am79C974

P R E L I M I N A R Y

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HIGH LEVEL BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RELATED PRODUCTS 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONNECTION DIAGRAM 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESIGNATIONS 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Number 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Name 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Quick Reference Pin Description 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Driver Type 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOGIC SYMBOL 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Interface 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Controller Pins 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Board Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Microwire EEPROM Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Attachment Unit Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted-Pair Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Controller Pins 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Interface 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Miscellaneous 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BASIC FUNCTIONS 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Bus Interface Function 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Interface 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Interfaces 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Interfaces 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DETAILED FUNCTIONS 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Interface Unit (BIU) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Slave Configuration Transfers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Slave I/O Transfers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Acquisition 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Master DMA Transfers 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Target Initiated Termination 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Master Initiated Termination 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Controller 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Buffer Management Unit (BMU) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Re-Initialization 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Buffer Management 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor Rings 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor Ring Access Mechanism 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Polling 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Descriptor Table Entry (TDTE) 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Descriptor Table Entry (RDTE) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD

5Am79C974

AMD

P R E L I M I N A R Y

Media Access Control 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit and Receive Message Data Encapsulation 48. . . . . . . . . . . . . . . . . . . . . . . . . . .

Media Access Management 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Manchester Encoder/Decoder (MENDEC) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Crystal Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Clock Drive Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MENDEC Transmit Path 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter Timing and Operation 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver Path 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signal Conditioning 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Acquisition 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Tracking 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Carrier Tracking and End of Message 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Decoding 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential Input Terminations 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision Detection 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jitter Tolerance Definition 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Attachment Unit Interface (AUI) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted-Pair Transceiver (T-MAU) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted-Pair Transmit Function 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted-Pair Receive Function 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Link Test Function 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Polarity Detection and Reversal 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted-Pair Interface Status 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision Detect Function 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Quality Error (SQE) Test (Heartbeat) Function 57. . . . . . . . . . . . . . . . . . . . . . . . . . .

Jabber Function 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Down 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10BASE-T Interface Connection 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Power Savings Modes 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Access 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet PCI Configuration Registers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Resources 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Register Access 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hardware Access 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCnet-SCSI Controller Master Accesses 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Slave Access to I/O Resources 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Microwire Access 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Operation 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Function Programming 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Pad Generation 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit FCS Generation 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Exception Conditions 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Operation 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Function Programming 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Pad Stripping 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive FCS Checking 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Exception Conditions 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loopback Operation 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LED Support 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Am79C974

P R E L I M I N A R Y

H_RESET, S_RESET, and STOP 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

H_RESET 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

S_RESET 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STOP 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Controller 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Specific DMA Engine 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA FIFO 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Blast Command 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Funneling Logic 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI DMA Programming Sequence 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MDL Based DMA Programming 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Scatter-Gather Mechanism 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Descriptor List (MDL) 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Scatter-Gather Operation (4k aligned elements) 78. . . . . . . . . . . . . . . . . . . . . . . .

DMA Scatter-Gather Operation (Non-4k aligned elements MDL not set) 80. . . . . . . . . .

Interrupts 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Fast SCSI Block 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Block ID 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI FIFO Threshold 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transmission 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REQ/ACK Control 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parity 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parity Checking on the SCSI Bus 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parity Generating on the SCSI Bus 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Levels 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Hard Reset: (H) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Soft Reset: (S) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Disconnected Reset: (D) 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Commands 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Command Stacking 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Invalid Commands 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Command Window 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initiator Commands 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Information Transfer Command 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initiator Command Complete Steps 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Message Accepted Command 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer Pad Bytes Command 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Set ATN Command 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset ATN Command 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Idle State Commands 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Select Without ATN Steps Command 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Select With ATN Steps Command 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Select With ATN and Stop Steps Command 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enable Selection/Reselection Command 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Disable Selection/Reselection Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Select With ATN3 Steps Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Commands 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

No Operation Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clear FIFO Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Device Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset SCSI Bus Command 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD

7Am79C974

AMD

P R E L I M I N A R Y

SCSI Power Management Features 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Activity Pin 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reduced Power Mode 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Down Pin (PWDN Pin) 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Disk Spin-Down 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NAND Tree Testing 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGES 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS: PCI Bus and Board Interface 92. . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS: Attachment Unit Interface 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS: 10BASE-T Interface 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS: SCSI Interface 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS: Capacitance, ESD, and Latch Up 95. . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING CHARACTERISTICS: PCI Bus and Board Interface 96. . . . . . . . . . . . . . . . .

AC SWITCHING CHARACTERISTICS: 10BASE-T Interface 97. . . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING CHARACTERISTICS: Attachment Unit Interface 98. . . . . . . . . . . . . . . . . . .

AC SWITCHING CHARACTERISTICS: SCSI Interface 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

KEY TO SWITCHING WAVEFORMS 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING TEST CIRCUITS 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING WAVEFORMS: System Bus Interface 103. . . . . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING WAVEFORMS: 10BASE-T Interface 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING WAVEFORMS: Attachment Unit Interface 107. . . . . . . . . . . . . . . . . . . . . . . .

AC SWITCHING WAVEFORMS: SCSI Interface 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PHYSICAL DIMENSIONS 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDIX A – Register Summary 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet Controller

Control and Status Registers 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR—Bus Configuration Registers 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCSI Controller

SCSI Register Map 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Register Map 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDIX B – PCnet-SCSI Compatible Media Interface Modules 119. . . . . . . . . . . . . . . . . .

APPENDIX C – Recommendation for Power and Ground Decoupling 121. . . . . . . . . . . . . . .

APPENDIX D – Alternative Method for Initialization of Ethernet Controller 123. . . . . . . . . . .

APPENDIX E – SCSI System Considerations 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDIX F – Designing a Single Motherboard for AMD PCI Family 132. . . . . . . . . . . . . . .

8

Am79C974

P R E L I M I N A R Y

LIST OF FIGURES

Figure 1. Slave Configuration Read 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 2. Slave Configuration Write 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 3. Slave I/O Read 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 4. Slave I/O Write 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 5. Bus Acquisition 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6. Non-Burst Read Cycles With Wait States 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 7. Non-Burst Read Cycles Without Wait States 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 8. Non-Burst Read Cycles With and Without Wait States 34. . . . . . . . . . . . . . . . . . . . . . . .

Figure 9. Burst Read Cycles 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 10. Burst Write Cycles 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 11. Disconnect With Data Transfer 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 12. Disconnect Without Data Transfer 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 13. Target Abort 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 14. Preemption When FRAME is Deasserted 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 15. Preemption When FRAME is Asserted 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 16. Master Abort 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 17. 16-Bit Data Structures: Initialization Block and Descriptor Rings 44. . . . . . . . . . . . . . .

Figure 18. 32-Bit Data Structures: Initialization Block and Descriptor Rings 45. . . . . . . . . . . . . . .

Figure 19. Receiver Block Diagram 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 20. Differential Input Termination 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 21. 10BASE-T Interface Connection 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 22. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 23. 802.3 Frame and Length Field Transmission Order 72. . . . . . . . . . . . . . . . . . . . . . . . .

Figure 24. LED Control Logic 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 25. PCI BIU – DMA Engine – SCSI Block 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26. DMA FIFO to SCSI FIFO Interface 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 27. Am79C974 NAND Tree Test Structure 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 28. NAND Tree Waveform 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 29. SCSI Clock Input 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 30. Asynchronous Initiator Transmit 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31. Asynchronous Initiator Receive 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 32. Synchronous Initiator Transmit 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 33. Synchronous Initiator Receive 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-1. Ideal Routing Scheme for SCSI 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-2. A Poor Routing Scheme for SCSI 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-3. Motherboard Layout – Approach #1 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-4. Motherboard Layout – Approach #2 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-5. Decoupling Capacitor Placement 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure E-6. Regulated Termination 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure F-1. PCI Family Connections 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD

9Am79C974

AMD

P R E L I M I N A R Y

LIST OF TABLES

Table 1. Crystal Specifications 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2. Clock Drive Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3. Bus Master Accesses 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4. Bus Slave Accesses 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 5. EEPROM Contents 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6. The DMA Registers 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7. Summary of SCSI Commands 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 8. NAND Tree Configuration 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

Am79C974

P R E L I M I N A R Y

RELATED PRODUCTS

Part No. Description

Am33C93A Synchronous SCSI Controller



Am386

TM

Am486
Am53C94/96 High-Performance SCSI Controller
Am53C974 PC
Am53CF94/96 Enhanced Fast SCSI-2 Controller
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98 Twisted-Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+)
Am79C900 Integrated Local Area Communications Controller
Am79C940 Media Acces Controller for Ethernet (MACE
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses)
Am79C970 PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus
Am79C981 Integrated Multiport Repeater Plus
Am79C987 Hardware Implemented Management Information Base
Am7990 Local Area Network Controller for Ethernet (LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am85C30 Enhanced Serial Communication Controller

High-Performance 32-Bit Microprocessor
High-Performance 32-Bit Microprocessor

TM

SCSI

Bus Mastering Fast SCSI Controller for PCI Systems

+

Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support)

TM

(IMR+TM)

TM

)

TM

(ILACCTM)

TM

(HIMIBTM)

AMD

11Am79C974

AMD

CONNECTION DIAGRAM

AD28

AD29

VSSB

AD30

132

131

130

129

VDDB

C/BE2

FRAME

IRDY

1
2AD27
3AD26
4VSSB
5AD25
6AD24
7C/BE3
8VDD
9IDSELA
10IDSELB
11VSS
12AD23
13AD22
14VSSB
15AD21
16AD20
17VDDB
18AD19
19AD18
20VSSB
21AD17
22AD16
23
24
25
26TRDY
27DEVSEL
28STOP
29LOCK
30VSS
31PERR
32SERR
33VDDB

34

35

36

37

AD31

128

38

REQA

REQB

127

126

40

VSS

125

41

P R E L I M I N A R Y

GNTA

GNTB

VDD

CLK

RST

VSS

INTB

124

123

122

121

120

119

118

Am79C974

PCnet-SCSI

43

44

45

46

47

48

INTA

RESERVE

117

116

49

50

SLEEP

EECS

115

114

51

52

DVSS

113

EESK/LED1

EEDI/LNKST

112

111

54

55

EEDO/LED3

DVDD

110

109

56

57

AVDD2

108

58

CI+

107

59

CI-

106

60

DI+

105

61

DI-

104

62

AVDD1

103

63

DO+

102

64

DO-

101

65

AVSS1

100

XTAL299
AVSS298
XTAL197
AVDD396
TXD+95
TXP+94
TXD-93
TXP-92
AVDD491
RXD+90
RXD-89
DVSS88

I/O87
C/D86
MSG85

VDD84
ACK83
VSSBS82

REQ81
SEL80

DVSS79

SDP78
SD777

VDDBS76

SD675
SD574
SD473

VSSBS72

SD371
SD270
SD169
SD068

VSSBS67

66

PAR

C/BE1

Pin 1 is marked for orientation.
RESERVE = Don’t Connect.

12

VSSB

AD15

AD1439AD13

AD12

VSSB

AD1142AD10

AD9

AD8

AD7

AD6

VDDB

C/BE0

Am79C974

VSSB

AD5

AD453AD3

AD2

VSSB

AD1

AD0

VDD

PWDN

VSS

BUSY

SCSICLK

VSS

ATN

BSY

SCSI^RST

18681A-3

P R E L I M I N A R Y

AMD

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:

AM79C974 K C \W

ALTERNATE PACKAGING OPTION

\W = Trimmed and Formed in a Tray

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0

PACKAGE TYPE (per Prod. Nomenclature)

K = Plastic Quad Flat Pack Trimmed and Formed

(PQB132)

°C to +70°C)

DEVICE NUMBER/DESCRIPTION

Am79C974
PCnet-SCSI Combination Ethernet and
SCSI Controller for PCI Systems

Valid Combinations

AM79C974

KC\W

SPEED OPTION

Not Applicable

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

13Am79C974

AMD

P R E L I M I N A R Y

PIN DESIGNATIONS
Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1VDDB 34 PAR 67 VSSBS 100 AVSS1
2 AD27 35 C/BE168 SD0 101 DO–
3 AD26 36 AD15 69 SD1 102 DO+
4VSSB 37 VSSB 70 SD2 103 AVDD1
5 AD25 38 AD14 71 SD3 104 DI–
6 AD24 39 AD13 72 VSSBS 105 DI+
7C/BE3 40 AD12 73 SD4 106 CI–
8VDD 41 AD11 74 SD5 107 CI+

9 IDSELA 42 AD10 75 SD6 108 AVDD2
10 IDSELB 43 VSSB 76 VDDBS 109 DVDD
11 VSS 44 AD9 77 SD7 110 EEDO/LED3
12 AD23 45 AD8 78 SDP 111 EEDI/LNKST
13 AD22 46 VDDB 79 DVSS 112 EESK/LED1
14 VSSB 47 C/BE080 SEL 113 DVSS
15 AD21 48 AD7 81 REQ 114 EECS
16 AD20 49 AD6 82 VSSBS 115 SLEEP
17 VDDB 50 VSSB 83 ACK 116 RESERVE
18 AD19 51 AD5 84 DVDD 117 INTA
19 AD18 52 AD4 85 MSG 118 INTB
20 VSSB 53 AD3 86 C/D 119 VSS
21 AD17 54 AD2 87 I/O 120 RST
22 AD16 55 VSSB 88 DVSS 121 CLK
23 C/BE2 56 AD1 89 RXD– 122 VDD
24 FRAME 57 AD0 90 RXD+ 123 GNTB
25 IRDY 58 PWDN 91 AVDD4 124 GNTA
26 TRDY 59 VDD 92 TXP– 125 VSS
27 DEVSEL 60 SCSICLK 93 TXD– 126 REQB
28 STOP 61 VSS 94 TXP+ 127 REQA
29 LOCK 62 BUSY 95 TXD+ 128 AD31
30 VSS 63 VSS 96 AVDD3 129 AD30
31 PERR 64 BSY 97 XTAL1 130 VSSB
32 SERR 65 ATN 98 AVSS2 131 AD29
33 VDDB 66 SCSI^RST 99 XTAL2 132 AD28

14

Am79C974

P R E L I M I N A R Y

PIN DESIGNATIONS
Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

ACK 83 ATN 65 GNTB 123 STOP 28
AD0 57 AVDD1 103 IDSELA 9 TRDY 26
AD1 56 AVDD2 108 IDSEL 10 XTAL1 97
AD2 54 AVDD3 96 INTA 117 XTAL2 99
AD3 53 AVDD4 91 INTB 118 TXD– 93
AD4 52 AVSS1 100 I/O 87 TXD+ 95
AD5 51 AVSS2 98 IRDY 25 TXP– 92
AD6 49 BSY 64 LOCK 29 TXP+ 94
AD7 48 BUSY 62 MSG 85 VDD 8
AD8 45 C/BE0 47 PAR 34 VDD 59

AD9 44 C/BE135 PERR 31 VDD 122
AD10 42 C/BE2 23 PWDN 58 VDDB 1
AD11 41 C/BE37 REQ 81 VDDB 17
AD12 40 C/D 86 REQA 127 VDDB 33
AD13 39 CLK 121 REQB 126 VDDB 46
AD14 38 CI– 106 RESERVE 116 VDDBS 76
AD15 36 CI+ 107 RST 120 VSS 11
AD16 22 DEVSEL 27 RXD– 89 VSS 30
AD17 21 DI– 104 RXD+ 90 VSS 61
AD18 19 DI+ 105 SCSICLK 60 VSS 63
AD19 18 DO– 101 SCSI^RST 66 VSS 119
AD20 16 DO+ 102 SD068 VSS 125
AD21 15 DVDD 84 SD169 VSSB 4
AD22 13 DVDD 109 SD270 VSSB 14
AD23 12 DVSS 79 SD371VSSB 20
AD24 6 DVSS 88 SD473VSSB 37
AD25 5 DVSS 113 SD574VSSB 43
AD26 3 EECS 114 SD675 VSSB 50
AD27 2 EEDI/LNKST 111 SD777VSSB 55
AD28 132 EEDO/LED3 110 SDP78 VSSB 130
AD29 131 EESK/LED1 112 SEL 80 VSSBS 67
AD30 129 FRAME 24 SERR 32 VSSBS 72
AD31 128 GNTA 124 SLEEP 115 VSSBS 82

AMD

15Am79C974

AMD

P R E L I M I N A R Y

PIN DESIGNATIONS
Quick Reference Pin Description

Pin Name Description Type Driver # Pins
PCI Bus Interface

AD[31:00] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I NA 1

DEVSEL Device Select IO TS6 1
FRAME Cycle Frame IO TS6 1
GNTA, GNTB Bus Grant I NA 1

IDSELA, IDSELB Initialization Device Select I NA 1

INTA, INTB Interrupt IO OD6 1
IRDY Initiator Ready IO TS6 1
LOCK Bus Lock IO TS6 1

PAR Parity IO TS6 1

PERR Parity Error IO TS6 1
REQA, REQB Bus Request IO TS3 1
RST Reset I NA 1
SERR System Error IO OD6 1
STOP Stop IO TS6 1
TRDY Target Ready IO TS6 1

ETHERNET SPECIFIC
Board Interface

EECS Microwire Serial PROM Chip Select O O8 1
EEDI/LNKST Microwire Serial EEPROM Data In/Link Status O LED 1
EEDO/LED3 Microwire APROM Data Out/LED predriver IO LED 1
EESK/LED1 Microwire Serial PROM Clock/LED1 IO LED 1
SLEEP Sleep Mode I NA 1
XTAL1–2 Crystal Input/Output IO NA 2

Attachment Unit Interface (AUI)

CI+/CI– AUI Collision Differential Pair I NA 2
DI+/DI– AUI Data In Differential Pair I NA 2
DO+/DO– AUI Data Out Differential Pair O DO 2

10BASE-T Interface

RXD+/RXD– Receive Differential Pair I NA 2
TXD+/TXD– Transmit Differential Pair O TDO 2
TXP+/TXP– Transmit Pre-distortion Differential Pair O TPO 2
LNKST/EEDI Link Status/Microwire Serial EEPROM Data In O LED 1

16

Am79C974

P R E L I M I N A R Y

AMD

PIN DESIGNATIONS (continued)
Quick Reference Pin Description

Pin Name Description Type Driver # Pins
SCSI SPECIFIC
SCSI Interface

SD [7:0] SCSI Data IO OD48 8
SDP SCSI Data Parity IO OD48 1
MSG Message I 1
C/D Command/Data I 1
I/O Input/Output I 1
ATN Attention O OD48 1
BSY Busy IO OD48 1
SEL Select IO OD48 1
SCSI^RST SCSI Bus Reset IO OD48 1
REQ Request I 1
ACK Acknowledge O OD48 1

Miscellaneous

SCSI CLK SCSI Core Clock I 1
RESERVE Reserved, DO NOT CONNECT I 1

Power Management

PWDN Power Down Indicator I 1

Test Interface

BUSY NAND Tree Test Output O O3 1

Power Supplies

AVDD Analog Power P NA 4
AVSS Analog Ground P NA 2
VDD/DVDD Digital Power P NA 5
VSS/DVSS Digital Ground P NA 9
VDDB/VDDBS I/O Buffer Power P NA 5
VSSB/VSSBS I/O Buffer Ground P NA 11

Listed by Driver Type

The following table describes the various types of drivers that are implemented in the PCnet-SCSI controller. Current
is given as milliamperes:

Name Type IOL (mA) IOH (mA) pF

TS3 Tri-State
TS6 Tri-State 6 –2.0 50

O3 Totem Pole 3 –0.4 50
O6 Totem Pole 6 –0.4 50
O8 Totem Pole 8 –0.4 50

OD6 Open Drain 6 NA 50

OD48 Open Drain 48 NA —

LED LED 12 –0.4 50

TM

3 –2.0 50

17Am79C974

AMD

LOGIC SYMBOL

P R E L I M I N A R Y

PCI Interface

AD [31:0]

C/BE [3:0]

PAR

FRAME

TRDY

IRDY

STOP

DEVSEL

IDSELA

IDSELB

REQA

REQB

GNTA

PCnet-SCSI

(Am79C974)

CI+/–
DI+/–

XTAL1
XTAL2
DO+/–

RXD+/–
TXD+/–
TXP+/–
EEDI/LINKST

EECS
EESK/LED1
EEDO/LED3

SD [7:0]
SDP

MSG

C/D

I/O

ATN

Ethernet

GNTB

CLK

RST

INTA

INTB

LOCK

PERR

SERR

VDD VSS

BSY

SEL

SCSI^RST

REQ

ACK

SCSI CLK
RESERVE

PWDN

BUSY

SCSI

Power

Management

Signals

Test Interface

18248B-4

18

Am79C974

P R E L I M I N A R Y

AMD

PIN DESCRIPTION
PCI Bus Interface
AD[31:00]

Address and Data
Input/Output, Active High

These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subse­quent clocks AD[31:00] contain data. Byte ordering is lit­tle endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnet­SCSI controller can be programmed for big endian byte
ordering. See CSR3, bit 2 (BSWP) for more details.

During the address phase of the transaction, when the
PCnet-SCSI controller is a bus master, AD[31:2] will ad­dress the active DWORD (double-word). The PCnet­SCSI controller always drives AD[1:0] to ‘00’ during the
address phase indicating linear burst order. When the
PCnet-SCSI controller is not a bus master, the
AD[31:00] lines are continuously monitored to deter­mine if an address match exists for I/O slave transfers.

During the data phase of the transaction, AD[31:00] are
driven by the PCnet-SCSI controller when performing
bus master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-SCSI controller when
performing bus master reads and slave write
operations.

When RST is active, AD[31:0] are inputs for NAND tree
testing.

C/BE [3:0]

Bus Command and Byte Enables
Input/Output, Active Low

These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/BE[3:0]
define the bus command. During the data phase
C/BE[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/BE0 applies to byte 0 (AD[07:00]) and C/BE3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).

When RST is active, C/BE[3:0] are inputs for NAND tree
testing.

CLK

Clock
Input

This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-SCSI controller. All bus signals are sampled on
the rising edge of CLK and all parameters are defined

with respect to this edge. The PCnet-SCSI controller op­erates over a range of 0 to 33 MHz.

When RST is active, CLK is an input for NAND tree
testing.

DEVSEL

Device Select
Input/Output, Active Low

This signal when actively driven by the PCnet-SCSI
controller as a slave device signals to the master device
that the PCnet-SCSI controller has decoded its address
as the target of the current access. As an input it indi­cates whether any device on the bus has been selected.

When RST is active, DEVSEL is an input for NAND tree
testing.

FRAME

Cycle Frame
Input/Output, Active Low

This signal is driven by the PCnet-SCSI controller when
it is the bus master to indicate the beginning and dura­tion of the access. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted when the
transaction is in the final data phase.

When RST is active, FRAME is an input for NAND tree
testing.

GNTA

Bus Grant
Input, Active Low

This signal indicates that the access to the bus has been
granted to the Am79C974’s SCSI controller.

The Am79C974 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNTA
without an active REQA from the Am79C974 controller,
the controller will actively drive the AD[31:00], C/
BE[3:0], and PAR lines.

When RST is active, GNTA is an input for NAND tree
testing.

GNTB

Bus Grant
Input, Active Low

This signal indicates that the access to the bus has been
granted to the Am79C974’s Ethernet controller. The
Am79C974 controller supports bus parking. When the
PCI bus is idle and the system arbiter asserts GNTB
without an active REQB from the Am79C974 controller,
the controller will actively drive the AD, C/BE and PAR
lines.

19Am79C974

AMD

P R E L I M I N A R Y

When RST is active, GNTB is an input for NAND tree
testing.

IDSELA

Initialization Device Select
Input, Active High

This signal is used as a SCSI controller selection for the
Am79C974 during configuration read and
write transaction.

When RST is active, IDSELA is an input for NAND tree
testing.

IDSELB

Initialization Device Select
Input, Active High

This signal is used as an Ethernet controller selection for
the PCnet-SCSI controller during configuration read
and write transaction.

When RST is active, IDSELB is an input for NAND tree
testing.

INTA

Interrupt Request
Input/Output, Active Low, Open Drain

This signal combines the interrupt requests from both
the SCSI DMA engine and the SCSI core. The interrupt
source can be determined by reading the SCSI DMA
Status Register. It is cleared when the Status Register is
read.

When RST is active, INTA is an input for NAND tree test­ing. This is the only time INTA is an input.

INTB

Interrupt Request
Input/Output, Active Low, Open Drain

An asynchronous attention signal which indicates that
one or more of the following status flags is set: BABL,
MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB,
MPCO, or TXSTRT. Each status flag has a mask bit
which allows for suppression of INTB assertion. The
flags have the following meaning:

BABL Babble
RCVCCO Receive Collision Count Overflow
RPCO Runt Packet Count Overflow
JAB Jabber
MISS Missed Frame
MERR Memory Error
MPCO Missed Packet Count Overflow
RINT Receive Interrupt
IDON Initialization Done
TXSTRT Transmit Start

When RST is active, INTB is an input for NAND tree
testing. This is the only time INTB is an input.

20

Am79C974

IRDY

Initiator Ready
Input/Output, Active Low

This signal indicates PCnet-SCSI controller’s ability, as
a master device, to complete the current data phase of
the transaction. IRDY is used in conjunction with the
TRDY. A data phase is completed on any clock when
both IRDY and TRDY are asserted. During a write IRDY
indicates that valid data is present on AD[31:00]. During
a read IRDY indicates that data is accepted by the
PCnet-SCSI controller as a bus master. Wait states are
inserted until both IRDY and TRDY are asserted simul­taneously.

When RST is active, IRDY is an input for NAND tree
testing.

LOCK

Lock
Input, Active Low

LOCK is used by the current bus master to indicate an
atomic operation that may require multiple transfers.

As a slave device, the PCnet-SCSI controller can be
locked by any master device. When another master at­tempts to access the PCnet-SCSI while it is locked, the
PCnet-SCSI controller will respond by asserting
DEVSEL and STOP with TRDY deasserted (PCI retry).

The PCnet-SCSI controller will never assert LOCK as a
master.

When RST is active, LOCK is an input for NAND tree
testing.

PAR

Parity
Input/Output, Active High

Parity is even parity across AD[31:00] and C/BE[3:0].
When the PCnet-SCSI controller is a bus master, it
generates parity during the address and write data
phases. It checks parity during read data phases. When
the PCnet-SCSI controller operates in slave mode and
is the target of the current cycle, it generates parity dur­ing read data phases. It checks parity during address
and write data phases.

When RST is active, PAR is an input for NAND tree
testing.

PERR

Parity Error
Input/Output, Active Low, Open Drain

This signal is asserted for one CLK by the PCnet-SCSI
controller when it detects a parity error during any data
phase when its AD[31:00] lines are inputs. The PERR
pin is only active when PERREN (bit 6) in the PCI com­mand register is set.

P R E L I M I N A R Y

AMD

The PCnet-SCSI controller monitors the PERR input
during a bus master write cycle. It will assert the Data
Parity Reported bit in the Status register of the Configu­ration Space when a parity error is reported by the target
device.

When RST is active, PERR is an input for NAND tree
testing.

REQA

Bus Request
Input/Output, Active Low

The Am79C974’s SCSI controller asserts REQA pin as
a signal that it wishes to become a bus master. Once as­serted, REQA remains active until GNTA has become
active.

When RST is active, REQA is an input for NAND tree
testing. This is the only time REQA is an input.

REQB

Bus Request
Input/Output, Active Low

The Am79C974’s Ethernet controller asserts REQB pin
as a signal that it wishes to become a bus master. Once
asserted, REQB remains active until GNT has become
active, independent of subsequent assertion of SLEEP
or setting of the STOP bit or access to the S_RESET
port (offset14h).

When RST is active, REQB is an input for NAND tree
testing. This is the only time REQB is an input.

RST

Reset
Input, Active Low

When RST is asserted low, then the PCnet-SCSI con­troller performs an internal system reset of the type
H_RESET (HARDWARE_RESET). RST must be held
for a minimum of 30 CLK periods. While in the H_RE­SET state, the PCnet-SCSI controller will disable or
deassert all outputs. RST may be asynchronous to the
CLK when asserted or deasserted. It is recommended
that the deassertion be synchronous to guarantee a
clean and bounce free edge.

When RST is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the BUSY output
(pin 62).

SERR

System Error
Input/Output, Active Low, Open Drain

This signal is asserted for one CLK by the PCnet-SCSI
controller when it detects a parity error during the ad­dress phase when its AD[31:00] lines are inputs.

The SERR pin is only active when SERREN (bit 8) and
PERREN (bit 6) in the PCI command register are set.

When RST is active, SERR is an input for NAND tree
testing.

STOP

Stop
Input/Output, Active Low

In the slave role, the PCnet-SCSI controller drives the
STOP signal to inform the bus master to stop the current
transaction. In the bus master role, the PCnet-SCSI
controller receives the STOP signal and stops the cur­rent transaction.

When RST is active, STOP is an input for NAND tree
testing.

TRDY

Target Ready
Input/Output, Active Low

This signal indicates the PCnet-SCSI controller’s ability
as a selected device to complete the current data phase
of the transaction. TRDY is used in conjunction with the

IRDY. A data phase is completed on any clock both
TRDY and IRDY are asserted. During a read TRDY indi-

cates that valid data is present on AD[31:00]. During a
write, TRDY indicates that data has been accepted.
Wait states are inserted until both IRDY and TRDY are
asserted simultaneously.

When RST is active, TRDY is an input for NAND tree
testing.

Ethernet Controller Pins

Board Interface

LED1

LED1
Output

This pin is shared with the EESK function. As LED1, the
function and polarity of this pin are programmable
through BCR5. By default, LED1 is active LOW and it in­dicates receive activity on the network. The LED1 output
from the PCnet-SCSI controller is capable of sinking the
12 mA of current necessary to drive an LED directly.

The LED1 pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present
at the PCnet-SCSI controller Microwire interface. At the
trailing edge of the RST pin, LED1 is sampled to deter­mine the value of the EEDET bit in BCR19. A sampled
HIGH value means that an EEPROM is present, and
EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection sec­tion for more details.

If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in or­der to resolve the EEDET setting.

21Am79C974

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P R E L I M I N A R Y

LED3

LED3
Output

This pin is shared with the EEDO function of the
Microwire serial EEPROM interface. When functioning
as LED3, the signal on this pin is programmable through
BCR7. By default, LED3 is active LOW and it indicates
transmit activity on the network. Special attention must
be given to the external circuitry attached to this pin. If
an LED circuit were directly attached to this pin, it would
create an I
serial EEPROM that would also be attached to this pin.

Therefore, if this pin is to be used as an additional LED
output while an EEPROM is used in the system, then
buffering is required between the LED3 pin and the LED
circuit. If no EEPROM is included in the system design,
then the LED3 signal may be directly connected to an
LED without buffering. The LED3 output from the
PCnet-SCSI controller is capable of sinking the 12 mA of
current necessary to drive an LED in this case. For more
details regarding LED connection, see the section on
LEDs.

OL requirement that could not be met by the

LNKST

LINK Status
Output

This pin provides 12 mA for driving an LED. By default, it
indicates an active link connection on the 10BASE-T in­terface. This pin can also be programmed to indicate
other network status (see BCR4). The LNKST pin
polarity is programmable, but by default, it is active
LOW. Note that this pin is multiplexed with the EEDI
function.

SLEEP

Sleep
Input

When SLEEP is asserted (active LOW), the PCnet­SCSI controller performs an internal system reset of the
S_RESET type and then proceeds into a power savings
mode. (The reset operation caused by SLEEP assertion
will not affect BCR registers.) The PCI interface section
is not effected by SLEEP. In particular, access to the
PCI configuration space remains possible. None of the
configuration registers will be reset by SLEEP. All I/O
accesses to the PCnet-SCSI controller will result in a
PCI target abort response. The PCnet-SCSI controller
will not assert REQ while in sleep mode. When SLEEP
is asserted, all non-PCI interface outputs will be placed
in their normal S_RESET condition. All non-PCI inter­face inputs will be ignored except for the SLEEP pin it­self. De-assertion of SLEEP results in wake-up. The
system must refrain from starting the network opera­tions of the PCnet-SCSI device for 0.5 seconds follow­ing the deassertion of the SLEEP signal in order to allow
internal analog circuits to stabilize.

22

Am79C974

Both CLK and XTAL1 inputs must have valid clock sig­nals present in order for the SLEEP command to take
effect. If SLEEP is asserted while REQ is asserted, then
the PCnet-SCSI controller will wait for the assertion of
GNT. When GNT is asserted, the REQ signal will be de-
asserted and then the PCnet-SCSI controller will pro­ceed to the power savings mode.

The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the asser­tion of SLEEP until three CLK cycles after the comple­tion of a valid pin RST operation.

The SLEEP pin does not affect the SCSI section.

XTAL1

Crystal Oscillator Input
Input

XTAL2

Crystal Oscillator Output
Output

The crystal frequency determines the network data rate.
The PCnet-SCSI controller supports the use of quartz
crystals to generate a 20 MHz frequency compatible
with the ISO 8802-3 (IEEE/ANSI 802.3) network fre­quency tolerance and jitter specifications. See the sec­tion External Crystal Characteristics (in section
Manchester Encoder/Decoder) for more detail.

The network data rate is one-half of the crystal fre­quency. XTAL1 may alternatively be driven using an ex­ternal CMOS level source, in which case XTAL2 must
be left unconnected. Note that when the PCnet-SCSI
controller is in coma mode, there is an internal 22 KΩ re­sistor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resis­tor. If XTAL1 is driven LOW at this time power consump­tion will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of SLEEP
and deassertion of REQ.

Microwire EEPROM Interface

EESK

EEPROM Serial Clock
Input/Output

The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EESK is con­nected to the Microwire EEPROM’s Clock pin. It is con­trolled by either the PCnet-SCSI controller directly
during a read of the entire EEPROM, or indirectly by the
host system by writing to BCR19, bit 1.

The EESK pin is also used during EEPROM Auto-detec­tion to determine whether or not an EEPROM is present

P R E L I M I N A R Y

AMD

at the PCnet-SCSI controller Microwire interface. At the
trailing edge of the RST signal, EESK is sampled to de­termine the value of the EEDET bit in BCR19. A sam­pled HIGH value means that an EEPROM is present,
and EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection sec­tion for more details.

EESK is shared with the LED1 function. If no LED circuit
is to be attached to this pin, then a pull up or pull down
resistor must be attached instead, in order to resolve the
EEDET setting.

EEDO

EEPROM Data Out
Input

The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EEDO is con­nected to the Microwire EEPROM’s Data Output pin. It
is controlled by the EEPROM during reads. It may be
read by the host system by reading BCR19 bit 0.

EEDO is shared with the LED3 function.

EECS

EEPROM Chip Select
Output

The function of the EECS signal is to indicate to the
Microwire EEPROM device that it is being accessed.
The EECS signal is active high. It is controlled by either
the PCnet-SCSI controller during command portions of
a read of the entire EEPROM, or indirectly by the host
system by writing to BCR19 bit 2.

EEDI

EEPROM Data In
Output

The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func­tions as an output. This pin is designed to directly inter­face to a serial EEPROM that uses the Microwire
interface protocol. EEDI is connected to the Microwire
EEPROM’s Data Input pin. It is controlled by either the
PCnet-SCSI controller during command portions of a
read of the entire EEPROM, or indirectly by the host sys­tem by writing to BCR19 bit 0.

Attachment Unit Interface

CI±

Collision In
Input

A differential input pair signaling the PCnet-SCSI con­troller that a collision has been detected on the network
media, indicated by the CI± inputs being driven with a
10MHz pattern of sufficient amplitude and pulse width
to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Op­erates at pseudo ECL levels.

DI±

Data In
Input

A differential input pair to the PCnet-SCSI controller car­rying Manchester encoded data from the network. Oper­ates at pseudo ECL levels.

DO±

Data Out
Output

A differential output pair from the PCnet-SCSI controller
for transmitting Manchester encoded data to the net­work. Operates at pseudo ECL levels.

Twisted-Pair Interface

RXD±

10BASE-T Receive Data
Input

10BASE-T port differential receivers.

TXD±

10BASE-T Transmit Data
Output

10BASE-T port differential drivers.

TXP±

10BASE-T Pre-Distortion Control
Output

These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.

EEDI is shared with the LNKST function.

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P R E L I M I N A R Y

SCSI Controller Pins

SCSI Bus Interface Signals
SCSI Bus Pins

SD [7:0]

SCSI Data
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger

These pins are defined as bi-directional SCSI data bus.

SDP

SCSI Data Parity
Input/Output, Active Low, Open Drain/Active
Negation, Schmitt Trigger

This pin is defined as bi-directional SCSI data parity.

MSG

Message
Input, Active Low, Schmitt Trigger

It is a Schmitt trigger input in the initiator mode.

C/D

Command/Data
Input, Schmitt Trigger

It is a Schmitt trigger input in the initiator mode.

I/O

Input/Output
Input, Schmitt Trigger

It is a Schmitt trigger input in the initiator mode.

ATN

Attention
Output, Active Low, Open Drain

This signal is a 48 mA output in the initiator mode. This
signal will be asserted when the device detects a parity
error; also, it can be asserted via certain commands.

BSY

Busy
Input/Output, Active Low, Schmitt Trigger,
Open Drain

As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.

SEL

Select
Input/Output, Active Low, Schmitt Trigger,
Open Drain

As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.

SCSI^RST

Reset
Input/Output, Active Low, Schmitt Trigger,
Open Drain

As a SCSI input signal it has a Schmitt trigger and as an
output signal it has a 48 mA drive.

REQ

Request
Input, Active Low, Schmitt Trigger

This is a SCSI input signal with a Schmitt trigger in the
initiator mode.

ACK

Acknowledge
Output, Active Low, Open Drain/Active Negation

This is a SCSI output signal with a 48 mA drive in the
initiator mode.

SCSI CLK

SCSI Clock
Input

The SCSI clock signal is used to generate all internal de­vice timings. The maximum frequency of this input is
40MHz and a minimum of 10 MHz is required to main­tain the SCSI bus timings.

Note:

A 40 MHz clock must be supplied at this input to achieve
10 Mbyte/s Synchronous Fast SCSI transfers.

PWDN

Power Down Indicator
Input, Active High

This signal, when asserted, sets the PWDN status bit in
the DMA status register and sends an interrupt to
thehost.

Test Interface

BUSY

NAND Tree Out
Output, Active Low

This signal is logically equivalent to the SCSI bus signal
BSY. It is duplicated so that external logic can be
connected to monitor SCSI bus activity.

The results of the NAND tree testing can be observed on
the BUSY pin where RST is asserted; otherwise, BUSY
will reflect the state of the SCSI Bus Signal line BSY
(pin64).

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Miscellaneous
RESERVED

Reserved_DO NOT CONNECT
Input

This pin (#116) is reserved for internal test logic. It
MUST NOT BE CONNECTED to anything for proper
chip operation. It’s use is subject to change in future
products.

Power Supply Pins
Analog Power Supply Pins
AVDD

Analog Power (4 Pins)
Power

There are four analog +5 V supply pins. Special atten­tion should be paid to the printed circuit board layout to
avoid excessive noise on these lines. Refer to
AppendixC and the
for details.

Technical Manual

(PID #18738A)

AVSS

Analog Ground (2 Pins)
Power

There are two analog ground pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on these lines. Refer to Appendix C and
the

Technical Manual

(PID #18738A) for details.

Digital Power Supply Pins
VDD/DVDD

Digital Power (5 Pins)
Power

There are 5 power supply pins that are used by the inter­nal digital circuitry. All VDD pins must be connected to a
+5 V supply.

VDDB/VDDB

I/O Buffer Power (5 Pins)
Power

There are 5 power supply pins that are used by the PCI
bus Input/Output buffer drivers. All VDDB pins must be
connected to a +5 V supply.

VSS/DVSS

Digital Ground (9 Pins)
Ground

There are 9 ground pins that are used by the internal
digital circuitry.

VSSB/VSSBS

I/O Buffer Ground (11 Pins)
Ground

There are 11 ground pins that are used by the PCI bus
Input/Output buffer drivers.

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P R E L I M I N A R Y

BASIC FUNCTIONS
System Bus Interface Function

During normal operations the Am79C974 operates as a
bus master with a few slave l/O accesses for status and
control functions.

The Ethernet controller is initialized through a combina­tion of PCI Configuration Space accesses, I/O space
Bus Slave accesses, Memory Space Bus Master ac­cesses, and optional reads of an external serial
EEPROM. The EEPROM is read through the Microwire
interface either automatically by the Am79C974 or indi­rectly by a series of bus slave accesses to one of the
Ethernet Bus Configuration Registers (BCRs). The
EEPROM normally contains the ISO 8802-3 (IEEE/
ANSI 802.3) Ethernet node address and data to be
loaded into some of the Ethernet BCRs.

The SCSI controller is initialized by bus slave writes to
SCSI Core and SCSI DMA registers.

Software Interface

The Am79C794 uses four address spaces: Ethernet
PCI configuration space, SCSI PCI configuration space,
I/O space, and memory space.

SCSI PCI configuration space is selected when the
IDSELA pin is active. Ethernet PCI configuration space
is selected when the IDSELB pin is active. The way that
IDSELA and IDSELB are controlled depends on exter­nal hardware. Section 3.6.4.1 of the PCI Specification
recommends two methods of generating configuration
cycles called Configuration Mechanism #1 and Configu­ration Mechanism #2.

The PCI Configuration Spaces are used by system soft­ware to identify the SCSI and Ethernet controllers and to
set up device configuration without the use of jumpers.
Certain PCI configuration registers have read-only infor­mation about the devices resource requirements. Other
registers are used as mail boxes that system configura­tion software uses to inform other software what re­sources have been allocated to the device. The only PCI
Configuration Registers that affect the operation of the
Am79C794 are the SCSI and Ethernet Base Address
Registers, which are found at offset 10h in each of the
two configuration spaces, and the Command Registers
at offset 4. Writing to these registers establishes the
base address of the SCSI l/O space and the base ad­dress of the Ethernet I/O space.

The SCSI controller registers occupy 96 bytes of l/O
space that starts on whatever 128-byte boundary that is
programmed into the Base Address Register at offset
10h in the SCSI PCI Configuration Space. The Ethernet
controller registers occupy 32 bytes of l/O space that
starts on whatever 32-byte boundary that is pro­grammed into the Base Address Register at offset 10h
in the Ethernet PCI Configuration Space. These

26

Am79C974

registers are used to set up controller operating modes,
to enable or disable various features, to start certain op­erations, and to monitor operating status.

In addition to the registers in the l/O space, the Ethernet
controller uses certain data structures that are set up
(typically by the host computer) in normal memory
space. These data structures are (1) the initialization
block that contains configuration data that the Ethernet
controller automatically loads into its Configuration and
Status Registers (CSRs), (2) the Receive and Transmit
Descriptor Rings, that contain pointers to receive and
transmit buffers and status and control information
about these buffers, and (3) the receive and transmit
buffers. The Ethernet controller uses bus master ac­cesses to read the locations of the buffers, to store
frames received from the network into the receive buff­ers, and to transmit the contents of the transmit buffers.

Ethernet Interfaces

The Am79C974 controller can be connected to an 802.3
network via one of two network interfaces. The Attach­ment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection.

SCSI Interfaces

The Am79C974 acts as a bridge between the PCI and
SCSI buses. As the maximum data transfer rate on the
PCI bus is a very high 132 Mbyte/s compared with the
SCSI bus 10 Mbyte/s, buffering is required between the
two buses. The buffering is provided by two FIFOs: a
16-byte (16X8 bits) SCSI Core FIFO and an additional
96-byte (24X32 bits) DMA FIFO. These FIFOs provide a
temporary storage for all command, data, status and
message bytes as they are transferred between the
32-bit PCI bus and the 8-bit SCSI bus.

The Am79C974’s SCSI Core and DMA registers are ad­dressed using the value in the Base Address Register
(offset 10h in the PCI Configuration Space). The SCSI
registers occupy 16 double words and the DMA engine
registers occupy 8 double word locations. The I/O ad­dress map is as follows:

Start Offset End Offset Block Name Size

0x0000 0x003F SCSI Core Reg 16 DW/64B
0x0040 0x005F PCI DMA CCB 8 DW/32B

The PCI configuration space, Ethernet controller and
SCSI controller are described in detail in the following
sections.

P R E L I M I N A R Y

AMD

DETAILED FUNCTIONS
Bus Interface Unit (BIU)

The bus interface unit is built of several state machines
that run synchronously to CLK. One bus interface unit
state machine handles accesses where the Am79C974
controller is the bus slave, and another handles ac­cesses where the Am79C974 controller is the bus mas­ter. All inputs are synchronously sampled. All outputs
are synchronously generated on the rising edge of CLK.

In the descriptions that follow, GNT, REQ, INT, and

IDSEL are used to refer to the set of GNTA, REQA,
INTA, and IDSELA for the SCSI controller and to the set

of GNTB, REQB, INTB, and IDSELB for the Ethernet
Controller, respectively.

Slave Configuration Transfers

The host can access the Am79C974 PCI configuration

CLK

123456

FRAME

space with a configuration read or write command. The
Am79C974 controller will assert DEVSEL if the IDSEL
input is asserted during the address phase and if the ac­cess is a configuration cycle. DEVSEL is asserted two
clock cycles after the host has asserted FRAME. All
configuration cycles are of fixed length. The Am79C974
controller will assert TRDY on the 3rd clock of the
dataphase.

Slave Configuration Read

The Slave Configuration Read command is used by the
host CPU to read the configuration space in the
Am79C974 controller. This provides the host CPU with
information concerning the device and its capabilities.
This is a single cycle, non-burst 8-bit, 16-bit, or 32-bit
transfer.

AD

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

IDSEL

ADDR DATA

1010 BE's

PAR PAR

18681A-5

Figure 1. Slave Configuration Read

27Am79C974

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P R E L I M I N A R Y

Slave Configuration Write

The Slave Configuration Write command is used by the
host CPU to write the configuration space in the
Am79C974 controller. This allows the host CPU to

CLK

123456

FRAME

AD

C/BE

PAR

IRDY

ADDR DATA

1011 BE's

PAR PAR

control basic activity of the device, such as enable/dis­able, change I/O location, etc. This is a single cycle,
non-burst 8-bit, 16-bit, or 32-bit transfer.

TRDY

DEVSEL

STOP

IDSEL

18681A-6

Figure 2. Slave Configuration Write

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Slave I/O Transfers

After the Am79C974 controller is configured as I/O de­vice (by setting IOEN in the PCI Command register), it
starts monitoring the PCI bus for access to its internal
registers. The Am79C974 controller will look for an ad­dress that falls within its I/O address space. The
Am79C974 controller will assert DEVSEL if it detects an
address match and the access is an I/O cycle. DEVSEL
is asserted two clock cycles after the host has asserted

FRAME. The Am79C974 controller will not assert DEV-
SEL if it detects an address match, but the PCI com-

mand is not of the type I/O read or I/O write. The

CLK

12345678

FRAME

AD

C/BE

ADDR DATA

0010 BE's

Am79C974 controller will suspend looking for I/O cycles
while being a bus master.

Slave I/O Read

The Slave I/O Read command is used by the host CPU
to read the Am79C974’s CSRs, BCRs and EEPROM lo­cations and SCSI and CCB registers. It is a single cycle,
non-burst 8-bit,16-bit or 32-bit transfer which is initiated
by the host CPU. The typical number of wait states
added to a slave I/O read access on the part of the
Am79C974 controller is 6 to 7 clock cycles. The
Am79C974 controller will not produce Slave I/O Read
commands while being a bus master.

91011

PAR

IRDY

TRDY

DEVSEL

STOP

PAR PAR

18681A-7

Figure 3. Slave I/O Read

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P R E L I M I N A R Y

Slave I/O Write

The Slave I/O Write command is used by the host CPU
to write to the Am79C974’s CSRs, BCRs and EEPROM
locations and SCSI and CCB registers. It is a single cy­cle, non-burst 8-bit, 16–bit, or 32-bit transfer which is

CLK

12345678

FRAME

AD

C/BE

PAR

IRDY

ADDR DATA

0011 BE's

PAR PAR

initiated by the host CPU. The typical number of wait
states added to a slave I/O write access on the part of
the Am79C974 controller is 6 to 7 clock cycles. The
Am79C974 controller will not produce Slave I/O write
commands while being a bus master.

91011

TRDY

DEVSEL

STOP

18681A-8

Figure 4. Slave I/O Write

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Am79C974