AMD Advanced Micro Devices AM79C975KCW, AM79C973VCW Datasheet

PRELIMINARY

Am79C973/Am79C975

PCnet™-FAST III
Single-Chip 10/100 Mbps PCI Ethernet Controller wi th Integrated PHY

DISTINCTIVE CHARACTERISTICS

■ Single-chip PCI-to-Wire Fast Ethernet controller

— 32-bit glueless PCI host interface
— Supports PCI clock frequency fr om DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization

— PCI specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor ID/

Vendor ID pr ogramming through the
EEPROM interface

— Supports both PCI 5.0 V and 3.3 V signaling

environments

— Plug and Play compatible
— Big endian and little endian byte alignments

supported

■ Fully Integrated 10/100 Mbps Physical Layer

Interface (PHY)
— Conforms to IEEE 802.3 standard for

10BASE-T, 100BASE-TX, and 100BASE-FX
interfaces

— Integrated 10BASE-T transceiver with on-

chip filtering

— Fully integrated MLT-3 encoder/decoder for

100BASE-TX

— Provides a PECL interface for 100BASE-FX

fiber implementations

— Full-duplex capability for 10BASE-T and

100BASE-TX

— IEEE 802.3u Auto-Negotiation between 10

Mbps and 100 Mbps, half- and full-duplex op­eration

■ Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards

■ Supports PC98/PC99 and Wired for

Management baseline specifications
— Full OnNow support including pattern

matching and link status wake-up events

— Implements AMD’s patented Magic Packet™

technology for remote wake-up & power-on

— Magic Packet mode and the physical address

loaded from EEPROM at power up without
requiring PCI clock

— Supports PCI Bus Power Management

Interface Specification Revision 1.1

— Supports Advanced Configuration and

Power Interface (ACPI) Specification Version

1.0

— Supports Network Device Class Power

Management Specification Version 1.0a

■ Serial Management Interface enables remote

alerting of system management events

2

— Inter-IC (I
— System Management Bus (SMBus)

compliant signaling interface and register
access protocol

— Optional interrupt pin simplifies software

interface

■ Large independent internal TX and RX FIFOs

— Programmable FIFO watermarks fo r both TX

and RX operations

— RX frame queuing for high latency PCI bus

host operation

— Programmable allocation of buffer space

between RX and TX queues

■ EEPROM interface supports jumperless design

and provides through-chip programming
— Supports extensive programmability of

device operation through EEPROM mapping

■ Supports up to 1 megabyte (Mbyte) optional

Boot PROM and Flash for diskless node
application

■ Extensive programmable internal/external

loopback capabilities

■ Extensive programmable LED status support

C) compliant electrical interface

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate thi s product. AMD reserves t he right to chan ge or discontinue work o n this proposed
product without notice.

i

Publication# 21510 Rev: E Amendment/0
Issue Date: August 2000

i

i

PRELIMINARY

■ Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame

■ Includes Programmable Inter Packet Gap (IPG)

to address less network aggressive MAC
controllers

■ Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

■ IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test

GENERAL DESCRIPTION

The Am79C973 and Am79C975 controllers are single­chip 32-bit full- duplex, 10/100-Megabit per second
(Mbps) fully integrated PCI-to -Wire Fast Ethernet sys­tem solution, designed to address high-performanc e
system application requirements. They are flexible bus
mastering device that can be used in any applic ation,
including network-ready PCs and bridge/router de­signs. The bus master archi tecture pr ovides high dat a
throughput and low CPU and system bus utilization.
The Am79C973 and Am79C975 controllers are fabri­cated with advanced low-power 3.3-V CMOS process
to provide low operating current for power sensitive ap­plications.

The third generation Am 79C973 and A m79C975 Fast
Ethernet controll ers also have several enhance ments
over their predecessors, the Am79C971 and
Am79C972 devices. Besides integrating the comp lete
10/100 Physical Layer (PHY) interface, they further re­duce system implementation cost by integrating the
SRAM buffers on chip.

The Am79C973 and Am79C975 controllers contain 12­kilobyte (Kbyte) buffers, the largest of their class in 10/
100 Mbps Ethernet controllers. The large internal buff­ers are fully programmable between t he RX and TX
queues for optimal performance.

The Am79C973 an d Am79C975 contr ollers are also
compliant with PC98/PC99 and Wired for Management
specifications. They fully suppor t Microsoft’s OnNow
and ACPI specifications, which are backward compati­ble with Magic Packet technology and compliant with
the PCI Bus Power Management Interface Specifica­tion by supporting th e four power management states
(D0, D1, D2, and D3), the optional PME
necessary configuration and data registers.

The Am79C973 and Am79C975 controllers are com­plete Ethernet nod es integrated into a s ingle VLSI de­vice. It contains a bus interface unit, a Direct Mem ory
Access (DMA) Buffer Management Unit, an ISO/IEC
8802-3 (IEEE 802.3)- compliant Media Access Control-

pin, and the

mode for board-level production connectivity
test

■ Compatible with the existing PCnet Family

driver/diagnostic software

■ Software compatible with AMD PCnet Family

and LANCE™/C-LANCE™ register and
descriptor architecture

■ Available in 160-pin PQFP and 176-pin TQFP

packages

■ Advanced +3.3 V CMOS process technology for

low power operation

ler (MAC), a large Transmit FIFO and a large Receive
FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY .

The integrated 10/100 PHY unit of the Am79C973 and
Am79C975 controll ers implement the c omplete physi­cal layer for 10BASE-T and the Physical Codin g Sub­layer (PCS), Physical Medium Attachment (PMA), and
Physical Medium Dependent (PMD) functionality for
100BASE-TX, incl uding MLT-3 encoding/ decoding. It
also supports 100BAS E-FX operation by providing a
Pseudo-ECL (PECL) interface for direct connection to
a fiber optic transceiver module. The internal 10/100
PHY implemen ts Auto-Negotiation for twisted-pa ir
(10T/100TX) operation by using a modified 10BASE-T
link integrity test pulse sequence as defined in the
IEEE 802.3u specifi catio n. The Auto-Negotiat ion fun c­tion automatically configures the controller to operate
at the maximum performance level supported across
the network link.

The Am79C975 controller also implements a Serial
Management Interface in addition to the advanced
management features offered with the Am79C973 con­troller. The Serial Management Interface is based on
the industry standard Inter-IC (I
agement Bus (SMBus) specifications and enables a
system to communicate with another network station
for remote monitoring and alerting of local system man­agement parameters and events. This simple yet pow­erful Serial Management Interface is capable of
communicating within the system and over the network
during normal operation or in low-power modes, even if
the device is not initialized or set up for transmit or re­ceive operation by the network software driver.

The 32-bit multiplexed bus interface unit provides a di­rect interface to the PCI loc al bus, simplifying the
design of an Ethernet node in a PC system. The
Am79C973 and Am79C975 controllers provide the
complete interface to an Ex pansi on ROM or F lash de­vice allowing add-on card desig ns with only a single
load per PCI bus interface pin. With their built-in s up­port for both little and big endian byte alignment, the

2

C) and System Man-

2 Am79C973/Am79C975

PRELIMINARY

controllers also address non-PC applications. The

Am79C973 and Am79C975 controllers’ advanced
CMOS design allows the bus interface to be connected
to either a +5-V or a + 3.3-V signaling environment. A
compliant IEEE 1149.1 JTAG test interface for board­level testing is also provided, as well as a NAND tree
test structure for those systems that cannot support the
JTAG interface.

The Am79C973 and Am79C975 controllers support
auto-configuration in the PCI co nfiguration spac e. Ad­ditional Am79C973 and Am 79C975 controll er co nfigu­ration parameters, including the un ique IEEE physical
address, can be rea d from an external non -volatile
memory ( EEPROM) immediately following system re­set.

In addition, the Am79C973 an d Am7 9C97 5 co ntr oller s
provide programmable on-chip LED drivers for trans­mit, receive, collision, link integrity, Magic Packet sta­tus, activity, link active, address match, full-duplex, 10
Mbps or 100 Mbps, or jabber status.

The Am79C973 and Am79C975 co ntrollers are regis­ter compatible with the LANCE™ (Am7990) Ethernet
controlle r, the C-LANCE™ (Am79C90) Ethernet con­troller, and all Ethernet controllers in the PCnet™ Fam­ily, except ILACC™ (Am79C900), including the PCnet­ISA™ (Am79C960), PCnet-ISA+™ (Am79C961),
PCnet-ISA II™ (Am79C961A), PCnet-32™
(Am79C965), PCnet-PCI™ (Am79C970),
PCnet-PCI II™ (Am79C970A), PCnet-FAST™
(Am79C971), and PCnet-FAST+™ (Am79C972). The
Buffer Management Unit supports the LANCE and
PCnet descriptor software models.

The Am79C973 and Am79C 975 c ont ro ller s ar e id eal ly
suited for LAN on the motherboard, network adapter
card, and embedded designs. It is available in a 160­pin Plastic Quad Flat Pack (PQFP) package and also in
a 176-pin Thin Quad Flat Pack (TQFP) package for
form factor sensitive designs.

Am79C973/Am79C975 3

BLOCK DIAGRAM

EBUA_EBA[7:0]
EBDA[15:8]
EBD[7:0]
EROMCS
AS_EBOE
EBWE
EBCLK

PRELIMINARY

MIIRXFRTGE
MIIRXFRTGD

SFBD
EAR

RXD[3:0],TXD[3:0]
MDIO

MDC

XTAL1 XTAL2

CLK
RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT
PERR
SERR

INTA

TCK

TMS

TDI

TDO

PCI Bus
Interface

Management

JTAG

Port

Control

Unit

Buffer

Unit

Expansion Bus

Bus
Rcv

FIFO

Bus
Xmt

FIFO

FIFO

Control

Interface

12K

SRAM

MAC

Rcv

FIFO

MAC

Xmt

FIFO

Network

Port

Manager

OnNow

Power

Management

Unit

EADI

MII

802.3
MAC
Core

Serial

Management

Interface Unit

MDC

MDIO

MII

Interface

MII

Management

Transmit

Block

Receive

Block

LED

Control

93C46

EEPROM

Interface

Clock

Reference

10/100 PHY Core

(100 BASE-TX)

(100 BASE-FX)

10 BASE-T

Link

Monitor

Negotiation

PHY Control

MLT3

PECL

Auto

TX±

RX±

SDI±

LED0
LED1
LED2
LED3

EECS
EESK
EEDI
EEDO

VAUXDET

PME

RWU

WUMI

PG

4 Am79C973/Am79C975

MCLOCK
MDATA

MIRQ

21510D-1

PRELIMINARY

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CONNECTION DIAGRAM (PQR160) - AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CONNECTION DIAGRAM (PQL176) AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CONNECTION DIAGRAM (PQR160) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CONNECTION DIAGRAM (PQL176) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975) . . . . . . . . . . . . . . . . . . . . 22

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975) . . . . . . . . . . . . . . . . . . . . . 23

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PIN DESIGNATIONS (PQR160, PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Serial Management Interface (SMI) (Am79C975 only) . . . . . . . . . . . . . . . . . . . . . . 37

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Serial Management Interface (Am79C975) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Expansion ROM Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Am79C973/Am79C975 5

PRELIMINARY

Bus Acquisition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Master Initiated Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Master Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Re-Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Descriptor Rings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Transmit Descriptor Table Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10/100 Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Transmit and Receive Message Data Encapsulation. . . . . . . . . . . . . . . . . . . . . 70

Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Media Access Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Transmit Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Receive Function Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Address Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Automatic Pad Stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Miscellaneous Loopback Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Full-Duplex Link Status LED Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10/100 PHY Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

100BASE-TX Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

100BASE-FX (Fiber Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Internal PHY Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6 Am79C973/Am79C975

PRELIMINARY

Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Link Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Far End Fault Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

MLT-3 and Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Serializer/Deserializer and Clock Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Medium Dependent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10BASE-T Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Receive Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Reverse Polarity Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Soft Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External Address Detection Interface: MII Snoop Mode . . . . . . . . . . . . . . . . . . 89

External Address Detection Interface: Receive Frame Tagging . . . . . . . . . . . . 89

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Expansion ROM - Boot Device Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Direct Flash Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

AMD Flash Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Direct SRAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Automatic EEPROM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

TAP Finite State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Supported Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

H_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

S_RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

PCI Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Am79C973/Am79C975 7

PRELIMINARY

PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PCI Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PCI Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Latency Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Header Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PCI Memory Mapped I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . 118

PCI Subsystem Vendor ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . 119

PCI Capabilities Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Interrupt Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI MIN_GNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Capability Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

PCI Power Management Capabilities Register (PMC). . . . . . . . . . . . . . . . . . . 121

PCI Power Management Control/Status Register (PMCSR) . . . . . . . . . . . . . . 121

PCI PMCSR Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . 122

PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

RAP: Register Address Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

CSR0: Am79C973/Am79C975 Controller Status and Control Register. . . . . . 123

CSR1: Initialization Block Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR2: Initialization Block Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . 126

CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

CSR5: Extended Control and Interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CSR7: Extended Control and Interrupt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CSR8: Logical Address Filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

CSR9: Logical Address Filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

CSR10: Logical Address Filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR11: Logical Address Filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR12: Physical Address Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR13: Physical Address Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR14: Physical Address Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

CSR15: Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . 140

CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . 140

CSR20: Current Transmit Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . 140

CSR21: Current Transmit Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . 140

CSR22: Next Receive Buffer Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . 140

CSR23: Next Receive Buffer Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . 140

8 Am79C973/Am79C975

PRELIMINARY

CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . 141

CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . 141

CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . 141

CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . 141

CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . 141

CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . 141

CSR30: Base Address of Transmit Ring Lower. . . . . . . . . . . . . . . . . . . . . . . . 141

CSR31: Base Address of Transmit Ring Upper. . . . . . . . . . . . . . . . . . . . . . . . 142

CSR32: Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . . . . . 142

CSR33: Next Transmit Descriptor Address Upper. . . . . . . . . . . . . . . . . . . . . . 142

CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . 142

CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . 142

CSR36: Next Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . 142

CSR37: Next Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . 142

CSR38: Next Next Transmit Descriptor Address Lower. . . . . . . . . . . . . . . . . . 143

CSR39: Next Next Transmit Descriptor Address Uper. . . . . . . . . . . . . . . . . . . 143

CSR40: Current Receive Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR41: Current Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR42: Current Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR43: Current Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR44: Next Receive Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

CSR45: Next Receive Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR46: Transmit Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR47: Transmit Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

CSR48: Receive Poll Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR49: Receive Polling Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR58: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

CSR60: Previous Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . 147

CSR61: Previous Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . 148

CSR62: Previous Transmit Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR63: Previous Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR64: Next Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR65: Next Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR66: Next Transmit Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CSR67: Next Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR76: Receive Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CSR80: DMA Transfer Counter and FIFO Threshold Control . . . . . . . . . . . . . 150

CSR82: Transmit Descriptor Address Pointer Lower. . . . . . . . . . . . . . . . . . . . 152

CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR88: Chip ID Register Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

CSR89: Chip ID Register Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR92: Ring Length Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Am79C973/Am79C975 9

PRELIMINARY

CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

CSR116: OnNow Power Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

CSR122: Advanced Feature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

CSR124: Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

CSR125: MAC Enhanced Configuration Control . . . . . . . . . . . . . . . . . . . . . . . 156

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BCR0: Master Mode Read Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

BCR1: Master Mode Write Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

BCR2: Miscellaneous Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

BCR4: LED 0 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

BCR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

BCR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

BCR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

BCR9: Full-Duplex Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

BCR16: I/O Base Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR17: I/O Base Address Upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR18: Burst and Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

BCR19: EEPROM Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

BCR20: Software Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

BCR22: PCI Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

BCR23: PCI Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR24: PCI Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR25: SRAM Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

BCR26: SRAM Boundary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

BCR27: SRAM Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

BCR28: Expansion Bus Port Address Lower

(Used for Flash/EPROM and SRAM Accesses) . . . . . . . . . . . . . . . . . . . . . 183

BCR29: Expansion Port Address Upper

(Used for Flash/EPROM Accesses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

BCR30: Expansion Bus Data Port Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 184

BCR31: Software Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

BCR32: PHY Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

BCR33: PHY Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR34: PHY Management Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR35: PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

BCR36: PCI Power Management Capabilities (PMC) Alias Register . . . . . . . 188

BCR37: PCI DATA Register Zero (DATA0) Alias Register . . . . . . . . . . . . . . . 188

BCR38: PCI DATA Register One (DATA1) Alias Register. . . . . . . . . . . . . . . . 188

BCR39: PCI DATA Register Two (DATA2) Alias Register. . . . . . . . . . . . . . . . 189

BCR40: PCI DATA Register Three (DATA3) Alias Register . . . . . . . . . . . . . . 189

BCR41: PCI DATA Register Four (DATA4) Alias Register . . . . . . . . . . . . . . . 189

BCR42: PCI DATA Register Five (DATA5) Alias Register. . . . . . . . . . . . . . . . 190

BCR43: PCI DATA Register Six (DATA6) Alias Register. . . . . . . . . . . . . . . . . 190

BCR44: PCI DATA Register Seven (DATA7) Alias Register . . . . . . . . . . . . . . 191

BCR45: OnNow Pattern Matching Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 191

BCR46: OnNow Pattern Matching Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 191

BCR47: OnNow Pattern Matching Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . 192

BCR48-BCR55: Reserved Locations for Am79C975. . . . . . . . . . . . . . . . . . . . 192

PHY Management Registers (ANRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

10 Am79C973/Am79C975

PRELIMINARY

ANR1: Status Register (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

ANR2 and ANR3: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . 196

ANR4: Auto-Negotiation Advertisement Register (Register 4). . . . . . . . . . . . . 197

ANR5: Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . 198

ANR6: Auto-Negotiation Expansion Register (Register 6). . . . . . . . . . . . . . . . 199

ANR7: Auto-Negotiation Next Page Register (Register 7). . . . . . . . . . . . . . . . 199

Reserved Registers (Registers 8-15, 20-23, and 25-31) . . . . . . . . . . . . . . . . . 199

ANR16: INTERRUPT Status and Enable Register (Register 16). . . . . . . . . . . 200

ANR17: PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . 200

ANR18: Descrambler Resynchronization Timer Register (Register 18) . . . . . 202

ANR19: PHY Management Extension Register (Register 19) . . . . . . . . . . . . . 202

ANR24: Summary Status Register (Register 24). . . . . . . . . . . . . . . . . . . . . . . 202

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Receive Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PROGRAMMABLE REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Am79C973/Am79C975 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . 220

Am79C973/Am79C975 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 222

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . 227

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS

DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

EXTERNAL CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . 236

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE . . . . . . . . . . . . . . . . 240

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

PQR160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

APPENDIX A: PCnet™-FAST III Recommended Magnetics . . . . . . . . . . . . . . . . 244

APPENDIX B: SERIAL MANAGEMENT INTERFACE UNIT

(AM79C975 ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Am79C975 PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Am79C975 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

User Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Am79C973/Am79C975 11

PRELIMINARY

Node ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Device Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

APPENDIX C: MEDIA INDEPENDENT INTERFACE (MII) . . . . . . . . . . . . . . . . . . . . 268

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

MII management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . 276

Auto-Negotiation Link Partner Ability Register (Register 5) . . . . . . . . . . . . . . . . . 277

Switching Characteristics: Media Independent Interface . . . . . . . . . . . . . . . . . . . 278

Switching Waveforms: Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . 279

Switching Waveforms: External Address Detection Interface . . . . . . . . . . . . . . . . 281

Switching Waveforms: Receive Frame Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

APPENDIX D: ALTERNATIVE METHOD FOR INITIALIZATION . . . . . . . . . . . . . . . 283

APPENDIX E: LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . 284

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Outline of LAPP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . 289

Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . 291

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

12 Am79C973/Am79C975

PRELIMINARY

LIST OF FIGURES

Figure 1. Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 2. Slave Configuration Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 3. Slave Read Using I/O Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 4. Slave Write Using Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 5. Expansion ROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6. Disconnect Of Slave Cycle When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 7. Disconnect Of Slave Burst Transfer - No Host Wait States . . . . . . . . . . . . . 44

Figure 8. Disconnect Of Slave Burst Transfer - Host Inserts Wait States . . . . . . . . . . 45

Figure 9. Address Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 10. Slave Cycle Data Parity Error Response 46

Figure 11. Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12. Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) . . . . . . . . . . . . . . . . . . 48

Figure 14. Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. Burst Write Transfer (EXTREQ = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17. Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18. Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20. Preemption During Burst Transaction 54

Figure 21. Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 22. Master Cycle Data Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 23. Initialization Block Read In Non-Burst Mode 57
Figure 24. Initialization Block Read In Burst Mode 57

Figure 25. Descriptor Ring Read In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 26. Descriptor Ring Read In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 27. Descriptor Ring Write In Non-Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 28. Descriptor Ring Write In Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29. FIFO Burst Write At Start Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. FIFO Burst Write At End Of Unaligned Buffer . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 31. 16-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 32. 32-Bit Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order . . . . . . . . . . . . . . 77

Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY . . . . . . 81

Figure 36. MLT-3 Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 37. TX± and RX± Termination 86

Figure 38. 10BASE-T Transmit and Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 39. Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 40. Flash Configuration for the Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 41. EPROM Only Configuration for the Expansion Bus (64K EPROM) . . . . . . . 92

Figure 42. EPROM Only Configuration for the Expansion Bus (64K EPROM) 93

Figure 43. Expansion ROM Bus Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 44. Flash Read from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 45. Flash Write from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 46. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 47. Block Diagram Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . 97

Figure 48. LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Am79C973/Am79C975 13

PRELIMINARY

Figure 49. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 50. Pattern Match RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 51. Address Match Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 52. External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 53. PMD Interface Timing (PECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 54. PMD Interface Timing (MLT-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Figure 55. 10 Mbps Transmit (TX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 56. 10 Mbps Receive (RX±) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 57. Normal and Tri-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 58. CLK Waveform for 5 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 59. CLK Waveform for 3.3 V Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 60. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 61. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

Figure 62. Output Tri-state Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 63. EEPROM Read Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 37

Figure 64. Automatic PREAD EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 65. JTAG (IEEE 1149.1) TCK Waveform for 5 V Signaling . . . . . . . . . . . . . . . 238

Figure 66. JTAG (IEEE 1149.1) Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 67. EBCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 68. Expansion Bus Read Timing 240

Figure 69. Expansion Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 70. Standard Data Transfer on the Serial Management Interface . . . . . . . . . . 247

Figure 71. Data Transfer with Change in Direction (with wait state) . . . . . . . . . . . . . . 247

Figure 72. Write Byte Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 73. Read Byte Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 48

Figure 74. Block Write Command 249
Figure 75. Block Read Command 250

Figure 76. System Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 77. Media Independent Interface 268

Figure 78. Frame Format at the MII Interface Connection . . . . . . . . . . . . . . . . . . . . . 270

Figure 79. MII Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Figure 80. Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 81. Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 82. MDC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Figure 83. Management Data Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 84. Management Data Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . 280

Figure 85. Reject Timing - External PHY MII @ 25 MHz . . . . . . . . . . . . . . . . . . . . . . . 281

Figure 86. Reject Timing - External PHY MII @ 2.5 MHz 281

Figure 87. Receive Frame Tag Timing with Media Independent Interface . . . . . . . . . 282

Figure 88. LAPP Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 89. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 90. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . .292

Figure 91. LAPP 3 Buffer Grouping for Two-interrupt Method . . . . . . . . . . . . . . . . . . 293

14 Am79C973/Am79C975

PRELIMINARY

LIST OF TABLES

Table 1. Interrupt Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 2. SDI± Settings for Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 3. Slave Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 4. Master Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 5. Descriptor Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 6. Descriptor Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 7. Receive Address Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 8. Encoder Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 9. Decoder Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 10. Auto-Negotiation Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 11. EADI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 12. Am29Fxxx Flash Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 13. Am79C973 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 14. Am79C975 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 15. LED Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 16. IEEE 1149.1 Supported Instruction Summary . . . . . . . . . . . . . . . . . . . . . . 106

Table 17. BSR Mode Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 18. Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 19. PCI Configuration Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 20. I/O Map In Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 21. Legal I/O Accesses in Word I/O Mode (DWIO = 0) . . . . . . . . . . . . . . . . . . .111

Table 22. I/O Map In DWord I/O Mode (DWIO =1). . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 23. Legal I/O Accesses in Double Word I/O Mode (DWIO =1). . . . . . . . . . . . . 111

Table 24. Loopback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 25. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 26. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 27. Transmit Start Point Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 28. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 29. BCR Registers (Am79C973) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 30. BCR Registers (Am79C975) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 31. ROMTNG Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 32. Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 33. Software Styles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 34. SRAM_BND Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 35. EBCS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 36. CLK_FAC Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 37. FMDC Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 38. APDW Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 39. Am79C973/Am79C975 Internal PHY Management Register Set . . . . . . . 193

Table 40. ANR0: PHY Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 41. ANR1: PHY Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 42. ANR2: PHY Identifier (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 43. ANR3: PHY Identifier (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 44. ANR4: Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . 197

Table 45. ANR5: Auto-Negotiation Link Partner Ability Register (Register 5)

- Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 46. ANR5: Auto-Negotiation Link Partner Ability Register (Register 5)

- Next Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Am79C973/Am79C975 15

PRELIMINARY

Table 47. ANR6: Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . 199

Table 48. ANR7: Auto-Negotiation Next Page Register (Register 7) . . . . . . . . . . . . . 199

Table 49. ANR16: INTERRUPT Status and Enable Register (Register 16) . . . . . . . . 200

Table 50. ANR17: PHY Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . 201

Table 51. ANR18: Descrambler Resynchronization Timer (Register 18) . . . . . . . . . . 202

Table 52. ANR19: PHY Management Extension Register (Register 19) . . . . . . . . . . . 202

Table 53. ANR24: Summary Status Register (Register 24) . . . . . . . . . . . . . . . . . . . . 203

Table 54. Initialization Block (SSIZE32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 55. Initialization Block (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 56. R/TLEN Decoding (SSIZE32 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 57. R/TLEN Decoding (SSIZE32 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 58. Receive Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 59. Receive Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 60. Receive Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 61. Transmit Descriptor (SWSTYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 62. Transmit Descriptor (SWSTYLE = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 63. Transmit Descriptor (SWSTYLE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 64. Clock (XTAL1, XCLK = 1) Switching Characteristics . . . . . . . . . . . . . . . . . 231

Table 65. Crystal (XTAL1, XTAL2, XCLK = 0) Requirements . . . . . . . . . . . . . . . . . . 231

Table 66. Crystal (XTAL1, XTAL2, XCLK = 0) Requirements . . . . . . . . . . . . . . . . . . 231

Table 67. Recommended Magnetics Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 68. Auto-Negotiation Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 69. EADI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Table 70. MII Management Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 71. MII Management Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . .274

Table 72. MII Management Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . 275

Table 73. Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . 276

Table 74. Technology Ability Field Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Table 75. Auto-Negotiation Link Partner Ability Register (Register 5)

- Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Table 76. Registers for Alternative Initialization Method (Note 1) . . . . . . . . . . . . . . . . 283

16 Am79C973/Am79C975

PRELIMINARY

RELATED AMD PRODUCTS

Part No. Description
Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses
Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus
Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

Manchester Encoder/Decoder

Am7992B Serial Interface Adapter (SIA)

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)
Am79C988A Quad Integrated Ether net Transceiver (QuIET™)
Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C981 Integrated Multiport Repeater Plus (IMR+)
Am79C982 Basic Integrated Multiport Repeater (bIMR)
Am79C983 Integrated Multiport Repeater 2 (IMR2™)
Am79C984A Enhanced Integrated Multiport Repeater (eIMR™)
Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)

Am79C973/Am79C975 17

PRELIMINARY

CONNECTION DIAGRAM (PQR160) - Am79C973

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

IDSEL

AD23
VSSB
AD22

VDD_PCI

AD21
AD20

VDD
AD19
AD18
VSSB
AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR
SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS
AD14
AD13
VSSB
AD12
AD11

VDD_PCI

AD10

AD9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Am79C973

PQR160

414243444546474849505152535455565758596061626364656667686970717273747576777879

132

PME

131

VSS

130

EAR

129

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

128

127

126

125

VDDB

XCLK/XTAL

VSSB

124

123

122

EED1/LED0

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

80

EEDO/LED3/MIIRXFRTGD
DVSSP
DVDDP
RX­DVDDRX
RX+
SDI­DVSSX
SDI+
TX­DVDDTX
TX+
DVDDD
IREF
DVSSD
DVDDA
DVDDCO
XTAL1
XTAL2
VDDB
NC
VSSB
NC
VDD
NC
VSSB
VAUXDET
EBD0/RXD0
EBD1/RXD1
EBD2/RXD2
VSS
EBD3/RXD3
VDDB
EBD4/RX_DV
EBD5/RX_CLK
EBD6/RX_ER
VSSB
EBD7/TX_CLK
EBDA15/COL
EBDA14/CRS

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

VSSB

C/BE0

VDD_PCI

VDD

VSSB

VDD_PCI

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

Pin 1 is marked for orientation.

18 Am79C973/Am79C975

VSS

VSSB

EBDA8/TXD0

EBDA9/TXD1

EBUA_EBA5/MDC

EBUA_EBA7/TX_ER

EBUA_EBA6/PHY_RST

VDDB

EBDA10/TXD2

EBDA11/TXD3

EBDA13/MDIO

EBDA12/TX_EN

21510D-2

PRELIMINARY

CONNECTION DIAGRAM (PQL176) Am79C973

NCNCC/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

NC
NC

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21
AD20

VDD
AD19
AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB
TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR
SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS
AD14
AD13

VSSB

AD12
AD11

VDD_PCI

AD10

AD9

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

Am79C973

PQL176

146

WUMI

PME

145

VSS

144

EAR

143

EECS

142

VSSB

141

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0NCNC

140

139

138

137

136

135

134

133

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

88

NC
NC
EEDO/LED3/MIIRXFRTGD
DVSSP
DVDDP
RX­DVDDRX
RX+
SDI­DVSSX
SDI+
TX­DVDDTX
TX+
DVDDD
IREF
DVSSD
DVDDA
DVDDCO
XTAL1
XTAL2
VDDB
NC
VSSB
NC
VDD
NC
VSSB
VAUXDET
EBD0/RXD0
EBD1/RXD1
EBD2/RXD2

VSS
99
98
97
96
95
94
93
92
91
90
89

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

NC

NC

NC

NC

AD8

AD7

VSSB

C/BE0

Pin 1 is marked for orientation.

AD6

AD5

VDD_PCI

VDD

AD4

AD3

AD2

VSSB

NC

AD1

AD0

VDD_PCI

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA7/TX_ER

EBUA_EBA6/PHY_RST

VSS

VSSB

EBDA8/TXD0

VDDB

EBDA9/TXD1

EBDA10/TXD2

NC

EBDA11/TXD3

EBDA13/MDIO

EBDA12/TX_EN

Am79C973/Am79C975 19

21510D-3

PRELIMINARY

CONNECTION DIAGRAM (PQR160) - Am79C975

C/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21
AD20

VDD
AD19
AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB
TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR
SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS
AD14
AD13

VSSB

AD12
AD11

VDD_PCI

AD10

AD9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Am79C975

PQR160

414243444546474849505152535455565758596061626364656667686970717273747576777879

131

VSS

130

EAR

129

EECS

VSSB

EESK/LED1/SFBD

LED2/MIIRXFRTGE

128

127

126

125

VDDB

XCLK/XTAL

VSSB

124

123

122

EED1/LED0

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

80

EEDO/LED3/MIIRXFRTGD
DVSSP
DVDDP
RX­DVDDRX
RX+
SDI­DVSSX
SDI+
TX­DVDDTX
TX+
DVDDD
IREF
DVSSD
DVDDA
DVDDCO
XTAL1
XTAL2
VDDB
MCLOCK
VSSB
MDATA
VDD
MIRQ
VSSB
VAUXDET
EBD0/RXD0
EBD1/RXD1
EBD2/RXD2
VSS
EBD3/RXD3
VDDB
EBD4/RX_DV
EBD5/RX_CLK
EBD6/RX_ER
VSSB
EBD7/TX_CLK
EBDA15/COL
EBDA14/CRS

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

VSSB

C/BE0

VDD_PCI

VDD

VSSB

VDD_PCI

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

Pin 1 is marked for orientation.

20 Am79C973/Am79C975

VSS

VSSB

VDDB

EBDA8/TXD0

EBDA9/TXD1

EBDA10/TXD2

EBUA_EBA7/TX_ER

EBUA_EBA6/PHY_RST

EBDA11/TXD3

EBDA13/MDIO

EBDA12/TX_EN

21510D-4

PRELIMINARY

CONNECTION DIAGRAM (PQL176) - Am79C975

NCNCC/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

REQ

GNT

CLK

RST

INTAPGVDD

TDI

VSSB

TDO

VDDB

TMS

TCK

RWU

WUMI

PME

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

NC
NC

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21
AD20

VDD
AD19
AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB
TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR
SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS
AD14
AD13

VSSB

AD12
AD11

VDD_PCI

AD10

AD9

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

Am79C975

PQL176

145

VSS

144

EAR

143

EECS

142

VSSB

141

EESK/LED1/SFBD

LED2/MIIRXFRTGE

VDDB

XCLK/XTAL

VSSB

EED1/LED0NCNC

140

139

138

137

136

135

134

133

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

NC
NC
EEDO/LED3/MIIRXFRTGD
DVSSP
DVDDP
RX­DVDDRX
RX+
SDI­DVSSX
SDI+
TX­DVDDTX
TX+
DVDDD
IREF
DVSSD
DVDDA
DVDDCO
XTAL1
XTAL2
VDDB
MCLOCK
VSSB
MDATA
VDD
MIRQ
VSSB
VAUXDET
EBD0/RXD0
EBD1/RXD1
EBD2/RXD2

VSS
99
98
97
96
95
94
93
92
91
90
89

88

EBD3/RXD3

VDDB

EBD4/RX_DV

EBD5/RX_CLK

EBD6/RX_ER

VSSB

EBD7/TX_CLK

EBDA15/COL

EBDA14/CRS

NC

NC

NC

NC

AD8

AD7

VSSB

C/BE0

Pin 1 is marked for orientation.

AD6

AD5

VDD_PCI

VDD

AD4

AD3

AD2

VSSB

NC

AD1

AD0

VDD_PCI

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5/MDC

EBUA_EBA7/TX_ER

EBUA_EBA6/PHY_RST

VSS

VSSB

EBDA8/TXD0

VDDB

EBDA9/TXD1

EBDA10/TXD2

NC

EBDA11/TXD3

EBDA13/MDIO

EBDA12/TX_EN

Am79C973/Am79C975 21

21510D-5

PRELIMINARY

PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975)

Listed By Pin Number

Pin

Pin

No.

Name

1 IDSEL 41 AD8 81 EBDA14/CRS 121 EEDI/LED0
2 AD23 42 C/BE0 82 EBDA15/COL 122 VSSB
3 VSSB 43 VSSB 83 EBD7/TX_CLK 123 XCLK/XTAL
4 AD22 44 AD7 84 VSSB 124 VDDB
5 VDD_PCI 45 VDD_PCI 85 EBD6/RX_ER 125 LED2
6 AD21 46 AD6 86 EBD5/RX_CLK 126 EESK/LED1
7 AD20 47 AD5 87 EBD4/RX_DV 127 VSSB
8 VDD 48 VDD 88 VDDB 128 EECS
9 AD19 49 AD4 89 EBD3/RXD3 129 EAR
10 AD18 50 AD3 90 VSS 130 VSS
11 VSSB 51 VSSB 91 EBD2/RXD2 131 PME
12 AD17 52 AD2 92 EBD1/RXD1 132 WUMI
13 VDD_PCI 53 VDD_PCI 93 EBD0/RXD0 133 RWU
14 AD16 54 AD1 94 VAUXDET 134 TCK
15 C/BE2 55 AD0 95 VSSB 135 TMS
16 VSS 56 VSS 96 MIRQ
17 FRAME
18 IRDY
19 VSSB 59 AS_EBOE
20 TRDY
21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG
22 DEVSEL 62 VSSB 102 XTAL2 142 INTA
23 STOP 63 EBUA_EBA1 103 XTAL1 143 RST
24 VDD 64 VDD 104 DVDDCO 144 CLK
25 PERR
26 SERR 66 EBUA_EBA2 106 DVSSD 146 REQ
27 VSSB 67 EBUA_EBA3 107 IREF 147 VDD_PCI
28 PAR 68 EBUA_EBA4 108 DVDDD 148 AD31
29 VDD_PCI 69 EBUA_EBA5/MDC 109 TX+ 149 VSSB

30 C/BE1
31 AD15 71 EBUA_EBA7/TX_ER 111 TX- 151 AD30

32 VSS 72 VSS 112 SDI+ 152 AD29
33 AD14 73 EBDA8/TXD0 113 DVSSX 153 AD28
34 AD13 74 VSSB 114 SDI- 154 AD27
35 VSSB 75 EBDA9/TXD1 115 RX+ 155 VDD_PCI
36 AD12 76 EBDA10/TXD2 116 DVDDRX 156 AD26
37 AD11 77 VDDB 117 RX- 157 VSSB
38 VDD_PCI 78 EBDA11/TXD3 118 DVDDP 158 AD25
39 AD10 79 EBDA12/TX_EN 119 DVSSP 159 AD24

40 AD9 80 EBDA13/MDIO 120

Note: For the Am79C973 controller, pins 96, 98, and 100 are no connects (NC).

Pin
No.

57 EROMCS 97 VDD 137 TDO
58 EBWE 98 MDATA (see Note) 138 VSSB

60 EBCLK 100 MCLOCK (see Note) 140 VDD

65 VDDB 105 DVDDA 145 GNT

70

Pin
Name

EBUA_EBA6/
PHY_RST

Pin
No.

99 VSSB 139 TDI

110 DVDDTX 150 VSS

Pin
Name Pin No.

(see Note) 136 VDDB

EEDO/LED3
MIIRXFRTGD

/

160 C/BE3

Pin
Name

/MIIRXFRTGE

/SFDB

22 Am79C973/Am79C975

PRELIMINARY

PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975)

Listed By Pin Number

Pin

Pin

No.

Name

1NC 45NC 89NC 133 NC
2NC 46NC 90NC 134 NC
3 IDSEL 47 AD8 91 EBDA14/CRS 135 EEDI/LED0
4 AD23 48 C/BE0 92 EBDA15/COL 136 VSSB
5 VSSB 49 VSSB 93 EBD7/TX_CLK 137 XCLK/XTAL
6 AD22 50 AD7 94 VSSB 138 VDDB
7 VDD_PCI 51 VDD_PCI 95 EBD6/RX_ER 139 LED2
8 AD21 52 AD6 96 EBD5/RX_CLK 140 EESK/LED1
9 AD20 53 AD5 97 EBD4/RX_DV 141 VSSB
10 VDD 54 VDD 98 VDDB 142 EECS
11 AD19 55 AD4 99 EBD3/RXD3 143 EAR
12 AD18 56 AD3 100 VSS 144 VSS
13 VSSB 57 VSSB 101 EBD2/RXD2 145 PME
14 AD17 58 AD2 102 EBD1/RXD1 146 WUMI
15 VDD_PCI 59 VDD_PCI 103 EBD0/RXD0 147 RWU
16 AD16 60 AD1 104 VAUXDET 148 TCK
17 C/BE2 61 AD0 105 VSSB 149 TMS
18 VSS 62 VSS 106 MIRQ
19 FRAME
20 IRDY
21 VSSB 65 AS_EBOE
22 TRDY
23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG
24 DEVSEL 68 VSSB 112 XTAL2 156 INTA
25 STOP 69 EBUA_EBA1 113 XTAL1 157 RST
26 VDD 70 VDD 114 DVDDCO 158 CLK
27 PERR
28 SERR 72 EBUA_EBA2 116 DVSSD 160 REQ
29 VSSB 73 EBUA_EBA3 117 IREF 161 VDD_PCI
30 PAR 74 EBUA_EBA4 118 DVDDD 162 AD31
31 VDD_PCI 75 EBUA_EBA5/MDC 119 TX+ 163 VSSB

32 C/BE1
33 AD15 77 EBUA_EBA7/TX_ER 121 TX- 165 AD30

34 VSS 78 VSS 122 SDI+ 166 AD29
35 AD14 79 EBDA8/TXD0 123 DVSSX 167 AD28
36 AD13 80 VSSB 124 SDI- 168 AD27
37 VSSB 81 EBDA9/TXD1 125 RX+ 169 VDD_PCI
38 AD12 82 EBDA10/TXD2 126 DVDDRX 170 AD26
39 AD11 83 VDDB 127 RX- 171 VSSB
40 VDD_PCI 84 EBDA11/TXD3 128 DVDDP 172 AD25
41 AD10 85 EBDA12/TX_EN 129 DVSSP 173 AD24

42 AD9 86 EBDA13/MDIO 130
43 NC 87 NC 131 NC 175 NC

44 NC 88 NC 132 NC 176 NC

Note: For the Am79C973 controller, pins 106, 108, and 110 are no connects (NC).

Pin
No.

63 EROMCS 107 VDD 151 TDO
64 EBWE 108 MDATA (see Note) 152 VSSB

66 EBCLK 110 MCLOCK (see Note) 154 VDD

71 VDDB 115 DVDDA 159 GNT

76

Pin
Name

EBUA_EBA6/
PHY_RST

Pin
No.

109 VSSB 153 TDI

120 DVDDTX 164 VSS

Pin
Name Pin No.

(see Note) 150 VDDB

EEDO/LED3
MIIRXFRTGD

/

174 C/BE3

Pin
Name

/MIIRXFRTGE

/SFDB

Am79C973/Am79C975 23

PRELIMINARY

PIN DESIGNATIONS (PQR160, PQL176)

Listed By Group

Pin Name Pin Function Type
PCI Bus Interface

AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I NA 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Fram e IO STS6 1
GNT Bus Grant I NA 1
IDSEL Initialization Device Select I NA 1
INTA Interrupt O OD6 1
IRDY Initiator Ready IO STS6 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request O TS3 1
RST Reset I NA 1
SERR System Error O OD6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1

Board Interface

LED0 LED0 O LED 1
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
XCLK External Clock Source Select I NA 1
XTAL Crystal Select I NA 1
XTAL1 Crystal Input -25 MHz Clock Reference I NA 1
XTAL2 Crystal Output O XTAL 1

EEPROM Interface

EECS Serial EEPROM Chip Select O O6 1
EEDI Serial EEPROM Data In O LED 1
EEDO Serial EEPROM Data Out I NA 1
EESK Serial EEPROM Clock IO LED 1

Expansion ROM Interface

AS_EBOE Address Strobe/Expansion Bus Output Enable O O6 1
EBCLK Expansion Bus Clock I NA 1
EBD[7:0] Expansion Bus Data [7:0] IO TS6 8
EBDA[15:8] Expansion Bus Data/Address [15:8] IO TS6 8

EBUA_EBA[7:0]
EBWE Expansion Bus Write Enable O O6 1

EROMCS Expansion Bus ROM Chip Select O O6 1

1. Not including test featu res

Expansion Bus Upper Addres s /Expansion Bus Addres s
[7:0]

1

O O6 8

Driver No. of Pins

24 Am79C973/Am79C975

PRELIMINARY

PIN DESIGNATIONS

Listed By Group

Pin Name Pin Function Type
Physical Layer Interface (PHY)

IREF Internal Current Reference I NA 1
RX± Serial R eceive Data I NA 2
TX± Serial Transmit Data O NA 2
SDI± Signal Detect Input I NA 2

Powe r Mana gemen t Interface

RWU Remote Wake Up O O6 1
PME Power Management Event O OD6 1
WUMI Wake-Up Mode Indication O OD6 1
PG Power Good I NA 1
VAUXDET Auxiliar y Power Detect I NA 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I NA 1
TDI Test Data In I NA 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I NA 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I NA 1
SFBD Start Frame Byte Delimiter O LED 1
MIIRXFRTGD MII Receive Frame Tag Data I NA 1
MIIRXFRTGE MII Receive Frame Tag Enable I NA 1

Media Independent Interface (MII)

COL Collision I NA 1
CRS Carrier Sense I NA 1
MDC Management Data Clock O OMII2 1
MDIO Management Data I/O I/O TSMII 1
RX_CLK Receive Clock I NA 1
RXD[3:0] Receive Data I NA 4
RX_DV Receive Data Valid I NA 1
RX_ER Receive Error I NA 1
TX_CLK Transmit Clock I NA 1
TXD[3:0] Transmit Data O OMII1 4
TX_EN Transmit Data Enable O OMII1 1
TX_ER Transmit Error O OMII1 1

Serial Management Interface (SMI) - Am79C975 only

MCLOCK SMI Clock I/O OD6 1
MDATA SMI Data I/O OD6 1
MIRQ SMI Interrupt O OD6 1

Note:

1. Not including test features.

1

Driver No. of Pins

Am79C973/Am79C975 25

PRELIMINARY

PIN DESIGNATIONS

Listed by Group (Concluded)

Pin Name Pin Function Type
Power Supplies (MAC, PCI, Buffer, ROM)

VDD Digital Power P NA 6
VSS Digital Ground P NA 7
VDDB I/O Buffer Power P NA 6
VSSB I/O Buffer Ground P NA 17
VDD_PCI PCI I/O Buffer Power P NA 9

Power Suppli es (PHY)

DVDDA Analog PLL Power P NA 1
DVDDD, DVDDP Physical Data Transceiver (PDX) Power, IREF P NA 2
DVSSD, DVSSP Physical Data Transceiver (PDX) Ground P NA 2
DVDDTX, DVDDRX PHY I/O Buffer Power P NA 2
DVSSX PHY Ground P NA 1
DVDDCO Crystal Oscillator Power P NA 1

2

1

Driver No. of Pins

Notes:

1. Not including test features.

2. PHY power and ground pins require careful decoupling to ensure proper device performance.

26 Am79C973/Am79C975

PIN DESIGNATIONS

PRELIMINARY

Listed By Driver Type

A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.

The following table describes th e various type s of o ut­put drivers used in the Am79C973/Am79C975 control­ler. All I

and IOH v alues shown in the table apply to 3.3

OL

V signaling.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50
OMII1 Totem Pole 4 -4 50
OMII2 Totem Pole 4 -4 390
O6 Totem Pole 6 -0.4 50
OD6 Open Drain 6 NA 50
STS6 Sustained Tri-State 6 -2 50
TS3 Tri-State 3 -2 50
TS6 Tri-State 6 -2 50
TSMII Tri-State 4 -4 470

TX is a differential output driver. Its characteristics and
those of X TAL2 output are des cribed in the DC Charac-
teristics sec ti on.

Am79C973/Am79C975 27

PRELIMINARY

ORDE RING INFORMATION

Standard Products

AMD standard produc ts are av ailable in sev eral pac kages and operating r anges. T he order number (Valid Combination) is formed
by a combination of the elements below.

AM79C973
AM79C975

K\V

C

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0° C to +70° C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL176)

Valid Combinations

AM79C973,
AM79C975

KC\W,
VC\W

SPEED OPTION

Not applicable

DEVICE NUMBER/DESCRIPTION

Am79C973/Am79C975
Single-Chip 10/100 Mbps PCI Ethernet Cont roll er
with Integrated PHY

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

28 Am79C973/Am79C975

PRELIMINARY

PIN DESCRIPTIONS

PCI Interface

AD [31:0]

Add r e s s a n d Da ta Inpu t/Ou t p u t

Address and data are multiplexed on the same b us inter­face pins. During the first clock of a transaction, AD[31:0]
contain a physical addres s ( 32 bi ts) . During the subs e­quent clocks, AD[31:0] contain data. Byte ordering is little
endian by default. AD[7:0] are defined as the least signifi­cant byte (LSB) and AD[31:24] are defined as the most
significant byte (MSB). For FIFO data transfers, the
Am 79C973/Am 79C975 controller can be programm ed for
big e ndian byte or dering. See CSR3, bit 2 ( BSWP) for
more details.

Duri ng the address phase of the t r ansac t ion, when the
Am79C973/Am79C975 contr ol l er i s a bus master,
AD[31:2] wi ll address the active Double Word (DWor d).
The Am79C973/Am79C975 control l er al ways drives
AD[1:0] to ’00’ during the address phase indicating linear
burst order. When the Am 79C973/Am79C 975 controller is
not a bus master, t he AD[31: 0] l ines ar e cont inuously
monitor ed to determine if an addr ess match exi s t s f or
slave transfers.

Duri ng the data phase of t he trans action, AD[ 31:0] are
driven by the Am79C973/Am 79C975 controller when per­forming bus master write and slave read operations. Data
on AD[31:0] is latched by the Am79C 973/Am79C 975 con­tr oller when per for ming bus maste r read and slave writ e
operations.

When RST
testing.

C/BE[3:0]

Bus Co mman d a n d B y te En a ble s
Input/Output

Bus command and byte enables are multiplexed on the
same b us interface pins. During the address phase of the
tr ansact ion, C/ BE
the data phase, C/BE
byte enables define which physical byte lanes carry mean­ingful data. C/BE
applies to byte 3 (AD[31:24]). The function of the byte en­ables is independent of t he by te or de ring mode (BSWP,
CSR3, bit 2).

When RST
tes tin g .

CLK

Cloc k Inp ut

This clock is used to dri ve the system bus int erfac e and
the internal buffer management un it. All bus signals are
sampled on the rising edge of CLK and all parameters are
defi ne d wit h r espec t t o t hi s e dge. The Am79C973/

is ac tive, AD[ 31:0] ar e inputs f or NAND tree

[3: 0] define t he bus command. During

[3:0] are used as byte enables. The

0 applies to byte 0 (AD[7:0]) and C/BE3

is active, C/BE [3:0] are inputs for NAND tree

Am 79C975 controller normally operates over a frequency
range of 10 to 33 MHz on the PCI bus due to networking
demands. See the Frequency Demands for Network Op-
eration sect ion for det ail s. The Am79C973/Am79C975
contr oller wil l support a cl ock fr equency of 0 MHz after
certain precautions are taken to ensure data integrity. This
clock or a derivation is not used to drive any network func­tions.

When RST
ing .

is active, CLK is an input for NAND tree test-

DEVSEL

Device Select Input/
Output

The Am79C973/Am79C975 contr ol ler dr i ves DEVSEL
when it detects a transaction that selects the device as a
target. The device samples DEVSEL
claims a transaction that the Am79C 973/Am79C 975 con­troller has initiated.

When RST
tes tin g .

is activ e , DEVSEL is an input for NAND tree

to de tect if a target

FRAM E

Cy cle F r a me In p u t/Ou t p u t

FRAME is driven by the Am 79C973/Am79C 975 controller
when it is the bus master to indicate the beginning and du­rat ion of a t ransaction. FRAME
bus tr ansac tion i s beginning. FRAME
data transfers continue. FRAME
final dat a phase of a transac tion. When the Am79C973/
Am 79C975 controller is in slave m ode, it samples FRAME
to determine the address phase of a transaction.

Wh en RS T
tes tin g .

is active, FRAME is an inpu t fo r NAND tree

is as se rted t o indicate a

is as serted while

is deasserted before the

GNT

Bus Gra n t Inp u t

This signal indicates that the access to the bus has been
granted to the Am79C 973/Am79C 975 controller.

The Am 79C973/Am 79C975 controller supports bus park­ing. When the PCI bus is idle and the system arbiter as­serts GNT
Am79C975 contr o ller, the devi c e will drive the AD[31:0],
C/BE

Wh en RST
ing .

without an active REQ from the Am79C973/

[3:0] and PA R lines.

is a ctiv e, GNT is an input for NAND tree test-

IDSEL

Initia liz a tio n D ev ic e Se le c t Inp u t

This signal is used as a chip select f or t he Am79C973/
Am 79C 975 controller during configuration read and write
transactions.

Wh en R ST
testing.

is acti ve, IDSEL is an input f or NAND tree

Am79C973/Am79C975 29

PRELIMINARY

INTA

Interrupt Request Output

An attention signal which indicates that one or more of
the following status flags is set: EXDINT, IDON, MERR,
MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,
TXSTRT, UINT, MCCINT, MPDTINT, M APINT, MRE­INT, and STINT. Each status flag has either a ma sk or
an enable bit which allows for suppression of IN TA

as-

sertion. Table 1 shows the flag descriptions. By default

is an open-drain output. For applications that

INTA
need a high-active edge-se nsitive interrupt si gnal, the

pin can be configured for this mode by setting IN-

INTA
TLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the output for NAND tree
testing.

IRDY

Initiator Ready Input/Output

IRDY indicates the ability of the initiator of the transac ­tion to complete the current data phase. IRDY
in conjunc ti o n w i t h T RDY
both IRDY

and TRDY are asserted simultaneously. A

. Wait states are inserted until

is used

data phase is completed on any clock when both IRDY
and TRDY are asserted.

When the Am79 C973/Am79C975 c ontroller is a bus
master, it asserts IRDY dur ing all wr ite d ata pha se s to
indicate that valid data is p resent on AD[31: 0]. Durin g
all read data phases, the device ass erts IRDY

to indi-

cate that it is ready to accept the data.
When the Am79C973/Am79C 975 controller is the tar-

get of a transaction, it checks IRDY

during all wri te data
phases to determine if valid data is present on
AD[31:0]. Durin g all read data phases, the device
checks IRDY

to determine if the initiator is ready to ac-

cept the data.

When RST is active, IRDY is an input for NAND tree
testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0 ] and C/BE[3:0].
When the Am79 C973/Am79C975 c ontroller is a bus
master, it generates parity during the address and write
data phases. It checks parity during read data phases.
When the Am79C973/Am79C975 controller operates
in slave mode, it checks parity during every address
phase. When it is the target of a cycle, it checks par ity
during write data phases and it generates parity during
read data phases.

When RST
testing.

is active, PAR is an input for NAND tre e

.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT

IDON
MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO

MPINT

RCVCCO

RINT
SINT System Error CSR 5, bit 10 CSR5, bit 11
TINT
TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MPDTINT

MAPINT

MREINT

STINT

Excessive
Deferral

Initialization
Done

Missed Frame
Count Over­flow

Magic Packet
Interrupt

Receive
Collision Count
Overflow

Receive
Interrupt

Transmit
Interrupt

MII
Management
Command
Complete
Interrupt

MII PHY Detect
Transition
Interrupt

MII Auto-Poll
Interrupt

MII
Management
Frame Read
Error Interrupt

Software Timer
Interrupt

CSR5, bit 6 CSR5, bit 7

CSR3, bit 8 CSR0, bit 8

CSR4, bit 8 CSR4, bit 9

CSR5, bit 3 CSR5, bit 4

CSR4, bit 4 CSR4, bit 5

CSR3, bit 10 CSR0, bit 10

CSR3, bit 9 CSR0, bit 9

CSR7, bit 4 CSR7, bit 5

CSR7, bit 0 CSR7, bit 1

CSR7, bit 6 CSR7, bit 7

CSR7, bit 8 CSR7, bit 9

CSR7, bit 10 CSR7, bit 11

PERR

Parity Error Input/Output

During any slave write transaction and any master read
transaction, the Am79C973/Am79C975 controller as­serts PERR
porting of the error is enabled by setting PERREN (PCI
Command register, bit 6) to 1. During any master write
transaction, the Am79C973/Am79C975 controller
monitors PERR
error.

When RST is active, PERR is an input for NAND tree
testing.

when it detects a data parity error and re-

to see if the target reports a data parity

30 Am79C973/Am79C975