Datasheet AM79C972BVIW, AM79C972BVCW, AM79C972BKIW, AM79C972BKCW Datasheet (AMD Advanced Micro Devices)

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Am79C972

PCnet™-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

DISTINCTIVE CHARACTERISTICS

n Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus — 32-bit gluele ss PCI hos t interf ace

— Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization

— PCI specification revision 2.1 compliant — Supports PCI Subsystem/Subvendor ID/

Vendor ID pr ogramming through the EEPROM interface

— Supports both PCI 3.3-V and 5.0-V signaling

environments

— Plug and Play compatible — Supports an unlimited PCI burst length — Big endian and little endian byte alignments

supported

— Implements optional PCI power management

event (PME

n Media Independent Interface (MII) for

connecting external 10/100 megabit per second (Mbps) transceivers

— IEEE 802.3-compliant MII — Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3compliant MII PHYs at full- or half-duplex

n Supports General Purpose Serial Interface

(GPSI) with receive frame tagging support for internetworking applications

n Full-duplex operation supported in MII and GPSI

ports with independent Transmit (TX) and Receive (RX) channels

) pin

n Supports PC97, PC98, and Net PC requirements

— Implements full OnNow features including

pattern matching and link status wake-up

— Implements Magic Packet mode — Magic Packet mode and the physical address

loaded from EEPROM at power up without requiring PCI clock

— Supports PCI Bus Power Management

Interface Specification Version 1.0

— Supports Advanced Configuration and

Power Interface (ACPI) Specification Version 1.0

— Supports Network Device Class Power

Management Specification Version 1.0

n Large independent internal TX and RX FIFOs

— Programmable FIFO watermarks for both

transmit and receive operations

— Receive frame queuing for high latency PCI

bus host operation

— Programmable allocation of buffer space

between transmit and receive queues

n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards

n EEPROM interface supports jumperless design

and provides through-chip programming — Supports full programmability of half-/full-

duplex operation for external 10/100 Mbps PHYs through EEPROM mapping

— Programmable PHY reset output pin capable

of resetting external PHY without needing buffering

n Integrated oscillator circuit eliminates need for

external crystal

n Extensive programmable LED status support n Support for operation in industrial temperature

range (-40°C to +85°C)

Publication# 21485 Rev: D Amendment/0 Issue Date: December 1999

Refer to AMD’s Website (www.amd.com) for the latest information.

n Supports up to 1 megabyte (Mbyte) optional

Boot PROM or Flash for diskless node application

n Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame

n Programmable Inter Packet Gap (IPG) to

address less network aggressive MAC controllers

n Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

n IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test mode for board-level production connectivity test

GENERAL DESCRIPTION

The Am79C972 PCnet-FAST+ controller is a highlyintegrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ethern et controller solution, desig ned to address high-perfor mance sys tem applicat ion requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data thro ughput and low CPU and system bus utilization. T he Am79C972 cont roller is fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.

The Am79C972 PCnet-FAST+ controller also has several enhancements over its predecessor, the Am79C971 PCnet-FAST device. In addition to integrating the SRAM on chip, it further reduces system implementation cost by the addition of a new EEPROM programmable pin (PHY_RST), an inter nal oscillator circuit eliminating the n eed for an extern al c rystal, and the integration of the PAL function needed for Magic Packet application. The P HY_RST pi n is i mpleme nted to reset the external PHY without increasing the load to the PCI bus and to block RST input is LOW.

The 32-bit multiplexed bus interface unit provides a direct interface to the PCI l ocal bus, simplifying the design of an Ethernet node in a PC system. The Am79C972 PCnet-FAST+ controller provides the complete interface to a n Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for both little and big endian byte alignment, this controller also address es non-PC ap plications. Th e Am79C972 controller’s advanced CMOS design allows th e bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG

to the PHY when PG

n Software compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor architecture

n Compatible with the existing PCnet Family

driver and diagnostic software

n Available in 160-pin PQFP and 176-pin TQFP

packages

n +3.3 V power supply with 5 V tolerant I/Os

enables broad system compatibility

n Extensive programmable internal/external

loopback capabilities

n Supports patented External Address Detection

Interface (EADI)

test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JT AG interface.

The Am79C972 PCnet-FAST+ controller is also compliant with the PC97, PC98, and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI speci fications, whi ch are backward compatible with the Magic Packet technology, and is compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0 , D1, D2, and D3), the optio nal

pin, and the necessary configuration and data

PME registers.

The Am79C972 PCn et-FAST+ controller is ideally suited for Network PC (Net PC), motherboard, network interface card (NIC), and embedded designs. It is available in a 160-pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs.

The Am79C972 PCnet-FAST+ controller is a complete Ethern et node integrated into a singl e VLSI device. It contains a bus interface unit, a Direct M emory Access (DMA) Buffer Management Uni t, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant MII. Both IEEE

802.3 compliant full -dup lex and half-du plex operations are suppor ted on the MII a nd GPSI interfaces. 10/100 Mbps operation is supported through the MII.

The Am79C972 PCnet-FAST+ controller is register compatible with the LANCE™ (Am7990) an d CLANCE™ (Am79C90) Ethernet controllers, and all Ethernet controller s in the PCnet Family exce p t ILACC™ (Am79C900), including the PCnet-ISA™ controller (Am79C960), PCnet-ISA+™ (Am79C961),

2 Am79C972

PCnet-ISA II™ (Am79C961A), PCnet-32™ (Am79C965), PCnet-PCI™ (Am79C970), PCnet-PCI II™ (Am79C970A), and the PCnet-FAST™ (Am79C971). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.

The Am79C972 PCnet-FAST+ controller contains 12-kilobyte (Kbyte) buffers, the largest of its class of 10/ 100 Mbps Et hernet controll ers. The large inter nal buffer is programmable between the transmit (TX) an d receive (RX) queues for optimal performance.

The Am79C972 PCnet-FAST+ controller supports auto-configuration in the PCI configuration space. Additional Am79C972 controller configuration parameters, including the unique IEEE physical address, can be read from an external nonvolatile memory (EEPROM) immediately following system reset.

In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, link integrity , Magic Packet status, activity, address match, full-duplex, or 100 Mbps status. The Am79C972 controller also provides an EADI t o allow external hardware a ddress filterin g in i nternetworking ap pli ca tio ns and a r eceive frame tagging feature.

With the rise of embedded networking applications operating in harsh environments where temperatures may exceed the normal com mercial temperatur e window (0°C to 70°C), an industrial temperature (-40°C to +85°C) version is available in both the 160-pin PQFP and the 176-p in TQFP package. The Am7 9C972 PCnet-FAST+ 10/100 Mbps Ethernet controller can be designed with the industrial temperature capable Am79C874 NetPHY-1LP 10/100 Mbps Ethernet PHY for a complete and robust Fast Ethernet solution that can withstand extreme temperature environments.

Am79C972 3

BLOCK DIAGRAM

EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE EBCLK

CLK RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT PERR SERR

INTA

TCK

TMS

TDI

TDO

PCI Bus

Interface

Management

JTAG

Port

Control

Unit

Buffer

Unit

Expansion Bus

Bus Rcv

FIFO

Bus Xmt

FIFO

Control

Interface

12K

SRAM

MAC

Rcv

FIFO

MAC

Xmt

FIFO

Network

Port

Manager

OnNow

Power

Management

Unit

802.3 MAC Core

GPSI

Port

MII

Port

EADI

Port

93C46

EEPROM

Interface

LED

Control

TXEN TXCLK TXDAT RXEN RXCLK RXDAT CLSN

TX_ER TXD[3:0] TX_EN TX_CLK COL RXD[3:0] RX_ER RX_CLK RX_DV CRS MDC MDIO

SRDCLK SRD SFBD EAR MIIRXFRTGD/RXFRTG MIIRXFRTGE/RXFRTGE

PHY_RST TBC_IN

TBC_EN EECS EESK EEDI EEDO

LED0 LED1 LED2 LED3

PME

RWU

WUMI

4 Am79C972

21485C-1

AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

DISTINCTIVE CHARACTERISTICS1 GENERAL DESCRIPTION2

TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CONNECTION DIAGRAM (PQR160)8 CONNECTION DIAGRAM (PQL176)9

PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PIN DESIGNATIONS (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PIN DESIGNATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

BASIC FUNCTIONS26

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DETAILED FUNCTIONS27

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

BLOCK DIAGRAM4

Am79C972 5

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Am79C972 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

DC CHARACTERISTICS OVER

OPERATING RANGES 190 COMMERCIAL AND INDUSTRIAL

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . .194

SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . .195

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .196

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .204

SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .206

SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .207

SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQR160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Plastic Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Thin Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

LAPP Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Auto-Negotiation Link Partner Ability Register (Register 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6 Am79C972

RELATED AMD PRODUCTS

Part No. Description

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79865 100 Mbps Physical Data Transmitter (PDT) Am79866A 100 Mbps Physical Data Receiver (PDR) Am79C871 Quad 100BASE-X Transceiver for Repeater Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support) Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus

Am79C972 7

CONNECTION DIAGRAM (PQR160)

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12 AD11

VDD_PCI

AD10

AD9

AD27

VDD_PCI

AD26

VSSB

C/BE3

AD24

AD25

160

159

158

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

157

414243444546474849505152535455565758596061626364656667687071727374757677787980

156

155

154

AD29

AD28

153

152

AD30

VSS

151

150

VSSB

GNT

REQ

AD31

VDD_PCI

149

148

147

146

145

PCnet“-FAST+

Am79C972BKC

Am79C972

CLK

144

RST

143

INTA

142

141

VDD

140

TDI

139

VSSB

TDO

138

137

TMS

VDDB

136

135

TCK

134

RWU

WUMI

133

132

PME

VSS

131

130

EAR

EECS

EESK/LED1/SFBD

VSSB

129

128

127

126

TBC_EN

VDDB

TBC_IN

EEDI/LED0

LED2/SRDCLK/MIIRXFRTGE

125

124

123

122

121

EEDO/LED3/SRD/MIIRXFRTGD

120

PHY_RST

119 118

MDIO

117

VSSB

116

MDC

115

RXD3

114

RXD2

113

VDDB

112

RXD1

111

RXD0/RXFRTGD

110

VSS

109

RX_DV/RXFRTGE

108

RX_CLK/RXCLK

107

RX_ER/RXDAT

106

VSSB

105

TX_ER

104

TX_CLK/TXCLK

103

TX_EN/TXEN

102

TXD0/TXDAT

101

VDDB

100

VDD

TXD1

TXD2

TXD3

COL/CLSN

VSSB

CRS/RXEN

EBD0

EBD1

EBD2

VSS

EBD3

VDDB

EBD4

EBD5

EBD6

VSSB

EBD7

EBDA15

EBDA14

VSSB

C/BE0

AD6

AD7

VDD_PCI

AD5

VDD

AD4

AD3

VSSB

AD2

AD0

AD1

VSS

VDD_PCI

EBWE

EBCLK

EROMCS

AS_EBOE

VDD

VSSB

VDDB

EBUA_EBA1

EBUA_EBA0

EBUA_EBA2

EBUA_EBA3

AD8

Pin 1 is marked for orientation.

8 Am79C972

VSS

EBUA_EBA6

EBUA_EBA4

EBUA_EBA5

EBUA_EBA7

VSSB

EBDA9

EBDA8

VDDB

EBDA11

EBDA10

EBDA12

EBDA13

21485C-2

CONNECTION DIAGRAM (PQL176)

NCNCC/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

NC NC

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR SERR VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12 AD11

VDD_PCI

AD10

AD9

NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

161

REQ

GNT

CLK

RST

INTAPGVDD

160

159

158

157

156

155

154

PCnet“-FAST+

Am79C972

Am79C972BVC

TDI

153

VSSB

152

TDO

151

VDDB

150

TMS

149

TCK

148

RWU

147

WUMI

146

PME

145

144

VSS

EAR

143

EECS

VSSB

EESK/LED1/SFBD

LED2/SRDCLK/MIIRXFRTGE

VDDB

TBC_EN

TBC_IN

142

141

140

139

138

137

136

EEDI/LED0NCNC

135

134

133

132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

NC NC EEDO/LED3/SRD/MIIRXFRTGD PHY_RST MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0/RXFRTGD VSS RX_DV/RXFRTGE RX_CLK/RXCLK RX_ER/RXDAT VSSB TX_ER TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT VDDB VDD TXD1 TXD2 TXD3 COL/CLSN VSSB CRS/RXEN EBD0 EBD1 EBD2

VSS 99 98 97 96 95 94 93 92 91 90 89

EBD3

VDDB

EBD4

EBD5

EBD6

VSSB

EBD7

EBDA15

EBDA14

AD8

VSSB

C/BE0

Pin 1 is marked for orientation.

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

AD2

VSSB

AD1

AD0

VDD_PCI

EBDA11

EBDA12

EBDA13

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5

EBUA_EBA6

VSS

VSSB

EBDA8

EBUA_EBA7

EBDA9

EBDA10

VDDB

Am79C972 9

21485C-3

PIN DESIGNATIONS (PQR160) Listed By Pin Number

No.

Name

1 IDSEL 41 AD8 81 EBDA14 121 EEDI/LED0 2 AD23 42 C/BE0 82 EBDA15 122 TBC_IN 3 VSSB 43 VSSB 83 EBD7 123 TBC_EN 4 AD22 44 AD7 84 VSSB 124 VDDB

5 VDD_PCI 45 VDD_PCI 85 EBD6 125 6 AD21 46 AD6 86 EBD5 126 EESK/LED1/SFBD

7 AD20 47 AD5 87 EBD4 127 VSSB 8 VDD 48 VDD 88 VDDB 128 EECS 9 AD19 49 AD4 89 EBD3 129 EAR 10 AD18 50 AD3 90 VSS 130 VSS 11 VSSB 51 VSSB 91 EBD2 131 PME 12 AD17 52 AD2 92 EBD1 132 WUMI 13 VDD_PCI 53 VDD_PCI 93 EBD0 133 RWU 14 AD16 54 AD1 94 CRS/RXEN 134 TCK 15 C/BE2 55 AD0 95 VSSB 135 TMS 16 VSS 56 VSS 96 COL/CLSN 136 VDDB 17 FRAME 57 EROMCS 97 TXD3 137 TDO 18 IRDY 58 EBWE 98 TXD2 138 VSSB 19 VSSB 59 AS_EBOE 99 TXD1 139 TDI 20 TRDY 60 EBCLK 100 VDD 140 VDD 21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG 22 DEVSEL 62 VSSB 102 TXD0/TXDAT 142 INTA 23 STOP 63 EBUA_EBA1 103 TX_EN/TXEN 143 RST 24 VDD 64 VDD 104 TX_CLK/TXCLK 144 CLK 25 PERR 65 VDDB 105 TX_ER 145 GNT 26 SERR 66 EBUA_EBA2 106 VSSB 146 REQ 27 VSSB 67 EBUA_EBA3 107 RX_ER/RXDAT 147 VDD_PCI 28 PAR 68 EBUA_EBA4 108 RX_CLK/RXCLK 148 AD31 29 VDD_PCI 69 EBUA_EBA5 109 RX_DV/RXFRTGE 149 VSSB 30 C/BE1 70 EBUA_EBA6 110 VSS 150 VSS 31 AD15 71 EBUA_EBA7 111 RXD0/RXFRTGD 151 AD30 32 VSS 72 VSS 112 RXD1 152 AD29 33 AD14 73 EBDA8 113 VDDB 153 AD28 34 AD13 74 VSSB 114 RXD2 154 AD27 35 VSSB 75 EBDA9 115 RXD3 155 VDD_PCI 36 AD12 76 EBDA10 116 MDC 156 AD26 37 AD11 77 VDDB 117 VSSB 157 VSSB 38 VDD_PCI 78 EBDA11 118 MDIO 158 AD25 39 AD10 79 EBDA12 119 PHY_RST 159 AD24

40 AD9 80 EBDA13 120

Pin No.

Pin Name

Pin No.

Pin Name

EEDO/LED3/SRD/ MIIRXFRTGD

Pin No.

160 C/BE3

Name

LED2/SRDCLK/ MIIRXFRTGE

10 Am79C972

PIN DESIGNATIONS (PQL176) Listed By Pin Number

No.

Name

1 NC 45 NC 89 NC 133 NC 2 NC 46 NC 90 NC 134 NC 3 IDSEL 47 AD8 91 EBDA14 135 EEDI/LED0 4 AD23 48 C/BE0 92 EBDA15 136 TBC_IN 5 VSSB 49 VSSB 93 EBD7 137 TBC_EN 6 AD22 50 AD7 94 VSSB 138 VDDB

7 VDD_PCI 51 VDD_PCI 95 EBD6 139 8 AD21 52 AD6 96 EBD5 140 EESK/LED1/SFBD

9 AD20 53 AD5 97 EBD4 141 VSSB 10 VDD 54 VDD 98 VDDB 142 EECS 11 AD19 55 AD4 99 EBD3 143 EAR 12 AD18 56 AD3 100 VSS 144 VSS 13 VSSB 57 VSSB 101 EBD2 145 PME 14 AD17 58 AD2 102 EBD1 146 WUMI 15 VDD_PCI 59 VDD_PCI 103 EBD0 147 RWU 16 AD16 60 AD1 104 CRS/RXEN 148 TCK 17 C/BE2 61 AD0 105 VSSB 149 TMS 18 VSS 62 VSS 106 COL/CLSN 150 VDDB 19 FRAME 63 EROMCS 107 TXD3 151 TDO 20 IRDY 64 EBWE 108 TXD2 152 VSSB 21 VSSB 65 AS_EBOE 109 TXD1 153 TDI 22 TRDY 66 EBCLK 110 VDD 154 VDD 23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG 24 DEVSEL 68 VSSB 112 TXD0/TXDAT 156 INTA 25 STOP 69 EBUA_EBA1 113 TX_EN/TXEN 157 RST 26 VDD 70 VDD 114 TX_CLK/TXCLK 158 CLK 27 PERR 71 VDDB 115 TX_ER 159 GNT 28 SERR 72 EBUA_EBA2 116 VSSB 160 REQ 29 VSSB 73 EBUA_EBA3 117 RX_ER/RXDAT 161 VDD_PCI 30 PAR 74 EBUA_EBA4 118 RX_CLK/RXCLK 162 AD31 31 VDD_PCI 75 EBUA_EBA5 119 RX_DV/RXFRTGE 163 VSSB 32 C/BE1 76 EBUA_EBA6 120 VSS 164 VSS 33 AD15 77 EBUA_EBA7 121 RXD0/RXFRTGD 165 AD30 34 VSS 78 VSS 122 RXD1 166 AD29 35 AD14 79 EBDA8 123 VDDB 167 AD28 36 AD13 80 VSSB 124 RXD2 168 AD27 37 VSSB 81 EBDA9 125 RXD3 169 VDD_PCI 38 AD12 82 EBDA10 126 MDC 170 AD26 39 AD11 83 VDDB 127 VSSB 171 VSSB 40 VDD_PCI 84 EBDA11 128 MDIO 172 AD25 41 AD10 85 EBDA12 129 PHY_RST 173 AD24

42 AD9 86 EBDA13 130 43 NC 87 NC 131 NC 175 NC

44 NC 88 NC 132 NC 176 NC

Pin No.

Pin Name

Pin No.

Pin Name

EEDO/LED3/SRD/ MIIRXFRTGD

Pin No.

174 C/BE3

Name

LED2/SRDCLK/ MIIRXFRTGE

Am79C972 11

PIN DESIGNATIONS (PQR160, PQL176) Listed By Group

Pin Name Pin Function Type PCI Bus Interface

AD[31:0] Address/Data Bus IO 32 C/BE[3:0] Bus Command/Byte Enable IO 4 CLK Bus Clock I 1 DEVSEL Device Select IO 1 FRAME Cycle Frame IO 1 GNT Bus Grant I 1 IDSEL Initialization Device Select I 1 INTA Interrupt O 1 IRDY Initiator Ready IO 1 PAR Parity IO 1 PERR Parity Error IO 1 REQ Bus Request O 1 RST Reset I 1 SERR System Error IO 1 STOP Stop IO 1 TRDY Target Ready IO 1

Board Interface

LED0 LED0 O 1 LED1 LED1 O 1 LED2 LED2 O 1 LED3 LED3 O 1 TBC_IN Test Pin I 1 TBC_EN Test Pin I 1 PHY_RST Reset to PHY O 1

EEPROM Interface

EECS Seri al EEPROM Chip Select O 1 EEDI Serial EEPROM Data In O 1 EEDO Serial EEPROM Data Out I 1 EESK Serial EEPROM Clock IO 1

Expansion ROM Interface

AS_EBOE Address Strobe/Expansion Bus Output Enable O 1 EBCLK Expansion Bus Clock I 1 EBD[7:0] Expansion Bus Data [7:0] IO 8 EBDA[15:8] Expansion Bus Data/Address [15:8] IO 8 EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address [7:0] O 8 EBWE Expansion Bus Write Enable O 1 EROMCS Expansion Bus ROM Chip Select O 1

No. of Pins

Note: 1. Not including test features.

12 Am79C972

PIN DESIGNATIONS Listed By Group

Pin Name Pin Function Type Media Independent Interface (MII)

COL Collision I 1 CRS Carrier Sense I 1 MDC Management Data Clock O 1 MDIO Management Data I/O IO 1 RX_CLK Receive Cloc k I 1 RXD[3:0] Receive Data I 4 RX_DV Receive Data Valid I 1 RX_ER Receive Error I 1 TX_CLK Transmit Clock I 1 TXD[3:0] Transmit Data O 4 TX_EN Transmit Data Enable O 1 TX_ER Transmit Error O 1

General Purpose Serial Interface (GPSI)

CLSN Collision I 1 RXCLK Receive Cloc k I 1 RXDAT Receive Data I 1 RXEN Receive Enab l e I 1 TXCLK Transmit Clock I 1 TXDAT Transmit Data O 1 TXEN Transmit Enable O 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I 1 SFBD Start Frame Byte Delimiter O 1 SRD Serial Receive Data O 1 SRDCLK Serial Receive Data Clock O 1 RXFRTGD Receive Frame Tag Data I 1 RXFRTGE Receive Frame Tag Enable I 1 MIIRXFRTGD MII Receive Frame Tag Data I 1 MIIRXFRTGE MII Receive Frame Tag Enable I 1

Powe r Mana gemen t Interface

RWU Remote Wake Up O 1 PME Power Management Even t O 1 WUMI Wak e-U p Mo de Indi cation O 1 PG Power Good I 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I 1 TDI Test Data In I 1 TDO Test Data Out O 1 TMS Test Mode Select I 1

Power Suppli es

VDD Digital Power P 6 VSS Digital Ground P 8 VDDB I/O Buffer Power P 7 VSSB I/O Buffer Ground P 17 VDD_PCI PCI I/O Buffer Power P 9

Note: 1. Not including test features.

No. of Pins

Am79C972 13

Listed By Driver Type

The following table describes th e various type s of o utput drive rs used i n the Am79C9 72 contro ller . All I

values shown in the table apply to 3.3 V signaling.

and

A sustained tri-state signal is a low active signal that is driven high for one clock period before it is left floating.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50 OMII1 Totem Pole 4 -4 50 OMII2 Totem Pole 4 -4 390 O6 Totem Pole 6 -0.4 50 OD6 Open Drain 6 NA 50 STS6 Sustained Tri-State 6 -2 50 TS3 Tri-State 3 -2 50 TS6 Tri-State 6 -2 50 TSMII Tri-State 4 -4 470

14 Am79C972

ORDERING INFORMATION Standard Products

AMD standard produc ts are av ailable in sev eral pac kages and operating ranges. T he order number (Valid Combination) is f ormed by a combination of the elements below.

Am79C972B

K\V

C/I

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0° C to +70° C) I = Industrial (-40° C to +85° C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR160) V = Thin Quad Flat Pack (PQL176)

SPEED OPTION

Not applicable

DEVICE NUMBER/DESCRIPTION

Am79C972B PCnet-FAST+ Enhanced 10/100 Mbps PC I Ether- net Controller with OnNow Support

Valid Combinations

Am79C972B

KC\W,

VC\W

KI\W, VI\W

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am79C972 15

PIN DESCRIPTIONS PCI Interfa ce AD[31:0]

Address and Data Input/Output

Address and data ar e multi pl exed on the same bus in terface pins. During the fir st clock of a transaction, AD[31:0] co ntain a physica l address (3 2 bits). Dur ing the subsequent clocks, AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are defined as the least signifi cant byte (LSB) and A D[31:24] are d efined as the most significant byte (MSB). For FIFO data transfers, the Am79C972 controller can be programmed for big endian byte ordering. See CSR3, bit 2 (BSWP) for more details.

eration section for details. The Am79C972 controller will support a clock frequency of 0 MHz after certain precautions are taken to ensure data integrity. This clock or a derivation i s not used to dr ive any network functions.

When RST testing.

is active, CLK is an inp ut for NAND tree

DEVSEL

Device Select Input/Output

The Am79C972 controller dr ives DEVSEL tects a transaction that select s the device as a target. The device samples DEVSEL claims a transaction that the Am79C972 controller has initiated.

to detect if a target

when it de-

During the address phase of the transaction, when the Am79C972 controller is a bus master, AD[31:2] will address the active Double Word (DWord). The Am79C972 controller always drives AD[1:0] to ’00’ during the address phase indicating linear burst order. When the Am79C972 controller is not a bus master, the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.

During the data phase of the transacti on, AD[31: 0] are driven by the Am79C972 controller wh en performing bus master write and slave read operations. Data on AD[31:0] is latched by the Am79C972 co ntroller when performing bus master read and slave write operations.

When RST testing.

is active, AD[31:0] are inputs for NAND tree

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the same bus interface pins. During the a ddress phase o f the transaction, C /BE During the data phase, C/BE ables. The byte enables define which physical byte lanes carry meaningful data. C/BE (AD[7:0]) and C/BE function of the byte enables is independent of the byte ordering mode (BSWP, CSR3, bit 2).

When RST tree testing.

is active, C/BE[3:0] are inputs for NAND

[3:0] define th e bus command.

[3:0] are used as by te en-

0 applies to byte 0

3 applies to byte 3 (AD[31:24]). The

CLK

Clock Input

This clock is used to drive the system bus interface and the internal buffer management unit. All bus signals are sampled on the rising edge of CLK and all parameters are defined with resp ect to this edge. The A m79C972 controller normally operates over a frequency range of 10 to 33 MHz on the PCI bus due to networking demands. See the Frequency Demands for Networ k Op-

When RST testing.

is activ e, DEVS EL is an inp ut f or NAND tr ee

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79 C972 controll er when it is the bus master to indicate the beginning and duration of a transaction. FRAME transaction is beginning. FRAME data transfers continue. FRAME the final data phase o f a transaction. When the Am79C972 controller is in slave mode, it samples FRAME tion.

When RST is active, FRAME is an input for NAND tree testing.

to determ ine the ad dress phas e of a tran sac-

is asser ted to indica te a bus

is asserted while

is deasserted before

GNT

Bus Grant Input

This signal indicates that the access to the bus has been granted to the Am79C972 controller.

The Am79C972 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNT without an active REQ from the Am79C972 controller, the device will drive the AD[31:0], C/BE lines.

When RST testing.

is active, GNT is an input for NAND tree

[3:0] and PA R

IDSEL

Initialization Device Select Input

This signal is used as a c hip sele ct for the Am79C97 2 controller duri ng configura tion read a nd write transactions.

When RST testing.

is active, IDSEL is an input for NAND tree

16 Am79C972

INTA

Interrupt Request Output

An attention signal which indicates that one or more of the following status flags is set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, and S TINT. Each status flag has either a ma sk or an enable bit which allows for suppression of IN TA

as-

sertion. Table 1 shows the flag descriptions. By default

is an open-drain output. For applications that

INTA need a high-active edge-se nsitive interrupt si gnal, the

pin can be configured for this mode by setting IN-

INTA TLEVEL (BCR2, bit 7) to 1.

When RST

is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready Input/Output

IRDY

indicates the ability of the initiato r of the transac tion to complete the current data phas e. IRDY in conjunc ti o n w i t h T RDY both IRDY

and TRDY are asser ted simultaneously. A

. Wait states are inserted until

is used

data phase is completed on any clock when both IRDY and TRDY are asserted.

When the Am79C972 c ontroll er is a bus mas ter, it asserts IRDY

during all write data phases to indicate that valid data is present on AD[31:0]. Dur ing all read dat a phases, the device asserts IRDY

to indicate that it is

ready to accept the data. When the Am79C972 controller is the target of a trans-

action, it checks IR DY

during all wr ite data phas es to determine if valid data is presen t on AD[31:0]. During all read data phases, the device checks IRDY

to deter-

mine if the initiator is ready to accept the data.

When RST

is active, IRDY is an input for NAND tree

testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0 ] and C/BE[3:0]. When the Am79C972 controller is a bus master, it generates parity during the address and write data phases. It checks parity during read data phases. When the Am79C972 controller operates in slave mode, it checks parity during every address phase. When it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases.

When RST testing.

is active, PAR is an input for NAND tre e

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT

IDON MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO

MPINT

RCVCCO

RINT SINT System Error CSR5, bit 10 CSR5, bit 11 TINT TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MPDTINT

MAPINT

MREINT

STINT

Excessive Deferral

Initialization Done

Missed Frame Count Overflow

Magic Packet Interrupt

Receive Collision Count Overflow

Receive Interrupt

Transmit Interrupt

MII Management Command Complete Interrupt

MII PHY Detect Transition Interrupt

MII Auto-Poll Interrupt

MII Management Frame Read Error Interrupt

Software Timer Interrupt

CSR5, bit 6 CSR5, bit 7

CSR3, bit 8 CSR0, bit 8

CSR4, bit 8 CSR4, bit 9

CSR5, bit 3 CSR5, bit 4

CSR4, bit 4 CSR4, bit 5

CSR3, bit 10 CSR0, bit 10

CSR3, bit 9 CSR0, bit 9

CSR7, bit 4 CSR7, bit 5

CSR7, bit 0 CSR7, bit 1

CSR7, bit 6 CSR7, bit 7

CSR7, bit 8 CSR7, bit 9

CSR7, bit 10 CSR7, bit 11

PERR

Parity Error Input/Output

During any slave write transaction and any master read transaction, the Am79C972 contro ller asserts PE RR when it detects a dat a p arity error and r epo rting of th e error is enabled by setting PERREN (PCI Command register, bit 6) to 1. During any master write transaction, the Am79C972 cont roller mo nitors PE RR target reports a data parity error.

When RST

is active, PERR is an input for NAND tree

testing.

to see if the

Am79C972 17

REQ

Bus Request Input/Output

The Am79C972 controller asserts REQ that it wishes to become a bus mas ter. REQ high when the Am79C972 control ler does not request the bus. In Po wer Management mode, the REQ not be driven.

When RST testing.

is active, REQ is an input for NAND tree

pin as a signal

is driven

pin will

RST

Reset Input

When RST then the Am79C972 controller performs an i nternal system reset of the type H_RESET (HARDWARE_RESET, see section on RESET). RST must be held for a minimum of 30 clock periods. While in the H_RESET state, the Am79C972 controller will disable or deassert all outputs. RST nous to clock when asserted or deasserted.

When the PG pin is LOW, RST disables all of the PCI pins except the PME

When RST is enabled.

is asserted LOW and the PG pin is HIGH,

may be asynch ro -

pin.

is LOW and PG is HIGH, NAND tree testing

SERR

System Error Output

During any slave transaction, the Am79C972 controller asserts S ERR and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1.

By default SERR nent test, it can be programmed to be an active-high totem-pole output.

When RST testing.

when it detects a n add re ss p ar i ty er r or,

is an open-drain out put. For compo-

is active, SERR is an input for NAND tree

STOP

Stop Input/Out put

In slave mode, the Am79C972 controller drives the

signal to inform the bus master to stop the cur-

STOP rent transaction. In bus mas ter mode, the Am79C97 2 controller checks STOP to disconnect the current transaction.

When RST testing.

is active, STOP is an input for NAND tree

to determine if the target wants

TRDY

Target Ready Input/Output

TRDY ind icates the ability of the targ et of the transaction to complete the current data phase. Wait states are inserted until both IRD Y

and TRDY are asserted simul-

taneously. A data phase is completed on any clock when both IRDY

When the Am79C972 controller is a bus master, it checks TRD Y during all read data phases to determine if vali d data is present on AD[31: 0]. Duri ng all write data phases, the device checks TRDY target is ready to accept the data.

When the Am79C972 controller is the target of a transaction, it asser ts TRDY indicate that valid data is present on AD[31 :0]. Durin g all write data phases, the device ass erts TRDY cate that it is ready to accept the data.

When RST testing.

and TRDY are asserted.

to determine if th e

during all read data phases to

to indi-

is active, TRDY is an input for NAND tree

PME

Power Management Event Output, Open Drain

PME

is an output that can be used to indicate that a power management event (a Magic Packet, an OnNow pattern match , or a change in link state) has been detected. The PME

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1. The PME

PCI clock.

signal is asynchronous with respect to the

pin is asserted when either

Board Interface

Note: Before programming the LED pins, see the description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By default, LED0 can also be programmed to indicate other network status (see BCR4). The LED0 ble, but by default it is active LOW. When the LED0 polarity is programmed to active LOW, the output is an open drain dr iver. When the LED0 grammed to active HIGH, the output is a totem pole driver.

Note: The LED0

indicates an active link connection. This pin

pin polarity is programma-

pin polarity is pro-

pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By default, LED1 This pin can also be programmed to indicate other network status (see BCR5). T he LED1 grammable, but by default, it is active LOW. W hen the LED1 output is an open drain driver. When the LED1

indicates receive activity on the network.

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

18 Am79C972

larity is pr ogrammed to active HIGH, th e output is a totem pole driver.

Note: The LED1 SFBD pins.

The LED1 Detection to deter mine whe ther or not an EE PROM is present at the Am79C972 controller interface. At the last rising edge of CLK while RST is sampled to determine the value of the EE DET bi t in BCR19. It is important to mai ntain adequ ate hol d tim e around the rising edge of the CLK at this time to ensure a correctly sampled value. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead i n order to resolve the EEDET setting.

WARNING insured for correct EEPROM detection before the deassertion of RST

pin is multiplexed with the EESK and

pin is also used dur ing EEPROM Auto-

is active LOW , LED1

: The input signal level of LED1 must be

LED2

LED2 Output

This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR6). T he L ED2 mable, but by default it is active LOW. When the LED 2 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED2 grammed to active HIGH, the output is a totem pole driver.

Note: The LED2 pin and the MIIRXFRTGE pins.

pin is multiplexed with the SRDCLK

pin polarity i s program-

pin polarity is pro-

LED3

LED3 Output

This output is designed to directly drive an LED. By default, LED3 This pin can also be programmed to indicate other network status (see BCR7). T he LED3 gramma ble, but by defaul t it is active LOW. When th e LED3 output is an open d rain driver. When the LED3 larity is pr ogrammed to active HIGH, th e output is a totem pole driver.

Special attention must be given to the external circuitry attached to this pin. Whe n this pin is used to dri ve an LED while an EEPROM is used in the system, then buffering maybe required between the LED3 the LED circuit. If an LED circuit were directly attached to this pin, it may create an I not be met by the serial EEPROM attached to this pin.

indicates tran smit activity on the network .

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

pin and

OL requirement that co ul d

If no EEPROM is includ ed in the system design or l ow current LEDs are used, then th e LED3 directly connected to an LED without buffering. For more details regarding LED connection, see the section on LED Support.

Note: The LED3 SRD, MIIRXFRTGD pins.

pin is multiplexed with the EEDO,

signal may be

Power Good Input

The PG pin has two functions: (1) it puts the device into Mag ic Packet™ mode, and (2) it blocks any resets when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is set to 1, the device enters the Magic Packet mode.

When PG is LOW , a LOW assertion of the PCI RST will only cause the PCI interface pins (except for PME to be put in the high impedance state. The internal logic will ignore the assertion of RST

When PG is HIGH, assertion of the PCI RST causes the controller logic to be reset and the configuration information to be loaded from the EEPROM.

PG input should be kept high during the NAND tree testing.

RWU

Remote Wake Up Output

RWU is an output that is asserted either when the controller is in the Magic Packet mode and a Magic Packet frame has been detected, or the controller is in the Link Change Detect mode and a Link Change has been detected.

This pin can dr ive the external system mana gement logic that causes the CP U to get out of a low power mode of operation. This pin is implemented for designs that do not support the PME

Three bits that are loaded from the EEP ROM into CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the RWU sig-

nal.

2. If RWU_GATE bit is set , RWU is forced to the high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or totem pole.

The internal power-on-reset signal forces this output into the high impedance state until after the polarity and drive type have been determined.

function.

WUMI

Wake-Up Mode Indicator Output

This output, which is ca pable of dri ving an LED, is asserted when the device is in Magic Packet mode. It can

)

Am79C972 19

be used to drive external logic that switches the device power source from the main p ower supply to an aux iliary power supp l y.

during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.

TBC_EN

Time Base Clock Enable Input

TBC_EN is an input that controls the selection of the source of the Time Ba se Clock. The Time Base Cl ock is used in loading the EEPROM, generation of the PHY_RST, and the timing of the MDC and MDIO signals. When the input to this pin is LOW , an internal free running oscillator with a maximum frequency of 20 MHz is used. When the inpu t to this pi n is HIGH, th e TBC_IN pin input is used to inject externally generated clock into the device. For typical applications which will use the internal oscillation, this pin should be tied to ground.

When RST testing.

is active, TBC_EN is an input for NAND tree

TBC_IN

Time Base Clock Input Input

TBC_IN may be used to connect to an external clock source to drive the internal circuitry that loads the EEPROM and controls the MDC and MDIO signals. This input is select ed when the TB C_EN pin is HIG H. This pin should be tied to ground when the TBC_EN pin is LOW.

PHY_RST

PHY Reset Output

PHY_RST is an output pin that is used to reset the external PHY. This output eliminates the need for a fan out buffer for the PCI RST signal, provides polarity for the specific PHY used, and prevents the resetting of the PHY when the PG input is LOW. The output polarity is determined by the RST_POL bit(CSR116, bit0).

EEPROM Interface EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EECS is connected to the EEPROM ’s chip select pin. It is controll ed by either the Am 79C972 controll er during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EEDI is connecte d to the EEPROM’s data input pin. It is controll ed by either the Am 79C972 controll er

Note: The EEDI pin is multiplexed with the LED0

pin.

EEDO

EEPROM Data Out Input

This pin is designe d to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EEDO is connected to the EEPROM’s data output pin. It is controlled by either the Am79C972 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3, MIIRXFRTGD, and SRD pins.

EESK

EEPROM Serial Clock Input/Output

This pin is designe d to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EESK is connected to the EEPROM’s clock pin. It is controlled by either the Am79C972 controller directly during a read of the entire EE PROM, or indirect ly by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 SFBD pins.

The EESK pin is also used during EEPROM AutoDetection to deter mine whe ther or not an EEPROM is present at the Am79C972 controller interface. At the rising edge of the last CLK edge while RST EESK is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is no t present, and EEDET will be set to 0. See the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead to resolve the EEDET setting.

WARNING valid for correct EEPROM detection before the deassertion of RST

: The input signal level of EESK must be

is asserted,

and

Expansion Bus Interface EBUA_EBA[7:0]

Expansion Bus Upper Address/ Expansion Bus Address [7:0] Output

The EBUA_EBA[7:0] pins provide the least and most significant bytes of address on the Expansion Bus. The most significant address byte (address bits [19:16] during boot device accesses) is valid on these pins at th e beginning of a boot device access, at the rising edge of AS_EBOE

. This upper address byte must be stored ex-

20 Am79C972

ternally in a D fli p-flop. During subseq uent cycles of a boot device access, addres s bits [7:0] are p resent on these pins.

All EBUA_EBA[7:0] outpu ts are forced to a constant level to conserve power while no access on the Expansion Bus is being performed.

EBDA[15:8]

Expansion Bus Data/Address [15:8] Input/Output

When EROMCS is asserted low, EBDA[15:8] contain address bits [15:8] for boot device accesses.

The EBDA[15:8] signals are driven to a constant level to conserve power while no access on the Expansion Bus is being performed.

EBD[7:0]

Expansion Bus Data [7:0] Input/Output

The EBD[7:0] pins provide data bit s [7:0] for EPROM/ FLASH accesses. The EBD[ 7:0] signals are internally forced to a constant level to conserve power while no access on the Expansion Bus is being performed.

EROMCS

Expansion ROM Chip Select Output

EROMCS It is asserted low during the data phases of boot device accesses.

serves as the chip select for the boot device.

AS_EBOE

Address Strobe/Expansion Bus Output Enable Output

AS_EBOE upper address bits on the EBUA_EBA[7:0] pins and as the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE supplied at the beginning of boot device accesses. This rising edge provides a clock edge for a ‘374 D-type edge-triggered flip-flop which must store the upper address byte during Expansion Bus accesses for EPROM/Flash.

AS_EBOE read operations on the expansion bus and is deasserted during boot device write operations.

functions as the address strobe for the

is asserted active LOW during boot device

EBWE

Expansion Bus Write Enable Output

EBWE provides the wr ite enable for writ e accesse s to the Flash device.

EBCLK

Expansion Bus Clock Input

EBCLK may be used as the fundamental clock to drive the Expansion Bus and inte rn al SRAM a ccess cy cles. The actual inter nal clock used to dr ive the Expansion

Bus cycles depends o n the values of the EBCS and CLK_F A C settings in BCR27. Refer to the SRAM Interface Bandwidth Requirements section for details on determining the requ ired EBCLK frequency. If a clock source other than the EBCLK pin is programmed (BCR27, bi ts 5: 3 ) to be used to run the Ex pa n si on Bu s interface, this input should be tied to VDD through a 4.7

Ω resistor.

k EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface TX_CLK

Transmit Clock Input

TX_CLK is a conti nuous clock input th at provides the timing reference for the transfer of the T X_EN, TXD[3:0], an d TX_ER signal s out of the Am 79C972 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, an MII transceiver operating at 10 Mbps must provid e a TX_CL K freq uency of 2.5 MHz and an MII transceiver operating at 100 Mbps must provide a TX_CLK frequency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the TXCLK pin.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. V alid data is generated on TXD[3:0] on every TX_CLK rising edge while TX_EN is asserted. While TX_EN is deasserted , TXD[3:0] values are dri ven to a 0. TXD[3:0] transitions synchronous to TX_CLK rising edges.

Note: The TXD[0] pin is multiplexed with the TXD pin.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C972 device is presenting valid transmit nibbles on the MII. While TX_EN is asserted, the Am79C972 device generates TXD[3:0] and TX_ER on TX_CLK rising edges. TX_EN is asserted with the first nibble of preamble and remains asserted throughout the duration of a packet until it is deassert ed p rior to the first TX_CL K following the final nibble of the frame. TX_EN transitio ns s ynch ro nous to TX_CLK rising edges.

Note: The TX_EN pin is multiplexed with the TXEN pin.

TX_ER

Transmit Error Output

TX_ER is an out put th at, if asserted wh ile TX _EN is asserted, i nstructs the MII PHY device connecte d to the Am79C972 device to transmit a code group error. TX_ER is unused and is reserved for future use and will always be driven to a logical zero.

Am79C972 21

COL

Collision Input

COL is an input that indicates that a collision has been detected on the network medium.

Note: The COL pin is multiplexed with the CLSN pin.

CRS

Carrier Sense Input

CRS is an input that indicates that a non-idl e medium, due either to transmit or receive activi ty, has been detected.

Note: The CRS pin is multiplexed with the RXEN pin.

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and RX_ER signals into the Am79C972 device. RX_CLK must provide a nibble rate cl ock (25% of the networ k data rate). Hence, an MII transceiver operating at 10 Mbps must provide an RX_ CLK freq uen cy of 2.5 MHz and an MII transceiver operating at 100 Mbps must provide an RX_CLK frequency of 25 MHz. When the external PHY switches the RX_CLK and TX_CLK, it must provide glitch-free clock pulses.

Note: The RX_CLK pin is multiplexed with the RXCLK pin.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII recei ve data bus. Data on RXD[3:0] is sampled on every rising edge of RX_CLK while RX_DV is asserted. RXD[3:0] is ignored while RX_DV is de-asserted.

Note: The RXD[0] pin is multiplexed with the RXFRTGD pin.

If the MII port is not sele cted, th e RXD[3:0] pin can be left floating.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that va lid received data is being presented o n the RXD[3:0] pins and RX_CLK is sync hronous to the receive data. In order for a frame to be fully received by the Am79C972 device on the MII, RX_DV must be asser ted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted pri or to the RX _CLK

rising edge which follows this final nibble. RX_DV transitions are synchronous to RX_CLK rising edges.

Note: The RX_DV pin is multiplexed with the RXFRTGE pin.

If the MII port is not selected, the RX_DV pin can be left floating.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receive frame currently being transferred on the RXD[3:0] pins. When RX_ER is asser ted whi le RX_DV is asserted, a CRC error will be indicated in the receive descriptor for the incoming receive frame. RX_ER is ignored while RX_DV is deasserted. Speci al co de group s gen erate d on RXD while RX_DV is deasserted are ig nored (e.g., Bad SSD in TX and IDLE in T4). RX_ER transitions are synchronous to RX_CLK rising edges.

Note: The RX_ER pin is multiplexed with the RXDAT pin.

MDC

Management Data Clock Out put

MDC is a non-continuous c lock output that provides a timing reference for bits on the MDIO pin. During MII management por t operations, MDC runs at a nominal frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW. The MDC is derived from the Time Base Clock.

If the MII port is not selected, the MDC pin can be left floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional M II management por t data pin. MDIO is an output during the header portion of the management frame transfers and dur ing the dat a portions of write transfers. MDIO is an input during the data portions of read data transfers. When an operation is not in progress on the management port, MDIO is not driven. M DIO tr ansiti ons fr om the Am79C9 72 contr oller are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connector, then the MDIO pin should be externally pulled down

SS with a 10-kΩ ±5% resistor. If the PHY is on

to V board, then the MDIO pin should be externally pulled up to V

CC with a 10-kΩ ±5% resistor.

22 Am79C972

General Purpose Serial Interface CLSN

Collision Input

CLSN is an input that indicates a collision has occurred on the network.

Note: The CLSN pin is multiplexed with the COL pin.

RXCLK

Receive Clock Input

RXCLK is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.

Note: The RXCLK pin is multiplexed with the RX_CLK pin.

RXDAT

Receive Data Input

RXDAT is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.

Note: The RXDAT pin is multiplexed with the RX_ER pin.

RXEN

Receive Enable Input

RXEN is an input. When this signal is HIGH, it indicates to the core logic that the data on the RXDAT input pin is valid.

Note: The RXEN pin is multiplexed with the CRS pin.

TXCLK

Transmit Clock Input

TXCLK is an input that provides a clock signal for MAC activity, both transmit and r ecei ve. The ri sing ed ges o f the TXCLK can be used to validate TXDAT output data.

Note: The TXCLK pin is multiplexed with the TX_CLK pin.

TXDAT

T ransmit Data Output

TXDAT is an output that provides the ser ial bit stream for transmission, including preamble, SFD, data, and FCS field, if applicable.

Note: The TXDAT pin is multiplexed with the TXD[0] pin.

TXEN

Transmit Enable Output

TXEN is an output that provides an enable signal for transmission. Data on the TXDA T pin is not valid unless the TXEN signal is HIGH.

Note: The TXEN pin is multiplexed with the TX_EN pin.

External Address Detection Interface EAR

External Address Reject Low Input

The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR’d with the value on the EAR pin. The EAR pin is defined as REJECT. The pin value is OR’d with the internal address detection result to determine if th e current frame sho uld be a ccepted or rejected.

The EAR be tied to VDD through a 10-k

When RST testing.

pin must not be left unconnect ed, it should

Ω ±5% resistor.

is active, EAR is an input for NAND tree

SFBD

Start Frame-Byte Delimiter Output For the GPSI port during External Address Detec-

tion:

An initial rising edge on the SFBD signal indicates that a start of frame delimiter has been detected. The serial bit stream will follow on the SRD signa l, commencing with the destination address field. SFBD will go high for 4 bit times (400 ns when operating at 10 Mbps) after detecting the second “1” in the SFD (St art of F rame De limiter) of a rece ived frame. SFBD will subsequent ly toggle every 4 bit times (1.25 MHz frequency when operating at 10 Mbps) with each rising edge indicating the first bit of each subsequen t byte of the received serial bit stream.

For the External PHY attached to the Media Independent Interface during External Address Detection:

An initial rising edge on the SFBD signal indicates that a start of valid data is present on the RXD[3:0] pins. SFBD will go high for one nibble time (400 ns when operating at 10 Mbps and 40 ns when operating at 100 Mbps) one RX_CLK perio d after RX_DV has been asserted and RX_ER is deasserted and t he detection o f the SFD (Start of Frame Delimiter) of a received frame. Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nibble time (1.25 MHz frequency when operating at 10 Mbps and 12.5 MHz fr equency when o peratin g at 10 0 Mbps) indicating the first nibble of each subsequent byte of the received nibble stream. The RX_CLK should be used in conjunction with t he SFBD to latch the correct data for external addre ss matching. SFBD will be active only during frame reception.

Note: The SFBD pin is multiplexed with the EESK and

pins.

LED1

Am79C972 23

SRD

Serial Receive Data Input/Output

SRD is the decoded NRZ data from th e n etwor k when in GPSI mode. This signal can be used for external address detection.

Note: When the MII port is selected, SRD will not generate transitions and receive data must be derived from the Media Independent Interface RXD[3:0] pins.

Note also that the SRD pin is multiplexed with the MIIRXFRTGD, EEDO, and LED3

pins.

SRDCLK

Serial Receive Data Clock Output

Serial Rece ive Data is synchronou s with reference to SRDCLK.

Note: When the MII port is selected, SRDCLK will not generate transitions and the receive clock must be derived from the MII RX_CLK pin.

Note also that the SRD CLK pin is mul tiplexed with the MIIRXFRTGE and LED2

pins.

RXFRTGD

Receive Frame T ag Data Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the MII is not selected , the RXFRTGD pin becomes a data input pin for the Receive Frame Tag. See the Receive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the RXD[0] pin.

RXFRTGE

Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the MII is not selected, the RX FRTGE pin becomes a data input enable pin for the Receive Frame Tag. See the Re ceive Frame Tagging section for de- tails.

Note: The RXFRTGE pin is multiplexed with the RX_DV pin.

MIIRXFRTGD

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXF RTG, CSR7, bit 14), and the MII is selected, the MIIRXFRTGD pin becomes a data i nput pin for the Recei ve Frame Tag. See the Receive Frame Tagging section for details.

Note: The MIIRXFRTGD pin is multiplexed with the SRD, EEDO, and LED3

pins.

MIIRXFRTGE

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the M II is selected, the MIIRXFRTGE pin becomes a data input enable pin for the Receive Frame Tag. See the Re ceive Frame Tagging section for de- tails.

Note: The MIIRXFRTGE pin is multiplexed with the SRDCLK and LED2

pins.

IEEE 1149.1 (1990) Test Access Port Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency of up to 10 MHz. TCK has an internal pull up resistor.

TDI

Test Data In Input

TDI is the test data input path to the Am79C9 72 controller. The pin has an internal pull up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C97 2 controller. The pin is tri-stated when the JT AG port is inactive.

TMS

Test Mode Select Input

A serial input bit stre am on the TMS pin is used to define the speci fic boundary scan test to be executed. The pin has an internal pull up resistor.

24 Am79C972

Power Supply Pins VDDB

I/O Buffer Power (7 Pins) Power

There are seven power supply pins that are used by the input/output buffer drivers. All VDDB pins must be connected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) Power

There are nine power supply pins tha t ar e us ed by the PCI input/output buffer drivers (except PME VDD_PCI pins must be connected to a +3.3 V supply.

driver). All

VSSB

I/O Buffer Ground (17 Pins) Power

There are 17 ground pins that are used by the input/ output buffer drivers.

VDD

Digital Power (6 Pins) Power

There are six power supply pins that are used by the internal digital c ir cuitry. All VDD pins must be connected to a +3.3 V supply.

VSS

Digital Ground (8 Pins) P ower

There are eight ground pins that ar e use d by the internal digital circuitry.

Am79C972 25

BASIC FUNCTIONS System Bus Interface

The Am79C972 controller is designed to operate as a bus master during nor mal operations. Some slave I/O accesses to t he Am79C972 controller are require d in normal operations as well. Initialization of the Am79C972 controller is achieved through a combination of PCI Configuration Space accesses, bus slave accesses, bus master acces ses, and an o ptional r ead of a serial EEPROM that is performed by the Am79C972 controller. The EEPROM read o peration is performed through the 93C46 EEPROM interface. The ISO 8802-3 (IEEE/A NSI 802.3) Ethernet Address may reside within the serial EEPROM. Some Am79C972 controller configuration registers may also be programmed by the EEPROM read operation.

The Address PROM, on-chip bo ard-configuration registers, and the Ether net contr oller register s occupy 32 bytes of address space. I/O an d memor y mapped I/O accesses are supported. Base Address registers in the PCI configuration sp ace allow locating the address space on a wide variety of starting addresses.

For diskless stations, the Am79C972 controller supports a ROM or Flash-based (both referred to as the Expansion ROM throughout this specification) boot device of up to 1 Mbyte in size. The host can map the boot device to any memory address that aligns to a 1-Mbyte boundary by modifyi ng the Expans ion ROM Base Address register in the PCI configuration space.

Software Interface

The software interface to the Am79C972 controller is divided into three parts. One part is the PCI configuration registers used to identify the Am79C972 controller and to setup the configuration of the device. The setup information includes the I/O or memory mapped I/O base address, mappin g of the Expansion ROM, an d the routing of the Am79 C9 72 controller interr upt cha nnel. This allows for a jumperless implementation.

or memory space (memory mapped I/O). The I/O Base Address Register i n th e P CI Configuration Space c ontrols the start address of the address space if it is mapped to I/O space. The Memor y Mapped I/O Base Address Register c ontrols the star t ad dress o f the address space if it is mapped to memory space. The 32byte address space is used by the software to program the Am79C972 con troller operating mo de, to enable and disable various features, to monitor o peratin g status, and to request par ticular functi ons to be executed by the Am79C972 controller.

The third por tion of th e software interface is the d escriptor and buffer areas that are shared between the software and the Am79C972 cont roller durin g normal network oper ations. The desc riptor area b oundaries are set by the software and do not chan ge dur ing normal network operations. There is one descriptor area for receive activity and there is a separate area for transmit activity. The descriptor space contains relocatable pointers to the network frame data, and it is used to transfer frame status from the Am79C972 controll er to the software. The buffer areas are locations that hold frame data for transmission or that acce pt frame data that has been received.

Network Interfaces

The Am79C972 controller can be connected to an IEEE 802.3 or propr ietar y network v ia one of two network interfaces. The Media Independent Interface (MII) provides an IEEE 802.3-complian t nibble-wide interface to an external 100- and/or 10 -Mbps transceiver device. The General Purpose Serial Interface (GPSI) is functionally equivalent to the GPSI found on the LANCE.

While in auto-selection mode, the interface in use is determined by the Network Port Manager. If the quiescent state of the MII MDIO pin is HIGH, the MII is activated. The GPSI por t can only be enabled by disabling the auto-selection and manually selecting the GPSI as the network port.

The second por tion of the software interface is the d irect access to the I/O resources of the Am79C972 controller. The Am79C972 controller occup ies 32 bytes of address space that must begin on a 32-byte block boundary. The address space can be mapped into I/O

26 Am79C972

The Am79C972 controller supports both half-duplex and full-duplex operation on network interfaces (i.e., GPSI and MII).

DETAILED FUNCTIONS Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Sta tus Registers (CSR), the Bu s Configuration Registers (BCR), the Ad dress PROM (APROM) lo cations, and the Expansion ROM. Table 2 shows the response of the Am79C972 controller to each of the PCI commands in slave mode.

Table 2. S lave Commands

C[3:0] Command Use

0000

0001 Special Cycle Not used

0010 I/O Read

0011 I/O Write

0100 Reserved 0101 Reserved

0110 Memory Read

0111 Memory Write

1000 Reserved 1001 Reserved

1010

1011

1100

1101

1110

1111

Interrupt Acknowledge

Configuration Read

Configuration Write

Memory Read Multiple

Dual Addres s Cycle

Memory Read Line

Memory Write Invalidate

Not used

Read of CSR, BCR, APROM, and Reset registers

Write to CSR, BCR, and APROM

Memory mapped I/O read of CSR, BCR, APROM, and Reset registers Read of the Expansion Bus

Memory mapped I/O write of CSR, BCR, and APROM

Read of the Configuration Space

Write to the Configuration Space

Aliased to Memory Read

Not used

Aliased to Memory Read

Aliased to Memory Write

Slave Configuration Transfers

The host can access the Am79C972 PCI configuration space with a configuration read or write command. The Am79C972 controller will assert DEVSEL address phase when IDSEL is asserted, AD[1:0] are both 0, and the access is a configuration cycle. AD[7:2]

during the

select the DWord location in the configuration space. The Am79C972 controller ignores AD[10:8], because it is a single function device. AD[31:11] are don’t care.

AD31 AD11

Don’t care Don’t care

AD10 AD8

AD7 AD2

DWord index

AD1 AD0

The active bytes within a DWord are determined by the byte enable signals. Eight-bit, 16-bit, a nd 32-bit transfers are supported . DEVSEL cles after the host has asserted FRAME

is asserted two clock cy-

. All configuration cycles are of fixed length. The Am79C972 controll er will asser t TRDY

on the third

clock of the data phase. The Am79C972 controller does not support burst trans-

fers for access to config uration space. When th e host keeps FRAME

asserted for a second data phase, the

Am79C972 controller will disconnect the transfer. When the host tries to access the PCI configuration

space while the automatic r ead of the EEPROM after H_RESET (see section on RESET) is on-going, the Am79C972 control ler will ter minate the access on the PCI bus with a disconnect/retry response.

The Am79C972 controller supports fast back-to-back transactions to different targets. This is indicated by the Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardw ired to 1. The Am79C97 2 controller is capable of detecting a configuration cycle even when its address phas e immediate ly follows the data phas e of a transaction to a different target without a ny idle state in-between. There will be no contention on the DEVSEL Am79C972 controll er asser ts DEV SEL clock after FRAME

, TRDY, and STOP signals, since the

on the second

is asserted (medium timing).

Slave I/O Transfers

After the Am79C972 co ntroller is c onfigured as an I/O device by setting IOEN (for regular I/O mode) or MEMEN (for memory mapped I/O mode) in the PCI Command register, it starts monito r ing the PCI bus for access to its CSR, BCR, or APROM locations. If configured for regular I/O mode, the Am79C972 cont roller will look for an address that falls within its 32 bytes of I/ O address space (starting from the I/O base add re ss) . The Am79C972 controller asserts DEVSEL an address mat ch and the access is an I/O cycle. If configured for memory mapped I/O mode, the Am79C972 controller wil l look for an address that falls within its 32 bytes of me mory address spa ce (star ting from the memory mapped I/O base address). The Am79C972 controll er asser ts DEVSEL address match and the access is a memory cycle. DEVSEL asserted FRAME

is asserted two clock cycles after the host has

. See Figure 1 and Figure 2.

if it detects

if it detects an

Am79C972 27

CLK

FRAME

1 23456

ADDR

DATA

the internal Buffer Manage ment Unit clock is a divideby-two version of the CLK signal.

The Am79C972 controller does not support burst transfers for access to its I/O resources. When the host keeps FRAME

asserted for a second data phase, the

Am79C972 controller will disconnect the transfer.

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

IDSEL

1010

PAR PAR

DEVSEL is sampled

21485C-4

Figure 1. Slave Configuration Read

The Am79C972 controller will not asser t DEVSE L

if it detects an address match, but the PCI command is not of the correct type. In memor y mapped I/O mode, the Am79C972 controller aliases all accesses to the I/O resources of the com man d ty pes Mem ory Read Multipl e and Memory Read Line to the basic Memory Read com- mand. All accesses of the typ e Memory Write and In- validate are aliased to the basic Memory Write command. Eight-bit, 16-bit, and 32-bit non-burst transactions are suppor ted. The Am79C972 controller decodes all 32 address lines to determine which I/O resource is accessed.

The typical number of wait st ates ad ded to a s lave I/O or memory mapped I/O read or write access on the part of the Am79C972 controller is six to seven clock cycles, depending upon the relative phases of the internal Buffer Management Unit clock and the CLK signal, sinc e

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

IDSEL

1 23456

ADDR

1011

PAR

DATA

PAR

21485C-5

Figure 2. Slave Configuration Write

The Am79C972 controller s upports fast back-to-back transactions to different targets. This is indicated by the Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardw ired to 1. The Am79C97 2 controller is capable of detecting an I/O or a memor y-mapped I/O cycle even when its address phase immediately follows the data phase of a transaction to a different target, without any idle state in-between. There will be no contention on the DEVSEL the Am79C972 controller asserts DEVSEL ond clock after FRAME

, TRD Y , and STOP signals, since

on the sec-

is asserted (medium timing) See

Figure 3 and Figure 4.

28 Am79C972

CLK

FRAME

1 2345678

109

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

ADDR

0010

PAR

Figure 3. Slave Read Using I/O Command

DATA

PAR

21485C-6

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

1 2345678

ADDR

0111

PAR

DATA

PAR

Figure 4. Slave Write Using Memory Command

109

21485C-7

Am79C972 29

Expansion ROM Transfers

The host must initiali ze the Expansion ROM Base Address register at offset 30H in the PCI configura tion space with a valid addre ss before enabling the access to the device. The Am79C972 controller will not react to any access to the Expansion ROM until bo th MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to 1. After the Ex pansion ROM is en abled, the Am79C9 72 controller will assert DEVSEL

on all memor y read accesses with an address between ROMBAS E and ROMBASE + 1M - 4. The Am79C972 controller aliases all accesses to the Expansion ROM of the command types Me mory Read Multiple and Memory Read Line to the basic Memory Read command. Eight-bit, 16-bit, and 32-bit read transfers are supported.

Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given the PCI Memor y Mapped I/O Base Address reg ister before enabling access to the Expansion ROM. The host must set the PCI Memor y Mapped I/O Bas e Ad-

dress register to a value that prevents the Am79C972 controller from claiming any memory cycles not intended for it.

The Am79C972 controller will always read four bytes for every host Expansion ROM read access. TRDY

will not be asserted until all four bytes are loaded into an internal scratch regis ter. The cycle TRDY

is asserted depends on the programming of the Expansion ROM interface timing. The following figure (F igure 5) assumes that ROMTMG (BCR18, bits 15- 12) is at its default value.

Note: The Expansion ROM should be read only during PCI configuration time for the PCI system.

When the host tries to write to the Expansion ROM, the Am79C972 controll er will claim the cycle by asser ting DEVSEL

. TRDY will be asserte d one clock cycle la ter. The write operation will have no effect. Writes to the Expansion ROM are done through the BCR30 Expansion Bus Data Port. Se e the sect ion on the Expansion Bus Interface for more details. See Figure 5.

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

1 2345 484950

ADDR

CMD

PAR

DATA

PAR

DEVSEL is sampled

Figure 5. Expansion ROM Read

30 Am79C972

21485C-8

During the boot procedure, the system will try to find an Expansion ROM. A PCI sys tem assumes that an Ex pansion ROM is present when it reads the ROM signature 55H (byte 0) and AAH (byte 1).

CLK

1 2345

Slave Cycle Termination

There are three scenar ios besides normal comp letion of a transaction where the Am79C9 72 control ler is th e target of a slave cycle and it will terminate the access.

Disconnect When Busy

The Am79C972 controller cannot service any slave access while it is reading the contents of the EEPROM. Simultaneous access is not allowed in order to avoid conflicts, since the EEPROM is used to initialize some of the PCI configuration space locations and most of the BCRs and CSR 116. The E EP ROM rea d o pera tio n will always happen automatic ally af ter the deas sertion of the RST

pin. In addition, the host can start the read operation by setting the PREAD bit (BCR19, bit 14) . While the EEPROM rea d is on-going, the A m79C972 controller will dis connect any slave access where it is the target by asser ting STOP while driving TRDY

high. STOP will stay asserted until

together with DEVSEL,

the end of the cycle. Note that I/O and memo r y s lave accesses will only be

disconnected if they are enabled by setting the IOEN or MEMEN bit in the PCI Co mmand registe r. Without the enable bit set, the cycles will not be claimed at all. Since H_RESET clears the IOEN and MEMEN bits for the automatic EEPROM read after H_RE SET, the disconnect only applies to conf igu rati on cycl es.

A second sit uat ion w her e th e Am 79C9 72 c ont roll er w ill generate a PCI disconnect/retry cycle is when the host tries to access any of the I/O resources right after having read the Reset register. Since the access generates an intern al re set pul se of abo ut 1

µs in length, all

further slave accesses will be deferred until the internal reset operation is completed. See Figure 6.

Disconnect Of Burst Transfer

The Am79C972 controller does not support burst access to the configuration space, the I/O resources, or to the Expansion Bus. The host indicates a burst transaction by keeping FRAME

asserted during the data phase. When the Am79C972 controller sees FRAME and IRD Y asse rted in the cl ock cycle before it wants to asser t TRDY

, it also asserts STOP at the same time. The transfer of th e first dat a phase is st ill succes sful, since IRDY

and TRDY are both asserted. See Figure 7.

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

ADDR

CMD

DATA

PAR PAR

21485C-9

Figure 6. Disconnect Of Slave Cycle When Busy

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

1 2345

1st DATA

PAR

DATA

PAR

21485C-10

Figure 7. Disconnect Of Slave Burst T ransfer - No

Host Wait States

Am79C972 31

If the host is not yet ready when the Am79C972 control-

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

1 23456

PAR

DATA

1st DATA

ler asserts TRDY sert IRDY

. When the host asserts IRDY and FRAME is

, the device will wait for the host to as-

still asserted, the Am79C972 controller will finish the first data phase by deasser ting TRDY At the same time, it will assert STOP nect to the host. STOP removes FRAME

will stay asserted until the host

. See Figure 8.

one clock later.

to signal a discon-

an address parity er ror when PERREN and SE RREN are set to 1. See Figure 9.

CLK

1 2345

FRAME

21485C-11

Figure 8. Disconnect Of Slave Burst Transfer -

Host Inserts Wait States

Parity Error Response

When the Am79C972 control ler is not the current bus master, it samples the AD[31:0], C/BE

[3:0], and the PAR li nes during the address phase of any PCI command for a parity error. When it detects an address parity error, the controller sets PERR (PCI Status register, bit 15) to 1. When repo r tin g of that erro r is ena bled by setting SERREN (PCI Command register, bit 8) an d PERREN (PCI Command register, bit 6) to 1, the Am79C972 control ler also dr ives the SE RR

signal low for one clock cycle and sets SERR (PCI Status register, bit 14) to 1. The assertion of SERR

follows the address phase by two clock cycle s. The Am79C972 controller will not assert DEVSEL

for a PCI transaction that has

C/BE

PAR

SERR

DEVSEL

ADDR

CMD

1st DATA

PAR

21485C-12

Figure 9. Ad dress Parity Error Response

During the data phase of an I/O write, memory-mapped I/O write, or config uration write co mmand that selec ts the Am79C972 controller as target, the device samples the AD[31:0] and C/BE

[3:0] lines for parity on the clock edge, and data is transferred as indicated by the assertion of IRD Y

and TRD Y. PAR is sampled in the following clock cycle. If a parity error is detected and reporting of that error is enabled by setting PERREN (PCI Command register, bit 6) to 1, PERR

is asser ted one clock later. The parity error will always set PERR (PCI Status register, bit 15) to 1 even when PERREN is cleared t o

0. The Am79C972 controller will finish a transaction that has a data parity error in the normal way by asserting TRDY

. The corrupted data wi ll be written to the ad-

dressed location. Figure 10 shows a t ransaction that su ffered a parity

error at the time data was transferred (clock 7, IRDY and TRDY are both asserted). P ERR is driven high at the beginning of the data phase and then drops low due to the parity error on clock 9, two clock cycles after the data was transferred. After PERR Am79C972 controller drives PERR cycle, since PERR

is a sustained tri-state signal.

is driven low, the

high for one clock

32 Am79C972

CLK

FRAME

1 2345678

109

C/BE

PAR

PERR

IRDY

TRDY

DEVSEL

ADDR

CMD

PAR

Figure 10. Slave Cycle Data Parity Error Response

Master Bus Interface Unit

The master Bus Interface Unit (BIU) controls the acquisition of the PCI bus and all acc esses to the initi alization block, descriptor rings, and the receive and transmit buffer memory. Table 3 shows the usage of PCI commands by the Am 79C 972 c ontr o lle r i n m as ter mode.

Table 3. Master Commands

C[3:0] Command Use

0000 0001 Special Cycle Not used

0010 I/O Read Not used 0011 I/O Write Not used 0100 Reserved 0101 Reserved

0110 Memory Read

Interrupt Acknowledge

Not used

Read of the initialization block and desc riptor rings Read of the transmit buffer in non-burst mode

DATA

PAR

21485C-13

Table 3. Master Commands (Continued)

0111 Memory Write Write to the descriptor

rings and to the receive buffer

1000 Reserved

C[3:0] Command Use

1001 Reserved 1010 Configuration Read Not used 1011 Configuration Write Not used

1100 1101 Dual Address Cycle Not used 1110 Memory Read Line

1111

Memory Read Multiple

Memory Write Invalidate

Read of the transmit buffer in b u rst mo de

Not used

Bus Acquisition

The Am79C972 microcode will determine when a DMA transfer should be initi ated. The first step in any Am79C972 bus master transfer is to acquire ownership of the bus. This task is hand led by synchronous logic within the BIU. Bus ownership is requested with the

signal and ownership is granted by the arbiter

REQ through the GNT

signal.

Am79C972 33

Figure 11 shows the Am79C972 controller bus acquisition. REQ

is asserted and the arbiter returns GNT while another bus master is transferring data. The Am79C972 controller waits until the bus is idle (FRAME and IRDY deasser ted ) before it star ts dr ivi ng AD[31:0 ] and C/BE

[3:0] on clock 5. FRAME is asserted at clock 5 indicating a valid address and command on AD[31:0] and C/BE

[3:0]. The Am79C972 controller does not use address stepping which is reflected by ADSTEP (bit 7) in the PCI Command register being hardwired to 0.

CLK

FRAME

1 2345

controller non-burst read acces ses are of the PCI command type Memory Read (type 6). Note that during a non-burst read operation, all byte lanes will always be active. The Am79C972 controller will internally discard unneeded bytes.

The Am79C972 controller typically performs more than one non-burst read transaction within a single bus mastership per iod. FRAME tive non-burst read cycles. REQ asserted until F RAME

is dropped between consecu-

however stays

is asser ted for the last tran saction. The Am79C972 controller supports zero wait state read cycles. It asserts IRDY

immediately after the address phase and at the same time starts sampling DEVSEL

. Figure 12 shows two non-burst read transactions. The first transaction has zero wait s tates. In the second transaction, the target extends the cycle by asserting TRDY

one clock later.

C/BE

IRDY

REQ

GNT

ADDR

CMD

21485C-14

Figure 11. Bus Acquisition

In burst mode, the deassertion of REQ

depends on the setting of EXTREQ (BCR18, bit 8). If EXTREQ is cleared to 0, REQ FRAME

is asser ted. (The Am79C972 contr oller never

is deasser ted at the same time as

performs more than one burst transaction with in a single bus mastership per iod.) If EXTRE Q is set to 1, th e Am79C972 controller does not deass ert REQ

until it

starts the last data phase of the transaction. Once asserted, REQ

remains active until GNT has become active and independent of su bs equ ent s etting o f STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The assertion of H_RESET or S_RESET, however, will cause

to go inactive immediately.

REQ

Bus Master DMA Transfers

There are four primary types of DMA transfers. The Am79C972 controller uses non-burst as well as burst cycles for read and write access to the main memory.

Basic Non-Burst Read Transfer

By default, the Am79C972 controller uses non-burst cycles in al l bus mast er read ope rations . All Am79C 972

Basic Burst Read Transfer

The Am79C972 controlle r supports burst mod e for all bus master read operations. The burst mode must be enabled by setting BREADE (BCR18, bit 6). To allow burst transfers in descriptor read o perations, the Am79C972 controller must also be programmed to use SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses to the initiali zation block and descr iptor r ing ar e of th e PCI command type Memo ry Read (type 6). Burst rea d accesses to the transmit buffer typically are longer than two data phases. When MEMCMD (BCR18, bit 9) is cleared to 0, all burst read accesses to the transmit buffer are of the PCI command type Memory Read Line (type 14). When MEMCMD (BCR18, bit 9) is set to1, all burst read accesses to the transm it buffer are of the PCI command type Memory Read Multiple (type 12). AD[1:0] will both be 0 during the address phase indicating a linear burst or der. Note that during a burst rea d operation, all byte lanes will always be active. The Am79C972 controller will internally discard unneeded bytes.

The Am79C972 controller will always perform only a single burst read transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. The Am79C972 controller supports zero wait state read cycles. It asserts IRDY

immediately after the address phase and at the s ame time star ts sampling DEVSEL FRAME

is deasserted when the next to last data phase

is completed. Figure 13 shows a typical burst read ac cess. The

Am79C972 controller arbitrates for the bus, is granted access, reads three 32-bit words (DWord) from the system memory, and then releases the bus. In the example, the memory system extends the data phase of each access by one wait state. The example assumes that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,

is deasserted in the same cycle as FRAME is as-

REQ serted.

34 Am79C972

CLK

FRAME

1 2345678

109

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

ADDR

0110

DEVSEL is sampled

Figure 12. Non-Burst Read Transfer

PAR

0000

DATA

ADDR

0110

PAR PAR

DATA

0000

PAR

21485C-15

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 2345678

ADDR

PAR

DEVSEL is sampled

DATA

00001110

PAR PAR

DATA

Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0)

DATA

109

PAR

21485C-16

Am79C972 35

Basic Non-Burst Write Transfer

By default, the Am79C972 controller uses non-burst cycles in all bus master write operations. All Am79C972 control ler non-burst write ac cesses are of the PCI command type Memory Write (type 7). The byte enable signals indicate the byte lanes that have valid data.The Am79C972 controller typically performs more than one non-burst write transaction within a single bus mastership period. FRAME

is dropped between consecutive non-burst write cycles. REQ however, stays asserted until FRAME

is asserted for the last transaction. The Am79C972 supports zero wait state write cycles except with descriptor write transfers. (See the section Descriptor DMA Transfer s f or the only exception.) It asserts IRDY

immediately after the ad-

dress phase. Figure 14 shows two non-burst write transacti ons. Th e

first transaction has two wait states. The target i nserts one wait st ate by as serting DEVSEL another wait state by also asserting TRDY

one clock late and

one clock late. The second transaction shows a zero wait state write cycle. The targ et assert s DEVSEL

and TRDY in

the same cycle as th e Am79C972 controlle r asserts

IRDY

Basic Burst Write Transfer

The Am79C972 controlle r supports burst mod e for all bus master write operation s. The burst mode must be enabled by setting BWRITE (BCR18, bit 5). To allow burst transfers in descriptor write operations, the Am79C972 controller must also be programmed to use SWSTYLE 3 (BCR20, bits 7-0). All Am79C972 controller burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be 0 during the

address phase indicating a linear burst order. The byte enable signals indicate the byte lanes that have valid data.

The Am79C972 c ontrolle r wi ll always perfor m a s ingle burst write transaction per bus mastership period, where transaction is defined as one address phase and one or mult iple dat a phase s. Th e Am79C 972 cont rol ler supports zero wait state write cycles except with the case of desc ript o r w rite transf er s . (S ee t h e s ec ti o n De- scriptor DMA Tr ansfers f or the only exception.) The device asserts IRDY

immediately after the address phase and at the same tim e starts sampling DE VSEL FRAME

is deasserted when the next to last data phase

is completed.

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 2345678

ADDR

0111

DEVSEL is sampled

PAR

DATA

PAR

ADDR

0111

DATA

PAR

109

PAR

21485C-17

Figure 14. Non-Burst Write Transfer

36 Am79C972

Figure 15 shows a typical burst write access. The Am79C972 controller arb itrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memor y and then re leases the bus. In this example, the memory system extends the data phase of the first access by one wait state. The following three data phases take one clock cycle each, which is determined by the timing of TRDY

. The example assumes that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ is not deasserted until the next to last data phase is finished.

Target Initiated Termination

When the Am79C972 controller is a bus master, the cycles it produces on t he PCI bus may be termin ated by the target in one of three different ways: disconnect

with data transfer, disconnect without data transfer, and target abort.

Disconnect With Data Transfer

Figure 16 shows a disconnection in which one last data transfer occurs after the target asser ted STOP

. STOP is asser ted on clock 4 to start the te rmination sequence. Data is still transferred during this cycle, since both IRDY

and TRDY are ass erted. The Am 79C972 controller terminates the current transfer with the deassertion of FRAME

on clock 5 and of IRDY one clock later. It finally releases the bus on clock 7. The Am79C972 controller will again request the bus after two clock cycles, if it wants to transfer more data. The starting address of the new transfer will be the address of the next non-transferred data.

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

12345678

ADDR

0111

PAR

DATA

DATA DATA

PAR

PAR PAR

DATA

PAR

GNT

DEVSEL is sampled

Figure 15. Burst Write Transfer (EXTREQ = 1)

Am79C972 37

21485C-18

CLK

FRAME

23456789

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

REQ

GNT

ADDR

DATA

PAR

DATA

00000111

PAR

ADDRi+8

0111

DEVSEL is sampled

Figure 16. Disconnect With Data Transfer

Disconnect Without Data Transfer

Figure 17 shows a tar get disconne ct se quence dur ing which no data is transferred. STOP 4 without TRDY

being asserted at the sam e tim e. The

is asserted on clock

Am79C972 controller terminates the access with the deassertion of FRAME

on clock 5 and of IRDY one clock cycle later. It finally releases the bus on cl ock 7. The Am79C972 controll er will again request the bus after two clock cycles to retry the last transfer. The starting address of the new transfer will be the address of the last non-transferred data.

Target Abort

Figure 18 shows a target abort sequ ence. The target asserts DEVSEL DEVSEL

and asser ts STOP on clock 4. A target can

for one clock. It then deasserts

use the target abor t sequence to indicate that it cannot service the data transfer and that it does not want the transaction to be retried. Additionally, the Am79C972 controller cannot make any assumption

21485C-19

about the success of the previous data transfers in the current transaction. The Am79C 972 controller terminates the current transfer with the deassertion of FRAME

on clock 5 and of IRDY one clock cycle later.

It finally releases the bus on clock 6. Since data integrity is not guaranteed, the Am79C972

controller cannot recover from a target abort event. The Am79C972 controller will reset all CSR locations to their STOP_RESET values. The BCR and PCI confi guration registers will not be clea red. Any on-goin g network transmission is terminated in an orderly sequence. If less than 512 bi ts have been transmitted onto the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or more have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

38 Am79C972

CLK

FRAME

23456789

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

REQ

GNT

ADDR

DEVSEL is sampled

DATA

00000111

PAR

ADDR

0111

21485C-20

Figure 17. Disconnect Without Data Transfer

RTABORT (PCI Status register, bit 12) will be set to indicate that the Am 79C972 control ler has received a target abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is set , INTA

is assert ed if t he enable bit SINTE (CSR5, bit 10 ) is set to 1. This me chanism can be used to inform the driver of the system error. The host can read the PCI Status reg ister to de termine the exact cause of the interrupt.

Master Initiated Termination

There are three scenar ios besides normal comp letion of a transaction wher e the Am79C972 cont roller will terminate the cycles it produces on the PCI bus.

Preemption During Non-Burst Transaction

When the Am79C972 controller performs multiple nonburst transactions, it keeps REQ sertio n of FRAME

for the last transaction. When GNT

asser ted until the as-

is removed, the Am79C972 controller will finish the current transaction and then release the bus. If it is not the

last transaction, REQ

will remain asserted to regain

bus ownership as soon as possible. See Figure 19.

Preemption During Burst Transaction

When the Am79C972 controller operates in burst mode, it only performs a single transaction per bus mastership period, where transaction is defined as one address phas e and one or mu ltiple data phases. The central arbiter can remove GNT

at any time dur ing th e transaction. The Am79C972 controller will ignore the deasser tion of GN T

and continue with data t ransfers, as long as the PCI Latency Timer is not expired. When the Latency Timer is 0 and GNT

is deasserted, the Am79C972 controller will finish the current data phase, deassert FRAM E

, finish the last data pha se, and release the bus. If EXTREQ (BCR18, bit 8) is clea red to 0, it will immediately ass er t REQ

to regain bus ownership as soon as possible. If EXTREQ is set to 1, R EQ will stay asserted.

Am79C972 39

CLK

FRAME

C/BE

234567

ADDR

0111

DATA

0000

The Am79C972 c ontroller will re set all CSR lo cations to their STOP_RESET values. The BCR and PCI configuration registers will not be cle ared. Any on-going network transmissi on is terminated in an orderly se quence. If less than 512 bits have been transmitted onto the network, the transmission will be terminated immediately, generating a runt packet. If 512 bits or more have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

PAR

IRDY

TRDY

DEVSEL

STOP

REQ

GNT

DEVSEL is sampled

PAR PAR

21485C-21

Figure 18. Target Abort

When the preempti on occurs after the counter has counted down to 0, the Am79C972 controller will finish the current data phase, deas sert F RAME

, finish the last data phase, and release the bus. Note that it is important for the host to program the PCI Lat ency Timer according to the bus bandwidth requirement of the Am79C972 controller. The host can determine this bus bandwidth re quirement by re ading the P CI MAX_LAT and MIN_GNT registers.

Figure 20 assumes that the PCI Latency Timer has counted down to 0 on clock 7.

Master Abort

The Am79C972 controller will terminate its cycle with a Master Abort sequence if DEVSEL within 4 clocks after FRAME

is asserted. Master Abort

is not asserted

is treated as a fatal error by the Am79C9 72 controll er.

RMABORT (in the PCI Status register, bit 13) will be set to indicate that the Am79C972 controller has terminated its transaction with a master abort. In addition, SINT (CSR5, bit 11) will be set to 1. When SINT is set,

is asserted if the enable bit SINTE (CSR5, bit 10)

INTA is set to 1. This mechanism can be used to inform the driver of the system erro r. The host can read the PCI Status register to deter mine the exact cause of the interrupt. See Figure 21.

Parity Error Response

During every data phase of a DMA r ead operation, when the target in dicates that the d ata is valid by asserting TRDY AD[31:0], C/BE

, the Am79C972 controller samples the

[3:0] and the PAR lines for a data parity error. When it detects a data parity error, the controller sets PERR (PCI Status regist er, bit 15) to 1. When reporting of that error is en abled by setting PERREN (PCI Command register, bit 6) to 1, the Am79C972 controller also drives the PERR

signal low and sets DATAPERR (PCI Status register, bit 8) to 1. The assertion of PERR

follows the corrupted data/byte enables

by two clock cycles and PAR by one clock cycle. Figure 22 shows a transaction that has a parity error in

the data phase. The Am79C972 controller asser ts

on clock 8, two clock cycles after data is valid.

PERR The data on clock 5 is not checked for parity, since on a read access PAR is only required to be valid one clock after the target has asserted TRDY Am79C972 controller then drives PERR clock cycle, since PERR

is a sustained tri-state signal.

high for one

. The

During every data phase of a DMA write operation, the Am79C972 controll er checks the P ERR

input to see if the target reports a parity error. When it sees the PERR input asserted, the controller sets PERR (PCI Status register, bit 15) to 1. When PERREN (PCI Command register, bit 6) is set to 1, the Am79C972 controller also sets DATAPERR (PCI Status register, bit 8) to 1.

40 Am79C972

CLK

FRAME

1 234567

PAR

DATA

BE0111

PAR

C/BE

PAR

ADDR

IRDY

TRDY

DEVSEL

REQ

GNT

DEVSEL is sampled

Figure 19. Preemption During Non-Burst Transaction

21485C-22

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 234

DEVSEL is sampled

ADDR

DATA

PAR PAR PAR

PAR

DATA

BE0111

DATA

Figure 20. Preemption During Burst Transaction

DATA

PAR

21485C-23

Am79C972 41

CLK

FRAME

1 234

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

ADDR

0111

DEVSEL is sampled

Figure 21. Master Abort

PAR

DATA

0000

PAR

21485C-24

CLK

FRAME

C/BE

PAR

PERR

IRDY

TRDY

DEVSEL

1 234

DEVSEL is sampled

ADDR

0111

PAR

DATA

PAR

Figure 22. Maste r Cycle Data Parity Error Response

21485C-25

42 Am79C972

Whenever the Am79C972 controller is the cu rrent bus master and a dat a pa rity error occurs, SINT (CS R 5, b it

11) will be set to 1. When SINT is set, INTA if the enable bit SINTE (CSR5, bi t 10) is set to 1 . This mechanism can be used to inform the driver of the system error. The host can read the PCI Status register to determine the exact cause of the interr u pt. Th e set tin g of SINT due to a data par ity e rror is no t depen dent o n the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the state of the MAC engine. The Am79C972 controller treats the data in all bus master transfers that have a parity error as if nothing has happened. All network activity continues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C972 cont ro ller provides a second, more advanced level of parity error handling. This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits (RMD1 and TMD1, bi t 23) are used to indic ate parity error in data transfers to the receive and transmi t buffers. Note that since the advanced parity error handling uses an additional bit in the descriptor, SWSTYLE (BCR20, bits 7-0) must be set to 2 or 3 to pr ogram the Am79C972 controller to use 32-bit software structures. The Am79C972 controller will react in the following way when a data parity error occurs:

is asserted

n Initialization block read: STOP (CSR0, bit 2) is set to

1 and causes a STOP_RESET of the device.

n Descriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP (CSR0, bit 2) is set to 1 to cause a STOP_RESET of the device.

n Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP (CSR0, bit 2) is set to 1 to cause a STOP_RESET of the device.

n Transmit buffer read: BPE (TMD1, b it 23) is set in

the current transmit descriptor. Any on-going network transmission is terminated in an orderly sequence.

n Receive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Ter minating on-going n etwork transmission in an or derly sequ ence means that if less than 512 bits have been transmitted onto th e network, the transmissio n

will be terminated immediately, generating a runt packet.

If 512 bits or more have been transmitted, the message will have the current FCS inverted and appended at the next byte boundary to guarantee an FCS error is detected at the receiving station.

APERREN does not affect the repor ting of address parity errors or dat a parity errors that oc cur when the Am79C972 controller is the target of the transfer.

Initialization Block DMA Transfers

During execution of the Am79C972 controller bus master initializ ation proced ure, the Am79C9 72 microcod e will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU will perform two data transfer cycles reading one DWord per transfer and then it will relinquish the bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the initialization block is organized as 32-bit software structures), there are seven DWords to transfer during the bus master initialization procedure, so four bus mastership periods are needed in order to complete the initialization sequence. Note that the last DWord transfer of the last bus mastership period of the initialization sequence accesses an unneeded location. Data from this transfer is discarded internally. When SSIZE32 is cleared to 0 (i.e., the initialization block is organized as 16-bit software structures) , then three bus mastership periods are ne eded to complete th e initialization s equence.

The Am79C972 supports two transfer modes for reading the initialization block: non-burst and burst mode, with burst mode being the preferred mode when th e Am79C972 controlle r is used in a PCI bus applica tion . See Figure 23 and Figure 24.

When BREADE is cleared to 0 (BCR18, bit 6), all initialization block read transfers will be executed in nonburst mode. There is a new address phase for every data phase. FRAME transfers. The two phases within a bus mastership period will have addresses of ascending contiguous order.

When BREADE is set to 1 (B CR18 , bi t 6), al l i niti al ization block read transfers will be executed in burst mode. AD[1:0] will be 0 during the address phase indicating a linear burst order.

will be dropped between the two

Am79C972 43

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 2345678

IADD

DEVSEL is sampled

DATA

00000110

PAR

IADDi+4

0110

PAR

DATA

0000

PAR

109

PAR

21485C-26

Figure 23. Initialization Block Read In Non-Burst Mode

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

1 234567

IADD

DATA DATA

00000110

PAR PAR PAR

GNT

DEVSEL is sampled

Figure 24. Initialization Block Read In Burst Mode

44 Am79C972

21485C-27

Descriptor DMA Transfers

Am79C972 microcode will determine when a descriptor access is required. A descriptor DMA read will consist of two data transfers. A descriptor DMA write will consist of one or two data transfers. The descriptor DMA transfers within a single bus mastership period will always be of the same type (either all read or all write).

During descri ptor read accesses, the byte enable signals will indicate that all byte lanes ar e active. Should some of the bytes not be needed, then the Am79C972 controller will internally discard the extraneous information that was gathered during such a read.

The settings of SWSTYLE (BCR20, bits 7-0) and BREADE (BCR18, bit 6) affect the way the Am79C972 controller performs descriptor read operations.

When SWSTYLE is set to 0 or 2, all descriptor read operations are performed in non-burst mode. The setting of BREADE has no effect in this configuration. See Figure 25.

When SWSTYLE is s et to 3 , the de sc riptor entrie s are ordered to allow burst transfers. The Am79 C972 controller will pe rform all descri ptor read operation s in burst mode, if BREADE is set to 1. See Figure 26.

Table 4 shows the descriptor read sequence. During descriptor write accesses, only the byte lanes

which need to be written are enabled. If buffer chaining is used, acc esses to the d escriptors

of all intermediate buffers consist of only one data transfer to return ownership of the buffer to the system. When SWSTYLE ( BCR20, bi ts 7-0) is cleare d to 0 (i.e ., the descriptor entries are orga nized as 16-bi t s oft ware structures), the descriptor access will write a single byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or 3 (i.e., the descriptor entries are organized as 32-bit software structures ), the descripto r access will wr ite a single word. On all single buffer transmit or receive descriptors, as well as on the last buffer in chain, writes to the descriptor consist of two data transfers.

The first data transfer writes a DWord containing status information. The second data transfer writes a byte (SWSTYLE cleared to 0), or otherwise a word containing additional status and the ownership bit (i.e., MD1[31]).

The settings of SWSTYLE (BCR20, bits 7-0) and BWRITE (BCR18, bit 5) affect the way the Am79C972 controller performs descriptor write operations.

When SWSTYLE is set to 0 or 2, all descriptor write operations are performed in non-burst mode. The setting of BWRITE has no effect in this configuration.

When SWSTYLE is s et to 3 , the de sc r ip t or en tries are ordered to allow burst transfers. The Am79C972 controller will perform all desc riptor write operations in burst mode, if BWRITE is set to 1. See Table 5 for the descriptor write sequence.

A write transaction to the descr iptor rin g entries is the only case where the Am79C972 controller inserts a wait state when being the bus master. Every data phase in non-burst and burst mode is extended by one clock cycle, during which IRDY

is deasserted.

Note that Figure 26 assumes that the Am79C972 controller is programmed to use 32- bi t so ftware structures (SWSTYLE = 2 or 3). The byte enable signals for the second data transfer would be 0111b, if the device was programmed to use 16-bit software structures (SWSTYLE = 0).

Table 4. Descriptor Read Sequence

SWSTYLE BCR20[7:0]

BREADE BCR18[6] AD Bus Sequence

Address = XXXX XX00h Turn around cycle Data = MD1[31:24],

MD0[23:0] Idle Address = XXXX XX04h Turn around cycle Data = MD2[15:0], MD1[15:0] Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Idle Address = XXXX XX00h Turn around cycle Data = MD0[31:0] Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Idle Address = XXXX XX08h Turn around cycle Data = MD0[31:0] Address = XXXX XX04h Turn around cycle Data = MD1[31:0] Data = MD0[31:0]

Am79C972 45

CLK

FRAME

1 2345678

109

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

MD1

DEVSEL is sampled

DATA DATA

00000110

PAR

MD0

PAR

Figure 25. Descriptor Ring Read In Non-Burst Mode

00000110

PAR PAR

21485C-28

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 234567

MD1

00000110

PAR PAR

DEVSEL is sampled

DATA

PAR

21485C-29

Figure 26. Descriptor Ring Read In Burst Mode

46 Am79C972

Table 5. Descriptor Write Sequence

SWSTYLE BCR20[7:0]

BWRITE BCR18[5] AD Bus Sequence

Address = XXXX XX04h Data = MD2[15:0],

MD1[15:0] Idle Address = XXXX XX00h Data = MD1[31:24] Address = XXXX XX08h Data = MD2[31:0] Idle Address = XXXX XX04h Data = MD1[31:16] Address = XXXX XX00h Data = MD2[31:0] Idle Address = XXXX XX04h Data = MD1[31:16] Address = XXXX XX00h Data = MD2[31:0] Data = MD1[31:16]

FIFO DMA Transfers

Am79C972 microcode will determine when a FIFO DMA transfer is requir ed. This transfer mode wi ll be used for transfers of data to and from the Am 79C972 FIFOs. Once the Am79C972 BIU has been granted bus mastership, it will perform a seri es of consecutive transfer cycles before rel inquishing t he bus. All transfers within the master cycle will be either read or write cycles, and all transfers will be to contiguous, ascending addresses. Both non-burst and burst cycles are used, with burst mode being the pr eferred mode whe n the device is used in a PCI bus application.

Non-Burst FIFO DMA Transfers

In the default mode, the Am79C972 controller uses non-burst transfers to read and write data when accessing the FIFOs. Each non-burst transfer will be performed sequentially with the issue of an address and the transfer of the corresponding data with appropriate output signals to indicate selection of the active data bytes during the transfer.

FRAME

will be deasserted aft er every add re ss phase. Several factors will affect the length of the bus master ship period. The possibilities are as follows:

Bus cycles will continue until the transmit FIFO is filled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold (write transfers). The exact number of total transfer cycles in the bus mastership period i s dependent on all of the following variables: the settings of the FIFO watermar ks, the conditions of the FIFOs, the laten cy of the sy stem bus to the Am79C972 controller’s bus request, the speed of bus operation and bus preemptio n events. The TRDY response time of the memory device will also affect the number of transfers, since the speed of the accesses will affect the state of the FIFO. During accesses, the FIFO may be filling or emptying on the network end. For example, on a receive operation, a slower TRDY

response will allow additional d ata to accumulate insid e of the FIFO. If the acce sses are sl ow enough, a complete DWord may become available before the end of the bus mastership period and, thereby, increase the number of transfers in that period. The general rule is that the longer the Bus Grant latency, the slower the bus transfer operations; the slower the clock speed, the higher the transmit watermark; or the higher the receive watermark, the longer the bus mastership period will be.

Note: The PCI Latency Timer is n ot signifi cant dur in g non-burst transfers.

Am79C972 47

CLK

FRAME

1 2345678

109

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

PAR

DATA

00110111

PAR

MD2

DEVSEL is sampled

PAR

DATA

00000111

PAR

MD1

Figure 27. Descri ptor Ring Write In Non-Burst Mode

21485C-30

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

REQ

GNT

1 2 4 6 7 8

DEVSEL is sampled

MD2

0110

DATA

0000 0011

PAR

DATA

Figure 28. Descriptor Ring Write In Burst Mode

PAR

21485C-31

48 Am79C972

Burst FIFO DMA Transfers

Bursting is only performed by the Am79C972 controller if the BREADE and/or BW RIT E bits of BCR18 are set. These bits individua lly enable /disable the abili ty of the Am79C972 controller to perform burst accesses during master read operations and master write operations, respectively.

A burst transaction will start with an address phase, followed by one or more data phases. AD[1:0] will always be 0 during the address phase indicating a linear burst order.

During FIFO DMA read operations, all byte lanes will always be active. The Am79C972 co ntroller will internally discard unused bytes. During the first and the last data phases of a FIFO DMA burst write operation, one or more of the byte enable sign al s may be in ac tive. All other data phases will always write a complete DWord.

CLK

FRAME

C/BE

PAR

IRDY

TRDY

1 23456

ADD

DATA

DATA DATA

0001

PAR PAR

00000111

PAR

Figure 29 shows the beginning of a FIFO DMA write with the beginning of the buffer not aligned to a DWord boundary. The Am79C972 controller star ts of f by writing only three bytes during the first data phase. This operation aligns the address for all other data transfers to a 32-bit boundary so that the Am79C972 controller can continue bursting full DWords.

If a receive buffer does not end on a DWord boundary, the Am79C972 controller will perform a non- DWord write on the last transfer to the buffer. Figure 30 shows the final three FIFO DMA transfers to a re ceive buffer. Since there were only nine bytes of space left in the receive buffer , the Am79C972 controller bursts three data phases. The first two data p hases write a f ull DWord, the last one only writes a single byte.

Note that t h e Am7 9C 9 7 2 c on tr o ll er wi ll al ways pe r form a DWord transfer as long as it owns the buffer space, even when there are less than four bytes to write. For example, if there is only one byte left for the current receive frame, the Am79C972 controller will write a full DWord, containing the last byte of the receive frame in the least signifi cant byte position (BSWP is c leared to 0, CSR3, bit 2). The content of the other three bytes is undefined. The message byte count in th e recei ve descriptor always reflects the exact length of the received frame.

DEVSEL

REQ

GNT

DEVSEL is sampled

21485C-32

Figure 29. FIFO Burst Write At Start Of Unaligned

Buffer

The Am79C972 controller will continue transferring FIFO data until the transmit FIFO is filled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold (wr ite transfers), or the Am79C972 controller is preempted, and the PCI Latency Timer is expired. The host should use the values in the PCI MIN_GNT and MAX_LAT registers to determine the value for the PCI Latency Timer.

Am79C972 49

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

1 234567

00000111

PAR

PAR PAR

PAR

DEVSEL is sampled

1110

PAR

DATA DATA

DATA

ADD

21485C-33

Buffer Management Unit

The Buffer Management Unit (BMU) is a microcoded state machine which implements the i nitialization procedure and manages th e descr iptors an d buffers. The buffer management unit operates at half the speed of the CLK input.

Initialization

Am79C972 initialization includes the reading of the initialization block in memory to obta in the operating parameters. The initialization block can be organized in two ways. When SSIZE32 (BCR20, bit 8) is at it s default value of 0, all initialization block entries are logically 16-bits wide to be backwards compatible with the Am79C90 C-LANCE and Am79C96x PCnet-ISA family . When SSIZE32 (BCR20, bit 8) is set to 1, all i nitial ization block entries are logically 32-bits wide. Note that the Am79C972 controller always performs 32-bit bus transfers to read the initialization block entries. The initialization block is read when the INIT bit in CSR0 is set. The INIT bit should be set before or concurrent with the STRT bit to insure correct oper ation. Once th e initialization block has been co mplete ly rea d in a nd inter nal registers have been updated, IDON will be set in CSR0, generating an interrupt (if IENA is set).

Figure 30. FIFO Burst Write At End Of Unaligned

Buffer

The exact number of total transfer cycles in the bus mastership per iod is dependent on all of the following variables: the settings of the FIFO watermarks, the conditions of the FIFOs, the l atency of the sy stem bus to the Am79C97 2 controller’s bus request, and the speed of bus operation. The TRDY the memory device will also affect the number of trans-

response time of

fers, since the speed of the accesses will affect the state of the FIFO. During ac cesses, the FIFO m ay be filling or emptying on the network end. For example, on a receive operation, a slower TRDY

response will allow additional data to accumulate inside of the FIFO. If the accesses are slow enough, a complete DWord may become available before the end of the bus mastership period and, thereby , increase the number of transfers in that period. The general rule is that the longer the Bus Grant latenc y, the slower the bus tra nsfer operation s; the slower the clock speed, the higher the transmit watermark; or the lower the receive watermark, the longer the total burst length will be.

When a FIFO DMA burst operation is preempted, the Am79C972 controlle r will not re linquish bus ownership until the PCI Latency Timer expires.

The Am79C972 con troller obta ins the sta rt address o f the initialization block from the contents of CSR1 (least significant 16 bits o f ad dress) a nd C SR2 (mos t signi ficant 16 bits of address). The host must write CSR1 and CSR2 before setting the INIT bit. The initialization block contains the user defined conditions for Am79C972 operation, together with the base addresses and length information of the transmit and receive descriptor rings.

There is an alternate method to initialize the Am79C972 controller. Instead of initialization v ia the initialization block in memory, data can be written directly into the appropriate registers. Either method or a combination of the two may be used at the discretion of the programmer. Please refer to Appendix A, Alterna- tive Method for Initialization for details on this alternate method.

Re-Initialization

The transmitter and receiver sections of the Am79C972 controller can be turned on via the initialization block (DTX, DRX, CSR15, bits 1-0). Th e state s of the transmitter and receiver are monitore d by the host through CSR0 (RXON, TXON bits) . The Am79C972 c ontroller should be re-initialized if the trans mitter and/or the receiver were not turned o n dur ing the or iginal initialization, and it was subsequently required to activate them or if either section was shut off due to the detectio n of an error condition (MERR, UFLO, TX BUFF error).

Re-initialization may be done via the initialization block or by setting the STOP bit in CSR0, followed by writing

50 Am79C972

to CSR15, and then setting the START bit in CSR0. Note that this form of resta rt will not per form th e s am e in the Am79C972 controller as in the C-LANCE device. In particular, upon restart, the Am79C972 controller reloads the transmit and receive descr iptor pointer s with their respective base addresses. This mea ns that the software must clear the descript o r OWN bits and reset its descriptor ring pointer s before restarting the Am79C972 contro ller. The reload of descri ptor base addresses is performed in the C-LANCE device only after initialization, so that a restart of the C-LANCE without initialization leaves the C-LANCE po inting at the same de scriptor locations as before the restart.

Suspend

The Am79C972 controller offers two suspend modes that allow easy updating of the CS R registers without going through a full re-initial ization of the d evice. The suspend modes also allow stopping the device with orderly termination of all network activity.

The host requests the Am79C972 controller to enter the suspend mode by setting SPND (CSR5, bit 0) to 1. The host must poll SPND until it reads back 1 to determine that the Am79C972 controller has entered the suspend mode. When the host sets SPND to 1, the procedure taken by the Am79C972 controller to enter the suspend mode depe nds o n the s etting of the fast suspend enable bit (FASTSPND, CSR7, bit 15).

When a fast suspend i s requested (FASTSPND is set to 1), the Am79C972 contr oller p erform s a quick e ntr y into the suspend mode. At the time the SPND bit is set, the Am79C972 controller will continue the DMA process of any transmit a nd/or receive packets that have already begun DMA activity until the network activity has been completed. In addition, any transmit packet that had started transmission will be fully transmitted and any receive packet that had begun reception will be fully received. However, no additional packets will be transmitted or received and no additional transmit or receive DMA activity will be gin afte r networ k acti vity has ceased. Hence, the Am7 9C972 controller may enter the suspend mode with transmit and/or receive packets still in the FIFOs or the SRAM. This offers a worst case suspend time of a maximum length packet over the possibility of comp letely emptying the SRA M. Care must be exercised in this mode, because the entire memory subsystem of the Am79C 972 contr oller is suspended. Any changes to eithe r the descri ptor rings or the SRAM can cause the Am79C972 controller to start up in an unknown condition and could c ause data corruption.

When FASTSPNDE is 0 and the SP ND bit is set, th e Am79C972 controll er may take longer before enterin g the suspend mode. At the time the SPND bit is set, the Am79C972 controller will complete the DMA process of a transmit packet if it had already begun and the

Am79C972 controlle r will compl etely receive a receive packet if it had already begun. The Am79C972 controller will not receive any new packets after the completion of the current reception. Additionally, all transmit packets stored in the transmit FI FOs and the transmi t buffer area in the SRAM (if one is present) will be transmitted, and all receive packets stored in the receive FIFOs and the rec eive buffer area in the SRAM (i f selected) will be transferred into system memo ry. Since the FIFO and the SRA M contents are flushe d, it may take much longer before the Am79C972 controller enters the suspend mode. The amount of time that it takes depends on many factors including the size of the SRAM, bus latency, and network traffic level.

Upon completion of the described operations, the Am79C972 controller sets the read-version of SPND to 1 and enters the suspend mode. In sus pend mod e, all of the CSR and BCR r eg ister s are ac ce ss ible. As lon g as the Am79C972 co ntroller is not re set while in suspend mode (by H_RESET, S_RESET, or by setting the STOP bit), no re-initialization of the device is req uired after the device come s out of suspend m ode. When SPND is set to 0, the Am79C972 controller will leave the suspend mode and will continue at the transmit and receive descri ptor ring l ocations where it was when it entered the suspend mode.

See the section on Magic Packet™ technology for de- tails on how that affects suspension of the Am7 9C97 2 controller.

Buffer Management

Buffer management is accomplished through message descriptor entries organized as ring structures in memory. There are two descriptor rings, one for transmit and one for receive. Each descriptor descr ibes a single buffer . A frame may occupy one or more buffers. If multiple buffers are used, this is referred to as buffer chaining.

Descriptor Rings

Each descriptor ring must occupy a contiguous area of memory. During initialization, the user-defined base address for the transmit and receive descriptor rings, as well as the num ber of entri es contained in the descriptor rings a re s et u p. The programming of the software style (SWSTYLE, BCR20, bits 7-0) affects the way the descriptor rings and their entries are arranged.

When SWSTYLE is at its default value of 0, the descriptor rings are backwards compatible with the Am79C90 C-LANCE and the Am79C96x PCnet-ISA family. The descriptor r ing base addresses must be aligned to an 8-byte boundar y an d a maximum of 128 ring entries is allowed when the ring length is set through the TLEN and RLE N fields of the initializa tion block. Each ring entry contains a subset of the three 32-bit transmit or receive message descriptors (TMD, RMD) that are organized as four 16-bit structures

Am79C972 51

(SSIZE32 (BCR20, bit 8) is set to 0). Note that even though the Am79C97 2 controller treat s the descript or entries as 16-bit structures, it will always perform 32-bit bus transfers to access the descriptor entries. The value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus master transfers.

When SWSTYLE is set to 2 or 3, the descriptor r ing base addresses must be aligned to a 16-byte boundary, and a maximum of 512 ring entries is allowed when the ring length is set through the TLEN and RLEN fields of the initializa tion block. Each r ing entr y is organi zed as three 32-bit message descriptors (SSIZE32 (BCR20, bit 8) is set to 1). The fourth DWord is reserved. When SWSTYLE is set to 3, the order of the message descriptors is optimized to allow read and write access in burst mode.

For any software style, the ring len gths can be set b eyond this range (up to 65535) by writing the transmit and receive ring length r egisters (CSR76, CSR78) directly.

Each ring entry contains the following information:

n The address of the act ual message data buffer in

user or host memory

n The length of the message buffer n Status information indicating the condition of the

buffer

To per mit the queuin g and de-queuing of m essage buffers, ownership of each buffer is allocated to either the Am79C972 controller or the host. The OWN bit within the descr iptor st atus informat ion, ei ther TMD or RMD, is used for this purpose.

When OWN is set to 1, it signifies that the Am7 9C972 controller currently ha s ownership of this ring descr iptor and its associa ted buffer. Only the owner is permitted to relinquish ownership or to write to any field in the descriptor entry. A device that is not the cu rre nt ow ner of a descriptor entry cannot assume ownership or change any field in t he entry. A device may, however, read from a descriptor that it does not currently own. Software should al ways read descriptor en tries in sequential order. When software finds that the current descriptor is owned by the Am79C972 controller, then the software must not read ahead to the next descriptor. The software should wait at a descriptor it does not own until the Am79C972 controller sets OWN to 0 to release ownership to the software. (When LAPPEN (CSR3, bit

5) is set to 1, this rule is modified. See the LAPPEN description. At initialization, the Am79C972 controller reads the base add ress of both the transmit an d receive descriptor rings into CSRs for use by the Am79C972 controller during subsequent operations.

Figure 31 illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the receive and transmit descr iptors, and the recei ve and transmit data buffers, when SSIZE32 is cleared to 0.

52 Am79C972

CSR2

CSR1

IADR[15:0]IADR[31:16]

1st desc.

Rcv Descriptor

Ring

2nd desc.

Initialization

PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0

LADRF[31:16] LADRF[47:32] LADRF[63:48]

RDRA[15:0]

RLE

RES

TDRA[15:0]

TLE RES

Block

MOD

RDRA[23:16]

TDRA[23:16]

RMD

Rcv

Buffers

Xmt

Buffers

1st desc.

TMD

Data

Buffer

Data

Buffer

Data

Buffer

Xmt Descriptor

Ring

TMD

Data

Buffer

Figure 31. 16-Bit Software Model

RMD

TMD

RMD0

2nd desc.

TMD

Data

Buffer

Data

Buffer

21485C-34

Note that the value of C SR2, bits 1 5-8, is u sed as th e upper 8-bits for all memory addresses during bus master transfers.

Figure 32 illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the receive and transmit descr iptors, and the recei ve and transmit data buffers, when SSIZE32 is set to 1.

Polling

If there is no network c hannel activity and t here is no pre- or post-receive or pre- or post-transmit activity being performed by the Am79C972 controller, then the Am79C972 controller will periodically poll the current receive and transmit des criptor entr ies in order to ascertain their ownership. If the TXDPOLL bit in CSR4 is set, then the transmit polling function is disabled.

A typical polling operation c onsi sts of the following sequence. The Am79C972 cont roll er will u se the curren t receive descriptor address stored internally to vector to the appropriate Receive Descriptor Table Entry

Am79C972 53

(RDTE). It will then use the current tran smit de scr iptor address (stored i nter nall y) to vector t o the a pprop r iate Transmit Descriptor T ab le Entry (TDTE). The accesses will be made in the following order: RMD1, then RMD0 of the curren t RDTE during on e bus arbitration, an d after that, TMD1, then TMD0 of the current TDTE during a second bus arbitration. All information collected during polling activity will be stored internally in the appropriate CSRs, if the OWN bit is set (i.e., CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52).

A typical receive poll is the product of the following conditions:

1. Am79C972 controller does not own the current RDTE and the poll time has elapsed and RXON = 1 (CSR0, bit 5) , or

2. Am79C972 controller does no t own the next RDTE and there is more than one receive descriptor in the ring and the poll time has elapsed and RXON = 1.

IADR[31:16] IADR[15:0]

CSR1CSR2

1st desc.

start

Rcv Descriptor

Ring

2nd desc. start

TLE

RES

RLE

RES

Initialization

Block

RES

PADR[31:0]

PADR[47:32]

LADRF[31:0

LADRF[63:32]

RDRA[31:0] TDRA[31:0]

RMD

MODE

Rcv

Buffers

Xmt

Buffers

1st desc.

start

TMD0

Data

Buffer

Xmt Descriptor

TMD1

Data

Buffer

Figure 32. 32-Bit Software Model

RMD

Data

Buffer

Ring

TMD2

Data

Buffer

2nd desc. start

TMD3

TMD0

Data

Buffer

Data

Buffer

21485C-35

If RXON is cleared to 0, the Am79C 972 controller will never poll RDTE locations.

In order to avoid missing frame s, the system should have at least one RDTE available. To minimize poll activity, two RDTEs should be available. In this case, the poll operation will only consist of the check of the status of the current TDTE.

A typical transmi t poll is the prod uct of the following conditions:

1. Am79C972 controller does not own the current TDTE and TXDPOLL = 0 (CSR4, bit 12) and TXON = 1 (CSR0, bit 4) and the poll time has elapsed, or

2. Am79C972 controller does not own the current TDTE and TXDPOLL = 0 and TXON = 1 and a frame has just been received, or

3. Am79C972 controller does not own the current TDTE and TXDPOLL = 0 and TXON = 1 and a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode controller to exit the poll cou nting code and immediately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE poll will be performed ahead of the TDTE poll. If the microcode is not executing the poll counting code whe n the TDMD bit is set, then the demanded poll of the TDTE will be delayed until the microcode returns to the poll counting code.

The user may change the poll time value from the default of 65,536 clock period s by modifying the value in the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) access, the Am79C972 con troller fi nds that the OWN bit of that TDTE is not set, the Am79C972 controller resumes the poll tim e count and re-examines the sam e TDTE at the next expiration of the poll time count.

If the OWN bit of the TDTE is set, but the Start of Packet (STP) bit is not set, the Am79C972 controller will immediately request the bus in order to clear the OWN bit of this descr iptor. (This condit ion would normally be found following a late collision (LCOL) or retry (RTRY) error that occurred in the midd le of a transmi t frame chain of buffers.) After resetting th e OWN bit of this descriptor, the Am79C972 controll er will ag ain im-

54 Am79C972

mediately request th e bus in order to access the next TDTE location in the ring.

If the OWN bit is set and the buffer length is 0, the OWN bit will be clear ed. In the C-LA NCE device, the buffer length of 0 is inter pret ed as a 409 6-byte buffer. A zero length buffer is acceptable as long as i t is not the last buffer in a chain (STP = 0 and ENP = 1).

If the OWN bit and STP are set, then microcode control proceeds to a routine that will enable transmit data transfers to the FIFO. The Am79C972 controller will look ahead to the next transmit descriptor after it has performed at least one transm it data transfer from the first buffer.

If the Am79C972 controller does not own the next TDTE (i.e., the second TDTE for this frame), it will complete transmission of the curr ent buffer and update the status of the current (first) TDTE with the BUFF an d UFLO bits being set. If DXSUFLO (CSR3, bit 6) is cleared to 0, the underflow error will cause the transmitter to be disabled (CSR0, TXON = 0). The Am79C972 controller will have to be re-initialized to restore the transmit function. Setting DXSUFLO to 1 enables the Am79C972 controller to gracefully recover from an underflow error. The device will scan the transmit descriptor ring until it finds either the start of a new frame or a TDTE it does not own. To avoid an underflow situation in a chained buffer transmission, the system should always set the transmit chain descriptor own bits in reverse order.

If the Am79C972 controller does own the second TDTE in a chain, it will gradually empty the contents of the first buffer (as the bytes are needed by the transmit operation), perform a single-cycle DMA transfer to update the status of the first descri ptor (clear the OWN bit in TMD1), and then it may perform one data DMA access on the second buffer in the ch ain before executing another lookahead operation. (i.e., a lookahead to the third descriptor.)

It is imperative that the host system never reads the TDTE OWN bits out of order. The Am79C972 controller normally clears OWN bits in strict FIFO order. However , the Am79C972 contr oller can queue u p to two fra mes in the transmit FIFO. When the second frame uses buffer chaining, the Am79C972 con troller m ight retur n ownership out of normal FIF O order. The OWN bit for last (and maybe only) buffer of the first frame is not cleared until transmi ssion is completed. Durin g the transmission the Am79C972 controller will read in buffers for the next frame and clear their OWN bits for all but the last one. The first and all intermediate buffers of the second fr a m e can have their OWN bit s c le a re d be fore the Am79C972 controller returns ownership for the last buffer of the first frame.

If an error occurs in the transmi ssion before all of the bytes of the current buffer have been transferred, trans-

mit status of the c urrent buffer will be immediat ely updated. If the buffer does not contain th e en d of packet, the Am79C972 contro ller will skip over the rest of the frame which experienced the error. This is done by returning to the polli ng microc ode where the Am79C97 2 controller will clear the OWN bit for all descriptors wit h OWN = 1 and STP = 0 and continue in like manner until a descriptor with OWN = 0 (no more transmit frames in the ring) or OWN = 1 and STP = 1 (the first buffer of a new frame) is reached.

At the end of any transmit operation, whether successful or with errors, immediately following the com ple tio n of the descriptor updates, the Am79C972 controller will always perform another polling operation. As described earlier, this polling operation will be gin with a check of the current RDTE, unless the Am79C972 controller already owns that descripto r. Then the Am79C972 controller will poll the next TDTE. If the transmit descriptor OWN bit has a 0 value, th e Am79C972 c ontroller will resume incrementing the poll time counter. If the transmit descriptor OWN bit has a value of 1, the Am79C972 controller will be gin filling the FIF O with transmit dat a and initiate a transmission . This end-o f-operation po ll coupled with the TDTE lookahead operation allows the Am79C972 controller to avoid inserting poll time counts between successive transmit frames.

By default, whenever the Am79C972 controller completes a transmit frame (either with or without error) and writes the stat us information to the current de scriptor, then the TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt signal if the IENA bit of CSR0 has been set a nd the TINTM bit of CSR3 is cleared. The Am79C972 controller provides two modes to reduce the number of transmit interrupts. The interrupt of a successfully transmitted frame can be suppressed by setting TINTOKD (CSR5, bit 15) to

1. Another mode, which is enabled by setting L TINTEN (CSR5, bit 14) to 1, allows suppression of interrupts for successful transmi ssions for all but the last frame in a sequence.

Receive D escriptor Table Entry

If the Am79C972 controller does not own both the current and the next Receive Descriptor Table Entry (RDTE), then the Am79C972 controller will continue to poll according to the polli ng sequence described above. If the receive descriptor ring length is one, then there is no next descriptor to be polled.

If a poll operation has revealed that the current and the next RDTE belong to the Am79C972 controller, then additional poll accesses are not necessary. Future poll operations will not includ e RDTE acce sses as lon g as the Am79C972 controlle r reta ins owners hip of the current and the next RDTE.

When receive activity is prese nt on the channel, the Am79C972 controller waits for the complete address of

Am79C972 55

the message to arrive. It then decides whether to accept or reject the frame based on all active addressing schemes. If the frame is accepted, the Am79C972 controller checks the current re ceive buffer status register CRST (CSR41) to determine the ownership of the current buffer.

If ownership is lacking, the Am79C972 controller will immediately perform a final poll of the current RDTE. If ownership is still denied, the Am79C972 controller has no buffer in which to store the incoming message. The MISS bit will be set in CSR0 and the Missed Frame Counter (CSR112) will be incremented. Another poll of the current RDTE will not occur until the frame has finished.

If the Am79C972 controller sees that the last poll (either a normal poll, or the final effort described in the above paragraph) of the current RDTE shows valid ownership, it proceeds to a poll of the next RDTE. Following this poll, and regardles s of the outcome of this poll, transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive descriptor, the Am79C972 control ler will conti nue to perform receive data DMA transfers to the first buffer. If the frame length exceeds the length of the first buffer, and the Am79C972 controller does not own the se cond buffer, ownership of the current descriptor will be passed back to the system by writing a 0 to the OWN bit of RMD1. Status will be written in dicating buffer (BUFF = 1) and possibly overflow (OFLO = 1) errors.

If the frame length exceeds the length of the first (cur rent) buffer, and the Am79C972 controller does own the second (next) buffer, ownership will be passed back to the system by writing a 0 to t he OWN bit of RMD1 when the first buffer is full. The OWN bit is the only bit modified in the de scriptor. Receive data tran sfer s to the second buffer may occur before the Am79C972 controller proceeds to look ahead to the ownership of th e third buffer. Such action will depen d upon the state o f the FIFO when the OWN bit has been updated in th e first descriptor. In any case, lookahea d will be performed to the third buffer and the information gathered will be stored in the c hip, regardles s o f the s tate of th e ownership bit.

This activity continues until the Am79C972 controller recognizes the completion of the frame (the last byte of this receive message h as been removed from the FIFO). The Am79C972 controller will subsequently update the current RDTE status with the end of frame (ENP) indication set, write the message byte count (MCNT) for the entire frame into RM D2, and overwrite the “current” entries in the CSRs with the “next” entries.

Receive Frame Queuing

The Am79C972 con tro ll er s up ports the lack o f R DT Es when SRAM (SRAM SIZE in BCR 25, bits 7-0) is en-

abled through the Receive Frame Queuing mechanism. When the SRAM SIZE = 0, then the Am79C972 controller reverts back to the PCnet PCI II mode of operation. This operation is automatic and does not require any programmin g by the host. When SRAM is enabled, the Receive Frame Queuing mechanism allows a slow protocol to manage more frames without the high frame loss rate normally attributed to FIFO based network controllers.

The Am79C972 controller will store the incoming frames in the extended FIFOs until polling takes place; if enabled, it discovers it owns an RDTE. The stored frames are not altered i n any way until written out into system buffers. When the receive FIFO overflows, further incoming receive frames will be missed during that time. As soon as the network receive FIFO is empty , incoming frames are proc essed as nor mal. Status on a per fram e basis is not k ept d uring the o v erflo w proc ess. Statistic counters are maintained and accurate during that time.

During the time that the Receive Frame Queuing mechanism is in op eration, the Am79 C972 controlle r relies on the Receive Poll Time Counter (CSR 48) to control the worst case access to the RDTE. The Re ceive Poll Time Counter is programmed through the Receive Polling Interval (CSR49) register. The Received Polling Interval defaults to approximately 2 ms. The Am79C972 controller will also tr y to access the RDTE during nor mal descriptor accesses whether they are transmit or receive accesses. The host can force the Am79C972 controller to imm ediately access th e RDTE by setting the RDMD (CSR 7, bit 13) to 1. Its operation is similar to the transmit o ne. The polling pr ocess can be disabled by setting the RXDPOLL (CSR7, bit 12) bit. This will stop the automatic polling process and the host must set the RDMD b it to initiate th e receive process into host memory. Receive frames are still stored even when the receive polling process is disabled.

Software Interrupt Timer

The Am79C972 controlle r is equipped with a software programmable free-running interrupt timer. The timer is constantly running and will generate an interrupt STINT (CSR 7, bit 11) when STINITE (CSR 7, bit 10) is set to

1. After generating the interrupt, the software timer will load the value stored in ST VAL and restart. The timer value STVAL (BCR31, bits 15-0) is inter preted as an unsigned number with a resolution of 256 Time Base Clock periods. For instance, a value of 122 m s would be programmed with a value of 9531 ( 253Bh), if the Time Base Clock is running at 20 MHz. The default value of STVAL is FFFFh which yields the appro xim ate maximum 838 ms tim er du rati on. A write to STVAL restarts the timer with the new contents of STVAL.

56 Am79C972

Media Access Control

The Media Access Con trol ( MAC) engin e incorpo rates the essential pro toc ol re qui re men ts for operation of a n Ethernet/IEEE 80 2.3- c om pli ant no de and pr ovid es the interface between the FIFO subsystem and the MII.

This section descr ibes operation of the MAC engine when operating in half-duplex mode. When operating in half-duplex mode, the MAC engine is fully compliant to Section 4 of ISO/IEC 88 02-3 (ANSI/IEEE Standar d 1990 Second Edition) and ANSI/IEEE 802.3 (1985). When operating in full-duplex mode, the MAC engine behavior changes as described in the section Full- Duplex Operation.

The MAC engine provides programmable enhanced features designed to min imize host super vision, bus utilization, and pre- or post-message processing. These features include the ability to disable retries after a collision, dynamic FCS generation on a frame-byframe basis, automatic pad fiel d i nsertion and de le tio n to enforce minimum frame size attributes, automatic retransmission withou t reloading the FIFO, and automatic deletion of collision fragments.

The two primary attributes of the MAC engine are:

n Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

n Media access management

— Medium allocation (collision avoidance, except

in full-duplex operation)

— Contention resolution (collision handling, except

in full-duplex operation)

T ransmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame size enforcement for transmit and receive frames. When APAD_XMT (CSR, bit 11) is set to 1, transmit messages will be pad ded with sufficie nt bytes (containin g 00h) to ensure that the receiving station will observe an information field (destin ati on add re ss, sou rce add re ss, length/type, data, and FCS) of 64 bytes. When ASTRP_RCV (CSR4, bit 10) is set to 1, the receiver will automatically strip pad bytes from the received message by observing th e value in the length fi eld and by stripping excess bytes if this value is below the minimum data size (46 bytes). Both features can be independently over-ridden to allow illegally short (less than 64 bytes of frame data) messag es to be transmitted and/or received. The use of this feature reduces bus

utilization because the pad bytes are not transferred into or out of main memory.

Framing

The MAC engine will autonomously h andle the construction of the transmit frame. Once the transmit FIFO has been filled to the pre determi ned threshold ( set by XMTSP in CSR80) and access to the channel is currently permitted, the MAC engine will commence the 7byte preamble sequence (10101010b, where first bit transmitted is a 1). The MAC engine will s ubseq uently append the Start Frame Delimiter (SFD) byte (10101011b) followed by the serialized data from the transmit FIFO. Once the data has been completed, the MAC engine will append the FCS (mos t significant bit first) which was computed on the entire data portion of the frame. The data portion of the frame consists of destination address, s ource address, len gth/type, and frame data. The user is respo nsible for the correct ordering and content in each of these fields in the frame. The MAC does not use the content in the length/type field unless APAD_XMT (CSR4, bit 11) is set and the data portion of the frame is shorter than 60 bytes.

During GPSI operation, the MAC will discard the first 8 bits of information before searching for the SFD sequence. Once the SFD is detected, all subsequent bits are treated as par t of the frame. Dur ing MII opera tion, the MAC engine will detec t the i ncomi ng pr ea mble sequence when the RX_DV signal is activated by the external PHY. The MAC will discard the preamble and begin searching for the SFD except in the case of 100BASE-T4. In that case, the SFD will be the first nibble across the MII interface. Once the SFD is detected, all subsequent nibbles are treated as part of the frame. The MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if enabled), and pass the rema ining bytes throu gh th e receive FIFO to the host. If pad strippi ng is per for med , the MAC engine will also strip the received FCS bytes, although norm al FCS computation and ch ecking will occur. Note that apart from pad stripping, the frame will be passed unmodified to the host. If the length field has a value of 46 or greater, all frame bytes including FCS will be passed unmodified to the receive buffer, regardless of the actual frame length.

If the frame termina tes or suffers a co llision before 64 bytes of information (after SFD) have been received, the MAC engine will automatically delete the frame from the receive FIFO, without host intervention. The Am79C972 controller has the ability to accept runt packets for diagnostic purposes and proprietar y networks.

Destination Address Handling

The first 6 bytes of in formation after SFD will be i nterpreted as the des tination addre ss field. The MAC en-

Am79C972 57

gine provides facilities for physical (unicast), logical (multicast), and broadcast address reception.

Error Detection

The MAC engine provides several facilities which report and recover from errors on the medium. In addition, it protects the network from gross errors due to inability of the h ost to keep pace with the MAC engin e activity.

On completion of transmission, the following transmit status is available in the appropriate Transmit Message Descriptor (TMD) and Control and Status Register (CSR) areas:

n The number of transmission retr y attempts (ONE,

MORE, RTRY, and TRC).

n Whether the MAC engine had to Defer (DEF) due to

channel activity.

n Excessive deferral (EXDEF), indicating that the

transmitter experienced Exc essive Deferral on this transmit frame, where Excessive Deferral is defined in the ISO 8802-3 (IEEE/ANSI 802.3) standard.

n Loss of Carrier (LCAR), indicating that there was an

interruption in the ability of the MAC engine to monitor its ow n tran smissi on. Repea ted LCA R error s indicate a potentially faulty transceiver or network connection.

n Late Collision (LCOL) indi cates that the transmis-

sion suffered a collision after the slot time. This is indicative of a badly configured network. Late collisions sho uld not occur i n a normal operating network.

n Collision Error (CERR) indicates that the trans-

ceiver did not respond w ith an SQE Test message within the first 4 pleted. This may be due to a failed transceiver, disconnected or faulty transce iver drop cable, or because the transceiver does not suppor t this feature (or it is disabled). SQE Test is only valid for 10Mbps networks.

In addition to the repor ting of networ k errors, the MAC engine will also atte mpt to prevent the creatio n of any network error due to the in ability o f the host to se r vi ce the MAC engine. During transmission , if the host fails to keep the transmit FIFO fil led suffi ci en tly, causing an underflow, the MAC engine will guarantee the message is either sent as a runt packet (which will be deleted by the receiving station) or as an invalid FCS (which will also cause the receiver to reject the message).

The status of each rece ive mess age is available in the appropriate Receive Message Descriptor (RMD) and CSR areas. All received frames are passed to the host regardless of any error. The FRAM error will only be reported if an FCS error is detected and there is a nonintegral number of bytes in the message.

µs after a tran smission was c om-

During the reception, the FCS is generated on every nibble (including the dribbling bits) coming from the cable, although the internally saved FCS value is only updated on the eigh th bit (on each byte bound ary). The MAC engine will ignore up to 7 additional bits at the end of a message (dribbling bits), which can occur under normal network operating conditions. The framing error is reported to the user as follows:

n If the number of dribbling bits are 1 to 7 and there is

no FCS error, then there is no Framing error (FRAM = 0).

n If the number of dribbling bits are 1 to 7 and there is

a FCS error, then there is also a Framing error (FRAM = 1).

n If the number of dribbling bi ts is 0, the n there is n o

Framing error. There may or may not be a FCS error.

n If the number of dribbling bits is EIGHT, then there

is no Framing error. FCS error will be reported and the receive message count will indicate one extra byte.

Media Access Management

The basic requirement for all stations on the network is to provide fairness of channel allocatio n. The IEEE

802.3/Ethernet protocols define a media access mechanism which permits all stations to access the channel with equality. Any node can attempt to con tend for the channel by waiting for a predetermined time (Inter Packet Gap) after the last activity, before transmitting on the media. The channel is a mult idrop commun ications media (with various topo logical configurations permitted), which allows a single station to transmit and all other statio ns to receive. If two nodes simultaneously contend for the channel, their signals will interact causing loss of data, defined as a collision. It is the responsibility of the MAC to attempt to avoid and recover from a collision, to guaran tee data i ntegr ity for the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990) requires that the CSMA/CD MAC monitor the medium for traffic by watching for carrier activity . When carrier is detected, the medi a is conside red busy, and the MAC should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also allows optionally a two-part deferral after a receive message.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: It is possible for the PLS carrier sense indication to fail to be asserted d ur in g a co lli s ion on the me di a. If the deference process simply times the inter-Frame gap based on this indication, it is possible for a short interFrame gap to be generated, leading to a potential

58 Am79C972

reception failure of a subsequent frame. To enhance system robustness, the following optional measures, as specified i n 4.2.8, are re commended whe n InterFrame-SpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the interrupted gap, as soon as transmitting and carrier sense are both false.

2. When timing an inter-frame gap following reception, reset the inter-frame gap timing if carrier sense becomes true during the first 2/3 of the inter-frame gap timing interval. During the final 1/3 of the interval, the timer shall not be reset to ens ure fair access to the medium. An initial period shorter than 2/3 of the interval is permissible including 0.

The MAC engine implements the optional r eceive two part deferral algorithm, with an InterFrameSpacingPart1 time of 6.0 terval is, therefore, 3.4

The Am79C972 controller will perform the two-part deferral algorithm as specified in Section 4.2.8 (Process Deference). The Inter Packet Gap (IPG) timer will start timing the 9.6 ceive carrier is deasserted. During the first part deferral (InterFrameSpacingPart1 - IFS1), the Am79C97 2 co ntroller will defer any pending transmit frame and respond to the receive message. The IPG counter will be cleared to 0 continuously until the carrier deasserts, at which point the IPG counter will resume the 9.6 count once again. Once the IFS1 period of 6.0 elapsed, the Am79C972 controller will begin timing the second par t deferral (InterFrameSpacingPart2 - IFS2)

µs. Once IFS1 has completed and IFS2 has com-

of 3.4 menced, the Am79C972 controller will not defer to a receive frame if a transmit frame is pending. This means that the Am79C972 controller will not attempt to receive the receive frame, since it will start to transmit and generate a collision at 9.6 will complete the preamble (64-bit) and jam (32-bit) sequence before ceasing transmission and invoking the random backoff algorithm.

The Am79C972 co ntroller allows the user to program the IPG and the first part deferral (InterFrameSpacingPart1 - IFS1) through CSR125. By changing the IPG default value of 96 bit times (60h), the user can adjust the fairness or aggressiveness of the Am79C972 MAC on the network. By programming a lower number of bit times than the ISO/IEC 8802-3 standard requires, the Am79C972 MAC engine will become more aggressive on the network. This aggressive nature will give rise to th e A m79 C972 c ontr olle r poss ibly capturing the net work at times by forcing other less aggressive compliant nodes to d efer. By programming a larger number o f bit times, the Am79C972 MAC will become less aggressive on the network and may defer more often than nor mal. The performance of the Am79C972 controller may decrease as the IPG value

µs. The InterFrameSpacingPart 2 in-

µs.

µs InterFrameSpacing after the re-

µs

µs has

µs. The Am79C972 controller

is increased from the default value, but the resulting behavior may improve network performance by reducing collisions. The Am79C972 controller uses the same IPG for back-to-back transmits and receive-to-transmit accesses. Changing IFS1 will alter the period for which the Am79C972 MAC engine will defer to incoming receive frames.

CAUTION: Care must be exercised when altering these parameters. Adverse network activity could result!

This transmit two-part deferral al gorithm is implemented as an option which ca n be disabled using the DXMT2PD bit in CSR3. The IFS1 programming will have no effect when DXMT2PD is set to 1, but the IPG programming value is still valid. Two part deferral after transmission is usefu l for ensuring that severe IPG shrinkage cannot oc cur in specific circumstances, causing a transmit message to follow a receive message so closely as to make them indistinguishable.

During the time period immediately after a transmission has been completed, the external transceiver should generate the SQE Test message within 0.6 to 1.6 after the transmission ceases. During the time period in which the SQE Test message is expected, the Am79C972 controller will not respond to receive carrier sense.

See ANSI/IEEE Std 802.3-1993 Edition, 7.2.4.6 (1):

“At the conclusion o f the outpu t function, the DT E opens a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when the CARRIER_STATUS becomes CARRIER_OFF. If execution of the output function does not cause CARRIE R_ON to occur, no SQE test occurs in the DTE. The duration of the window shall be at least 4 .0 During the time window the Carrier Sense Function is inhibited.”

The Am79C972 controller implements a carr ier sense “blindi ng ” period of 4.0 deassertion of carrier sense after transmission. This effectively means that when tran smit two pa rt deferral is enabled (DXMT2PD is c leared), the IFS 1 time is f rom

µs to 6 µs after a transmission. However, since IPG

4 shrinkage bel ow 4 correctly configured network, and since the fragment size will be larger than the 4 IPG counter will be res et by a worst case IPG shr inkage/fragment scenario and the Am79C972 controller will defer its transmission. If carrier is detected within the 4.0 to 6.0 will not restart the “blinding” period, but only restart IFS1.

µs IFS1 period , t he Am 79C 972 cont rol ler

µs but no more than 8.0 µs.

µs length starting from the

µs will rarely be en countered on a

µs blinding window, the

µs

Am79C972 59

Collision Handling

Collision detection is performed and reported to the MAC engine via the COL/CLSN input pin.

If a collision is detected before the complete preamble/ SFD sequence has bee n tran sm itt ed, t he M AC engine will complete the pream ble/SFD before appending the jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits being transmitted, the MAC engine will abort the transmission and append the jam sequence immediately. The jam sequence is a 32-bit all zeros pattern.

The MAC engine will attempt to transmit a frame a total of 16 times (initial attemp t plus 15 retries ) due to normal collisions (th ose wit hin the slo t time). Detection of collision will caus e the trans mi ssio n to be res ch edu le d to a time determine d by the random ba ckoff algorit hm . If a single retry was required, the 1 bit will be set in the transmit frame status. If more than one retry was required, the MORE bit will be set. If all 16 attempts experienced col lisions, the RTRY bit will be set (1 and MORE will be clear), and the transmit mes sa ge will be flushed from the FIFO. If retries have been disabled by setting the DRTY bit in CSR15, the MAC engine will abandon transmission of the frame on detectio n o f th e first collision. In this case, only the RTRY bit will be set and the transmit message will be flushed from the FIFO.

If a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. The MAC engine will abor t the transmissi on, append the jam sequence, and set the L COL bit. No retry attempt will be scheduled on detection of a late collision, and the transmit message will be flushed from the FIFO.

The ISO 8802-3 (IEEE/ANS I 802 .3) Stan dard r equ ir es use of a “truncated binary exponential backoff” algorithm, which provides a controlled pseudo random mechanism to enforce the collision backoff interval, before retransmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jam ming), the CSMA/CD s ublayer dela ys befor e atte mpting to retransmit the frame. The delay is an integer multiple of slot time. The number of slot time s to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range:

≤ r < 2

The Am79C972 controller provides an alternative algorithm, which suspends the counting of the slot time/IPG during the time tha t receive carrier sense is detected . This aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. It effectively accelerates the increa se in the backoff time in busy networks and allows n odes not involved in the

where k = min (n,10).”

collision to access the channel, while the colliding nodes await a reduction in channel activity . Once channel activity is reduced, the nodes resolving the collision time-out their slot time counters as normal.

This modified backoff algorithm is enabled when EMBA (CSR3, bit 3) is set to 1.

Transmit Operation

The transmit operation and features of the Am7 9C972 controller are c ontro lled b y pr ogr amm able opti ons . The Am79C972 controller offers a large transmit FIFO to provide frame buffering for increased system latency, automatic retransmission with no FIFO reload, and automatic transmit padding.

Transmit Function Programming

Automatic transmit features such as retr y on collision , FCS generation/transmission, and pad field insertion can all be programmed to provide flexibility in the (re-) transmission of messages.

Disable retry on collision (DRTY) is controlled by the DRTY bit of the Mode register (CSR15) in the initialization block.

Automatic pad field inser tion is controlled by the APAD_XMT bit in CSR4.

The disable FCS generation/transmission feature can be programmed as a static feature or dynamically on a frame-by-frame basis.

T r ansmit FIFO Watermark (XMTFW) in CSR80 se ts the point at which the BMU requests more data from the transmit buffers for the FIFO. A minimum of XMTFW empty spaces must be available in the transmit FIFO before the BMU will request the system bus in order to transfer transmit frame data into the transmit FIFO.

Transmit St art Point (XMTSP) in CS R80 sets th e p oin t when the transmitter actually attempts to transmit a frame onto the media. A minimum of XMTSP bytes must be written to the transmit FIFO for the current frame before transmission of the c ur rent frame wil l begin. (When automatically padded packets are being sent, it is conceivable that the XMTSP i s not reached when all of the data ha s bee n transferred to th e FIFO. In this case, the transmission will begin when all of the frame data has been placed into the transmit FIFO.) The default value of XMTSP is 01b, meaning there has to be 64 bytes in the transmit FIFO to start a transmission.

Automatic Pad Generation

T ransmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). This allows the minimum frame size o f 64 bytes (512 bits) for IEEE 802.3/ Ethernet to be gu aranteed with no softw are intervention f rom the host/con trolling proces s. Setting the APAD_XMT bit in CSR4 enables the automatic

60 Am79C972

padding feature. The pad is placed between the LLC data field and FCS field in the IEEE 802 .3 frame. FCS is always added if the frame is padded, regardless of the state of DXMTFCS (CSR15, bit 3) or ADD_FCS (TMD1, bit 29). Th e transmit frame will be pa dded by bytes with the value of 00H. The default value of APAD_XMT is 0, which will disable automatic pad generation after H_RESET .

It is the responsibility of uppe r layer software to correctly define the actual length field contained in the message to corresp ond to the total number of LLC Data bytes encapsulated in the frame (length field as

defined in the ISO 8802-3 (IEEE/ANSI 802.3) standard). The length value contained in the message is not used by the Am79C972 controller to com pute the actual number of pad bytes to be inserted. The Am79C972 controller will append pad bytes dependent on the actual number of bits transmitted onto t he network. Once the last data byte of the frame has completed, prior to appending the FCS, the Am79C972 controller will check to ensure that 544 bits have been transmitted. If not, pad bytes are added to extend the frame size to this value, and the FCS is then added. See Figure 33.

Preamble

1010....1010

Bits

SFD

10101011

Bits

Destination

Address

Bytes

Source

Address

Bytes

Figure 33. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble/SFD, including FCS) 64 bytes 512 bits

Preamble/SFD size 8 bytes 64 bits FCS size 4 bytes 32 bits

At the point that FCS is to be appended, the transmitted frame should contain:

Preamble/SFD + (Min Frame Size - FCS) 64 + (512-32) = 544 bits

A minimum length transmit frame from the Am79C97 2 controller, therefore, will b e 576 bits, af ter the FCS i s appended.

Transmit FCS Generation

Automatic generation and tran smission of FCS for a transmit frame depends on the value of DXMTFCS (CSR15, bit 3). If DXMTFCS is cleared to 0, the transmitter will generate and append th e FCS to the transmitted frame. If the a utomatic padding feature is invoked (APAD_XMT is set in CSR4), the FCS will be appended to frames shorter than 64 bytes by the Am79C972 controller regardless of the state of DXMTFCS or ADD_FCS (TMD1, bit 29). Note that the calculated FCS is transmitted most significant bit first. The default value of DXMTFCS is 0 after H_RESET.

Length

Bytes

LLC

Data

46 — 1500

Pad FCS

Bytes

21485C-36

ADD_FCS (TMD1, bit 2 9) allows th e autom atic gener ation and transmission of FCS on a frame-by-frame basis. DXMTFCS should be set to 1 in this mode. To generate FCS for a frame, ADD_FCS must be set in all descriptors of a frame (STP is set to 1). Note that bit 29 of TMD1 has the function of ADD_FCS if SWS TYLE (BCR20, bits 7-0) is programmed to 0, 2, or 3.

Transmit Exception Conditions

Exception conditions for frame transmission fall into two distinct categories: those conditions which are the result of norma l network operation, and those wh ich occur due to abnor mal network and/or host relate d events.

Normal events which may occur and which are handled autonomously by the Am79C972 controller include collisions within the slot time with automatic retry. The Am79C972 controller will ensure that collisions which occur within 512 bit times from the start of transmission (including p reamble) will be automat ically retr ied with no host intervention. The transmit FIFO ensures this by guaranteeing th at data contained wit hin the FIFO will not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length, and data fields have been transmitted onto th e network with out encountering a collisio n. Note that i f DRTY (CSR15, bit 5 ) is se t to 1 or if the network interface is operating in full-duplex mode, no collision handling is required, and any byte of

Am79C972 61

frame data in the FIFO can be overwritten as soon as it is transmitted.

If 16 total attempts (ini tial attempt plus 1 5 retries) fail, the Am79C972 controller s ets the RTRY bit in the current transmit TDTE in ho st memor y (TMD2), gives up ownership (resets the OWN bit to 0) for this frame, and processes the next frame in the transmit r ing for transmission.

Receive Operation

The receive operation and features of the Am79C97 2 controller are c ontro lled b y pr ogr amm able opti ons . The Am79C972 controller offers a large receive FIFO to provide frame buffering for increased system latency, automatic flushing of collision fragments (runt packets), automatic receive pad stripping, and a variety of address match options.

Abnormal network conditions include:

n Loss of carrier n Late collision n SQE Tes t Error (Does not apply to 100-Mbps net-

works.)

These conditions should not occ ur on a co rrectly configured IEEE 80 2.3 network operatin g in half-duplex mode. If they do, they will be reported. None of these conditions will occur on a networ k operating in fullduplex mode. (See th e section Full-Duplex Operation for more detail.)

When an error occurs in the middle of a multi-buffer frame transmission, the error status will be written in the current descri ptor. The OWN bit(s) in the subsequent descriptor(s) will be cleared until the STP (the next frame) is found.

Loss of Carrier

When operating in ha lf-duplex mode, a loss of carr ier condition will be reported if the Am79C972 controller cannot obser ve receive activity wh ile it is transmitti ng on the GPSI port.

When the MII por t is selecte d, LCAR will be r eported for every frame transmitted if the controller detects a loss of carrier.

Late Collision

A late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the transmit process was initiated (first bit of preamble commenced). The Am79C972 controller will abandon the transmit process for that fram e, set Late Collision (LCOL) in the assoc i ated TMD 2, and process the next transmit frame in the r ing. Frames experiencing a late collision will not be retried. Recovery from this condition must be performed by upper layer software.

SQE Test Error

In GPSI mode, CLSN must be asserted after the transmission or otherwise CERR will b e set. CERR will be asserted in the 10BASE-T mod e through the MII after transmit, if the network port is in Link Fail state. CERR will never cause INTA set the ERR bit CSR0.

to be activated. It wil l, however,

Receive Function Programming

Automatic pad field str ipping is enabled by sett ing the ASTRP_RCV bit in CSR4. This can provide flexibility in the reception of messages using the IEEE 802.3 frame format.

All receive frames can be accepted by setting th e PROM bit in CSR15. Acceptance of unicast and broadcast frames can be individually turned off by setting the DRCVPA or DRCVBC bits in CSR15. The Physical Address register (CSR12 to CSR14) stores the address that the Am79C972 controller compares to the destination address of the in coming frame for a unicast address match. The Logical Address F ilter register (CSR8 to CSR11) ser ves as a hash filter for multicast address match.

The point at which the BMU will start to transfer data from the receive FIFO to buffer memory is controlled by the RCVFW bits in CSR80. The default established during H_RESET is 01b, which sets the watermark flag at 64 bytes filled.

For test purposes, the Am79C972 controller can be programmed to accept r unt packets by setting RPA in CSR124.

Address Matching

The Am79C972 controll er suppor ts three types of address matching: unicast, multicast, and broadcast. The normal address matching procedure can be modified by prog rammin g three bi ts in CSR1 5, the mode register (PROM, DRCVPA, and DRCVBC).

If the first bit received afte r the SFD (the least s ignificant bit of the first byte of the destination address field) is 0, the frame is unicast, which indicates that the frame is meant to be recei ved by a single nod e. If the fir st bi t received is 1, the frame is multicast, which indicates that the frame is meant to be received by a group of nodes. If the destination addr ess field contains all 1s, the frame is broadcast, which is a special type of multicast. Frames with the broadcast address in the destination address field are meant to be received by all nodes on the local area network.

When a unic ast frame arr ives at the Am 79C972 controller, the controller will accept the frame if the destination address field of the incoming frame exactly matches the 6-byte station address stored in the Physical Address register s (PADR, CSR12 to CSR14). The

62 Am79C972

byte ordering is such that the first byte received from the network (after the SFD) must match the least significant byte of CSR12 (P ADR[7:0]), and the sixth byte received must match the most si gni fic an t byte of C SR1 4 (PADR[47:40]).

When DRCVPA (CSR15, bit 13) is set to 1, the Am79C972 controller will not accept unicast frames.

If the incoming frame is multicast, the Am79C972 controller performs a calculation on the contents of the destination address field to determine whether or not to accept the frame. This calculation is explained in the section that de scribes the Logical Addres s Filter (LADRF).

When all bits of the LADRF registers are 0, no multicast frames are accepted, except for broadcast frames.

Although broadcast frames are classified as special multicast frames, they are treated differently by the Am79C972 controlle r hardwa re. Bro adcas t f rames a re always accepted, except when DRCVBC (CSR15, bit

14) is set and there is no Logical Address match.

None of the addres s filtering described ab ove applies when the Am79C972 contro ller is op erating in the pr omiscuous mode. In the promiscuous mode, all properly formed packets are received, regar dless of the co ntents of their destination address fields. The promiscuous mode overrides the Disable Receive Broadcast bit (DRCVBC bit l4 in the MODE register) and the Disable Receive Physical Address bit (DRCVPA, CSR15, bit

13).

The Am79C972 controll er operates in promiscuous mode when PROM (CSR15, bit 15) is set.

In addition, the Am79C972 controlle r provides the External Address De tection Interface (EADI) to all ow external address filter ing. See the section External Address Detection Interface for further detail.

The receive descriptor entry RMD1 contain s t hree bits that indicate which method of address matching caused the Am79C97 2 controller to a ccept the fram e. Note that these indicator bits are only available when the Am79C972 controlle r is programmed to use 32-bit structures for the descriptor entries (BCR20, bit 7-0, SWSTYLE is set to 2 or 3).

PAM (RMD1, bit 22) is set by the Am79C972 controller when it accepted the received frame due to a match of the frame’s destination address wi th the co nten t of th e physical address register.

LAFM (RMD1, bit 21) is se t by the Am79C 972 c ont ro ller when it accepted the r eceived frame based on the value in the logical address filter register.

BAM (RMD1, bit 20) is set by the Am79C972 controller when it accepte d the received frame because the frame’s destination address is of the type ’Broadcast’.

If DRCVBC (CSR15, bit 14) i s clea red t o 0 , on ly B AM , but not LAFM will be set when a Broadcast frame is received, even if the Logical Address Filter is programmed in such a way that a Broa dcast frame would pass the hash filter. If DRCVBC is set to 1 and the Logical Address Filter is programmed in such a way that a Broadcast frame would pass the hash filter, LAFM will be set on the reception of a Broadcast frame.

When the Am79C972 control ler operates in promi scuous mode and none of the three match bits is set, it is an indication that the Am79C972 controller only accepted the frame because it was in promiscuous mode.

When the Am79C972 c ontroller is no t programmed to be in promiscuous mod e, but the EADI i nte rface is enabled, then when none of the three match bits is set, it is an indication that the A m79C972 c ontroller only a ccepted the frame because it was not rejected by driving the EAR

pin LOW within 64 bytes after SFD.

See Table 6 for receive address matches.

Table 6. Receive Address Match

LAF

PAM

000X

1 0 0 X Physical address match

0100

0101

0010Broadcast frame

MBAM

DRC VBC Comment

Frame accepted due to PROM = 1 or no EADI reject

Logical address filter match; frame is not of type broadcast

Logical address filter match; frame can be of type broadcast

Automatic Pad Stripping

During reception of an IEEE 802.3 frame, the pad field can be stripped automatically. Setting ASTRP_RCV (CSR4, bit 0) to 1 enables the automa tic pa d str ippin g feature. The pad field will be stri pp ed b efore the fram e is passed to the F IFO, thus pres erving FIFO sp ac e for additional frames. The FCS fie ld will also be stri pped, since it is computed at the transmitting station based on the data and pad field characters, and will be invalid for a receive frame that has had the pad characters stripped.

The number of bytes to be s tripped is calculat ed from the embedded length field (as defined in the ISO 88023 (IEEE/ANSI 802.3) definition) contained in the frame. The length indicates the actual number of LLC data bytes contained in the mes sage. Any received frame which contains a length field less than 46 bytes will have the pad field str ippe d (if A STRP_RCV is se t). Re ceive

Am79C972 63

frames which have a length field of 46 bytes or greater will be passed to the host unmodified.

Figure 34 shows the byte/bit order ing of the received length field for an IEEE 802.3-compatible frame format.

46 — 1500

Bytes

Bits

Preamble

1010....1010

Start of Frame

at Time = 0

Increasing Time

Bits

SFD

10101011

Bytes

Destination

Address

Bit

Bytes

Source

Significant

Figure 34. IEEE 802.3 Frame And Length Field Transmission Order

Since any valid Ethernet T ype field value will always be greater than a normal IEEE 802.3 Length field (

≥46),

the Am79C972 contro ller will not attem pt to str ip valid Ethernet fr ames . Note that for some network protocols,

the value passed in the Ethernet Ty pe and/or IEEE

802.3 Length field is not compliant with either standard

and may cause problems if pad stripping is enabled.

Receive FCS Checking

Reception and che cking of the received FCS is per formed automatically by the Am79C972 controller. Note that if the Automatic Pad Strippi ng feature is enabled, the FCS for padded frames will be verified against the value computed for the incoming bit stream including pad chara cte rs, but the F CS value for a pa dded frame will not be passed to the host. If an FCS error is detected in any frame, the error will be reported in the CRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two distinct categori es, i .e., thos e co ndi tio ns whic h a re th e result of normal network operation, and those whi ch occur due to abnor mal network and/or host relate d events.

Normal events which may occur and which are handled autonomously by the Am79C972 co ntroller are basi-

Most

Byte

Bytes

Length

Bit 7Bit

LLC

Data

1 — 1500

Bytes

Least

Significant

Byte

Pad FCS

45 — 0

Bytes

Bit

Bytes

cally collisio ns within the sl ot time and automatic runt packet rejection. The Am79C972 co ntr ol le r w ill e ns ure that collisions tha t occur within 512 bit times from the start of reception (excluding preamble) will be automatically deleted from the rec eive FIFO with no host intervention. The receive FIFO will delete any frame that is composed of fewer than 64 bytes provided that the Runt Packet Accept (RPA bit in CSR124) feature has not been enabled and the networ k interface is operating in half-duplex mode, or the full-duplex Runt Packet Accept Disable bit (FDRPAD, BCR9, bit 2) is set. This criterion w ill be met regardl ess of whether the receive frame was the first (or onl y) frame i n th e F I FO or if the receive frame was queued behind a previously received message.

Abnormal network conditions include:

n FCS errors n Late collision

Host related receive exception conditions include MISS, BUFF, and OFLO. These are described in the section, Buffer Management Unit.

Loopback Operation

Loopback is a mode of operation intende d for system diagnostics. In this mode, the trans mitter and receiver

21485C-37

64 Am79C972

are both operating at the same time so that the controller receives its own transmissions. The control ler provides two basic types of loopback. In internal loopback mode, the transmitted data is looped back to the receiver inside the controller without actually transmitting any data to the external network. The receiver will move the received data to the next receive buffer, where it can be examined by software. Alternatively, in external loopback mode, data can be transmitted to and received from the external network.

Refer to Table 21 for various bit settings required for Loopback modes.

GPSI Loopback Modes

When GPSI is the active network por t, there are only two modes of loopback operation: internal and external loopback. Loopback operation is enabled by setting LOOP (CSR15, bit 2) to 1.

When INTL is set to 1, internal loopback is selected. Data coming out of the transmit FIFO is fed directly to the receive FIFO. All GPSI outputs are inactive; inputs are ignored.

During the internal loopback, the TXD, TX_CLK, and TX_EN pins will toggle appropriately with the correct data.

Miscellaneous Loopback Features

All transmit and receive function programming, such as automatic transmit p adding and re ceive pad str ipping, operates identically in loopback as in normal operation.

Runt Packet Accept is internally enabled (RPA bit in CSR124 is not affected) when any loopback mode is invoked. This is to be backwards compatible to the CLANCE (Am79C90) software.

Since the Am79C972 control ler has two FCS generators, there are no more restricti ons on FC S generatio n or checking, or on testing multicast address detection as they exist in the half-duplex PCnet family devices and in the C-LANCE. On receive, the Am79C972 controller now provides true FCS status. The descriptor for a frame with an FCS error will have the FCS bit (RMD1, bit 27) set to 1. The FCS generator on the transmit side can still be disabled by setting DX MTFCS (CSR15 , bit

3) to 1.

External loopback operation is selected by setting INTL to 0. Data is transmitted to the network and is expected to be looped back to the GPSI receive pins outside the chip. Collision detection is active in this mode.

Media Independent Interface Loopback Features

Loopback through the MII can be handled in two ways. The Am79C972 controller supports an internal MII loopback and an external MII loopback. The MII loopback requires that the MII port be manually configured through software using ASEL ( BCR 2, bit 1) and PORTSEL (CSR 15, bits 8-7).

The external loopba ck through the MII requires a twostep operation. The exter nal PHY must be plac ed into a loopback mode by writing to the MII Control Register (BCR33, BCR34). Then the Am79C972 controller must be placed into an external loopback mode by setting the Loop bits.

The internal loopback through the MII is controlled by MIIILP (BCR32, bit 1). When set to 1, this bit will cause the internal portion of the MII data port to loopback on itself. The MII management port (MDC, MDIO) is unaffected by the MIILP bit. The internal MII interface is mapped in the following way:

n The TXD[3:0] nibble data path is loo ped back onto

the RXD[3:0] nibble data path;

n TX_CLK is looped back as RX_CLK; n TX_EN is looped back as RX_DV. n CRS is correctly OR’d with TX_EN and RX_DV and

always encompasses the transmit frame.

n TX_ER is not driven by the Am79C9 72 and there-

fore not looped back.

In internal lo opb ack operation , the Am 79C972 controller provides a s pecial mod e to test the co llision logi c. When FCOLL (CSR1 5, bit 4) is set to 1, a co llision is forced during every transmissi on attempt. T his will result in a Retry erro r.

General Purpose Serial Interface

The General Purp os e Se r ial Inte rface (GPSI) provides a direct interface to the MAC section of the Am79C972 controller. All signals are digital and data is non-encoded. The GPSI allows use of an external Manchester encoder/decoder such as the A m7992B Serial Interface A dapter (SIA). I n addi tion, it allo ws the Am79C972 controller to be used a s a MAC sublayer engine in repeater designs based on the IMR+ device (Am79C981).

GPSI mode is invoked by selecting the interface through the PORTSEL bits of the Mode register (CSR15, bits 8-7).

The GPSI interface uses some of the same pins as the interface to the MII. Simultaneous use of both functions is not possible.

After an H_RESET, all MII pins are internally configured to function as the MII interface. When the GPSI interface is selected by setting PORTSEL (CSR15 , bits 8-7) to 10b, the Am79C972 controller will ter mi nate all further accesses to the MII.

GPSI signal functions are described in the pin description section under the GPSI subheading.

Full-Duplex Operation

The Am79C972 contro ller supports ful l-duplex operation on both network inte rfaces. Full-duplex operation

Am79C972 65

allows simultaneous transmit and receive activity on the TXDAT and RXDAT pins of the GPSI port, and the TXD[3:0] and RXD[3:0] pins of the MII port. Full-duplex operation is enabled by the FDEN bit loc ated in BCR 9 for all ports. Full-duplex operation is also enabled through Auto-Negotiation when DANAS (BCR 32, bit 7) is not enabled on the MII port and the ASEL bit is se t, and both the external PHY and its li nk par tner are capable of Auto-Negotiation and full-duplex operation.

When operating in full-duplex mode, the following changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

n The first 64 bytes of every transmit frame are not

preserved in the T ransmit FIFO during transmission of the first 512 bits as described in the Transmit Exception Conditions section. Instead, when full-duplex mode is active and a frame is being transmitted, the XMTFW bits (CS R80, bits 9-8) always govern when transmit DMA is requested.

n Successful rec eption of the first 64 bytes o f every

receive frame is not a requirement for Receive DMA to begin as described in the Receive Exception Conditions section. Instead, receive DMA will be requested as soon as either the RCVFW threshold (CSR80, bits 12-13) is reached o r a co mplete valid receive frame is detected, regardless of length. This Receive FIFO operation is identical to when the RP A bit (CSR124, bit 3) is set dur ing half-duplex mode operation.

n Changes to the Transmit Deferral mechanism:

— Transmission is not deferred while receive is

active.

— The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits is star ted when transmit activity for the firs t packet ends, instead of when transmi t and carrier activity ends.

n The 4.0 µs carrier sense blinding period after a

transmission duri ng which the SQE test normally occurs is disabled.

n The collision indicati on input to the MAC engine is

ignored.

The MII changes for full-dupl ex operation are as follows:

n The collision detect (COL) pin is disabled. n The SQE test function is disabled.

n Loss of Carrier (LCAR) reporting is disabled.

Full-Duplex Link Status LED Support

The Am79C972 controller provides bits in each of the LED Status registers (BCR4, BCR5, BCR6, B CR7) to display the Full-Duplex Link Status. If the FDLSE bit (bit

8) is set, a value of 1 will be sent to the associated LEDOUT bit when in Full-Duplex.

The MAC engine changes for full-duplex operation ar e as follows:

66 Am79C972

Media Independent Interface

The Am79C972 controller fully supports the MII according to the IEEE 802.3 standard. This Reconciliation Sublayer interface allows a variety of PHYs (100BASE-TX, 100BASE-FX, 100BASE-T4, 100BASE-T2, 10BA SE-T, etc.) to be attached to the Am79C972 MAC engine without futu re upgrade problems. The MII interface is a 4-bit (nibble) wide data path interface that runs at 25 MHz for 100-Mbps networks or

2.5 MHz for 10-Mbps networks. The in terface consis ts

of two independent data paths, receive (RXD(3:0)) and transmit (TXD(3:0)), control signals for each data path (RX_ER, RX_DV, TX_ER, TX_EN), network status signals (COL, CRS), clocks (RX_CLK, T X_CLK) for each data path, and a two-wire management interface (MDC and MDIO). See Figure 35.

MII Transmit Interface

The MII transmit clock is generated by the external PHY and is sent to the Am79C972 controller on the TX_CLK input pin. The clock can run at 25 MHz or 2.5 MHz, depending on the s pee d of t he network to which the external PHY is attached. The data is a nibble-wide

(4 bits) data path, TXD(3:0), from the Am79C9 72 controller to the external PHY and is synchronous to the rising edge of TX_CLK. The transmit process starts when the Am79C972 controller asserts the TX_EN, which indicates to the external PHY that the data on TXD(3:0) is valid.

Normally, unrecoverable errors are signaled throug h the MII to the external PHY with the TX_ER output pin. The external PHY will respond to this error by generating a TX coding error on the current transmitted frame. The Am79C972 controller does not use this method of signaling errors on the transmit side. The Am79C972 controller will invert the FCS on the last byte generating an invalid FCS. The TX_ER pin is reserved for future use and is actively driven to 0.

MII Receive Interface

The MII receive clock is also generated by the external PHY and is sent to the Am79C972 controller on the RX_CLK input pin. The clock will be the same frequency as the TX_CLK but will be out of phase and can run at 25 MHz or 2 .5 M Hz, dep ending on the speed o f the network to which the external PHY is attached.

Am79C972

Figure 35. Media Independent Interface

The RX_CLK is a continuous clock during the reception of the frame, but can be stopped for up to two RX_CLK periods at the beginning and the end of frames, so that the external PHY can sync up to the network data traffic necessary to r ecover the receive clock. During this time, the external PHY may switch to the TX_CLK to maintain a stable clock on the receive interface. The Am79C972 controller will handle this situation with no loss of data. The data is a nibble-wide (4 bits) data path, RXD(3:0), from the external PHY to the Am79C972 controll er and is s ynchronou s to the r ising edge of RX_CLK.

MII Interface

The receive process starts when RX_DV is asserted. RX_DV will remain asserted until the end of the receive frame. The Am79C972 controller requires CRS (Carrier Sense) to toggle in be tween f rames in order t o receive them properly. Errors in the currently received frame are signaled acr oss the MII by the RX_ER pin. RX_ER can be used to signal special conditions out of band when RX_DV is not asserted. Two defined out-ofband conditions for this are the 100BASE-TX signaling of bad Star t of Frame Delimiter and the 10 0BASE-T4 indication of illeg al code group before the receiver has synched to the incoming data. The Am79C972 controller will not respond to th ese c ond iti ons. Al l out of band

RXD(3:0) RX_DV RX_ER RX_CLK

CRS COL

TXD(3:0) TX_EN TX_CLK

MDC MDIO

Receive Signals

Network Status Signals

Transmit Signals

Management Port Signals

21485C-38

Am79C972 67

conditions are currently tre ated as NULL events. Certain in band non-IEEE 802.3u-compliant flow control sequences may cause erratic behavior for the Am79C972 controller. Consult the switch/bridge/router/ hub manual to disable the in-band flow control sequences if they are being used.

ware suppor t of the external PHY device without software support. The PHY address of 1Fh is reserved and should not be used. To a ccess the 31 exter nal PHYs, the software driver must have knowledge of the external PHY’s address when multiple PHYs are present before attempting to address it.

MII Network Status Interface

The MII also provides signals that are consistent and necessary for IEEE 802.3 and IEEE 8 02.3 u o peration. These signals are CRS (Carrier Sense) and COL (Collision Sense). Carrier Sense is us ed to de tec t non -idl e activity on the network. Collision Sense is used to indicate that simultaneou s trans missio n has o ccur red in a half-duplex network.

MII Management Interface

The MII provides a two-wire managemen t interface so that the Am79C972 contro ller can control and re ceive status from external PHY devices.

The Am79C972 controller can suppor t up to 31 external PHYs attached to the MII Management Inte rface with software support and only one such device without software support.

The Network Port Manager copies the PHY AD after the Am79C972 controller re ads the EEPROM and uses it to communicate with the external PHY. The PHY address must be programmed into the EEP ROM prior to starting the Am79C972 controller. This is necessary so that the inter nal managemen t controller can work autonomously from the software driver and can always know where to access the external PHY. The Am79C972 controll er is un iqu e by offering dire ct h ar d-

The MII Management Interface uses the MII Control, Address, and Data registers (BCR32, 33, 34) to control and communicate to the external PHYs. The Am79C972 controller generates MII management frames to the external PHY through the MDIO pin synchronous to the rising edge of the Management Data Clock (MDC) based on a combination of writes and reads to these registers.

MII Management Frames

MII management frames are automatically generated by the Am79C972 controller and conform to the MII clause in the IEEE 802.3u standard.

The start of the frame is a preamble of 32 ones and guarantees that all of the external PHYs are synchronized on the same interface. (See Figure 36.) Loss of synchronization is possible due to the hot-plugging capability of the exposed MII.

The IEEE 802.3 speci fication allows you to drop the preamble, if after reading the MII S tatus Re gister f rom the external PHY you can d etermine tha t the external PHY will support Preamble Suppression (BCR34, bit

6). After having a valid MII Status Register read, the Am79C972 controller will then dro p the creati on of the preamble stream unti l a reset occur s, receives a read error, or the external PHY is disconnected.

Preamble

1111....1111

Bits

OP 10 Rd 01 Wr

Bits

PHY

Address

Bits

Figure 36. Fra me Format at the MII Interface Connection

This is followed by a start field (S T) and an operation field (OP). The operation f ield (OP) indicat es whether the Am79C972 controller is initiating a read or write operation. This is followed by the exter nal PHY address (PHYAD) and the register address (REGAD) programmed in BCR33. The PHY add ress of 1Fh is reserved and should not be used. The external PHY may have a larger address space starting at 10h - 1Fh. This is the address range set aside by the IEE E as vendor usable address space and will vary from vendor to ven-

Bits

TA Z0 Rd 10 Wr

Bits

Data

Bits

Idle

Bit

21485C-39

dor. This field is followed by a bus turnaround field. During a read operation, the bus turnaround field is used to determine if the external PHY is responding correctly to the read request or not. The Am7 9C972 control ler will tri-state the MDIO for both MDC cycles.

During the se cond cycle, if the external PHY is synchronized to the Am79C972 controller, the external PHY will drive a 0. If the external PHY does not drive a 0, the Am79C972 controller will signal a MREINT (CSR7, bit 9) interrupt, if MREINTE (CSR7, bit 8) is set

68 Am79C972

to a 1, indicating the Am79C972 con troller had an MII management frame read error and that the data in BCR34 is not valid. The data field to/from the external PHY is read or written into the BCR34 register. The last field is an IDLE field that is necessary to give ample time for drivers to turn off before the n ext access. The Am79C972 controller will drive the MDC to 0 and tristate the MDIO anytime the MII Management Por t is not active.

To help to speed up the r eading an d writin g of th e MII management frames to the external PHY , the MDC can be sped up to 10 MH z by setting the FMDC bits in BCR32. The IEEE 802.3 specification requires use of the 2.5-MHz clock rate, but 5 MHz and 10 MHz are available for the user. The intended applications are that the 10-MHz clock rate can be used for a single external PHY on an adapter card or motherboard. The 5MHz clock rate can be used for an exposed MII with one external PHY attach ed. T he 2.5-MHz clock rate is intended to be used when multiple external PHYs are connected to the MII Management Por t or if compliance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external PHY attached to the Am79C972 controller’s MII has no way of communicating important timely status information back to Am79C972 controller. The Am79C972 controller has no way of knowing that an external PHY has undergon e a change in s tatus without po lling the MII status register. To prevent problems from occurring with inadequate host or software polling, the Am79C972 controller will Auto-Poll when APEP (BCR32, bit 11) is set to 1 to insure that the m ost cur rent information is available. See Appendix C, MII Management Regi sters, for the bit descri ptions of the MII Status Register. The contents of the latest read from the external PHY will be stored in a shadow register in the Auto-Poll bloc k. The first read of the MII Status Register will just be stored, but subseque nt reads will be compared to the contents already stored in the shadow register. If there has been a change in the contents of the MII Status Register, a MAPINT (CSR7, bit

7) interrupt will b e generated o n INTA

if the MAPINTE (CSR7, bit 6) is set to 1. The Auto-Poll features can be disabled if software driver polling is required.

The Auto-Poll’s frequency of generating MII management frames can be adj usted by setting of the A PDW bits (BCR32, bits 10-8). The delay can be adjusted from 0 MDC periods to 2048 MDC periods. Auto-P oll by default will only read the MII Status regis ter in the external PHY.

Network Port Manager

The Am79C972 controlle r is unique in that it does no t require software intervention to control and configure an external PHY attached to the MII. This was done to

ensure backwards compatibility with existing software drivers. To the current software drivers, the Am79C972 controller will look and act like the PCnet-PCI II and will interoperate with existing PCnet drivers from revision

2.5 upward. The heart of this system is the Network Port Manager.

If the external PHY is present and is active, the Network Port Manager will request status from the external PHY by generating MII management frames. These frames will be sent roughly every 900 ms. These frames are necessary so that the Network Port Manager can monitor the current acti ve link and can selec t a different network port if the current link goes down.

Auto-Negotiation

Through the external PHY, the following capabilities are possible: 100BASE-T4, 100BASE-TX Ful l-/Half-Duplex, and 10BASE-T Full-/Half-Duplex. The capabilities are then sent to a link partner that will also send its capabilities. Both sides l ook to see what is po ssible and then they will connect at the greatest possible speed and capability as defined in the IEEE 802.3u stand ard and according to Table 7.

By default, the link partner must be at least 10BASE-T half-duplex capable. The Am79C972 controller can automatically negotiate with the network and yield the highest performance possible without software support. See the section on Network Por t Manager for more details.

Table 7. Auto-Negotiation Capabilities

Network Speed Physical Network Type

200 Mbps 100BASE-X, Full Duplex 100 Mbps 100BASE-T4, Half Duplex 100 Mbps 100BASE-X, Half Duplex

20 Mbps 10BASE-T, Ful l Duplex 10 Mbps 10BASE-T, Half Duplex

Auto-Negotiation goes further by providing a messagebased communication scheme called, Next Pages, before connecting to the Link Par tner. This feature is not

supported in Am79C972 unless the DANAS (BCR32, bit 10) is selected and the software driver is capable of controlling the external PHY . A complete bit description

of the MII and Auto-Negotiation registers can be found in Appendix C.

Automatic Network P ort Selection

If ASEL (BCR2, bit 0) is set to 1 and DANAS (BCR 32, bit 7) is set to 0, then the Network Port Manager will start to configu re the external PHY if it detects the external PHY on the MII Interface.

Am79C972 69

Automatic Network Selection: Exceptions

If ASEL (BCR2, bit 0) is set to 0 or DANAS (BCR 32, bit

7) is set to 1, then the Network Port Manager will discontinue actively tr ying to esta blish the conne ction s. It is assumed that the software driver is attempting to configure the network port and the Am79C972 controller will always defer to the softwar e driver. When The ASEL is set to 0, the so ftware driver should the n configure the port s with PORTSEL (CSR15, bit s 7- 8). Th e GPSI does not participate in the automatic selection process and should be manually configured with the PORTSEL bits.

Note: It is highly recommended that ASEL and PORTSEL be used when tr ying to ma nually configure a specific network port.

In order to manually configure the External PHY, the recommended procedure is to force the PHY configurations when Auto-Negotiation is not enabled. Set the DANAS bit (BCR32, bit 7) to turn off the Network Port Manager. Then write again to B CR32 wit h th e DANAS and XPHANE (BCR32, bit 5) bits cleared, together with the XPHYFD (BCR32, bit 4) and XPHYSP (BCR32, bit 3) bits set to the desired configuration. The Network Port Manager will send a few frames to validate the configuration.

CAUTION: The Network Port Manager utilizes the PHYADD (BCR33, bits 9-5) to c ommunicate with the external PHY dur ing the autom atic por t selection process. The PHYADD is co pied into a shadow register after the Am79C972 co ntr olle r has rea d the configuration information from the EEPROM. Extreme care must be exercised by the host software not to access BCR33 during this time. A read of PVALID (BCR19, bit 15) before accessing BCR33 will guarantee that the PHY ADD has been shadowed.

Am79C972’s Automatic Network Port selection mechanism falls within the following general categories:

n External PHY Not Auto-Negotiable n External PHY Auto-Negotia ble

Automatic Network Selection: External PHY Not Auto-Negotiable

This case occurs when the MIIPD (BCR32, bit 14) bit is

pabilities with the XPHYFD (BCR 32, bit 4) and the XPHYSP (BCR32, bit 3) bits programmed from the EEPROM. The Am79C972 controller will then program the external PHY with those values. A new read of the external PHYs MII Status regis ter will be made to see if the link is up. If the link does not come up as programmed after a specific tim e, the Am 79C9 72 c on tro ller will fail the external PHY link. The Network Port Manager will periodica lly query the external PHY for active links.

Automatic Network Selection: External PHY Auto-Negotiable

This case occurs when the MIIPD (BCR32, bit 14) bit is

1. This indicates that there is an external PHY attached to Am79C972 controller’s MII. If more than one external PHY is attached to the MII Management Interface, then the DANAS (BCR32, bit 7) bit must be set to 1 and then all configuration co ntrol sh ould revert to software. The Am79C972 controller will read the MII Status register of the external PHY t o determi ne its status and n etwork capabilities. See Ap pend ix C for the bi t d escriptions of the MII Status register. If the external PHY is Auto-Negotiation capable and/or th e XPHYA NE (BCR3 2, b it 5) bit is set to 1, then th e Am79C972 contro ller will star t the external PHY’s Auto-Negotiation pro cess. The Am79C972 controller will write to the external PHY’s Advertisement register with the following conditions set: turn off the Next Pages support, set the T echnology Ability Field ( See Appe ndix C for the Auto-Negotia tion register bit descriptions) from the external PHY MII Status register read, and set the Type Selector field to the IEEE 802.3 standard. The Am79C972 controller will then write to the external PHY’s MII Control register instructing the external PHY to negotiate the link. The Am79C972 controller will poll the external P HY’s MII Status register until the Auto-Negoti ation Complete bi t is set to 1and the Link Status bit is set to 1. The Am79C972 control le r wil l t hen wait a s pe ci fic t ime an d then again read the external PHY’s MII Status register. If the Am79C972 co ntroller sees that the external PHY’s link is down, it will try to bring up the external PHY’s link manually as described above. A new read of the external PHY’s MII Status register will be made to see if the link is up. If the link does not come up as programmed after a specific tim e, the Am 79C9 72 c on tro ller will fail the external PHY link and start the process again.

Automatic Network Selection: Force External Reset

If the XPHYRST bit (BCR32, bit 6 ) is set to 1, then th e flow changes slightly. The Am79C972 controller will write to the external PHY’s MII Control register with the RESET bit set to 1 (See Appendix C, MII Management Registers, for the MII register bit descriptions). This will force a complete reset of the external PHY. The Am79C972 controller after a specific time will pol l the external PHY’s MII Control register to see if the RESET

70 Am79C972

bit is 0. After the RESET bit is cleared, then the normal flow continues.

External Address Detection Interface

The EADI is provided to allow external address filtering and to provide a Receive Frame Tag word for proprietary routing information. It is selected by setting the EADISEL bit in B CR2 to 1. This feature is typi call y ut ilized by terminal servers, bridges and/or router products. The EADI interface can be used in conjunction with external logic to capture the packet destination address from the serial bit str eam as it arrives at the Am79C972 controller, to compare the cap tured address with a table of stored add resses or identifiers, and then to deter mine whether or not the Am79C97 2 controller should accept the packet.

External Address Detection Interface: GPSI Port

The EADI interface outputs are delivered d irectly from the NRZ decoded data and clock recovered by the external PHY. T his allows the extern al addr ess det ection to be performed in parallel with frame reception and address comparis on in the MAC Station A ddress Detection (SAD) block of the Am79C972 controller.

SRDCLK is provided to allow clocking of the receive bit stream into the exter nal address detection logic. Once a received frame commences and data an d clock are available, the EADI logic will monitor the alternating (“1,0”) preamble patter n until the two 1s of the Sta rt Frame Delimiter (SFD, 10101011 bit pattern) are detected, at which point the SFBD output will be driven HIGH.

The SFBD signal will initially be LOW. The assertion of SFBD is a signal to the external address detection logic that the SFD has been detected an d that subsequent SRDCLK cycles will deliver packet data to the external logic. Therefore, when SFBD i s asse r ted, the external address matching logic should begin de-serialization of the SRD data and send the resulting destination address to a Content Addressable Memory (CAM) or other address detec tion device. In order to reduce the amount of logic external to the Am79C972 controller for multiple address decoding systems, the SFBD signal will toggle at each new byte boundar y within the packet, subsequent to the SFD. This eliminates the need for externally supplying byte framing logic.

SRD is the decoded NRZ data from the net work. This signal can be used for external address detection.

The EAR dress comparison logic to reject a frame.

pin should be driven LOW by the external ad-

frame is of the type 'B roadcas t', the n the frame will be accepted regardless of the condition of EAR EADISEL bit of BCR2 is set to 1 and the Am79C972 controller is programmed to promiscuous mode (PROM bit of the Mode Register is set to 1), then all incoming frames will be acc epted, r egardle ss of a ny activity on the EAR

Internal address match is disabled when PROM (CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the Logical Address Fil ter registers ( CSR8 to CSR1 1) are programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal address match is disabled, then all incoming frames will be accepted by the Am79C972 controller, unless the EAR the frame (excluding preamble and SFD). This allows external address l ookup logic approximatel y 58 byte times after the last d estinatio n address bit i s available to generate the EAR Am79C972 controller is not configured to accept runt packets. The EADI logic on ly samples EAR times after SFD until 512 bit times (64 bytes) after SFD. The frame will be accepted if EAR serted dur ing this window. In order for the EAR be functional in full -duplex mode, FDRPAD bit (BCR9, bit 2) needs to be set. If Runt Packet Accept (CSR124, bit 3) is enabled, then the EAR ated prior to the 8 bytes received, if frame rejec tion is to be guaranteed. Runt packet sizes could b e a s short as 12 byte times (assuming 6 bytes for source address, 2 bytes for length, no data, 4 bytes for FCS) after the last bit of the destination address is available. EAR must have a pulse width of at least 110 ns.

The EADI outputs continue to provide data throu ghout the reception of a frame. Thi s al lows the external logic to capture frame head er infor mation to de ter mi ne pr otocol type, internetwor king i nforma tion, an d other useful data.

The EADI interface will operate as long as the STRT bit in CSR0 is set, even if the receiver and/or transmitter are disabled by software (DTX and DRX bits in CSR15 are set). This conf iguration is us eful as a semi-powerdown mode in that the Am79 C972 controller will not perform any power-consuming DMA ope rations. However, external circuitry ca n still respond to control frames on the network to facilitate remote node control. Table 8 summarizes the operation of the EADI in terface.

pin becomes active during the first 64 bytes of

pin.

signal, assuming that the

has not been as-

signal must be gener-

. When the

from 2 bit

pin to

If an address match is detected by comparison with either the Physical Address or Logical Address Filter registers contained within the Am79C972 controller or the

Am79C972 71

Table 8. EADI Operations

PROM EAR

1 X

0 1

0 0

Required

Timing

No timing requirements

Low for two bit times plus 10 ns

Received

Frames

All received frames

All received frames Frame rejected if in

address match mode

External Address Detection Interface: External PHY

When using the MII, the EADI int er face changes to reflect the changes on that interface. Except for the notations below the interface conforms to the previous functionality. The data arrives in nibbles and can be at a rate of 25 MHz or 2.5 MHz.

The MII provides all necessar y data and clo ck signals needed for the EADI interface. Consequently, SRDCLK and SRD are not used and are driven to 0. Data for the EADI is the RXD(3:0) receive data provided to the MII. Instead of deserializ ing the network data, the user will receive the data as 4 bi t nibbles. RX_CLK is provided to allow clocking of the RXD(3:0) receive nibble stream into the external address detection logic. The RXD(3:0) data is synchronous to the rising edge of the RX_CLK.

The assertion of SFBD is a signal to the external address detection log ic that the SFD has been detected and that the first valid data n ibble is on the RXD (3:0) data bus. The SFBD signal is delayed one RX _CLK cycle from the above definition and actually signals the start of valid data. In order to reduce the amount of logic external to th e Am79C972 control ler for multiple address decoding systems, the SFBD signal will go HIGH at each new byte b oundary wi thin the packet, subsequent to the SFD. This eliminates the need for externally supplying byte framing logic.

The EAR

pin function is the same and should be driven LOW by the external address comparison logic to reject a frame. See the External Addres s De tec tion Int erface: GPSI Port section for more details.

External Address Detection Interface: Receive Frame Tagging

The Am79C972 cont roller suppo rts receive frame tagging in both GPSI or MII mode. The method remains constant, but the chip interface pins will change between the MII and the GPSI modes. The receive frame tagging implementation will be a two- and three-wire chip interface, respectively, added to the existing EADI.

The Am79C972 contro ll er support s up t o 15 bi ts o f receive frame tagging per frame in the receive frame status (RFRTAG). The RFRTAG bits are in the receive frame status field in RMD2 (bits 30-16) in 32-bit soft-

ware mode. The receive frame tagging is not supported in the 16-bit software mode. The RFRTAG field are all zeros when either the EADISEL (BCR2, bit3) or the RXFRTAG (CSR7, bit 14) are set to 0. When EADISEL (BCR2, bit 3) and RXFRTAG (CSR7, bit 14 ) are set to 1, then the RFRTAG reflects the tag word shifted in during that receive frame.

In the MII mode, the two-wire interface will use the MIIRXFRTGD and MIIRXFRTGE pins from the EADI interface. These pins will provide the data input and data input enable for the receive frame tagging, respectively. These pins ar e no rmally not used dur in g the M II operation.

In the GPSI mode, the three-wire in ter face will use th e RXFRTGD , SRDCLK, and the RXFRTGE pins from the EADI and MII. These pins will provide the data input, data input clock, a nd the data input for the rec eive frame tagging enable, respectively.

The receive frame tag register is a shift register that shifts data in MSB first, so that less than the 15 bits allocated may be utilized by the user. The upper bits not utilized will return zeros. The receive frame tag register is set to 0 in between reception of frames. After receiving SFBD indication on the EADI, the user can sta rt shifting data into the rece ive tag reg ister u ntil o ne network clock period before the Am79C972 controll er receives the end of the current receive frame.

In the MII mode, the user must see the RX_CLK to drive the synchronous receive frame tag data interface. After receiving the SFBD indication, sampled by the rising edge of the RX_CLK, the user will drive the data input and the data input enable synchro nous with the rising edge of the RX_CLK. The user has until one network clock period before the deassertion of the RX_DV to input the data into th e recei ve frame tag register. At the deassertion of the RX_DV, the receive frame tag register will no longer accept data from the two-wire interface. If the user is still dri ving the data inpu t enable pin, erroneous or corrupted data may reside in the receive frame tag register. See Figure 37.

In the GPSI mode, the user must use the recovered receive data clock driven on the SRDCLK pin to drive the synchronous receive frame tag data interface. After receiving the SFBD indication, sampled by the rising edge of the recovered receive data cl ock, the user wi ll drive the data input and the data input enable synchronous with the rising edge of the recovered receive data clock. The user has until one network clock perio d before the deasser tion of the data from the network to input the data into the receive frame tag register. At the completion of received network data, the receive frame tag register will no longer accept data from the two-wire interface. If the user is still driving the data input enable pin, erroneous or corrupted data may reside in the receive frame tag register. See Figure 38.

72 Am79C972

RX_CLK

RX_DV

SF/BD

MIIRXFRTGE

MIIRXFRTGD

Figure 37. MII Receive Frame Tagging

SRDCLK

Bit0

SRD

SFBD

MIIRXFRTGE

MIIRXFRTGD

SFD

Note:

Bitz is last data bit.

Bit1

Figure 38. GPSI Mode Frame Tagging

Expansion Bus Interface

The Am79C972 controll er contains an Ex pansion Bus Interface that suppor ts Flash and EPROM devices as boot devices, as well as provides read/wr ite acces s to Flash or EPROM.

The signal AS_EBOE bits of the address into an external ‘374 (D flip-flop) ad dress latch. AS_EBOE EPROM/Flash read operatio ns to c ontr ol the OE of the EPROM/Flash.

The Expansion Bus Address is split into two different buses, EBUA_EBA[7:0] and EBDA[15:8]. The EBUA_EBA[7:0] provides the least and the most significant address byte. When accessing EPROM/Flash, the EBUA_EBA[7:0] is strobed into an external ‘374 (D flip-flop) address latch. This constitutes the most significant por tion of the Expa nsion Bus Address. For EPROM/Flash accesses, EBUA_EBA[7:0] constitutes the remain ing least s ignificant address byte. For byte oriented EPROM/F lash accesses, EBDA[15:8] con stitutes the upper or middle addres s byte. EBADDRU (BCR29, bits 3-0) should be set to 0 when not used, since EBADDRU constitutes the EBUA portion of the EBUA_EBA address byte and is strobed into the external ’374 address latch.

is provided to strobe the upper 8

is asser ted LOW during

input

21485C-40

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Bitx

Bity

Bitz

.. ..

21485C-41

The signal EROMCS of the EPROM/Flash. The signal EBWE to the WE

of the Flash device.

The Expansion Data Bus is configured for 8-bit byte access during EPROM/Flash accesses. During EPROM/ Flash accesses, EBD[7:0] provides the data byte. See Figure 39, Figure 40, and Figure 41.

Expansion ROM - Boot Device Access

The Am79C972 controller supports EPROM or Flash as an Expansion ROM boo t device. Both are configured using the same me thods and operate the same. See the previous section on Expansion ROM transfers to get the PCI timing and f unctional descr iption of the transfer method. The Am79C972 controller is functionally equivalent to the PCnet-PCI II controller with Expansion ROM. See Figure 40 and Figure 41.

The Am79C972 controller will always read four bytes for every host Expansion ROM read access. The interface to the Expansion Bus runs synchronous to the PCI bus interface clock. The Am79C9 72 co ntr oller w il l start the read operation to the Expansio n ROM by driving the upper 8 bits of the Expansion ROM address on EBUA_EBA[7:0]. One-half clock later, AS_EBOE high to allow registering of the upper addr ess bits externally. The upper portion of the Expansion ROM address will be the same for all four byte read cycles.

is connected to the CS /CE input

is connected

goes

Am79C972 73

AS_EBOE is driven high for one-half clock, EBUA_EBA[7:0] are driven with the upp er 8 bits of th e Expansion ROM address for one more clock cycle after AS_EBOE

goes low. Next, the Am79C972 controller starts dr iving the lower 8 bits of the Expansio n ROM address on EBUA_EBA[7:0].

The time that the Am79C972 controller waits for data to be valid is programmable. ROMTMG (BCR18, bits 15-

12) defines the time from when the Am79C972 controller drives EBUA_EBA[7:0] with the lower 8 bits of the Expansion ROM address to when the Am79C972 con-

EBD[7:0]

EBWE

troller latches in t he data on the EB D[7:0] inputs. The register value specifies the time in number of clock cycles. When ROMTMG is set to nine (the default value), EBD[7:0] is sampled with the next risi ng edge of CLK ten clock cycles after E BUA_EBA[7:0] was dr iven with a new address value. The clock edge that is used to sample the data is also th e clock edge that gene rates the next Expansion ROM address. All four bytes of Expansion ROM data are stored in holding registers. One clock cycle after the last data byte is available, the Am79C972 controller asserts TRDY

EBUA_EBA[7:0]

AS_/EBOE

EBDA[15:8]

Am79C972

EROMCS

’374

D-FF

Figure 39. Flash Configuration for the Expansion Bus

A[23:16] A[15:8] A[7:0]

FLASH

WE DQ[7:0] CS OE

21485C-42

The access time for the Expansion ROM or the EBDATA (BCR30) device (t

ACC) during read ope rations

can be calculated by subtracting the clock to output delay for the EBUA_EBA[7:0] outputs (t

v_A_D) and by

subtracting the input to clock setup time for the EBD[7:0] inputs (t

s_D) from the time defined by

ROMTMG:

ACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) -

t (t

The access time for the Expansion ROM or for the EBDATA (BCR30) device (t can be calculated by subtracting the clock to output delay for the EBUA EBA[7:0] outputs

74 Am79C972

s_D)

ACC) during write operations

(tv_A_D) and by

adding the input to clock setup time for Flash/EPRO in-

s_D) from the time defined by ROMTMG:

puts (t t

ACC = ROMTMG * CLK period * CLK_F A C - (tv_A_D) -

s_D)

(t The timing di agram in Figure 42 assumes th e default

programming of ROMTMG (1001b = 9 CLK). After reading the first byte, the Am79C972 controller reads in three more bytes by increm enting the l ower por tion of the ROM address. After the last byte is strobed in, TRD Y will be asserted on clock 50. When the host tries to perform a burst read of the Expansion ROM, the Am79C972 controller will disco nne ct the acces s at th e second data phase.

EBD[7:0]

The host must program the Ex pa nsion ROM Base Address register in the PCI configuration space before the first access to the Expansion ROM. The Am79C972 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to 1. A fter the Expansion ROM is enabled, the Am79C972 controller will claim all memory read accesses with an address between ROMBASE and ROMBASE + 1M - 4 ( ROMBASE, PCI E xpansio n ROM Base Address register, bits 31-20). The add ress output to the Expansion ROM is the offset from the address on the PCI bus to ROMBASE. The Am79C972 controller aliases all acces ses to the Expansion ROM of the command types Memory Read Multiple and Mem- ory Read Line to the basic Memory Read command.

EBUA_EBA[7:0]

Am79C972

EBWE

EROMCS

EBDA[15:8]

A[15:8] A[7:0]

EPROM

DQ[7:0] CS OE

AS_EBOE

Figure 40. EPROM Only Configuration for the Expansion Bus (64K EPROM )

Am79C972 75

21485C-43

EBD[7:0]

Am79C972

EBWE

EBUA_EBA[7:0]

EROMCS

EBDA[15:8]

’374

D-FF

A[23:16] A[15:8] A[7:0]

EPROM

DQ[7:0] CS OE

AS_EBOE

Figure 41. EPROM Only Configuration for the Expansion Bus (>64K EPROM)

Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given to the PCI Memory Mapped I/O Base Address register, before enabling access to the Expansion ROM. The host must set the PCI Memor y Mapped I/O Bas e Address register to a value that prevents the Am79C972 controller from claiming any memory cycles not intended for it.

During the boot procedure, the system will try to find an Expansion ROM. A PCI sys tem assumes that an Ex pansion ROM is present when it reads the ROM signature 55h (byte 0) and AAh (byte 1).

Direct Flash Access

Am79C972 controll er su pports Flas h as an E xpa ns io n ROM device, as well as providing a read/write data path to the Flash. The Am79C972 controller will support up to 1 Mbyte of Flash on the Expansion Bus. The Flash is accessed by a read or wri te to the Expans ion

21485C-44

Bus Data por t (BCR30) . The use r must load t he up per address EP ADDRU (BCR 29, bits 3-0) and then set the FLASH (BCR29, bit 15) bit to a 1. The Flash read/write utilizes the PCI clock instead of the E BCLK during all accesses. EPADDRU is not needed if the Flash size is 64K or less, but still must be programmed. The user will then load the lower 16 bits of address, EP ADDRL (BCR 28, bits 15-0).

Flash/EPROM Read

A read to the Expansion Bus Data Port (BCR30) will start a read cycle on the Expansion Bus Interface. The Am79C972 contro ller will drive EBUA_EBA[7:0] wit h the most significant ad dres s byte at the sa me tim e th e Am79C972 controller will drive AS_EBOE

high to strobe the address in the external ‘374 (D flip-flop). On the next clock, the Am79C972 controller will drive EBDA[15:8] and EBUA_EBA[7:0] with the middle and least significant address bytes.

76 Am79C972

EBUA_EBA [7:0] Latched Address

CLK

EBDA [15:8]

EBD

AS_EBO

EROMCS

FRAME

IRDY

TRDY

DEVSEL

A[19:16]

10 15 20 25

30 35 40 45 50 55 60 66

A[7:2], 0, 1A[7:2], 0, 0

Figure 42. Expansion ROM Bus Read Sequence

A[7:2], 1, 0 A[7:2], 1, 1

21485C-45

EBUA[19:16]

CLK

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EROMCS

AS_EBOE

1 2

Figure 43. Flash Read from Expansion Bus Data Port

The EROMCS is driven low for the value ROMTMG +

1. Figure 43 assumes that ROMTMG is set to nine. EBD[7:0] is sampled with the next rising edge of CLK ten clock cycles after E BUA_EBA[7:0] was dr iven with a new address value. This PCI slave access to the Flash/EPROM will result in a retry for the very first access. Subsequent accesses may give a retry or not, depending on whether or not the data is present and valid. The access time is dependent on the ROMTMG bits (BCR18, bits 15-12) and the Flash/EPROM. This access mechanism di ffers from the Expansi on ROM access mechanism since only one byte is read in this manner, instead of the 4 bytes in an Expansi on ROM access. The PCI bus will not be held d uring ac cesses through the Expansion Bus Data Port. If the LAAINC

3 4 5 6 7 8 9 10 11 12 13

EBA[7:0]

EBDA[15:8]

(BCR29, bit 15) is set, the EBADDRL address wil l be incremented and a continuous series of reads from the Expansion Data Port (EBDATA, BCR30) is possible. The address incre mentor wi ll ro ll over without war nin g and without incrementing the upper address EBADDRU.

The Flash write is almost the same procedure as the read access, except that the Am7 9C972 c ontr oller wi ll not drive AS_EBOE

low. The EROMCS and EBWE are driven low for the value ROMTMG again. The wri te to the FLASH port is a posted write and will not result in a retry to the PCI unless the host tries to write a new value before the previous write is complete, then the host will experience a retry. See Figure 44.

21485C-46

Am79C972 77

EBUA[19:16]

CLK

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EROMCS

AS_EBOE

EBWE

1 2

Figure 44. Flash Write from Expansion Bus Data Port

AMD Flash Programming

AMD’s Flash products are p rogrammed on a byte-bybyte basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of EBWE and the data is latched on the rising edge of EBWE. The rising edge of EBWE

begins programming.

Upon executing the AMD Flash Em bedded Program Algorithm command sequence, the Am79C972 controller is not required to provide fur th er controls or timing. The AMD Flash product wil l compliment EBD[7] during a read of the programmed location until the programming is complete. Th e host sof tware should poll the programmed address u ntil EBD[7] matches th e programmed value.

AMD Flash byte programming is allowed in any sequence and across sector boundaries. Note that a data

0 cannot be programmed back to a 1. Only erase operations can convert zeros to ones. AMD Flash chip

erase is a six-bus cycle operation. There are two unlock write cycles, followed by writing the set-up command. Tw o mo re unlock cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erasure. Upon executing

3 4 5 6 7 8 9

EBA[7:0]

EBDA[15:8]

10 11 12 13

the AMD Flash Embedde d Erase Algor ithm com mand sequence, the Flash device will program and verify the entire memory for an all zero data pattern prior to electrical erase. The Am 79C972 controll er is not require d to provide any controls or timi ngs durin g these operations. The automatic erase begins on the rising edge of the last EBWE

pulse in the command sequence and terminates when the data on EBD[7] is 1, at which time the Flash device retur ns to the read m ode. Polling by the Am79C972 controller is not required dur ing the erase sequen ce. The following F LASH program mingtable excerpt (Table 9) sh ows the comm and seque nce for byte programming and sector/chip erasure on an AMD Flash device. In the following table, PA and PD stand for programmed address and programmed data, and SA stands for sector address.

The Am79C972 controller will support only a single sector erase per comman d and not concurrent s ector erasures. The Am79C972 contr oller will suppor t most FLASH devices as long a s there is no timing r equirement between the completion of commands. The FLASH access time cannot be guaranteed with the Am79C972 controller access mechanism. The Am79C972 controller will also support only Flash devices that do not require data hold times after write operations.

21485C-47

Table 9. Am29Fxxx Flash Command

Bus

Write

Command

Sequence

Byte Program 4 5555h AAh 2AAAh 55H 5555h A0h PA PD

Chip Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h

Sector Erase 6 5555h AAh 2AAAh 55H 5555h 80h 5555h AAh 2AAAh 55h SA 3h

Cycles

Req’d

First Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Write Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

78 Am79C972

SRAM Configuration

The Am79C972 controller supports SRAM as a FIFO extension as well as providing a read/write data path to the SRAM. The Am79C972 controller contains 12 Kbytes of SRAM.

Internal SRAM Configuration

The SRAM_SIZE (BCR25, bi ts 7-0) pr ograms the size of the SRAM. SRAM_SIZE can be programmed to a smaller value than 12 Kbytes.

The SRAM should be programmed on a 512-byte boundary. Howe ver , there should be no accesses to the RAM space while the Am79C972 controller is running. The Am79C972 controller assumes that it completely owns the SRAM while it is in operation. To specify how much of the SRAM is allocated to transmit and how much is allocated to receive, the user sho uld program SRAM_BND (BCR26, bits 7-0) with the page boundary where the receive buffer begins. The SRAM_BND also should be programmed on a 512-byte boundary. The transmit buffer space starts at 0000h. It is up to the user or the software driver to sp lit up the mem or y for transmit or receive; there is no defaulted value. The minimum SRAM size required is four 512-byte pages for each transmit and receive queue, which li mits the SRAM size to be at least 4 Kbytes.

The SRAM_BND upon H_RESET will be reset to 0000h. The Am79C 972 controller will not have any transmit buffer space unless SRAM_BND is programmed. The last configuration parameter necessary is the clock source us ed to contr ol the E xpansion B us interface. This is programmed through the SRAM Interface Control register. The externally driven Expansion Bus Clock (EBCLK) can be used by specifyi ng a value of 010h in EBCS (BCR27, bits 5-3). This allows the user to utilize any clock that may be available.

There are two standa rd clocks that can be c hosen as well, the PCI clock or the externally provided time base clock. Use of the internal clock is not recommended. When the PCI or time base clock is used, the EBCLK does not have to be dr iven, but it must be ti ed to VDD through a resistor. The user must specify an SRAM clock (BCR27, bits 5-3) that will not stop unless the Am79C972 controller is stopped. Otherwise, the Am79C972 controller will report buffer overflows, underflows, corrupt data, and will hang eventually.

The user can decide to use a fast clock and then divide down the frequency to get a better duty-cycl e if required. The choices are a di vide by 2 or 4 and is programmed by the CLK_FA C bits (BCR27, bits 2-0). Note that the Am79C972 controller does not support an SRAM frequency above 33 MHz regardless of the clock and clock factor used.

No SRAM Configuration

If the SRAM_SIZE (BCR2 5, bits 7-0) value is 0 i n the SRAM size regist er, the Am79C972 controller wi ll assume that there is no SR AM pres ent a nd wi ll rec onfi gure the four intern al FIFOs into two FIFOs, one for transmit and one for receive. The FIFOs will operate the same as in the PCnet-PC I II controller. When th e SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM BND (BCR26, bits 7-0) are i gnored by the Am7 9C972 controller. See Figure 45.

Low Latency Receive Configuration

If the LOLATRX (BCR2 7, bit 4) bit is set to 1, then the Am79C972 controller will configure itself for a low latency receive configuration . In thi s mod e, SRAM is required at all times. If th e SRAM_SIZ E (BCR25, bi ts 7-

0) value is 0, the Am79C972 control ler will not configure for low latency receive mode. The Am79C972 controller will provide a fast path on the receive side bypassing the SRAM. All trans mit traffic will go to the SRAM, so SRAM_BND (BCR26, bits 7-0) has no meaning in low latency receive mode. When the Am79C972 controller has received 16 bytes from the network, it will start a DMA reques t to the PCI B us Interface Unit. The Am79C972 controller wi ll not wait for the first 64 bytes to pass to check for collisions in L ow Latency Receive mode. The Am79C972 co ntroller must be in STOP before switching to this mode. See Figure 46.

CAUTION: T o pr ovide data integrity when switching into and out of the low latency mode, DO NOT SET the F AS TSPNDE bit when sett ing the SPND bit. Receive frames WILL Am79C972 controller may give erratic behavior when it is enabled again.

Direct SRAM Access

The SRAM can be acce ssed through the Expans ion Bus Data por t (BCR30). To access this data por t, the user must load the upper address EPADDRU (BCR29, bits 3-0) and set FLASH (BCR29, bit 15) to 0. Then the user will load the lower 16 bits of address EPADDRL (BCR28, bits 15-0). To initiate a read, the user reads the Expansion Bus Da ta Port (BCR 30). Th is slave access from the PCI wil l resul t in a r etry for the very first access. Subsequent a cces s es m ay give a retr y or no t, depending on whether or not the data is present and valid. The direct SRAM access uses the same FLASH/ EPROM access except for accessing the SRAM in word format instead of byte format. This access is meant to be a diagnostic acces s only. The SRAM can only be accessed wh ile the Am79C9 72 control ler is i n STOP or SPND (FASTSPNDE is set to 0) mode.

be overwritten and the

Am79C972 79

Bus

Rcv

FIFO

MAC

Rcv

FIFO

PCI Bus

Interface

Unit

MAC

Xmt

FIFO

Buffer

Management

Unit

Bus Xmt

FIFO

Control

Figure 45. Block Diagram No SRAM Configuration

802.3 MAC Core

21485C-48

Bus Rcv

FIFO

PCI Bus

Interface

Unit

Bus Xmt

FIFO

Buffer

Management

Unit

SRAM

FIFO

Control

Figure 46. Block Diagram Low Latency Receive Configuration

80 Am79C972

MAC

Rcv

FIFO

802.3 MAC Core

MAC

Xmt

FIFO

21485C-49

EEPROM Interface

The Am79C972 con t roll er contains a built-in ca pab il ity for reading and wr iting to an exter nal serial 93 C46 EEPROM. This built-in capability consists of an interface for direct connection to a 93C46 compatible EEPROM, an automatic EEPROM read feature, and a user-programmable register that allows direct access to the interface pins.

Automatic EEPROM Read Operation

Shortly afte r the deassertion of the RST Am79C972 controller will read the cont ents of the EEPROM that is attac hed to the in terface. Becaus e of this automatic-read capability of the Am79C972 controller, an EEPROM can be used to program many of the features of the Am79C972 controller at power-up, allowing system-dependent configuration information to be stored in the hardware, instead of inside the device driver.

If an EEPROM exists on the interface, the Am79C972 controller will read the EEPROM contents at the end of the H_RESET operation. The EEPROM contents will be serially shifted into a temporary register and then sent to various register locations on board the Am79C972 controller. Access to the Am79C972 configuration space, the Expansion ROM or any I/O resource is not possible during the EEPROM read operation. The Am79C972 controller will te rminate any access attempt with the assertion of DEVSEL

while TRDY is not asse r t ed, signal ing to the ini-

STOP tiator to disconnect and retry the access at a later time.

A checksum verification is per formed on the data tha t is read from the EEPROM. If the checksum verification passes, PVALID (BCR19, bit 15) will be set to 1. If the checksum verification of the EEPROM data fails, PVALID will be cleared to 0, and the Am79C972 controller will force all EEPROM- programmable BCR registers back to their H_RESET default values. However, the content of the Address PROM locations (offsets 0h - Fh from the I/O or mem ory ma pped I/O base address) will not be cleared. The 8-b it checksum for the entire 68 bytes of the EEPROM should be FFh.

If no EEPROM is present a t the time of the automatic read operation, the Am79C972 controller will recognize this condition and will abor t the autom atic read op eration and clear both the P READ and PVALID bits in BCR19. All EEPROM-programmable BCR registers will be assigned their default values after H_RESET. The content of the Address PROM loc ations (offsets 0h - Fh from the I/O or mem ory ma pped I/O base address) will be undefined.

EEPROM Auto-Detection

The Am79C972 controller uses the EESK/LED1 pin to determin e if an EEPROM is pres ent in the system. At the rising edge of CLK during the last clock dur-

pin, the

and

/SFBD

ing which RST will sample the value of t he EESK/LED1 the sampled value is a 1, then the Am79C972 controller assumes that an EEPROM is present, and the EEPROM read operation begins shortly after the RST is deasserted. If the sampled value of EESK/LED1 SFBD is a 0, the Am79C972 controller assumes that an external pulldown device is holding the EESK/LED1 SFBD pin low, indicating that there is no EEPROM in the system. Note that if the designer crea tes a syste m that contains an LED circuit on the EESK/LED1 pin, but has no EEPROM prese nt, then the EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the system. However, this will not pose a problem for the Am79C972 controller, since the checksum verification will fail.

Direct Access to the Interface

The user may directly access the port through the EEPROM register, BCR19. This regist er contains bits that can be used to con trol the interface pins. By performing an approp riate sequence of acc esses to BCR19, the user can effectively write to and read from the EEPROM. This feature may be used by a syste m configuration utility to program har dware configuration information into the EEPROM.

EEPROM- Programmable Registers

The following registers contain configuration information that will b e programmed aut omatically du ring the EEPROM read operation:

n I/O offsets 0h-Fh Address PROM locations n BCR2 Miscellaneous Configuration n BCR4 LED0 Status n BCR5 LED1 Status n BCR6 LED2 Status n BCR7 LED3 Status n BCR9 Full-Duplex Control n BCR18 Burst and Bus Control n BCR22 PCI Latency n BCR23 PCI Subsystem Vendor ID n BCR24 PCI Subsystem ID n BCR25 SRAM Size n BCR26 SRAM Boundary n BCR27 SRAM Interface Control n BCR32 MII Control and Status n BCR33 MII Address n BCR35 PCI Vendor ID n BCR36 PCI Power Management

is asserted, the Am79C972 controller

/SFBD pin. If

/SFBD

Capabilities (PMC) Alias Register

/ /

Am79C972 81

n BCR37 PCI DA TA Register Zero (DAT A0)

Alias Registe r

n BCR38 PCI DATA Register One (DATA1)

Alias Register

n BCR39 PCI DATA Register Two (DATA2)

Alias Registe r

n BCR40 PCI DATA Register Three

(DATA3) Alias Register

n BCR41 PCI DA TA Regi ste r Four (DATA4)

Alias Registe r

n BCR42 PCI DATA Register Five (DATA5)

Alias Registe r

n BCR43 PCI DATA Register Six (DATA6)

Alias Registe r

n BCR44 PCI DATA Register Seven

(DATA7) Alias Register

n BCR45 OnNow Pattern Matching

n BCR46 OnNow Pattern Matching

n BCR47 OnNow Pattern Matching

n CSR116 OnNow Miscellaneous

If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15) are cleared to 0, then the EEPROM read has experienced a failure and the contents of the EEPROM programmable BCR register will be set to default H_RESET values. The content of the Address PROM locations, however, will not be cleared.

Accesses to the Address PROM I/O locations do not directly access the Address EEPROM itself. Instead, these accesses are routed to a set of shadow registers on board the Am79C972 controller that are loaded with a copy of the EEPROM contents dur ing the aut omatic read operation that imm ediately follows the H_RESET operation.

EEPROM MAP

The automatic EEPROM read operation will access 34 words (i.e., 68 bytes) of the EEPROM. The format of the EEPROM contents is sh own in Table 10 (next page), beginning with the byte that resides at the lowest EEPROM address.

Note: The first bit out of any word loc ation in the EEPROM is treated as the MSB of the register being programmed. For example, the first bit out o f EEPROM word location 09h will be wri tten into BCR4 , bi t 15; th e second bit out of EEPROM word location 09h will be written into BCR4, bit 14, etc.

There are two checksum locations within the EEPROM. The first checksum will be used by AMD driver software to verify that the ISO 8802-3 (IEEE/ANSI

802.3) station address has not been corrupted. The value of bytes 0Ch and 0Dh should ma tch the su m of bytes 00h through 0Bh and 0Eh and 0Fh. The sec ond checksum location (byte 43h) is not a checksum total, but is, instead, a checksum adjustment. The value of this byte should be such that the total checksum for the entire 68 bytes of EEPROM data equals the value FFh. The checksum adjust byte is needed by the Am79C972 controller in order to verif y that the EEP ROM content has not been corrupted.

LED Support

The Am79C9 72 contr oller ca n suppo rt up to fo ur LEDs . LED outputs LED0 connection of an LED and its supporting pullup device.

In applications that want to use the pin to drive an LED and also have an EEPROM, it mig ht be necessar y to buffer the LED3 When an LED circuit is directly connec ted to the EEDO/LED3 EEPROM devices to sink enough I low level on the EEDO input to the Am79C972 controller. Use of buffering can be avoided if a low power LED is used.

, LED1, and LED2 allow for direct

circuit from the EEPROM connec tion.

/SRD pin, then it is not possible for most

to maintain a valid

Each LED can be programmed through a BCR register to indicate one or more of the following network st atus or activities: Col lision Status, Fu ll-Duplex Link Status, Half-Duplex Link Status, Receive Match, Recei ve Status, Magic Packet, Disable Transceiver, and Transmit Status.

82 Am79C972

Table 10. EEPROM Map

Word

Address

00h* 01h

01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h CSR116[15:8] (OnNow Misc. Config.) 06h CSR116[7:0] (OnNow Misc. Config.)

04h 09h 05h 0Bh User programm able space 0Ah User programmable space

06h 0Dh

07h 0Fh 08h 11h BCR2[15:8] (Miscellaneous Configurat ion) 10h BCR2[7:0] (Miscellaneous Confi gur at ion )

09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED) 0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status)

0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status) 0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status) 0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control)

0Eh 1Dh BC R18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control)

0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Lat ency)

10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BC R23[7:0] (PCI Subsystem Vendor ID)

11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR24[7:0] (PCI Subsystem ID)

12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size)

13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7: 0] (SRAM Bo und ary)

14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control)

15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status)

16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address)

17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID)

18h 31h BCR36[15:8] (Conf. Space byte 43h alias) 30h BCR36[7:0] (Conf. Space byte 42h alias)

19h 33h BCR37[15:8] (DATA_SCALE alias 0) 32h BCR37[7:0] (Conf. Space byte 47h 0 alias)

1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Space. byte 47h 1 alias)

1Bh 75h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Space. byte 47h 2 alias) 1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Space. byte 47h 3 alias) 1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Space. byte 47h 4 alias)

1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 0) 3Ch BCR42[7:0] (Conf. Space. byte 47h 5 alias)

1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 0) 3Eh BCR43[7:0] (Conf. Space. byte 47h 6 alias)

20h 41h BCR44[15:8] (DATA_SCALE alias 0) 40h BCR44[7:0] (Conf. Space. byte 47h 7 alias)

21h 43h

Byte

Address

Most Significant Byte

2nd byte of the ISO 8802-3 (IEEE/ANSI 802. 3) station physical address for this node.

Hardware ID; must be 11h if compatibility to AMD drivers is desired

MSB of two-byte c he cksum, which is the s um of bytes 00h-0Bh and bytes 0Eh and 0Fh

Must be ASCII “W” (57h) if compatibility to AMD driver so ftware is desired

Checksum adjust byte for the 68 bytes of the EEPROM contents. Chec ksum of the 68 bytes of the EEPROM should total FFh.

Byte

Address

First byte of the ISO 8802-3 (IEEE/ANSI

00h

08h Reserved location: must be 00h

0Ch

0Eh

42h Reserved location: must be 00h

802.3) station physical address for this node, where “fi rst byte” refers to the first byte to appear on the 802.3 medium.

LSB of two-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh

Must be ASCII “W” (57h) if compatibility to AMD driver software is desired

Least Significant Byte

Unused locations - Ignored by device

3Fh 7Fh Reserved 7Eh Reserved

(active high). The output can be stret ched t o all ow the human eye to recognize even short events that last only several microseconds. After H_RESET, the four LED

The LED pins can be configur ed to operate in either

outputs are configured as shown in Table 11.

open-drain mode (acti ve low) or in totem-pole mode

Am79C972 83

Table 11. LED Default Configuration

LED

Output Indication Driver Mode Pulse Stretch

Open Drain -

LED0 Link Status

Receive

LED1

LED2 --

LED3

Status

Transmit

Status

Active Low Enabled

Open Drain -

Active Low Enabled

Open Drain -

Active Low Enabled

Open Drain -

Active Low Enabled

For each LED register, each of the status signals is AND’d with its enable signal, and thes e signa ls are all OR’d together to form a combined stat us signal. Each LED pin combined status signal can be programmed to run to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 Hz (26 ms). The data in put of each shift register is norm ally at logic 0. The OR gat e output for each LED register asynchronously sets all three bits of its shift register when the output becomes asser ted. The invert ed output of eac h shift regis ter is used to control an L ED pin. Thus, the pulse s tretcher provides 2 to 3 cl ocks of stretche d LED output, or 52 ms to 78 ms. See Figure 47.

Power Savings Mode

Power Management Support

PCnet-FAST+ supports power management as defined in the PCI Bus Power Management Interface Specification V1.0 and Network Device Class Power Management Reference Specification V1.0.These specifications def ine the network device power states, PCI power management interface includin g the Capabilities Data Structure and power management registers block definitions, power manageme nt events, and OnNow network Wake-up events. In addition, PCnet-FAST+ supports legacy power management schemes, such as Re mote Wake-Up (RWU) mode. When the system is in RWU mode, PCI bus power is on, the PCI clock may be slowed down or stopped, and the wake-up output pin may drive the CPU's System Management Interrupt (SMI) line.

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

SPEED_SEL

100E

MPS

MPSE

Pulse Stretcher

21485C-50

Figure 47. L ED Control Logic

The general scheme for the PCnet-FAST+ power management is that when a PCI Wake-up event is detected, a signal is generated to cause hardware external to the PCnet-FAST+ device to put the computer into the working (S0) mode.

The PCnet-FAST+ device supports three types of wake-up events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change Figure 48 shows the relationship between these Wake-

up events and the various outputs used to signal to the external hardware.

Note: The OnNOW Pattern Match and Link State Change only work on the MII interface.

OnNow Wake-Up Sequence

The system software enables the PME

pin by settin g the PME_EN bit in the PMCSR register (PCI configuration registers, offse t 44h, bit 8) to 1 . When a Wake-up event is detected, the PCnet-FAST+ device sets the PME_STATUS bit in the PMCSR register (PCI configuration registers, offset 44h, bit 15). Setting this bit causes the PME

signal causes exter nal hardware to wake up the

PME

signal to be asserted. Assertion of the

CPU. The system software then reads the PMCSR register of every PCI device in the system to determin e which device asserted the PME

signal.

84 Am79C972

MPPEN

MPMODE

Magic Packet

WUMI

MPINT

MPMAT

SET

LED

MPEN

LCMODE

Link Change

Input

Pattern

MPDETECT

Link Change

H_RESET

Pattern Match

BCR47 BCR46 BCR45

Pattern Match RAM (PMR)

POR

SET

CLR

POR

CLR

RWU

LCDET

SET

CLR

POR

SET

CLR

PMAT

PME_EN

MPMAT

POR

PME Status

PME_STATUS

DET

CLR

PME

Figure 48. OnNow Functional Diagram

When the software determines that the signal came from the PCnet-FAST+ device, it writes to th e device’s PMCSR to put the device into power state D0. The software then writes a 0 to the PME_STATUS bit to clear the bit and turn off the PM E

signal, and it call s the device’s software driver to tell it that the device is now in state D0. The system software can clear the PME_STATUS bit either before, after, or at the same time that it puts the device back into the D0 state.

Link Change Detect

Link change dete ct is one of Wake-up events defined by the OnNow specificati on and is suppor ted by the RWU mode. Link Change Detect mode is set when the LCMODE bit (CSR116, bit 8) is set either by software or loaded through the EEPROM.

PME_EN_OVR

LCEVENT

21485C-51

When this bit is set, any chan ge in th e Link sta tus will cause the LCDET bit (CSR116, bit 9) to be set. When the LCDET bit is set, the RWU pin will be asserted and the PME_STATUS bit (P MCSR register, bit 15) will b e set. If either the PME_EN bit (PMCSR, bit 8) or the PME_EN_OVR bit (CSR116, bit 10) are set, then the

will also be asserted.

PME

OnNow Pattern Match Mode

In the OnNow Pattern Match Mode, the PCnet- FAST+ compares the incoming packets with up to eight patterns stored in the Pattern Match RAM (PMR). T he stored patter ns ca n be comp ared with pa rt or all of incoming packets, depending on the pattern len gth and the way the PMR is programmed. When a pattern match has been detected, then PMAT bit (CSR116, bit

7) is set. The setting of the PMAT bit causes the

Am79C972 85

PME_STATUS bit (PMCSR, bi t 15) to be set, whic h in turn will assert the PME (PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an array of 64 words by 40 bits as shown in Figure 49. The PMR is programmed indirectly through the BCRs 45, 46, and 47. When the BC R45 is written and the PMAT_MODE bit (BCR45, bit 7) is set to 1, Pattern Match logic is enabled. No bus access es into the PMR are pos sible when the PMAT_MODE bit is set, and BCR46, BCR47, and all other bits in BCR45 are ignored. When PMAT_MODE is set, a read of BCR45 returns all bits undefined except for PMAT _MODE. In order to a ccess the contents o f the PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 is wri tten to set th e PMAT_MODE bit to 0, the Pattern Match l ogic i s d is abled and accesses to the PMR are possible. Bits 6:0 of BCR45 specify the address of the PMR word to be accessed. Writing to BCR45 does not immediately affect the contents of the PMR. Following the write to BCR45, the PMR word addressed by the bits 6:0 of the BCR45 may be read by reading BCR45, BCR46, and BCR47 in any order. To write to the PMR word, the write to B CR45 must be followed by a write to BCR46 and a write to BCR 47 in that order to complete the operation. The PMR will not actually be written until the write to BCR47 is complete.

The first two 40-bit words in this RAM serve as pointers and contain ena ble bits for the eight possible mat ch patterns. The remainder of the RAM contains the match patterns and associated match pattern control bits. The byte 0 of the fir st word cont ains the Patter n Enable bits. Any bit position set in this byte enables the corresponding match pattern in the PMR, as an example if the bit 3 is set, then the Pattern 3 is ena bled for matching. Bytes 1 to 4 i n the first word are poin ters to the beginning of the patterns 0 to 3, and bytes 1 to 4 in the second word are pointers to the beginning of the patterns 4 to 7, respectively . Byte 0 of the second word has no function associated with it.The byte 0 of the words 2 to 63 is the Control Fiel d of the PMR. B it 7 of this field is the End of Packet (EOP) bit. When this bit is set, it indicates the end of a pattern in the PMR. Bits 64 of the Control Field byte are the SKIP bits. The value of the SKIP field indicates the number of the Dwords to be skipped before the pattern in this PMR word is compared with data from t he incoming fram e. A maximum of seven Dwords may be skipped. Bits 3-0 of the Control Field byte are the MASK bits. These bits correspond to the pattern match bytes 3-0 of the same PMR word (PMR bytes 4-1). If bit n of this field is 0, then byte n of the corresponding pa ttern word is ignor ed. If this field is programmed to 3, then bytes 0 and 1 of the pattern match fi eld (bytes 2 and 1 of the word) are used

pin if the PME_EN bit

and bytes 3 and 2 are ign ored in t he p atter n ma tchin g operation.

The contents of the PMR are not affected by H_RESET, S _RESET, or STOP. The contents are undefined after a power up reset (POR).

Magic Packet Mode

In Magic Packet mode, the PCnet-FAST+ controller remains fully powered up (all VDD an d VDDB pins must remain at their supply levels). The device will not generate any bus master transfers. No transmit operations will be initiated on the network. The device will continue to receive frames from the networ k, but all frames will be automatically fl ushed from the re ceive FIFO. Slave accesses to the PCnet-FAST+ controll er ar e st ill p ossi - ble. A Magic Packet is a frame that is addressed to the PCnet-FAST+ controller and contains a data sequence anywhere in its data field made up of 16 consecutive copies of the device’s physical address (PADR[47:0]). The PCnet-FAST+ controller will search incoming frames until it finds a Magic Packet frame. It starts scanning for the sequence after proc essing the l ength field of the frame. The data sequenc e can begin anywhere in the data field of the frame, but must be detected before the PCnet-FAST+ controller reaches the frame’s FCS field. A ny deviation of the incom ing frame’s data sequence from the required physical address sequen ce, even by a single bit, will prevent the detection of that frame as a Magic Packet frame.

The PCnet-FAST+ controller suppo rts two different modes of address detec tion for a Magic Packet frame. If MPPLBA (CSR5, bit 5) or EMPPLBA (CSR116, bit 6) are at their default value of 0, the PCnet-FAST+ controller will only detect a Ma gic Packet frame if the destination address of t he packet matches the content of the physical address register (PADR). If MPP LBA or EMPPLBA are set to 1 , the desti nation addres s of the Magic Packet frame can be unicast, multicast, or broadcast.

Note: The setting of M PPLBA or EMPPLBA onl y effects the address detection of the Magic Packet frame. The Magic Packet’s data sequence must be made up of 16 consecutive copies of the device’s physical ad- dress (P ADR[47:0]), regardless of what kind of destination address it has.

86 Am79C972

BCR 47 BCR 46 BCR 45 BCR Bit Number 15 8 7 0 15 8 7 0 15 8

PMR_B4 PMR_B3 PMR_B2 PMR_B1 PMR_B0

Pattern Match RAM Address

2+n Data Byte 4n+3 Date Byte 4n+2 Data Byte 4n+1 Data Byte 4n+0 Pattern Control End P atte rn P

J Data Byte 3 Data Byte 2 Data Byte 1 Data Byte 0 Pattern Control Start Pattern P

J+m Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P

63 Last Address

39 32 31 24 23 16 15 8 7 0

P3 pointer P2 pointer P1 pointer P0 pointer

P7 pointer P6 pointer P5 pointer P4 pointer X

Data Byte 3 Data Byte 2 Data Byte1 Data Byte 0 Pattern Control

Pattern Match RAM Bit Number

Pattern Enable

bits

Comments

First Address

Second

Address

Start Pattern

Figure 49. Pattern Match RAM

There are two ge neral methods to place the PC netFAST+ into the Magic Packet mode. The first is the software method. In this meth od, e ither th e BIO S o r other software, sets the MPMODE bit (CSR5, bit 1). Then PCnet-FAST+ control ler must be put into suspend mode (see description of CSR5, bit 0), allowing any current network activity to finish. Finally , either PG must be deasserted (hardware control) or MPEN (CSR5, bit

2) must be set to 1 (software control).

Note: F ASTSPNDE (CSR7, bit 15) has no meaning in Magic Packet mode.

The second method is the hardware method . In this method, the MPPEN bit (CSR116, bit 4) is set at power up by the loading of the EEPROM. This bit can also be set by software. The PCnet-FAST+ will be place d in the

7 6 5 4 3 2 1 0 EOP SKIP MASK

21485C-52

Magic Packet Mode when either the PG input is deasserted or the MPEN bit is set. WUMI

output wi ll be assert ed when the PCnet-FAST+ is in the Magic Packet mode. Magic Packet mode can be disabled a t any time by asserting PG or clearing MPEN bit.

When the PCnet-FAST+ controller detec ts a Magic Packet frame, it sets the MPMAT bit (CSR116, bit 5), the MPINT bit (CSR5, bit 4), and the PME_STATUS bit (PMCSR, bit 15). The setting of the MPMAT bit will also cause the RWU pin to be asserted and if the PME_EN or the PME_EN_OVR bits are set, then the PME

will be asserted as well. If IENA (CSR0, bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA

will be asser ted. Any one of the four LED pins c an be programmed to indicate that a Magic Packet frame has been received.

Am79C972 87

MPSE (BCR4-7, bit 9) must be set to 1 to enable that function.

Note: The polarity of the LED pin can be programmed to be active HIGH by setting LEDPOL (BCR4-7, bit 14) to 1.

Once a Magic Packet frame is detected, the PCnetFAST+ controller will discard the frame internally, but will not resume normal transmit and receive operations until PG is asserted or MP E N is cl ea re d. O nc e b oth o f these events has occurred, indicating that the system has detected the Magic Packet and is awake, the controller will continue polling receive and transmit descriptor rin gs where i t left off. It is not neces sar y to reinitialize the device. If the par t is reinitia lized, then the descriptor locations will be reset and the PCnet-FAST+ controller will not start where it left off.

If magic packet mode is disabled by the assertion of PG, then in order to immediately re-enable Magic Packet mode, the PG pin must re main asser ted for at least 200 ns before it is deasserted. If Magic Packet mode is disabled by cleari ng M PE N bi t, the n it may be immediately re-enabled by setting MPEN back to 1.

The PCI bus interface clock (CLK) is not required to be running while th e device is operating in Magic Packet mode. Either of the INTA

signal may be used to indicate the receipt of a

PME

, the LED pins, RWU or the

Magic Packet frame when the CLK is stopped. If the system wishes to stop the CLK, it will do so after enabling the Magic Packet mode.

CAUTION: To prevent unwanted interrupts from oth er active parts of the PCnet-FAST+ controller, care must be taken to mask all likely interruptible events during Magic Packet mode. An example would be the interrupts from the Media Independent Interface, which could occur while the device is in Magic Packet mode.

IEEE 1149.1 (1990) Test Access Port Interface

An IEEE 1149.1-comp atible boundary scan Test Access Port is provided for board-level continuity test and diagnostics. All digital input, output, and input/output pins are tested. The following paragraphs summarize the IEEE 1149.1-compatible test functions implemented in the Am79C972 controller.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK, TMS, TDI, and TDO), defined as the Test Access Port (TAP). It inc ludes a finite state machine ( FSM), an instruction r egis ter, a data regist er ar r a y, and a po w er -on reset circuit. Inter nal pull-up resistors are pr ovided for the TDI, TCK, and TMS pins.

Mode Select (TMS) pins. An independent power-on reset circuit is provided to ensure that the FSM is in the TEST_LOGIC_RESET st ate at power-up. Therefore, the TRST

is not provided. The FSM is also reset when

TMS and TDI are high for five TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requ irements (BYPASS, EXTEST, and SAMPLE instructions), three additional instructions (IDCODE, TRIBYP, and SETBYP) are provided to fur ther ease bo ard-level testing. All unused instruction codes are reserved. See Table 12 for a summary of supported instructions.

Table 12. IEEE 1149.1 Supported Instruction

Summary

Instructio

Name

EXTEST 0000 External Test Test BSR IDCODE 0001

SAMPLE 0010

TRIBYP 0011 Force Float Normal Bypass

SETBYP 0100

BYPASS 1111 Bypass Scan Normal Bypass

Instructi

Code

Description Mode

ID Code Inspection

Sample Boundary

Control Boundary To 1/0

Normal ID REG

Normal BSR

Test Bypass

Selected

Data

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE i nstr ucti on is always invoked. The decoding logic gives signals to control the data flow in the Data registers according to the current instruction.

Boundary Scan Register

Each Boundar y Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the Serial Shift Stage and the Parallel Output Stage, respectively. There are four possible operation modes in the BSR cell shown in Table 13.

Table 13. BSR Mode Of Operation

1 Capture 2 Shift 3 Update 4 System Function

TAP Finite State Machine

The TAP eng ine is a 16-state finite state machine (FSM), driven by the Test Clock (TCK), and the Test

88 Am79C972

Other Data Registers

Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 14).

Table 14. Device ID Register

Bits 31-28 Version Bits 27-12 Part Number (0010 0110 0010 0100)

Manufact urer ID. The 11 bit manufacturer ID

Bits 11-1

Bit 0 Always a logic 1

cod for AMD is 000000 00001 in accord ance with JEDEC publication 106-A.

Note: The content of the Device ID register is the same as the content of CSR88.

NAND Tree Testing

The Am79C972 controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit bo ar d. The NAND tree is built on all PCI bus, TBC_EN, and EAR

NAND tree test ing is enabled by ass erting RST input should be driven HIGH during NAND tree testing. All PCI bus signals will become inputs on the assertion

pins.

. PG

of RST served on the INTA

Pin 143 (RST

. The result of the NAND tree test can be ob-

pin. See Figure 50.

) is the first input to the NAND tree. Pi n 144 (CLK) is the second input to the NAND tree, followed by pin 145 (GNT low, counterclockwise, with pin 129 (EAR

). All other PCI bus signals fol-

) being the last. T able 15 shows the complete list of pins connected to the NAND tree.

must be asserted low to start a NAND tree test se-

RST quence. Initially, all NAND tree inputs except RST should be driven high. This will result in a high outpu t at the INTA

pin. If the NAND tree inputs are driven from high to low in the same order as they are connected to build the NAND tree, INT A ditional input is driven low. INTA

will toggle every time an ad-

will change to low, when CLK is driven low and all other NAND tree inputs stay high. INTA

will toggle back to high, when GNT is additionally dr iven low. The square wave will continue until all NAND tr ee inputs ar e driven low. INTA

will be high, when all NAND tree inputs are driven low. See Figure 51.

Some of the pins connected to the NAND tree are outputs in normal mode of operation. They must not be driven from an external source until the Am79C972 controller is configured for NAND tree testing.

RST (pin143)

CLK (pin 144)

GNT (pin 145)

EAR (pin 129)

VDD

....

Am79C972

Core

INTA

B A

MUX

INTA (pin 142)

21485C-53

Figure 50. NAND Tree Circuitry

Am79C972 89

Table 15. NAND Tree Pin Sequence

NAND T ree

Input No.

Pin No. Name

NAND Tree

Input No.

Pin No. Name

NAND Tree

Input No.

Pin No. Name

1 143 RST 18 7 AD20 35 34 AD13 2 144 CLK 19 9 AD19 36 36 AD12 3 145 GNT 20 10 AD18 37 37 AD11 4 146 REQ 21 12 AD17 38 39 AD10 5 148 AD31 22 14 AD16 39 40 AD9 6 151 AD30 23 15 C/BE2 40 41 AD8 7 152 AD29 24 17 FRAME 41 42 C/BE0

8 153 AD28 25 18 IRDY 42 44 AD7

9 154 AD27 26 20 TRDY 43 46 AD6 10 156 AD26 27 22 DEVSEL 44 47 AD5 11 158 AD25 28 23 STOP 45 49 AD4 12 159 AD24 29 25 PERR 46 50 AD3 13 160 C/BE3 30 26 SERR 47 52 AD2

14 1 IDSEL 31 28 PAR 48 54 AD1 15 2 AD23 32 30 C/BE1 49 55 AD0

16 4 AD22 33 31 AD15 50 123 TBC_EN 17 6 AD21 34 33 AD14 51 129 EAR

RST

CLK

GNT

REQ

AD[31:0]

C/BE[3:0]

IDSEL

FRAME

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

...

INTA

FFFFFFFF

... ...

Figure 51. NAND Tree Waveform

0000FFFF

21485C-54

90 Am79C972

Reset

There are four different types of RESET operations that may be performed on the Am79C972 device, H_RESET, S_RESET, STOP, and POR. The following is a description of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C972 reset operation that ha s been create d by the proper as sertion of the RST PG pin is HIGH. When the minimum pulse width timing as specified in the RST fied, then an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR registers to their default value. Note that there are several CSR and BCR registers that are undefined after H_RESET. See the sections on the individual registers for details.

H_RESET will clear most of the registers in the PCI configuration space. H_RESET will cause the microcode program to jump to its reset s tate. Following the end of the H_RESET operation, the Am79C972 controller will attempt to read the EEPROM device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the Am79C972 controller will be in 16-bit I/O mode after the reset operation. A DWord write operation to the RDP (I/O offs et 10h ) must be performed to set t he device into 32-bit I/O mode.

S_RESET

Software Reset (S_RESET) is an Am79C972 reset operation that has been created by a read acc ess to th e Reset regist er, which is located at offs et 14h in Word I/O mode or offset 18h in DWord I/O mode from the Am79C972 I/O or memory mapped I/O base address.

S_RESET will reset all of or some portions of CSR0, 3, 4, 15, 80, 100, and 124 to default values. For the identity of individual CSRs and bit locations that are affected by S_RESET, see the individual CSR register descriptions. S_RESET will not affect any PCI configuration space location. S_RESET will not affect any of the BCR register values. S_RESET will cause the microcode program to jump to its reset state. Following the end of the S_RESET operation, the Am79C972 controller will not attempt to read the EEPROM device. After S_RESET, the host must perfor m a full re-i nitialization of the Am79C972 controller before starting network activity. S_RESET will cause REQ immediately. STOP (CSR0, bit 2) or SPND (CSR5, bi t

0) can be used to ter minate any pend ing bus mastership request in an orderly sequence.

S_RESET termina tes all network activity abruptly. The host can use the suspend mode (SP ND, CSR5, bit 0)

pin of the Am79C972 device while the

pin description has been satis-

to deassert

to terminate all network activity in an orderly sequence before issuing an S_RESET.

STOP

A STOP reset is generated by the assertion of the STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0, when the stop bit currently has a value of 0, will initiate a STOP reset. If the STOP bit is already a 1, then writing a 1 to the STOP bit will not generate a STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4 to default values. For the identity of individual CSRs and bit locations that are affected by STOP, see the individual CSR register descriptions. STOP will not affect any of the BCR and PCI configuration space locations. STOP will cause the microcode p rogram to jum p to its reset state. Following the end of the STOP operation, the Am79C972 controller will not attempt to read the EEPROM device.

Note: STOP will not cause a deasser tion of the R EQ signal, if it happens to be active at the time of the write to CSR0. The Am79C972 controller will wait until it gains bus ownership and it will first finish all scheduled bus master accesses before the STOP reset is executed.

STOP terminates all network activity abruptly. The host can use the suspend mode (SPND, CSR5, bit 0) to terminate all network ac tivity in an order ly sequence before setting the STOP bit.

Power on Reset

Power on Reset (POR) is generated when the Am79C972 controller is powered up. POR generates a hardwar e res et (H_R ESE T). In addit ion , it cle ars so me bits that H_RESET does not affect.

Software Access

PCI Configuration Registers

The Am79C972 controller implements the 2 56-byte configuration space as defined by the PCI specification revision 2.1. The 64-byte header includ es all registers required to id entify the Am79C97 2 controller and i ts function. Additionall y, PCI Power Management Interface registers are implemented at location 40h - 47h. The layout of the Am79C972 PCI configuration space is shown in Table 16.

The PCI configuration regi sters ar e acce ssible only by configuration cycles. All multi-byte numeric fields follow little endian byte ordering. All write accesses to Reserved locations have no effect; reads from these locations will return a data value of 0.

I/O Resources

The Am79C972 controller requires 32 bytes of address space for access to all the various internal registers as well as to s om e set u p in formation st or ed in a n external serial EEPROM. A software reset port is available, too.

Am79C972 91

Table 16. PCI Configuration Space Layout

31 24 23 16 15 8 7 0 Offset

Device ID Vendor ID 00h

Status Command 04h

Base-Class Sub-Class Programming IF Revision ID 08h

Reserved Header Type Latency Timer Reserved 0Ch

I/O Base Address 10h

Memory Mapped I/O Base Address 14h

Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved CAP-PTR 34h

Reserved 38h

MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3Ch

PMC NXT_ITM_PTR CAP_ID 40h

DATA_REG PMCSR_BSE PMCSR 44H

Reserved Reserved FCh

. .

The Am79C972 controller supports mapping the address space to both I/O and memory space. The value in the PCI I/O Base Address register determines the start addres s of the I/O addres s space. The regi ster is typically programmed by the PCI configuration utility after system power-up. The PCI configuration utility must also set the IOEN bit in the PCI Command register to enable I/O accesses to the Am79C972 controller. For memory mapped I/O access, the PCI Memory Mapped I/O Base Address register controls the start address of the memory s pace. The MEMEN bit in the PCI Command register must also be set to enable the mode. Both base address registers can be active at the same time.

The Am79C972 contr oller supports two modes for accessing the I/O resources. For backwards compatibility with AMD’s 16- bit E thernet controlle rs, Word I/O is the default mode after power up. The device can be configured to DWord I/O mode by software.

I/O Registers

The Am79C972 controller registers are divided into two groups. The Control and Status Registers (CSR) are used to configure the Ether n et MAC engine and to obtain status information. The Bus Control Registers (BCR) are used to configu re the bus in ter face unit and the LEDs. Both sets of registers are accessed using indirect addressing.

The CSR and BCR share a common Register Address Port (RAP). Th ere are, however, separate data por ts. The Register Data Port (RDP) is used to access a

CSR. The BCR Data Por t (BDP) is used to access a BCR.

In order to access a par ticular CSR location, the RAP should first be written with the appropriate CSR address. The RDP will then point to the selected CSR. A read of the RDP will yiel d the selected CSR data. A write to the RDP will write to the selected CSR. In order to access a particular BCR location, the RAP should first be written with the app ropr iate B CR addr ess. The BDP will then poi nt t o th e s elected BCR. A read of th e BDP will yield the selected BCR dat a. A write to the BDP will write to the selected BCR.

Once the RAP has b een wr i tten with a value, the RAP value remains unchanged until anot her RAP write occurs, or until an H_RESET or S_RE SET occurs. RAP is cleared to all 0s when an H_RESET or S_RESET occurs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C972 controll er allows for connection of a serial EEPROM. The first 16 bytes of the EEPROM will be automatically loaded into the Address PROM (APROM) space after H_RESET. Additionally, the fir st six bytes of the EEPROM will be loaded into CSR12 to CSR14. The Address PROM space is a convenient place to store the value of th e 48-bit IEEE s tation address. It can be overwritten by the host computer and its content has no effect on the operation of the controller. The software must copy the station address from the Address PROM spa ce to the initializati on block in

92 Am79C972

order for the receiver to accept unicast frames directed to this station.

The six bytes of the IEEE st ation address occu py the first six locations of the Address PROM space. The next six bytes are reserved. Bytes 12 and 13 should match the value of the checksum of bytes 1 through 11 and 14 and 15. Bytes 14 and 15 should each be ASCII “W” ( 57h). The above requirements must be met in order to be compatible with AMD driver software. APROMWE bit (BCR2, bit 8) must be set to 1 to enable write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal software reset (S_RESET) pulse in the Am79C972 controller. The internal S_RESET puls e that is generated by this access is different from both the assertion of the hardware RST

pin (H_RESET) a nd fr om th e as se rtion of the software STOP bit. Specifically , S_RESET is the equivalent of the assertion of the RST

pin (H_RESET) except that S_RESET has no effect on the BCR or PCI Configuration space locations.

The NE2100 LANCE-based family of Ether net cards requires tha t a write acces s to the Reset reg ister follows each read access to the Reset register. The Am79C972 controlle r does not have a similar requirement. The write access is not required and does not have any effect.

Note: The Am79C972 controller cannot service any slave accesses for a very short time after a read access of the Reset re gister, because the int ernal S_R ESET operation takes about 1

µs to finish. The Am79C972

controller will terminate all slave accesses wit h the as sertion of DEVSEL

and STOP while TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.

Word I/O Mode

After H_RESET, the Am79C972 c ontroller is programmed to operate in Word I/O mode. DWIO (BCR18, bit 7) will be cleared to 0. Table 17 shows how the 32 bytes of address space are used in Word I/O mode.

gramming of the Am79C972 control registers. T ab le 18 shows legal I/O accesses in Word I/O mode.

Table 17. I/O Map In Word I/O Mode (DWIO = 0)

No. of

Offset

00h - 0Fh 16 APROM

10h 2 RDP 12h 2 RAP (shared by RDP and BDP) 14h 2 Reset Register 16h 2 BDP

18h - 1Fh 8 Reserved

Bytes

Double Word I/O Mode

The Am79C972 controller can be configured to operate in DWord (32-bit) I/O mode. The software can invoke the DWIO mode by performing a DWord write access to the I/O location at offset 10h (RDP). The data of the write access must be such that it does not affect the intended operation of the A m79C972 controller. Setting the device into 32-bit I/O mode is usually the first operation after H_RESE T or S_RESET. The RAP register will point to CSR0 at that time. Wr iting a value of 0 to CSR0 is a safe operation. DWIO (BCR18, bit 7) will be set to 1 as an indication th at the Am 79C 972 contr oller operates in 32-bit I/O mode.

Note: Even though the I/O resource mapping changes when the I/O mode settin g cha nges, the RDP lo catio n offset is the same for both modes. Onc e the DWIO bit has been set to 1, only H_RESET can clear it to 0. The DWIO mode setting is unaffected by S_RESET or setting of the STOP bit. Table 19 shows how the 32 bytes of address space are used in DWord I/O mode.

All I/O resource s must be accessed i n DWord quantities and on DWord addresses. A read access other than listed in Table 20 will yield undefined data, a write operation may cause unexpected reprogramming of the Am79C972 control registers.

All I/O resources must be ac cess ed in word q uantiti es and on word addresses. The Address PROM locations can also be read in byte quantities. The only allowed DWord operation is a wr ite access to the RDP, which switches the device to DWord I/O mode. A read access other than listed in the table below will yield un define d data, a write operation may cause unexpected repro-

Am79C972 93

T able 18. Legal I/O Accesses in Word I/O Mode (DWIO = 0)

AD[4:0] BE[3:0] Type Comment

0XX00 1110 RD Byte read of APROM location 0h, 4h, 8h or Ch 0XX01 1101 RD Byte read of APROM location 1h, 5h, 9h or Dh 0XX10 1011 RD Byte read of APROM location 2h, 6h, Ah or Eh 0XX11 0111 RD Byte read of APROM location 3h, 7h, Bh or Fh

0XX00 1100 RD

0XX10 0011 RD

10000 1100 RD Word read of RDP 10010 0011 RD Word read of RAP 10100 1100 RD Word read of Reset Register 10110 0011 RD Word read of BDP

0XX00 1100 WR

0XX10 0011 WR

10000 1100 WR Word write to RDP 10010 0011 WR Word write to RAP 10100 1100 WR Word write to Reset Register 10110 0011 WR Word write to BDP

10000 0000 WR

Word read of APROM locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h and 9h or Ch and Dh

Word read of APR OM lo cat ion s 3 h (M SB) a nd 2 h (L SB), 7h an d 6 h, Bh and Ah o r Fh and Eh

Word write to APROM lo cat ion s 1h (MSB) an d 0h (LS B ), 5h an d 4h, 8h and 9h or Ch and Dh

Word write to APROM loc ation s 3h (MSB) and 2h (LSB), 7h and 6h, Bh an d Ah or Fh and Eh

DWord write to RD P, switches device to DWord I/O mode

Table 19. I/O Map In DWord I/O Mode (DWIO = 1)

Offset No. of Bytes Register

00h - 0Fh 16 APROM

10h 4 RDP 14h 4 18h 4 Reset Register

1Ch 4 BDP

RAP (shared by RDP and

BDP)

Table 20. Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

AD[4:0] BE[3:0] Type Comment

DWord read of APROM locations 3h (MSB) to 0h

0XX00 0000 RD

10000 0000 RD DWord read of RDP 10100 0000 RD DWord read of RAP

11000 0000 RD

0XX00 0000 WR

10000 0000 WR DWord write to RDP 10100 0000 WR DWord write to RAP

11000 0000 WR

(LSB), 7h to 4h, Bh to 8h or Fh to Ch

DWord read of Reset Register

DWord write to APROM locations 3h (MSB) to 0h (LSB), 7h to 4h, Bh to 8h or Fh to Ch

DWord write to Reset Register

94 Am79C972

USER ACCESSIBLE REGISTERS

The Am79C972 controll er has thr e e ty pes of user registers: the PCI configu ration regist ers, the Control an d Status registers (CSR ), and the Bus Control registers (BCR).

The Am79C972 contro ller implements all PC net-ISA (Am79C960) registers, all C-LANCE (Am79C90) registers, plus a number o f additional registers. The Am79C972 CSRs are compatible upon power up with both the PCnet-ISA CSRs and all of the C-LANCE CSRs.

The PCI configuration registers can be accessed in any data width. All other registers must be a ccessed according to the I/O mode that is currently selected. When WIO mode is sel ected, all other register l ocations are defined to be 16 bits in width. When DWIO mode is selected, all these register locations are defined to be 32 bits in width, with the upper 16 bits of most register locations marked as reserved locations with undefined values. W hen p erformin g re gister wr ite operations in DWIO mode, the upper 16 bits should always be written as zeros. When perfor ming register read operations in DWIO mode, the upper 16 bits of I/O resource s should alw ays be regarded a s having undefined values, except for CSR88.

The Am79C972 registers can be divided into four groups: PCI Configuration, Setup, Running, and Test. Registers not included in any of the se categories ca n be assumed to be intended for diagnostic purposes.

n PCI Configuration Registers

These registers are intended to be initialized by the system initialization procedure (e.g., BIOS device initialization routine) to program the operation of the Am79C972 controller PCI bus interface.

The following is a list of the registers that would typically need to be programmed once during the initialization of the Am79C972 controller within a system:

The following is a list of the registers that would typically need to be programmed once dur i ng the setu p of the Am79C972 contr oller with in a system . The contr ol bits in each of the se registers ty pically d o not need to be modified once they have been written. However, there are no restrictions as to how many times these registers may actually be accessed. Note that if the default power up values of any of these registers is acceptable to the application, then such registers need never be accessed at all.

Note: Registers marked with “^” may be programma- ble through the EEPROM read operation and, therefore, do not necessarily nee d to be written to by the system initialization procedure or by the driver software. R egist ers mark ed wit h “*” will be initialized by the initialization block read operation.

CSR1 Initialization Block Address[15:0] CSR2* Initialization Block Address[31:16] CSR3 Interrupt Masks and Deferral Control CSR4 Test and Features Control CSR5 Extended Control and Interrupt CSR7 Extended Control and Interrupt2 CSR8* Logical Address Filter[15:0] CSR9* Logical Address Filter[31:16] CSR10* Logical Address Filter[47:32] CSR11* Logical Address Filter[63:48] CSR12*^ Physical Address[15:0] CSR13*^ Physical Address[31:16] CSR14*^ Physical Address[47:32] CSR15* Mode CSR24* Base Address of Receive Ring Lower CSR25* Base Address of Receive Ring Upper

— PCI I/O Base Address or Memory Ma pped I/O

Base Address register

— PCI Expansion ROM Base Address register — PCI Interrupt Line register — PCI Latency T ime r regis te r — PCI Status register — PCI Command register — OnNow register

n Setup Registers

These registers are intended to be initialized by the device driver to program the operation of various Am79C972 controller features.

Am79C972 95

CSR30* Base Address of Transmit Ring Lower CSR31* Base Address of Transmit Ring Upper CSR47* Transmit Polling Interval CSR49* Receive Polling Interval CSR76* Receive Ring Length CSR78* Transmit Ring Length CSR80 DMA Transfer Counter and FIFO Thresh-

old Control CSR82 Bus Activity Timer CSR100 Memory Error Timeout CSR116^ OnNow Miscellaneous CSR122 Receiver Packet Alignment Control

CSR125^ MAC Enhanced Configuration Control BCR2^ Misc el la neou s Conf igu ratio n BCR4^ LED0 Status

These registers are in tended to be use d by the device driver software after the Am79C972 controller is running to acces s status infor mation an d to pass co ntrol information.

BCR5^ LED1 Status BCR6^ LED2 Status BCR7^ LED3 Status BCR9^ Full-Duplex Control BCR18^ Bus and Burst Control BCR19 EEPROM Control and Status BCR20 Software Style BCR22^ PCI Latency BCR23^ PCI Subsystem Vendor ID BCR24^ PCI Subsystem ID BCR25^ SRAM Size BCR26^ SRAM Boundary BCR27^ SRAM Interface Control BCR32^ MII Control and Status BCR33^ MII Address BCR35^ PCI Vendor ID BCR36 PCI Power Management Capabilities

(PMC) Alias Register

BCR37 PCI DATA Register Zero (DATA0) Alias

BCR38 PCI DATA Register One (DATA1) Alias

BCR39 PCI DATA Register Two (DATA2) Alias

BCR40 PCI DATA Register Three (DATA3) Alias

BCR41 PCI DATA Register Four (DATA4) Alias

BCR42 PCI DATA Register Five (DATA5) Alias

BCR43 PCI DAT A Register Six (DAT A6) Alias Reg-

ister

BCR44 PCI DATA Register Seven (DATA7) Alias

Register BCR45 OnNow Pattern Matching Register 1 BCR46 OnNow Pattern Matching Register 2 BCR47 OnNow Pattern Matching Register 3

n Running Registers

The following is a list of the registers that would typically need to be per iodically r ead and perhaps w ritten during the nor m al running operation of the Am7 9C97 2 controller within a system. Each of these registers contains control bits, or status bits, or both.

RAP Register Address Port CSR0 Am79C972 Controller Status CSR3 Interrupt Masks and Deferral Control CSR4 Test and Features Control CSR5 Extended Control and Interrupt CSR7 Extended Control and Interrupt2 CSR112 Missed Frame Count CSR114 Receive Collision Count BCR32 MII Control and Status BCR33 MII Address BCR34 MII Management Data

n Test Registers

These registers are intended to be used only for testing and diagnostic pur p os es. Those r egi ste rs not included in any of the above lists can be assumed to be intended for diagnostic purposes.

PCI Configuration Registers

PCI Vendor ID Register

Offset 00h

The PCI V endor ID register is a 16-bit register that identifies the manufacturer of the Am79C972 controller. AMD’s Vendo r ID is 1022h. Note tha t this vendor ID is not the same as the Manufacturer ID in CSR8 8 and CSR89. The vendor ID is assigned by the PCI Special Interest Group.

The PCI Vendor ID register is located at offset 00h in the PCI Configuration Space. It is read only.

This register is the same as BCR35 and can be written by the EEPROM.

PCI Device ID Register

Offset 02h

The PCI Device ID regi ster is a 16-bit re gister that uniquely identifies the Am79C972 controller within AMD's product line. The Am79C972 Device ID is 2000h. Note that this Device ID is not the s am e as th e Part number in CSR88 and CSR8 9. The Device ID is assigned by AMD. The Device ID is the same as the

96 Am79C972

PCnet-PCI II (Am79C970A) and PCnet-FAST (Am79C971) devices.

The PCI Device ID register is located at offset 02h in the PCI Configuration Space. It is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to control the gross functionality of the Am79C972 controller. It controls the Am79C972 controller’s ability to generate and respond to PCI bus cycles. To logically disconnect the Am79C 972 device from all PCI bus cycles except configuration cycles, a value of 0 should be written to this register.

The PCI Command register is loca ted at offset 04h in the PCI Configuration Space. It is rea d and wr itten by the host.

Bit Name Description

15-10 RES Rese rved locations . Read as ze-

ros; write operations have no effect.

9 FBTBEN Fast Back-to-Back Enable. Read

as zero; write operations have no effect. The Am79C972 controller will not generate Fast Back-toBack cycles.

8 SERREN SERR Enable. Controls the as-

sertion of th e SER R disabled when SERREN is cleared. SERR on detection of an add ress p arity error and if both SERREN and PERREN (bit 6 of this register) are set.

SERREN is cleared by H_RESET and is not effecte d by S_RESET or by setting the STOP bit.

7 RES Reserved location. Read as ze-

ros; write operations have no effect.

pin. SERR is

will be asserted

also sets the DATAPERR bit (PCI Status register, bit 8), when the data parity error occ urred during a master cycle. PERREN also enables reporting address parity errors through the SERR the SERR register.

PERREN is cleared by H_RESET and is not affe cted by S_RESET or by setting the STOP bit.

5 VGASNOOP VGA Palette Snoop. Read as ze-

ro; write operations have no effect.

4 MWIEN M emo ry Wr it e and Inv ali da te Cy-

cle Enable. Read as zero; write operations have no effect. The Am79C972 controller only generates Memory Write cycles.

3 SCYCEN Special Cycle Enable. Read as

zero; write operations have no effect. The Am79C972 controller ignores all Special Cycle operations.

2 BMEN Bus Master Enable. Setting

BMEN enables the Am79C972 controller to become a bus master on the PCI bus. The host must set BMEN before setting the INIT or STRT bit in CSR0 of the Am79C972 controller.

BMEN is cleared by H_RESET and is not effected by S_RE SET or by setting the STOP bit.

1 MEMEN Memory Space Access Enable.

The Am79C972 control ler will ignore all memory acc esses when MEMEN is cleared. The host must set MEMEN before the first memory access to the device.

bit in the PCI Status

pin and

6 PERREN Parity Error Response Enable.

Enables the parity error response functions. When PERREN is 0 and the Am79C972 controller detects a parity error, it only sets the Detected Parity Error bit in the PCI Status register. When PERREN is 1, the Am79C972 controller asserts PERR detection of a data pari ty err or. It

on the

Am79C972 97

For memory mapped I/O, the host must program the PCI Memory Mapped I/O Base Address register with a valid memory address before setting MEMEN.

For accesses to the Expansion ROM, the host must program the PCI Expansion ROM Base Address register at offset 30h with a

valid memory address before setting MEMEN. The Am79C972 controller will only respond to accesses to the Expansion ROM when both ROMEN (PCI Expansion ROM Base Address register, bit 0) and MEMEN are se t to 1. Since MEMEN also enables the memory mapped access to the Am79C972 I/O resources, the PCI Memory Mapped I/O Base Address register must be programmed with an address so that the device does not c laim cycles not intended for it.

MEMEN is cleared by H_RESET and is not effected b y S_RESET or by setting the STOP bit.

0 IOEN I/O Space Access Enable. The

Am79C972 controller will ignore all I/O accesses when IOEN is cleared. The host mus t set IOE N before the first I/O access to the device. The PCI I/O Base Address register must be programmed with a valid I/O address before setting IOEN.

IOEN is cleared by H_RESET and is not effected b y S_RESET or by setting the STOP bit.

PCI Status Register

Offset 06h

The PCI Status register is a 16-bit register that contains status information for the PCI bus related events. It is located at offset 06h in the PCI Configuration Space.

Bit Name Description

15 PERR Parity Error. PERR is set when

the Am79C972 controller detects a parity error.

The Am79C972 controller samples the AD[31:0], C/BE the PAR lines for a par i ty e r ror a t the following times:

• In slave mode, during the address phase of any PCI bus command.

• In slave mode, for all I/O, me mory and configuration write commands that select the Am79C972 controller when data is trans-

[3:0], and

ferred (TRDY serted).

• In master mode, during the data phase of all memory read commands.

In master mode, during th e data phase of the memory wr ite command, the Am79C972 controller sets the PERR bit if the target reports a data parity error by asserting the PERR

PERR is not effected by the state of the Parity Error Respons e enable bit (PCI Comm and register, bit 6).

PERR is set by the Am79C972 controller and cleared by writing a

1. Writing a 0 has no effect. PERR is cleared by H_RESET and is not affected b y S_RESET or by setting the STOP bit.

14 SERR Signaled SERR. SERR is set

when the Am79C972 controller detects an address parity error and both SERREN and PERREN (PCI Command register, bits 8 and 6) are set.

SERR is set by the Am79C972 controller and cleared by writing a

1. Writing a 0 has no effect. SERR is cleared by H_RESET and is not affected b y S_RESET or by setting the STOP bit.

13 RMABORT Received Master Abort. RM-

ABORT is set when the Am79C972 controller terminates a master cycle with a master abort sequence.

RMABORT is set by the Am79C972 controller and cleared by writing a 1. Writing a 0 has no effect. RMABORT is cleared by H_RESET and i s not affected by S_RESET or by setting the STOP bit.

12 RTABORT Received Target Abort. RT-

ABORT is set when a target terminates an Am79C972 master cycle with a target abort sequence.

and IRDY are as-

signal.

98 Am79C972

RTABORT is set by the Am79C972 controller and cleared by writing a 1. Writing a 0 has no effect. RTABORT is cleared by H_RESET and i s not affected by S_RESET or by setting the STOP bit.

fast back-to-back transactions with the first transaction addressing a different target.

6-5 RES Reserved locations. Read as

zero; write operations have no effect.

11 STABO RT Send Target Ab ort. Read as ze-

ro; write operations have no effect. The Am79C972 controller will never terminate a slave access with a target abort sequence.

STABORT is r ead only.

10-9 DEVSEL Device Select Timing. DEVSEL

is set to 01b (medium), which means that the Am79C972 controller will assert DEVSEL clock periods aft e r F RA ME serted.

DEVSEL is read only.

8 DATAPERR Data Parity Error Detected.

DATAPERR is set when the Am79C972 controller is the current bus master and it detec ts a data parity error and the Parity Error Response enable bit (PCI Command register, bit 6) is set.

two

is as-

4 NEW_CAP New Capabilities. This bit indi-

cates whether this function implements a list of extended capabilities such as PCI power management. When set, this bit indicates the presence of New Capabilities. A value of 0 means that this function does n ot implement New Capabilities.

Read as one; write operations have no effect. The Am79C972 controller supports the Linked Additional Capabilit ies Lis t.

3-0 RES Reserved locations. Read as

zero; write operations have no effect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8 -bit register that specifies the Am79C972 controller revision number. The value of this register is 3Xh with the lower four bits being silicon-revision dependent.

During the data phase of all memory read commands, the Am79C972 controller checks for parity error by sampling the AD[31:0] and C/BE PAR lines. During the data phase of all memory write commands, the Am79C972 controlle r checks the PERR the target has reported a parity error.

DATAPERR is set by the Am79C972 controller and cleared by writing a 1. Writing a 0 has no effect. DATAPERR is cleared by H_RESET and i s not affected by S_RESET or by setting the STOP bit.

7 FBTBC Fast Back-To-Back Capable.

Read as one; write operations have no effect. The Am79C972 controller is c apa bl e o f a cc ep tin g

input to detect whether

[3:0] and the

The PCI Revision ID register is located at offset 08h in the PCI Configuration Space. It is read only.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit register that identifies the programming interface of Am79C972 controller. PCI does not define any specific register-level programming interfaces for network devices. The value of this register is 00h.

The PCI Programming Interface register is locate d at offset 09h in the PCI Configuration Space. It is read only.

PCI Sub-Class Register

Offset 0Ah

The PCI Sub-Class register is an 8-bit register that identifies specifically the function of the Am79C972 controller. The value of this register is 00h which identifies the Am79C972 device as an Ethernet controller.

The PCI Sub-Clas s regis ter is lo cated at offse t 0Ah i n the PCI Configuration Space. It is read only.

Am79C972 99

PCI Base-Class Register

Offset 0Bh

The PCI Base-Class register is an 8-bit register that broadly classifies the function of the Am79C972 co ntroller. The value of this register is 02h which classifies the Am79C972 device as a network controller.

The PCI Base-Class register is located at offset 0Bh in the PCI Configuration Space. It is read only.

PCI Latency Timer Register

Offset 0Dh

The PCI Latency Timer register is an 8-bit register that specifies the minimum guaranteed time the Am79C972 controller will control the bus once it starts its bus mastership period. T he time is measured in clock cycl es. Every time the Am79C972 controller asserts FRAME the beginni ng of a bus mast ership period, it will copy t he value of the PCI Latency T imer regi ster in to a counter and start c ounting down. The counter will freeze at 0. When the system arbiter removes GNT counter is non-zero, the Am79C972 controller will continue with its data transfers. It will only release the bus when the counter has reached 0.

The PCI Latency Timer is only significant in burst transactions, where FRAME phase. In a non-burst transactio n, FRAME serted during the addr ess phase. The inter nal laten cy counter will be cleared and suspended while FRAME deasserted.

All eight bits of the PCI Latency Timer register are programmable. The host should rea d the Am 79C972 PCI MIN_GNT and PCI MAX_LA T registers to determine the latency requireme nts for the device and then initial ize the Latency Timer register with an appropriate value.

The PCI Latency Timer register is located at offset 0Dh in the PCI Configuration Space. It is read and written by the host. The PCI Laten cy T im er r egi ster is cle ar ed by H_RESET and is not effected by S_RESET or by setting the STOP bit.

PCI Header Type Register

Offset 0Eh

The PCI Header Type register is an 8-bit register tha t describes the for mat of the PCI Configuration Space locations 10h to 3Ch and that identifie s a device to be single or multi-function. The PCI Header Type register is located at address 0Eh in the PCI Configuration Space. It is read only.

Bit Name Description

7 FUNCT Single-function/multi-function de-

stays asserted until the last data

vice. Read as zero; write op erations have no effect. The Am79C972 controller is a single function device.

while the

is only as-

6-0 LAYOUT PCI configuration space layout.

Read as zeros; write operations have no effect. The layo ut of the PCI configuration space locations 10h to 3Ch is as shown in the table at the beginning of this section.

PCI I/O Base Address Register

Offset 10h

The PCI I/O Base Address register is a 32-bit register that determines the location of the Am79C972 I/O resources in all of I/O space. It is located at offs et 10h in the PCI Configuration Space.

Bit Name Description

31-5 IOBASE I/O base address most significant

27 bits. These bits are written by the host to specify the locati on o f the Am79C972 I/O resources in all of I/O spac e. I OBAS E mus t be written with a valid address before the Am79C972 controller slave I/O mode is turned on by setting the IOEN bit (PCI Command register, bit 0).

When the Am79C972 controller is enabled for I/O mode (I OEN is set), it monitors the PCI bus for a valid I/O command. If the value on AD[31:5] during the address phase of the cycles matc hes the value of IOBASE, the Am79C972 controller will drive DEV SE L cating it will respond to the access.

IOBASE is read and written by the host. IOBASE is cleared by H_RESET and is not affec ted by S_RESET or by setting the STOP bit.

4-2 IOSIZE I/O size requirements. Read as

zeros; write operations have no effect.

IOSIZE indicates the size of the I/O space the Am79C972 controller requires. When the host writes a value of FFFF FFFFh to the I/O Base Addres s reg ister , it w ill re ad back a value of 0 in bits 4-2. That indicates an Am79C972 I/O space requirement of 32 bytes.

indi-

100 Am79C972

Datasheet AM79C972BVIW, AM79C972BVCW, AM79C972BKIW, AM79C972BKCW Datasheet (AMD Advanced Micro Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

Am79C972

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

BLOCK DIAGRAM

TABLE OF CONTENTS

RELATED AMD PRODUCTS

CONNECTION DIAGRAM (PQR160)

CONNECTION DIAGRAM (PQL176)

Listed By Driver Type

DEVSEL

C/BE[3:0]

FRAME

IDSEL

INTA

IRDY

PERR

Board Interface

LED0

LED1

LED2

LED3

EEDI

EEDO

EESK

EBDA[15:8]

EBD[7:0]

EROMCS

AS_EBOE

EBWE

EBCLK

TXD[3:0]

TX_EN

TX_ER

RX_CLK

RXD[3:0]

RX_DV

RX_ER

MDIO

RXCLK

RXDAT

RXEN

TXCLK

TXDAT

TXEN

SFBD

SRDCLK

RXFRTGD

RXFRTGE

MIIRXFRTGD

MIIRXFRTGE

IEEE 1149.1 (1990) Test Access Port Interface

VDD_PCI

VSSB

Software Interface

Network Interfaces

Slave Configuration Transfers

Slave I/O Transfers

Master Bus Interface Unit

Buffer Management Unit

Software Interrupt Timer

Media Access Control

Transmit Operation

Receive Operation

Loopback Operation

General Purpose Serial Interface

Media Independent Interface

Auto-Negotiation

Automatic Network P ort Selection

External Address Detection Interface

Expansion Bus Interface

EEPROM Interface

LED Support

Power Savings Mode

Magic Packet Mode

IEEE 1149.1 (1990) Test Access Port Interface

NAND Tree Testing