AMD Advanced Micro Devices AM79C972BVIW, AM79C972BVCW, AM79C972BKIW, AM79C972BKCW Datasheet

Am79C972

PCnet™-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support

DISTINCTIVE CHARACTERISTICS

n Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus — 32-bit gluele ss PCI hos t interf ace

— Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization

— PCI specification revision 2.1 compliant — Supports PCI Subsystem/Subvendor ID/

Vendor ID pr ogramming through the EEPROM interface

— Supports both PCI 3.3-V and 5.0-V signaling

environments

— Plug and Play compatible — Supports an unlimited PCI burst length — Big endian and little endian byte alignments

supported

— Implements optional PCI power management

event (PME

n Media Independent Interface (MII) for

connecting external 10/100 megabit per second (Mbps) transceivers

— IEEE 802.3-compliant MII — Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Supports both auto-negotiable and non

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3compliant MII PHYs at full- or half-duplex

n Supports General Purpose Serial Interface

(GPSI) with receive frame tagging support for internetworking applications

n Full-duplex operation supported in MII and GPSI

ports with independent Transmit (TX) and Receive (RX) channels

) pin

n Supports PC97, PC98, and Net PC requirements

— Implements full OnNow features including

pattern matching and link status wake-up

— Implements Magic Packet mode — Magic Packet mode and the physical address

loaded from EEPROM at power up without requiring PCI clock

— Supports PCI Bus Power Management

Interface Specification Version 1.0

— Supports Advanced Configuration and

Power Interface (ACPI) Specification Version 1.0

— Supports Network Device Class Power

Management Specification Version 1.0

n Large independent internal TX and RX FIFOs

— Programmable FIFO watermarks for both

transmit and receive operations

— Receive frame queuing for high latency PCI

bus host operation

— Programmable allocation of buffer space

between transmit and receive queues

n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards

n EEPROM interface supports jumperless design

and provides through-chip programming — Supports full programmability of half-/full-

duplex operation for external 10/100 Mbps PHYs through EEPROM mapping

— Programmable PHY reset output pin capable

of resetting external PHY without needing buffering

n Integrated oscillator circuit eliminates need for

external crystal

n Extensive programmable LED status support n Support for operation in industrial temperature

range (-40°C to +85°C)

Publication# 21485 Rev: D Amendment/0 Issue Date: December 1999

Refer to AMD’s Website (www.amd.com) for the latest information.

n Supports up to 1 megabyte (Mbyte) optional

Boot PROM or Flash for diskless node application

n Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame

n Programmable Inter Packet Gap (IPG) to

address less network aggressive MAC controllers

n Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

n IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test mode for board-level production connectivity test

GENERAL DESCRIPTION

The Am79C972 PCnet-FAST+ controller is a highlyintegrated 32-bit full-duplex, 10/100-Megabit per second (Mbps) Ethern et controller solution, desig ned to address high-perfor mance sys tem applicat ion requirements. It is a flexible bus mastering device that can be used in any application, including network-ready PCs and bridge/router designs. The bus master architecture provides high data thro ughput and low CPU and system bus utilization. T he Am79C972 cont roller is fabricated with advanced low-power 3.3-V CMOS process to provide low operating current for power sensitive applications.

The Am79C972 PCnet-FAST+ controller also has several enhancements over its predecessor, the Am79C971 PCnet-FAST device. In addition to integrating the SRAM on chip, it further reduces system implementation cost by the addition of a new EEPROM programmable pin (PHY_RST), an inter nal oscillator circuit eliminating the n eed for an extern al c rystal, and the integration of the PAL function needed for Magic Packet application. The P HY_RST pi n is i mpleme nted to reset the external PHY without increasing the load to the PCI bus and to block RST input is LOW.

The 32-bit multiplexed bus interface unit provides a direct interface to the PCI l ocal bus, simplifying the design of an Ethernet node in a PC system. The Am79C972 PCnet-FAST+ controller provides the complete interface to a n Expansion ROM or Flash device allowing add-on card designs with only a single load per PCI bus interface pin. With its built-in support for both little and big endian byte alignment, this controller also address es non-PC ap plications. Th e Am79C972 controller’s advanced CMOS design allows th e bus interface to be connected to either a +5-V or a +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG

to the PHY when PG

n Software compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor architecture

n Compatible with the existing PCnet Family

driver and diagnostic software

n Available in 160-pin PQFP and 176-pin TQFP

packages

n +3.3 V power supply with 5 V tolerant I/Os

enables broad system compatibility

n Extensive programmable internal/external

loopback capabilities

n Supports patented External Address Detection

Interface (EADI)

test interface for board-level testing is also provided, as well as a NAND tree test structure for those systems that cannot support the JT AG interface.

The Am79C972 PCnet-FAST+ controller is also compliant with the PC97, PC98, and Net PC specifications. It includes the full implementation of the Microsoft OnNow and ACPI speci fications, whi ch are backward compatible with the Magic Packet technology, and is compliant with the PCI Bus Power Management Interface Specification by supporting the four power management states (D0 , D1, D2, and D3), the optio nal

pin, and the necessary configuration and data

PME registers.

The Am79C972 PCn et-FAST+ controller is ideally suited for Network PC (Net PC), motherboard, network interface card (NIC), and embedded designs. It is available in a 160-pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs.

The Am79C972 PCnet-FAST+ controller is a complete Ethern et node integrated into a singl e VLSI device. It contains a bus interface unit, a Direct M emory Access (DMA) Buffer Management Uni t, an ISO/IEC 8802-3 (IEEE 802.3)-compliant Media Access Controller (MAC), a large Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant MII. Both IEEE

802.3 compliant full -dup lex and half-du plex operations are suppor ted on the MII a nd GPSI interfaces. 10/100 Mbps operation is supported through the MII.

The Am79C972 PCnet-FAST+ controller is register compatible with the LANCE™ (Am7990) an d CLANCE™ (Am79C90) Ethernet controllers, and all Ethernet controller s in the PCnet Family exce p t ILACC™ (Am79C900), including the PCnet-ISA™ controller (Am79C960), PCnet-ISA+™ (Am79C961),

2 Am79C972

PCnet-ISA II™ (Am79C961A), PCnet-32™ (Am79C965), PCnet-PCI™ (Am79C970), PCnet-PCI II™ (Am79C970A), and the PCnet-FAST™ (Am79C971). The Buffer Management Unit supports the LANCE and PCnet descriptor software models.

The Am79C972 PCnet-FAST+ controller contains 12-kilobyte (Kbyte) buffers, the largest of its class of 10/ 100 Mbps Et hernet controll ers. The large inter nal buffer is programmable between the transmit (TX) an d receive (RX) queues for optimal performance.

The Am79C972 PCnet-FAST+ controller supports auto-configuration in the PCI configuration space. Additional Am79C972 controller configuration parameters, including the unique IEEE physical address, can be read from an external nonvolatile memory (EEPROM) immediately following system reset.

In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, link integrity , Magic Packet status, activity, address match, full-duplex, or 100 Mbps status. The Am79C972 controller also provides an EADI t o allow external hardware a ddress filterin g in i nternetworking ap pli ca tio ns and a r eceive frame tagging feature.

With the rise of embedded networking applications operating in harsh environments where temperatures may exceed the normal com mercial temperatur e window (0°C to 70°C), an industrial temperature (-40°C to +85°C) version is available in both the 160-pin PQFP and the 176-p in TQFP package. The Am7 9C972 PCnet-FAST+ 10/100 Mbps Ethernet controller can be designed with the industrial temperature capable Am79C874 NetPHY-1LP 10/100 Mbps Ethernet PHY for a complete and robust Fast Ethernet solution that can withstand extreme temperature environments.

Am79C972 3

BLOCK DIAGRAM

EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE EBCLK

CLK RST

AD[31:0]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT PERR SERR

INTA

TCK

TMS

TDI

TDO

PCI Bus

Interface

Management

JTAG

Port

Control

Unit

Buffer

Unit

Expansion Bus

Bus Rcv

FIFO

Bus Xmt

FIFO

Control

Interface

12K

SRAM

MAC

Rcv

FIFO

MAC

Xmt

FIFO

Network

Port

Manager

OnNow

Power

Management

Unit

802.3 MAC Core

GPSI

Port

MII

Port

EADI

Port

93C46

EEPROM

Interface

LED

Control

TXEN TXCLK TXDAT RXEN RXCLK RXDAT CLSN

TX_ER TXD[3:0] TX_EN TX_CLK COL RXD[3:0] RX_ER RX_CLK RX_DV CRS MDC MDIO

SRDCLK SRD SFBD EAR MIIRXFRTGD/RXFRTG MIIRXFRTGE/RXFRTGE

PHY_RST TBC_IN

TBC_EN EECS EESK EEDI EEDO

LED0 LED1 LED2 LED3

PME

RWU

WUMI

4 Am79C972

21485C-1

AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

DISTINCTIVE CHARACTERISTICS1 GENERAL DESCRIPTION2

TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CONNECTION DIAGRAM (PQR160)8 CONNECTION DIAGRAM (PQL176)9

PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PIN DESIGNATIONS (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PIN DESIGNATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

BASIC FUNCTIONS26

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DETAILED FUNCTIONS27

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

BLOCK DIAGRAM4

Am79C972 5

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Am79C972 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

DC CHARACTERISTICS OVER

OPERATING RANGES 190 COMMERCIAL AND INDUSTRIAL

SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . .194

SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . .195

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .196

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .204

SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .206

SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .207

SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQR160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Plastic Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Thin Quad Flat Pack (measured in millimeters). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Outline of LAPP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

LAPP Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Control Register (Register 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Auto-Negotiation Link Partner Ability Register (Register 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

6 Am79C972

RELATED AMD PRODUCTS

Part No. Description

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79865 100 Mbps Physical Data Transmitter (PDT) Am79866A 100 Mbps Physical Data Receiver (PDR) Am79C871 Quad 100BASE-X Transceiver for Repeater Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support) Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses) Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Ethernet Controller for PCI Local Bus

Am79C972 7

CONNECTION DIAGRAM (PQR160)

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB

TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR SERR

VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12 AD11

VDD_PCI

AD10

AD9

AD27

VDD_PCI

AD26

VSSB

C/BE3

AD24

AD25

160

159

158

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

157

414243444546474849505152535455565758596061626364656667687071727374757677787980

156

155

154

AD29

AD28

153

152

AD30

VSS

151

150

VSSB

GNT

REQ

AD31

VDD_PCI

149

148

147

146

145

PCnet“-FAST+

Am79C972BKC

Am79C972

CLK

144

RST

143

INTA

142

141

VDD

140

TDI

139

VSSB

TDO

138

137

TMS

VDDB

136

135

TCK

134

RWU

WUMI

133

132

PME

VSS

131

130

EAR

EECS

EESK/LED1/SFBD

VSSB

129

128

127

126

TBC_EN

VDDB

TBC_IN

EEDI/LED0

LED2/SRDCLK/MIIRXFRTGE

125

124

123

122

121

EEDO/LED3/SRD/MIIRXFRTGD

120

PHY_RST

119 118

MDIO

117

VSSB

116

MDC

115

RXD3

114

RXD2

113

VDDB

112

RXD1

111

RXD0/RXFRTGD

110

VSS

109

RX_DV/RXFRTGE

108

RX_CLK/RXCLK

107

RX_ER/RXDAT

106

VSSB

105

TX_ER

104

TX_CLK/TXCLK

103

TX_EN/TXEN

102

TXD0/TXDAT

101

VDDB

100

VDD

TXD1

TXD2

TXD3

COL/CLSN

VSSB

CRS/RXEN

EBD0

EBD1

EBD2

VSS

EBD3

VDDB

EBD4

EBD5

EBD6

VSSB

EBD7

EBDA15

EBDA14

VSSB

C/BE0

AD6

AD7

VDD_PCI

AD5

VDD

AD4

AD3

VSSB

AD2

AD0

AD1

VSS

VDD_PCI

EBWE

EBCLK

EROMCS

AS_EBOE

VDD

VSSB

VDDB

EBUA_EBA1

EBUA_EBA0

EBUA_EBA2

EBUA_EBA3

AD8

Pin 1 is marked for orientation.

8 Am79C972

VSS

EBUA_EBA6

EBUA_EBA4

EBUA_EBA5

EBUA_EBA7

VSSB

EBDA9

EBDA8

VDDB

EBDA11

EBDA10

EBDA12

EBDA13

21485C-2

CONNECTION DIAGRAM (PQL176)

NCNCC/BE3

AD24

AD25

VSSB

AD26

VDD_PCI

AD27

AD28

AD29

AD30

VSS

VSSB

AD31

VDD_PCI

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

NC NC

IDSEL

AD23

VSSB

AD22

VDD_PCI

AD21 AD20

VDD AD19 AD18

VSSB

AD17

VDD_PCI

AD16

C/BE2

VSS

FRAME

IRDY

VSSB TRDY

VDD_PCI

DEVSEL

STOP

VDD

PERR SERR VSSB

PAR

VDD_PCI

C/BE1

AD15

VSS AD14 AD13

VSSB

AD12 AD11

VDD_PCI

AD10

AD9

NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

161

REQ

GNT

CLK

RST

INTAPGVDD

160

159

158

157

156

155

154

PCnet“-FAST+

Am79C972

Am79C972BVC

TDI

153

VSSB

152

TDO

151

VDDB

150

TMS

149

TCK

148

RWU

147

WUMI

146

PME

145

144

VSS

EAR

143

EECS

VSSB

EESK/LED1/SFBD

LED2/SRDCLK/MIIRXFRTGE

VDDB

TBC_EN

TBC_IN

142

141

140

139

138

137

136

EEDI/LED0NCNC

135

134

133

132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

NC NC EEDO/LED3/SRD/MIIRXFRTGD PHY_RST MDIO VSSB MDC RXD3 RXD2 VDDB RXD1 RXD0/RXFRTGD VSS RX_DV/RXFRTGE RX_CLK/RXCLK RX_ER/RXDAT VSSB TX_ER TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT VDDB VDD TXD1 TXD2 TXD3 COL/CLSN VSSB CRS/RXEN EBD0 EBD1 EBD2

VSS 99 98 97 96 95 94 93 92 91 90 89

EBD3

VDDB

EBD4

EBD5

EBD6

VSSB

EBD7

EBDA15

EBDA14

AD8

VSSB

C/BE0

Pin 1 is marked for orientation.

AD7

VDD_PCI

AD6

AD5

VDD

AD4

AD3

AD2

VSSB

AD1

AD0

VDD_PCI

EBDA11

EBDA12

EBDA13

VSS

EROMCS

EBWE

AS_EBOE

VSSB

EBCLK

EBUA_EBA0

VDD

VDDB

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

EBUA_EBA5

EBUA_EBA6

VSS

VSSB

EBDA8

EBUA_EBA7

EBDA9

EBDA10

VDDB

Am79C972 9

21485C-3

PIN DESIGNATIONS (PQR160) Listed By Pin Number

No.

Name

1 IDSEL 41 AD8 81 EBDA14 121 EEDI/LED0 2 AD23 42 C/BE0 82 EBDA15 122 TBC_IN 3 VSSB 43 VSSB 83 EBD7 123 TBC_EN 4 AD22 44 AD7 84 VSSB 124 VDDB

5 VDD_PCI 45 VDD_PCI 85 EBD6 125 6 AD21 46 AD6 86 EBD5 126 EESK/LED1/SFBD

7 AD20 47 AD5 87 EBD4 127 VSSB 8 VDD 48 VDD 88 VDDB 128 EECS 9 AD19 49 AD4 89 EBD3 129 EAR 10 AD18 50 AD3 90 VSS 130 VSS 11 VSSB 51 VSSB 91 EBD2 131 PME 12 AD17 52 AD2 92 EBD1 132 WUMI 13 VDD_PCI 53 VDD_PCI 93 EBD0 133 RWU 14 AD16 54 AD1 94 CRS/RXEN 134 TCK 15 C/BE2 55 AD0 95 VSSB 135 TMS 16 VSS 56 VSS 96 COL/CLSN 136 VDDB 17 FRAME 57 EROMCS 97 TXD3 137 TDO 18 IRDY 58 EBWE 98 TXD2 138 VSSB 19 VSSB 59 AS_EBOE 99 TXD1 139 TDI 20 TRDY 60 EBCLK 100 VDD 140 VDD 21 VDD_PCI 61 EBUA_EBA0 101 VDDB 141 PG 22 DEVSEL 62 VSSB 102 TXD0/TXDAT 142 INTA 23 STOP 63 EBUA_EBA1 103 TX_EN/TXEN 143 RST 24 VDD 64 VDD 104 TX_CLK/TXCLK 144 CLK 25 PERR 65 VDDB 105 TX_ER 145 GNT 26 SERR 66 EBUA_EBA2 106 VSSB 146 REQ 27 VSSB 67 EBUA_EBA3 107 RX_ER/RXDAT 147 VDD_PCI 28 PAR 68 EBUA_EBA4 108 RX_CLK/RXCLK 148 AD31 29 VDD_PCI 69 EBUA_EBA5 109 RX_DV/RXFRTGE 149 VSSB 30 C/BE1 70 EBUA_EBA6 110 VSS 150 VSS 31 AD15 71 EBUA_EBA7 111 RXD0/RXFRTGD 151 AD30 32 VSS 72 VSS 112 RXD1 152 AD29 33 AD14 73 EBDA8 113 VDDB 153 AD28 34 AD13 74 VSSB 114 RXD2 154 AD27 35 VSSB 75 EBDA9 115 RXD3 155 VDD_PCI 36 AD12 76 EBDA10 116 MDC 156 AD26 37 AD11 77 VDDB 117 VSSB 157 VSSB 38 VDD_PCI 78 EBDA11 118 MDIO 158 AD25 39 AD10 79 EBDA12 119 PHY_RST 159 AD24

40 AD9 80 EBDA13 120

Pin No.

Pin Name

Pin No.

Pin Name

EEDO/LED3/SRD/ MIIRXFRTGD

Pin No.

160 C/BE3

Name

LED2/SRDCLK/ MIIRXFRTGE

10 Am79C972

PIN DESIGNATIONS (PQL176) Listed By Pin Number

No.

Name

1 NC 45 NC 89 NC 133 NC 2 NC 46 NC 90 NC 134 NC 3 IDSEL 47 AD8 91 EBDA14 135 EEDI/LED0 4 AD23 48 C/BE0 92 EBDA15 136 TBC_IN 5 VSSB 49 VSSB 93 EBD7 137 TBC_EN 6 AD22 50 AD7 94 VSSB 138 VDDB

7 VDD_PCI 51 VDD_PCI 95 EBD6 139 8 AD21 52 AD6 96 EBD5 140 EESK/LED1/SFBD

9 AD20 53 AD5 97 EBD4 141 VSSB 10 VDD 54 VDD 98 VDDB 142 EECS 11 AD19 55 AD4 99 EBD3 143 EAR 12 AD18 56 AD3 100 VSS 144 VSS 13 VSSB 57 VSSB 101 EBD2 145 PME 14 AD17 58 AD2 102 EBD1 146 WUMI 15 VDD_PCI 59 VDD_PCI 103 EBD0 147 RWU 16 AD16 60 AD1 104 CRS/RXEN 148 TCK 17 C/BE2 61 AD0 105 VSSB 149 TMS 18 VSS 62 VSS 106 COL/CLSN 150 VDDB 19 FRAME 63 EROMCS 107 TXD3 151 TDO 20 IRDY 64 EBWE 108 TXD2 152 VSSB 21 VSSB 65 AS_EBOE 109 TXD1 153 TDI 22 TRDY 66 EBCLK 110 VDD 154 VDD 23 VDD_PCI 67 EBUA_EBA0 111 VDDB 155 PG 24 DEVSEL 68 VSSB 112 TXD0/TXDAT 156 INTA 25 STOP 69 EBUA_EBA1 113 TX_EN/TXEN 157 RST 26 VDD 70 VDD 114 TX_CLK/TXCLK 158 CLK 27 PERR 71 VDDB 115 TX_ER 159 GNT 28 SERR 72 EBUA_EBA2 116 VSSB 160 REQ 29 VSSB 73 EBUA_EBA3 117 RX_ER/RXDAT 161 VDD_PCI 30 PAR 74 EBUA_EBA4 118 RX_CLK/RXCLK 162 AD31 31 VDD_PCI 75 EBUA_EBA5 119 RX_DV/RXFRTGE 163 VSSB 32 C/BE1 76 EBUA_EBA6 120 VSS 164 VSS 33 AD15 77 EBUA_EBA7 121 RXD0/RXFRTGD 165 AD30 34 VSS 78 VSS 122 RXD1 166 AD29 35 AD14 79 EBDA8 123 VDDB 167 AD28 36 AD13 80 VSSB 124 RXD2 168 AD27 37 VSSB 81 EBDA9 125 RXD3 169 VDD_PCI 38 AD12 82 EBDA10 126 MDC 170 AD26 39 AD11 83 VDDB 127 VSSB 171 VSSB 40 VDD_PCI 84 EBDA11 128 MDIO 172 AD25 41 AD10 85 EBDA12 129 PHY_RST 173 AD24

42 AD9 86 EBDA13 130 43 NC 87 NC 131 NC 175 NC

44 NC 88 NC 132 NC 176 NC

Pin No.

Pin Name

Pin No.

Pin Name

EEDO/LED3/SRD/ MIIRXFRTGD

Pin No.

174 C/BE3

Name

LED2/SRDCLK/ MIIRXFRTGE

Am79C972 11

PIN DESIGNATIONS (PQR160, PQL176) Listed By Group

Pin Name Pin Function Type PCI Bus Interface

AD[31:0] Address/Data Bus IO 32 C/BE[3:0] Bus Command/Byte Enable IO 4 CLK Bus Clock I 1 DEVSEL Device Select IO 1 FRAME Cycle Frame IO 1 GNT Bus Grant I 1 IDSEL Initialization Device Select I 1 INTA Interrupt O 1 IRDY Initiator Ready IO 1 PAR Parity IO 1 PERR Parity Error IO 1 REQ Bus Request O 1 RST Reset I 1 SERR System Error IO 1 STOP Stop IO 1 TRDY Target Ready IO 1

Board Interface

LED0 LED0 O 1 LED1 LED1 O 1 LED2 LED2 O 1 LED3 LED3 O 1 TBC_IN Test Pin I 1 TBC_EN Test Pin I 1 PHY_RST Reset to PHY O 1

EEPROM Interface

EECS Seri al EEPROM Chip Select O 1 EEDI Serial EEPROM Data In O 1 EEDO Serial EEPROM Data Out I 1 EESK Serial EEPROM Clock IO 1

Expansion ROM Interface

AS_EBOE Address Strobe/Expansion Bus Output Enable O 1 EBCLK Expansion Bus Clock I 1 EBD[7:0] Expansion Bus Data [7:0] IO 8 EBDA[15:8] Expansion Bus Data/Address [15:8] IO 8 EBUA_EBA[7:0] Expansion Bus Upper Address /Expansion Bus Address [7:0] O 8 EBWE Expansion Bus Write Enable O 1 EROMCS Expansion Bus ROM Chip Select O 1

No. of Pins

Note: 1. Not including test features.

12 Am79C972

PIN DESIGNATIONS Listed By Group

Pin Name Pin Function Type Media Independent Interface (MII)

COL Collision I 1 CRS Carrier Sense I 1 MDC Management Data Clock O 1 MDIO Management Data I/O IO 1 RX_CLK Receive Cloc k I 1 RXD[3:0] Receive Data I 4 RX_DV Receive Data Valid I 1 RX_ER Receive Error I 1 TX_CLK Transmit Clock I 1 TXD[3:0] Transmit Data O 4 TX_EN Transmit Data Enable O 1 TX_ER Transmit Error O 1

General Purpose Serial Interface (GPSI)

CLSN Collision I 1 RXCLK Receive Cloc k I 1 RXDAT Receive Data I 1 RXEN Receive Enab l e I 1 TXCLK Transmit Clock I 1 TXDAT Transmit Data O 1 TXEN Transmit Enable O 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I 1 SFBD Start Frame Byte Delimiter O 1 SRD Serial Receive Data O 1 SRDCLK Serial Receive Data Clock O 1 RXFRTGD Receive Frame Tag Data I 1 RXFRTGE Receive Frame Tag Enable I 1 MIIRXFRTGD MII Receive Frame Tag Data I 1 MIIRXFRTGE MII Receive Frame Tag Enable I 1

Powe r Mana gemen t Interface

RWU Remote Wake Up O 1 PME Power Management Even t O 1 WUMI Wak e-U p Mo de Indi cation O 1 PG Power Good I 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I 1 TDI Test Data In I 1 TDO Test Data Out O 1 TMS Test Mode Select I 1

Power Suppli es

VDD Digital Power P 6 VSS Digital Ground P 8 VDDB I/O Buffer Power P 7 VSSB I/O Buffer Ground P 17 VDD_PCI PCI I/O Buffer Power P 9

Note: 1. Not including test features.

No. of Pins

Am79C972 13

Listed By Driver Type

The following table describes th e various type s of o utput drive rs used i n the Am79C9 72 contro ller . All I

values shown in the table apply to 3.3 V signaling.

and

A sustained tri-state signal is a low active signal that is driven high for one clock period before it is left floating.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50 OMII1 Totem Pole 4 -4 50 OMII2 Totem Pole 4 -4 390 O6 Totem Pole 6 -0.4 50 OD6 Open Drain 6 NA 50 STS6 Sustained Tri-State 6 -2 50 TS3 Tri-State 3 -2 50 TS6 Tri-State 6 -2 50 TSMII Tri-State 4 -4 470

14 Am79C972

ORDERING INFORMATION Standard Products

AMD standard produc ts are av ailable in sev eral pac kages and operating ranges. T he order number (Valid Combination) is f ormed by a combination of the elements below.

Am79C972B

K\V

C/I

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0° C to +70° C) I = Industrial (-40° C to +85° C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR160) V = Thin Quad Flat Pack (PQL176)

SPEED OPTION

Not applicable

DEVICE NUMBER/DESCRIPTION

Am79C972B PCnet-FAST+ Enhanced 10/100 Mbps PC I Ether- net Controller with OnNow Support

Valid Combinations

Am79C972B

KC\W,

VC\W

KI\W, VI\W

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am79C972 15

PIN DESCRIPTIONS PCI Interfa ce AD[31:0]

Address and Data Input/Output

Address and data ar e multi pl exed on the same bus in terface pins. During the fir st clock of a transaction, AD[31:0] co ntain a physica l address (3 2 bits). Dur ing the subsequent clocks, AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are defined as the least signifi cant byte (LSB) and A D[31:24] are d efined as the most significant byte (MSB). For FIFO data transfers, the Am79C972 controller can be programmed for big endian byte ordering. See CSR3, bit 2 (BSWP) for more details.

eration section for details. The Am79C972 controller will support a clock frequency of 0 MHz after certain precautions are taken to ensure data integrity. This clock or a derivation i s not used to dr ive any network functions.

When RST testing.

is active, CLK is an inp ut for NAND tree

DEVSEL

Device Select Input/Output

The Am79C972 controller dr ives DEVSEL tects a transaction that select s the device as a target. The device samples DEVSEL claims a transaction that the Am79C972 controller has initiated.

to detect if a target

when it de-

During the address phase of the transaction, when the Am79C972 controller is a bus master, AD[31:2] will address the active Double Word (DWord). The Am79C972 controller always drives AD[1:0] to ’00’ during the address phase indicating linear burst order. When the Am79C972 controller is not a bus master, the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.

During the data phase of the transacti on, AD[31: 0] are driven by the Am79C972 controller wh en performing bus master write and slave read operations. Data on AD[31:0] is latched by the Am79C972 co ntroller when performing bus master read and slave write operations.

When RST testing.

is active, AD[31:0] are inputs for NAND tree

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the same bus interface pins. During the a ddress phase o f the transaction, C /BE During the data phase, C/BE ables. The byte enables define which physical byte lanes carry meaningful data. C/BE (AD[7:0]) and C/BE function of the byte enables is independent of the byte ordering mode (BSWP, CSR3, bit 2).

When RST tree testing.

is active, C/BE[3:0] are inputs for NAND

[3:0] define th e bus command.

[3:0] are used as by te en-

0 applies to byte 0

3 applies to byte 3 (AD[31:24]). The

CLK

Clock Input

This clock is used to drive the system bus interface and the internal buffer management unit. All bus signals are sampled on the rising edge of CLK and all parameters are defined with resp ect to this edge. The A m79C972 controller normally operates over a frequency range of 10 to 33 MHz on the PCI bus due to networking demands. See the Frequency Demands for Networ k Op-

When RST testing.

is activ e, DEVS EL is an inp ut f or NAND tr ee

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79 C972 controll er when it is the bus master to indicate the beginning and duration of a transaction. FRAME transaction is beginning. FRAME data transfers continue. FRAME the final data phase o f a transaction. When the Am79C972 controller is in slave mode, it samples FRAME tion.

When RST is active, FRAME is an input for NAND tree testing.

to determ ine the ad dress phas e of a tran sac-

is asser ted to indica te a bus

is asserted while

is deasserted before

GNT

Bus Grant Input

This signal indicates that the access to the bus has been granted to the Am79C972 controller.

The Am79C972 controller supports bus parking. When the PCI bus is idle and the system arbiter asserts GNT without an active REQ from the Am79C972 controller, the device will drive the AD[31:0], C/BE lines.

When RST testing.

is active, GNT is an input for NAND tree

[3:0] and PA R

IDSEL

Initialization Device Select Input

This signal is used as a c hip sele ct for the Am79C97 2 controller duri ng configura tion read a nd write transactions.

When RST testing.

is active, IDSEL is an input for NAND tree

16 Am79C972

INTA

Interrupt Request Output

An attention signal which indicates that one or more of the following status flags is set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, and S TINT. Each status flag has either a ma sk or an enable bit which allows for suppression of IN TA

as-

sertion. Table 1 shows the flag descriptions. By default

is an open-drain output. For applications that

INTA need a high-active edge-se nsitive interrupt si gnal, the

pin can be configured for this mode by setting IN-

INTA TLEVEL (BCR2, bit 7) to 1.

When RST

is active, INTA is the output for NAND tree

testing.

IRDY

Initiator Ready Input/Output

IRDY

indicates the ability of the initiato r of the transac tion to complete the current data phas e. IRDY in conjunc ti o n w i t h T RDY both IRDY

and TRDY are asser ted simultaneously. A

. Wait states are inserted until

is used

data phase is completed on any clock when both IRDY and TRDY are asserted.

When the Am79C972 c ontroll er is a bus mas ter, it asserts IRDY

during all write data phases to indicate that valid data is present on AD[31:0]. Dur ing all read dat a phases, the device asserts IRDY

to indicate that it is

ready to accept the data. When the Am79C972 controller is the target of a trans-

action, it checks IR DY

during all wr ite data phas es to determine if valid data is presen t on AD[31:0]. During all read data phases, the device checks IRDY

to deter-

mine if the initiator is ready to accept the data.

When RST

is active, IRDY is an input for NAND tree

testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0 ] and C/BE[3:0]. When the Am79C972 controller is a bus master, it generates parity during the address and write data phases. It checks parity during read data phases. When the Am79C972 controller operates in slave mode, it checks parity during every address phase. When it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases.

When RST testing.

is active, PAR is an input for NAND tre e

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

EXDINT

IDON MERR Memory Error CSR3, bit 11 CSR0, bit 11

MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO

MPINT

RCVCCO

RINT SINT System Error CSR5, bit 10 CSR5, bit 11 TINT TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCINT

MPDTINT

MAPINT

MREINT

STINT

Excessive Deferral

Initialization Done

Missed Frame Count Overflow

Magic Packet Interrupt

Receive Collision Count Overflow

Receive Interrupt

Transmit Interrupt

MII Management Command Complete Interrupt

MII PHY Detect Transition Interrupt

MII Auto-Poll Interrupt

MII Management Frame Read Error Interrupt

Software Timer Interrupt

CSR5, bit 6 CSR5, bit 7

CSR3, bit 8 CSR0, bit 8

CSR4, bit 8 CSR4, bit 9

CSR5, bit 3 CSR5, bit 4

CSR4, bit 4 CSR4, bit 5

CSR3, bit 10 CSR0, bit 10

CSR3, bit 9 CSR0, bit 9

CSR7, bit 4 CSR7, bit 5

CSR7, bit 0 CSR7, bit 1

CSR7, bit 6 CSR7, bit 7

CSR7, bit 8 CSR7, bit 9

CSR7, bit 10 CSR7, bit 11

PERR

Parity Error Input/Output

During any slave write transaction and any master read transaction, the Am79C972 contro ller asserts PE RR when it detects a dat a p arity error and r epo rting of th e error is enabled by setting PERREN (PCI Command register, bit 6) to 1. During any master write transaction, the Am79C972 cont roller mo nitors PE RR target reports a data parity error.

When RST

is active, PERR is an input for NAND tree

testing.

to see if the

Am79C972 17

REQ

Bus Request Input/Output

The Am79C972 controller asserts REQ that it wishes to become a bus mas ter. REQ high when the Am79C972 control ler does not request the bus. In Po wer Management mode, the REQ not be driven.

When RST testing.

is active, REQ is an input for NAND tree

pin as a signal

is driven

pin will

RST

Reset Input

When RST then the Am79C972 controller performs an i nternal system reset of the type H_RESET (HARDWARE_RESET, see section on RESET). RST must be held for a minimum of 30 clock periods. While in the H_RESET state, the Am79C972 controller will disable or deassert all outputs. RST nous to clock when asserted or deasserted.

When the PG pin is LOW, RST disables all of the PCI pins except the PME

When RST is enabled.

is asserted LOW and the PG pin is HIGH,

may be asynch ro -

pin.

is LOW and PG is HIGH, NAND tree testing

SERR

System Error Output

During any slave transaction, the Am79C972 controller asserts S ERR and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to 1.

By default SERR nent test, it can be programmed to be an active-high totem-pole output.

When RST testing.

when it detects a n add re ss p ar i ty er r or,

is an open-drain out put. For compo-

is active, SERR is an input for NAND tree

STOP

Stop Input/Out put

In slave mode, the Am79C972 controller drives the

signal to inform the bus master to stop the cur-

STOP rent transaction. In bus mas ter mode, the Am79C97 2 controller checks STOP to disconnect the current transaction.

When RST testing.

is active, STOP is an input for NAND tree

to determine if the target wants

TRDY

Target Ready Input/Output

TRDY ind icates the ability of the targ et of the transaction to complete the current data phase. Wait states are inserted until both IRD Y

and TRDY are asserted simul-

taneously. A data phase is completed on any clock when both IRDY

When the Am79C972 controller is a bus master, it checks TRD Y during all read data phases to determine if vali d data is present on AD[31: 0]. Duri ng all write data phases, the device checks TRDY target is ready to accept the data.

When the Am79C972 controller is the target of a transaction, it asser ts TRDY indicate that valid data is present on AD[31 :0]. Durin g all write data phases, the device ass erts TRDY cate that it is ready to accept the data.

When RST testing.

and TRDY are asserted.

to determine if th e

during all read data phases to

to indi-

is active, TRDY is an input for NAND tree

PME

Power Management Event Output, Open Drain

PME

is an output that can be used to indicate that a power management event (a Magic Packet, an OnNow pattern match , or a change in link state) has been detected. The PME

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1. The PME

PCI clock.

signal is asynchronous with respect to the

pin is asserted when either

Board Interface

Note: Before programming the LED pins, see the description of LEDPE in BCR2, bit 12.

LED0

LED0 Output

This output is designed to directly drive an LED. By default, LED0 can also be programmed to indicate other network status (see BCR4). The LED0 ble, but by default it is active LOW. When the LED0 polarity is programmed to active LOW, the output is an open drain dr iver. When the LED0 grammed to active HIGH, the output is a totem pole driver.

Note: The LED0

indicates an active link connection. This pin

pin polarity is programma-

pin polarity is pro-

pin is multiplexed with the EEDI pin.

LED1

LED1 Output

This output is designed to directly drive an LED. By default, LED1 This pin can also be programmed to indicate other network status (see BCR5). T he LED1 grammable, but by default, it is active LOW. W hen the LED1 output is an open drain driver. When the LED1

indicates receive activity on the network.

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

18 Am79C972

larity is pr ogrammed to active HIGH, th e output is a totem pole driver.

Note: The LED1 SFBD pins.

The LED1 Detection to deter mine whe ther or not an EE PROM is present at the Am79C972 controller interface. At the last rising edge of CLK while RST is sampled to determine the value of the EE DET bi t in BCR19. It is important to mai ntain adequ ate hol d tim e around the rising edge of the CLK at this time to ensure a correctly sampled value. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead i n order to resolve the EEDET setting.

WARNING insured for correct EEPROM detection before the deassertion of RST

pin is multiplexed with the EESK and

pin is also used dur ing EEPROM Auto-

is active LOW , LED1

: The input signal level of LED1 must be

LED2

LED2 Output

This output is designed to directly drive an LED. This pin can be programmed to indicate various network status (see BCR6). T he L ED2 mable, but by default it is active LOW. When the LED 2 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED2 grammed to active HIGH, the output is a totem pole driver.

Note: The LED2 pin and the MIIRXFRTGE pins.

pin is multiplexed with the SRDCLK

pin polarity i s program-

pin polarity is pro-

LED3

LED3 Output

This output is designed to directly drive an LED. By default, LED3 This pin can also be programmed to indicate other network status (see BCR7). T he LED3 gramma ble, but by defaul t it is active LOW. When th e LED3 output is an open d rain driver. When the LED3 larity is pr ogrammed to active HIGH, th e output is a totem pole driver.

Special attention must be given to the external circuitry attached to this pin. Whe n this pin is used to dri ve an LED while an EEPROM is used in the system, then buffering maybe required between the LED3 the LED circuit. If an LED circuit were directly attached to this pin, it may create an I not be met by the serial EEPROM attached to this pin.

indicates tran smit activity on the network .

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

pin and

OL requirement that co ul d

If no EEPROM is includ ed in the system design or l ow current LEDs are used, then th e LED3 directly connected to an LED without buffering. For more details regarding LED connection, see the section on LED Support.

Note: The LED3 SRD, MIIRXFRTGD pins.

pin is multiplexed with the EEDO,

signal may be

Power Good Input

The PG pin has two functions: (1) it puts the device into Mag ic Packet™ mode, and (2) it blocks any resets when the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is set to 1, the device enters the Magic Packet mode.

When PG is LOW , a LOW assertion of the PCI RST will only cause the PCI interface pins (except for PME to be put in the high impedance state. The internal logic will ignore the assertion of RST

When PG is HIGH, assertion of the PCI RST causes the controller logic to be reset and the configuration information to be loaded from the EEPROM.

PG input should be kept high during the NAND tree testing.

RWU

Remote Wake Up Output

RWU is an output that is asserted either when the controller is in the Magic Packet mode and a Magic Packet frame has been detected, or the controller is in the Link Change Detect mode and a Link Change has been detected.

This pin can dr ive the external system mana gement logic that causes the CP U to get out of a low power mode of operation. This pin is implemented for designs that do not support the PME

Three bits that are loaded from the EEP ROM into CSR116 can program the characteristics of this pin:

1. RWU_POL determines the polarity of the RWU sig-

nal.

2. If RWU_GATE bit is set , RWU is forced to the high

impedance state when PG input is LOW.

3. RWU_DRIVER determines whether the output is

open drain or totem pole.

The internal power-on-reset signal forces this output into the high impedance state until after the polarity and drive type have been determined.

function.

WUMI

Wake-Up Mode Indicator Output

This output, which is ca pable of dri ving an LED, is asserted when the device is in Magic Packet mode. It can

)

Am79C972 19

be used to drive external logic that switches the device power source from the main p ower supply to an aux iliary power supp l y.

during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.

TBC_EN

Time Base Clock Enable Input

TBC_EN is an input that controls the selection of the source of the Time Ba se Clock. The Time Base Cl ock is used in loading the EEPROM, generation of the PHY_RST, and the timing of the MDC and MDIO signals. When the input to this pin is LOW , an internal free running oscillator with a maximum frequency of 20 MHz is used. When the inpu t to this pi n is HIGH, th e TBC_IN pin input is used to inject externally generated clock into the device. For typical applications which will use the internal oscillation, this pin should be tied to ground.

When RST testing.

is active, TBC_EN is an input for NAND tree

TBC_IN

Time Base Clock Input Input

TBC_IN may be used to connect to an external clock source to drive the internal circuitry that loads the EEPROM and controls the MDC and MDIO signals. This input is select ed when the TB C_EN pin is HIG H. This pin should be tied to ground when the TBC_EN pin is LOW.

PHY_RST

PHY Reset Output

PHY_RST is an output pin that is used to reset the external PHY. This output eliminates the need for a fan out buffer for the PCI RST signal, provides polarity for the specific PHY used, and prevents the resetting of the PHY when the PG input is LOW. The output polarity is determined by the RST_POL bit(CSR116, bit0).

EEPROM Interface EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EECS is connected to the EEPROM ’s chip select pin. It is controll ed by either the Am 79C972 controll er during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EEDI is connecte d to the EEPROM’s data input pin. It is controll ed by either the Am 79C972 controll er

Note: The EEDI pin is multiplexed with the LED0

pin.

EEDO

EEPROM Data Out Input

This pin is designe d to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EEDO is connected to the EEPROM’s data output pin. It is controlled by either the Am79C972 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3, MIIRXFRTGD, and SRD pins.

EESK

EEPROM Serial Clock Input/Output

This pin is designe d to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EESK is connected to the EEPROM’s clock pin. It is controlled by either the Am79C972 controller directly during a read of the entire EE PROM, or indirect ly by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1 SFBD pins.

The EESK pin is also used during EEPROM AutoDetection to deter mine whe ther or not an EEPROM is present at the Am79C972 controller interface. At the rising edge of the last CLK edge while RST EESK is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to 1. A sampled LOW value means that an EEPROM is no t present, and EEDET will be set to 0. See the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead to resolve the EEDET setting.

WARNING valid for correct EEPROM detection before the deassertion of RST

: The input signal level of EESK must be

is asserted,

and

Expansion Bus Interface EBUA_EBA[7:0]

Expansion Bus Upper Address/ Expansion Bus Address [7:0] Output

The EBUA_EBA[7:0] pins provide the least and most significant bytes of address on the Expansion Bus. The most significant address byte (address bits [19:16] during boot device accesses) is valid on these pins at th e beginning of a boot device access, at the rising edge of AS_EBOE

. This upper address byte must be stored ex-

20 Am79C972

ternally in a D fli p-flop. During subseq uent cycles of a boot device access, addres s bits [7:0] are p resent on these pins.

All EBUA_EBA[7:0] outpu ts are forced to a constant level to conserve power while no access on the Expansion Bus is being performed.

EBDA[15:8]

Expansion Bus Data/Address [15:8] Input/Output

When EROMCS is asserted low, EBDA[15:8] contain address bits [15:8] for boot device accesses.

The EBDA[15:8] signals are driven to a constant level to conserve power while no access on the Expansion Bus is being performed.

EBD[7:0]

Expansion Bus Data [7:0] Input/Output

The EBD[7:0] pins provide data bit s [7:0] for EPROM/ FLASH accesses. The EBD[ 7:0] signals are internally forced to a constant level to conserve power while no access on the Expansion Bus is being performed.

EROMCS

Expansion ROM Chip Select Output

EROMCS It is asserted low during the data phases of boot device accesses.

serves as the chip select for the boot device.

AS_EBOE

Address Strobe/Expansion Bus Output Enable Output

AS_EBOE upper address bits on the EBUA_EBA[7:0] pins and as the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE supplied at the beginning of boot device accesses. This rising edge provides a clock edge for a ‘374 D-type edge-triggered flip-flop which must store the upper address byte during Expansion Bus accesses for EPROM/Flash.

AS_EBOE read operations on the expansion bus and is deasserted during boot device write operations.

functions as the address strobe for the

is asserted active LOW during boot device

EBWE

Expansion Bus Write Enable Output

EBWE provides the wr ite enable for writ e accesse s to the Flash device.

EBCLK

Expansion Bus Clock Input

EBCLK may be used as the fundamental clock to drive the Expansion Bus and inte rn al SRAM a ccess cy cles. The actual inter nal clock used to dr ive the Expansion

Bus cycles depends o n the values of the EBCS and CLK_F A C settings in BCR27. Refer to the SRAM Interface Bandwidth Requirements section for details on determining the requ ired EBCLK frequency. If a clock source other than the EBCLK pin is programmed (BCR27, bi ts 5: 3 ) to be used to run the Ex pa n si on Bu s interface, this input should be tied to VDD through a 4.7

Ω resistor.

k EBCLK is not used to drive the bus interface, internal

buffer management unit, or the network functions.

Media Independent Interface TX_CLK

Transmit Clock Input

TX_CLK is a conti nuous clock input th at provides the timing reference for the transfer of the T X_EN, TXD[3:0], an d TX_ER signal s out of the Am 79C972 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, an MII transceiver operating at 10 Mbps must provid e a TX_CL K freq uency of 2.5 MHz and an MII transceiver operating at 100 Mbps must provide a TX_CLK frequency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the TXCLK pin.

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. V alid data is generated on TXD[3:0] on every TX_CLK rising edge while TX_EN is asserted. While TX_EN is deasserted , TXD[3:0] values are dri ven to a 0. TXD[3:0] transitions synchronous to TX_CLK rising edges.

Note: The TXD[0] pin is multiplexed with the TXD pin.

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C972 device is presenting valid transmit nibbles on the MII. While TX_EN is asserted, the Am79C972 device generates TXD[3:0] and TX_ER on TX_CLK rising edges. TX_EN is asserted with the first nibble of preamble and remains asserted throughout the duration of a packet until it is deassert ed p rior to the first TX_CL K following the final nibble of the frame. TX_EN transitio ns s ynch ro nous to TX_CLK rising edges.

Note: The TX_EN pin is multiplexed with the TXEN pin.

TX_ER

Transmit Error Output

TX_ER is an out put th at, if asserted wh ile TX _EN is asserted, i nstructs the MII PHY device connecte d to the Am79C972 device to transmit a code group error. TX_ER is unused and is reserved for future use and will always be driven to a logical zero.

Am79C972 21

COL

Collision Input

COL is an input that indicates that a collision has been detected on the network medium.

Note: The COL pin is multiplexed with the CLSN pin.

CRS

Carrier Sense Input

CRS is an input that indicates that a non-idl e medium, due either to transmit or receive activi ty, has been detected.

Note: The CRS pin is multiplexed with the RXEN pin.

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and RX_ER signals into the Am79C972 device. RX_CLK must provide a nibble rate cl ock (25% of the networ k data rate). Hence, an MII transceiver operating at 10 Mbps must provide an RX_ CLK freq uen cy of 2.5 MHz and an MII transceiver operating at 100 Mbps must provide an RX_CLK frequency of 25 MHz. When the external PHY switches the RX_CLK and TX_CLK, it must provide glitch-free clock pulses.

Note: The RX_CLK pin is multiplexed with the RXCLK pin.

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII recei ve data bus. Data on RXD[3:0] is sampled on every rising edge of RX_CLK while RX_DV is asserted. RXD[3:0] is ignored while RX_DV is de-asserted.

Note: The RXD[0] pin is multiplexed with the RXFRTGD pin.

If the MII port is not sele cted, th e RXD[3:0] pin can be left floating.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate that va lid received data is being presented o n the RXD[3:0] pins and RX_CLK is sync hronous to the receive data. In order for a frame to be fully received by the Am79C972 device on the MII, RX_DV must be asser ted prior to the RX_CLK rising edge, when the first nibble of the Start of Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted pri or to the RX _CLK

rising edge which follows this final nibble. RX_DV transitions are synchronous to RX_CLK rising edges.

Note: The RX_DV pin is multiplexed with the RXFRTGE pin.

If the MII port is not selected, the RX_DV pin can be left floating.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receive frame currently being transferred on the RXD[3:0] pins. When RX_ER is asser ted whi le RX_DV is asserted, a CRC error will be indicated in the receive descriptor for the incoming receive frame. RX_ER is ignored while RX_DV is deasserted. Speci al co de group s gen erate d on RXD while RX_DV is deasserted are ig nored (e.g., Bad SSD in TX and IDLE in T4). RX_ER transitions are synchronous to RX_CLK rising edges.

Note: The RX_ER pin is multiplexed with the RXDAT pin.

MDC

Management Data Clock Out put

MDC is a non-continuous c lock output that provides a timing reference for bits on the MDIO pin. During MII management por t operations, MDC runs at a nominal frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW. The MDC is derived from the Time Base Clock.

If the MII port is not selected, the MDC pin can be left floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional M II management por t data pin. MDIO is an output during the header portion of the management frame transfers and dur ing the dat a portions of write transfers. MDIO is an input during the data portions of read data transfers. When an operation is not in progress on the management port, MDIO is not driven. M DIO tr ansiti ons fr om the Am79C9 72 contr oller are synchronous to MDC falling edges.

If the PHY is attached through an MII physical connector, then the MDIO pin should be externally pulled down

SS with a 10-kΩ ±5% resistor. If the PHY is on

to V board, then the MDIO pin should be externally pulled up to V

CC with a 10-kΩ ±5% resistor.

22 Am79C972

General Purpose Serial Interface CLSN

Collision Input

CLSN is an input that indicates a collision has occurred on the network.

Note: The CLSN pin is multiplexed with the COL pin.

RXCLK

Receive Clock Input

RXCLK is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.

Note: The RXCLK pin is multiplexed with the RX_CLK pin.

RXDAT

Receive Data Input

RXDAT is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.

Note: The RXDAT pin is multiplexed with the RX_ER pin.

RXEN

Receive Enable Input

RXEN is an input. When this signal is HIGH, it indicates to the core logic that the data on the RXDAT input pin is valid.

Note: The RXEN pin is multiplexed with the CRS pin.

TXCLK

Transmit Clock Input

TXCLK is an input that provides a clock signal for MAC activity, both transmit and r ecei ve. The ri sing ed ges o f the TXCLK can be used to validate TXDAT output data.

Note: The TXCLK pin is multiplexed with the TX_CLK pin.

TXDAT

T ransmit Data Output

TXDAT is an output that provides the ser ial bit stream for transmission, including preamble, SFD, data, and FCS field, if applicable.

Note: The TXDAT pin is multiplexed with the TXD[0] pin.

TXEN

Transmit Enable Output

TXEN is an output that provides an enable signal for transmission. Data on the TXDA T pin is not valid unless the TXEN signal is HIGH.

Note: The TXEN pin is multiplexed with the TX_EN pin.

External Address Detection Interface EAR

External Address Reject Low Input

The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR’d with the value on the EAR pin. The EAR pin is defined as REJECT. The pin value is OR’d with the internal address detection result to determine if th e current frame sho uld be a ccepted or rejected.

The EAR be tied to VDD through a 10-k

When RST testing.

pin must not be left unconnect ed, it should

Ω ±5% resistor.

is active, EAR is an input for NAND tree

SFBD

Start Frame-Byte Delimiter Output For the GPSI port during External Address Detec-

tion:

An initial rising edge on the SFBD signal indicates that a start of frame delimiter has been detected. The serial bit stream will follow on the SRD signa l, commencing with the destination address field. SFBD will go high for 4 bit times (400 ns when operating at 10 Mbps) after detecting the second “1” in the SFD (St art of F rame De limiter) of a rece ived frame. SFBD will subsequent ly toggle every 4 bit times (1.25 MHz frequency when operating at 10 Mbps) with each rising edge indicating the first bit of each subsequen t byte of the received serial bit stream.

For the External PHY attached to the Media Independent Interface during External Address Detection:

An initial rising edge on the SFBD signal indicates that a start of valid data is present on the RXD[3:0] pins. SFBD will go high for one nibble time (400 ns when operating at 10 Mbps and 40 ns when operating at 100 Mbps) one RX_CLK perio d after RX_DV has been asserted and RX_ER is deasserted and t he detection o f the SFD (Start of Frame Delimiter) of a received frame. Data on the RXD[3:0] will be the start of the destination address field. SFBD will subsequently toggle every nibble time (1.25 MHz frequency when operating at 10 Mbps and 12.5 MHz fr equency when o peratin g at 10 0 Mbps) indicating the first nibble of each subsequent byte of the received nibble stream. The RX_CLK should be used in conjunction with t he SFBD to latch the correct data for external addre ss matching. SFBD will be active only during frame reception.

Note: The SFBD pin is multiplexed with the EESK and

pins.

LED1

Am79C972 23

SRD

Serial Receive Data Input/Output

SRD is the decoded NRZ data from th e n etwor k when in GPSI mode. This signal can be used for external address detection.

Note: When the MII port is selected, SRD will not generate transitions and receive data must be derived from the Media Independent Interface RXD[3:0] pins.

Note also that the SRD pin is multiplexed with the MIIRXFRTGD, EEDO, and LED3

pins.

SRDCLK

Serial Receive Data Clock Output

Serial Rece ive Data is synchronou s with reference to SRDCLK.

Note: When the MII port is selected, SRDCLK will not generate transitions and the receive clock must be derived from the MII RX_CLK pin.

Note also that the SRD CLK pin is mul tiplexed with the MIIRXFRTGE and LED2

pins.

RXFRTGD

Receive Frame T ag Data Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the MII is not selected , the RXFRTGD pin becomes a data input pin for the Receive Frame Tag. See the Receive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the RXD[0] pin.

RXFRTGE

Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the MII is not selected, the RX FRTGE pin becomes a data input enable pin for the Receive Frame Tag. See the Re ceive Frame Tagging section for de- tails.

Note: The RXFRTGE pin is multiplexed with the RX_DV pin.

MIIRXFRTGD

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXF RTG, CSR7, bit 14), and the MII is selected, the MIIRXFRTGD pin becomes a data i nput pin for the Recei ve Frame Tag. See the Receive Frame Tagging section for details.

Note: The MIIRXFRTGD pin is multiplexed with the SRD, EEDO, and LED3

pins.

MIIRXFRTGE

MII Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the Receive Frame Tagging is enabled (RXFRTG, CSR7, bit 14), and the M II is selected, the MIIRXFRTGE pin becomes a data input enable pin for the Receive Frame Tag. See the Re ceive Frame Tagging section for de- tails.

Note: The MIIRXFRTGE pin is multiplexed with the SRDCLK and LED2

pins.

IEEE 1149.1 (1990) Test Access Port Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency of up to 10 MHz. TCK has an internal pull up resistor.

TDI

Test Data In Input

TDI is the test data input path to the Am79C9 72 controller. The pin has an internal pull up resistor.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C97 2 controller. The pin is tri-stated when the JT AG port is inactive.

TMS

Test Mode Select Input

A serial input bit stre am on the TMS pin is used to define the speci fic boundary scan test to be executed. The pin has an internal pull up resistor.

24 Am79C972

Power Supply Pins VDDB

I/O Buffer Power (7 Pins) Power

There are seven power supply pins that are used by the input/output buffer drivers. All VDDB pins must be connected to a +3.3 V supply.

VDD_PCI

PCI I/O Buffer Power (9 Pins) Power

There are nine power supply pins tha t ar e us ed by the PCI input/output buffer drivers (except PME VDD_PCI pins must be connected to a +3.3 V supply.

driver). All

VSSB

I/O Buffer Ground (17 Pins) Power

There are 17 ground pins that are used by the input/ output buffer drivers.

VDD

Digital Power (6 Pins) Power

There are six power supply pins that are used by the internal digital c ir cuitry. All VDD pins must be connected to a +3.3 V supply.

VSS

Digital Ground (8 Pins) P ower

There are eight ground pins that ar e use d by the internal digital circuitry.

Am79C972 25

BASIC FUNCTIONS System Bus Interface

The Am79C972 controller is designed to operate as a bus master during nor mal operations. Some slave I/O accesses to t he Am79C972 controller are require d in normal operations as well. Initialization of the Am79C972 controller is achieved through a combination of PCI Configuration Space accesses, bus slave accesses, bus master acces ses, and an o ptional r ead of a serial EEPROM that is performed by the Am79C972 controller. The EEPROM read o peration is performed through the 93C46 EEPROM interface. The ISO 8802-3 (IEEE/A NSI 802.3) Ethernet Address may reside within the serial EEPROM. Some Am79C972 controller configuration registers may also be programmed by the EEPROM read operation.

The Address PROM, on-chip bo ard-configuration registers, and the Ether net contr oller register s occupy 32 bytes of address space. I/O an d memor y mapped I/O accesses are supported. Base Address registers in the PCI configuration sp ace allow locating the address space on a wide variety of starting addresses.

For diskless stations, the Am79C972 controller supports a ROM or Flash-based (both referred to as the Expansion ROM throughout this specification) boot device of up to 1 Mbyte in size. The host can map the boot device to any memory address that aligns to a 1-Mbyte boundary by modifyi ng the Expans ion ROM Base Address register in the PCI configuration space.

Software Interface

The software interface to the Am79C972 controller is divided into three parts. One part is the PCI configuration registers used to identify the Am79C972 controller and to setup the configuration of the device. The setup information includes the I/O or memory mapped I/O base address, mappin g of the Expansion ROM, an d the routing of the Am79 C9 72 controller interr upt cha nnel. This allows for a jumperless implementation.

or memory space (memory mapped I/O). The I/O Base Address Register i n th e P CI Configuration Space c ontrols the start address of the address space if it is mapped to I/O space. The Memor y Mapped I/O Base Address Register c ontrols the star t ad dress o f the address space if it is mapped to memory space. The 32byte address space is used by the software to program the Am79C972 con troller operating mo de, to enable and disable various features, to monitor o peratin g status, and to request par ticular functi ons to be executed by the Am79C972 controller.

The third por tion of th e software interface is the d escriptor and buffer areas that are shared between the software and the Am79C972 cont roller durin g normal network oper ations. The desc riptor area b oundaries are set by the software and do not chan ge dur ing normal network operations. There is one descriptor area for receive activity and there is a separate area for transmit activity. The descriptor space contains relocatable pointers to the network frame data, and it is used to transfer frame status from the Am79C972 controll er to the software. The buffer areas are locations that hold frame data for transmission or that acce pt frame data that has been received.

Network Interfaces

The Am79C972 controller can be connected to an IEEE 802.3 or propr ietar y network v ia one of two network interfaces. The Media Independent Interface (MII) provides an IEEE 802.3-complian t nibble-wide interface to an external 100- and/or 10 -Mbps transceiver device. The General Purpose Serial Interface (GPSI) is functionally equivalent to the GPSI found on the LANCE.

While in auto-selection mode, the interface in use is determined by the Network Port Manager. If the quiescent state of the MII MDIO pin is HIGH, the MII is activated. The GPSI por t can only be enabled by disabling the auto-selection and manually selecting the GPSI as the network port.

The second por tion of the software interface is the d irect access to the I/O resources of the Am79C972 controller. The Am79C972 controller occup ies 32 bytes of address space that must begin on a 32-byte block boundary. The address space can be mapped into I/O

26 Am79C972

The Am79C972 controller supports both half-duplex and full-duplex operation on network interfaces (i.e., GPSI and MII).

DETAILED FUNCTIONS Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Sta tus Registers (CSR), the Bu s Configuration Registers (BCR), the Ad dress PROM (APROM) lo cations, and the Expansion ROM. Table 2 shows the response of the Am79C972 controller to each of the PCI commands in slave mode.

Table 2. S lave Commands

C[3:0] Command Use

0000

0001 Special Cycle Not used

0010 I/O Read

0011 I/O Write

0100 Reserved 0101 Reserved

0110 Memory Read

0111 Memory Write

1000 Reserved 1001 Reserved

1010

1011

1100

1101

1110

1111

Interrupt Acknowledge

Configuration Read

Configuration Write

Memory Read Multiple

Dual Addres s Cycle

Memory Read Line

Memory Write Invalidate

Not used

Read of CSR, BCR, APROM, and Reset registers

Write to CSR, BCR, and APROM

Memory mapped I/O read of CSR, BCR, APROM, and Reset registers Read of the Expansion Bus

Memory mapped I/O write of CSR, BCR, and APROM

Read of the Configuration Space

Write to the Configuration Space

Aliased to Memory Read

Not used

Aliased to Memory Read

Aliased to Memory Write

Slave Configuration Transfers

The host can access the Am79C972 PCI configuration space with a configuration read or write command. The Am79C972 controller will assert DEVSEL address phase when IDSEL is asserted, AD[1:0] are both 0, and the access is a configuration cycle. AD[7:2]

during the

select the DWord location in the configuration space. The Am79C972 controller ignores AD[10:8], because it is a single function device. AD[31:11] are don’t care.

AD31 AD11

Don’t care Don’t care

AD10 AD8

AD7 AD2

DWord index

AD1 AD0

The active bytes within a DWord are determined by the byte enable signals. Eight-bit, 16-bit, a nd 32-bit transfers are supported . DEVSEL cles after the host has asserted FRAME

is asserted two clock cy-

. All configuration cycles are of fixed length. The Am79C972 controll er will asser t TRDY

on the third

clock of the data phase. The Am79C972 controller does not support burst trans-

fers for access to config uration space. When th e host keeps FRAME

asserted for a second data phase, the

Am79C972 controller will disconnect the transfer. When the host tries to access the PCI configuration

space while the automatic r ead of the EEPROM after H_RESET (see section on RESET) is on-going, the Am79C972 control ler will ter minate the access on the PCI bus with a disconnect/retry response.

The Am79C972 controller supports fast back-to-back transactions to different targets. This is indicated by the Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardw ired to 1. The Am79C97 2 controller is capable of detecting a configuration cycle even when its address phas e immediate ly follows the data phas e of a transaction to a different target without a ny idle state in-between. There will be no contention on the DEVSEL Am79C972 controll er asser ts DEV SEL clock after FRAME

, TRDY, and STOP signals, since the

on the second

is asserted (medium timing).

Slave I/O Transfers

After the Am79C972 co ntroller is c onfigured as an I/O device by setting IOEN (for regular I/O mode) or MEMEN (for memory mapped I/O mode) in the PCI Command register, it starts monito r ing the PCI bus for access to its CSR, BCR, or APROM locations. If configured for regular I/O mode, the Am79C972 cont roller will look for an address that falls within its 32 bytes of I/ O address space (starting from the I/O base add re ss) . The Am79C972 controller asserts DEVSEL an address mat ch and the access is an I/O cycle. If configured for memory mapped I/O mode, the Am79C972 controller wil l look for an address that falls within its 32 bytes of me mory address spa ce (star ting from the memory mapped I/O base address). The Am79C972 controll er asser ts DEVSEL address match and the access is a memory cycle. DEVSEL asserted FRAME

is asserted two clock cycles after the host has

. See Figure 1 and Figure 2.

if it detects

if it detects an

Am79C972 27

CLK

FRAME

1 23456

ADDR

DATA

the internal Buffer Manage ment Unit clock is a divideby-two version of the CLK signal.

The Am79C972 controller does not support burst transfers for access to its I/O resources. When the host keeps FRAME

asserted for a second data phase, the

Am79C972 controller will disconnect the transfer.

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

IDSEL

1010

PAR PAR

DEVSEL is sampled

21485C-4

Figure 1. Slave Configuration Read

The Am79C972 controller will not asser t DEVSE L

if it detects an address match, but the PCI command is not of the correct type. In memor y mapped I/O mode, the Am79C972 controller aliases all accesses to the I/O resources of the com man d ty pes Mem ory Read Multipl e and Memory Read Line to the basic Memory Read com- mand. All accesses of the typ e Memory Write and In- validate are aliased to the basic Memory Write command. Eight-bit, 16-bit, and 32-bit non-burst transactions are suppor ted. The Am79C972 controller decodes all 32 address lines to determine which I/O resource is accessed.

The typical number of wait st ates ad ded to a s lave I/O or memory mapped I/O read or write access on the part of the Am79C972 controller is six to seven clock cycles, depending upon the relative phases of the internal Buffer Management Unit clock and the CLK signal, sinc e

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

IDSEL

1 23456

ADDR

1011

PAR

DATA

PAR

21485C-5

Figure 2. Slave Configuration Write

The Am79C972 controller s upports fast back-to-back transactions to different targets. This is indicated by the Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardw ired to 1. The Am79C97 2 controller is capable of detecting an I/O or a memor y-mapped I/O cycle even when its address phase immediately follows the data phase of a transaction to a different target, without any idle state in-between. There will be no contention on the DEVSEL the Am79C972 controller asserts DEVSEL ond clock after FRAME

, TRD Y , and STOP signals, since

on the sec-

is asserted (medium timing) See

Figure 3 and Figure 4.

28 Am79C972

CLK

FRAME

1 2345678

109

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

ADDR

0010

PAR

Figure 3. Slave Read Using I/O Command

DATA

PAR

21485C-6

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

1 2345678

ADDR

0111

PAR

DATA

PAR

Figure 4. Slave Write Using Memory Command

109

21485C-7

Am79C972 29

Expansion ROM Transfers

The host must initiali ze the Expansion ROM Base Address register at offset 30H in the PCI configura tion space with a valid addre ss before enabling the access to the device. The Am79C972 controller will not react to any access to the Expansion ROM until bo th MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to 1. After the Ex pansion ROM is en abled, the Am79C9 72 controller will assert DEVSEL

on all memor y read accesses with an address between ROMBAS E and ROMBASE + 1M - 4. The Am79C972 controller aliases all accesses to the Expansion ROM of the command types Me mory Read Multiple and Memory Read Line to the basic Memory Read command. Eight-bit, 16-bit, and 32-bit read transfers are supported.

Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given the PCI Memor y Mapped I/O Base Address reg ister before enabling access to the Expansion ROM. The host must set the PCI Memor y Mapped I/O Bas e Ad-

dress register to a value that prevents the Am79C972 controller from claiming any memory cycles not intended for it.

The Am79C972 controller will always read four bytes for every host Expansion ROM read access. TRDY

will not be asserted until all four bytes are loaded into an internal scratch regis ter. The cycle TRDY

is asserted depends on the programming of the Expansion ROM interface timing. The following figure (F igure 5) assumes that ROMTMG (BCR18, bits 15- 12) is at its default value.

Note: The Expansion ROM should be read only during PCI configuration time for the PCI system.

When the host tries to write to the Expansion ROM, the Am79C972 controll er will claim the cycle by asser ting DEVSEL

. TRDY will be asserte d one clock cycle la ter. The write operation will have no effect. Writes to the Expansion ROM are done through the BCR30 Expansion Bus Data Port. Se e the sect ion on the Expansion Bus Interface for more details. See Figure 5.

CLK

FRAME

C/BE

PAR

IRDY

TRDY

DEVSEL

STOP

1 2345 484950

ADDR

CMD

PAR

DATA

PAR

DEVSEL is sampled

Figure 5. Expansion ROM Read

30 Am79C972

21485C-8

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