connecting external 10- or 100-Megabit per
second (Mbps) transceivers
— IEEE 802.3-compliant MII
— Intelligent Auto-Poll™ external PHY status
monitor and interrupt
— Includes intelligent on-chip Network Port
Manager that provides auto-port selection
between MII, on-chip 10BASE-T port, and A UI
without software support
— Supports both auto-negotiable and non
auto-negotiable external PHYs
— Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3compliant MII PHYs at full- or half-duplex
■ Internal/external loopback capabilities on all
ports
■ Supports patented External Address Detection
Interface (EADI)
— Receive frame tagging support for inter-
networking applications
■ Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
■ Full-duplex operation supported in AUI,
10BASE-T, MII, and GPSI ports with
independent Transmit (TX) and Receive (RX)
channels
■ Flexible buffer architecture
— Large independent internal TX and RX FIFOs
— SRAM-based FIFO buffer extension
supporting up to 128 kilobytes (Kbytes)
— 1/2 Gigabit per second (Gbps) internal data
bandwidth
— Programmable FIFO watermarks fo r both TX
and RX operations
— RX frame queuing for high latency PCI bus
host operation
— Programmable allocation of buffer space
between RX and TX queues
■ EEPROM interface supports jumperless design
and provides through-chip programming
— Supports full programmability of half-/full-
duplex operation f or external 100 Mbps PHYs
through EEPR OM mapping
■ Extensive LED status support
Publication# 20550Rev: E Amendment: /0
Issue Date: May 2000
■ Supports up to 1 Megabyte (Mbyte) optional
Boot PROM and Flash for diskless node
application
■ Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame
■ Includes Programma ble Inter Packet Gap (IPG)
to address less network aggressive MAC
controllers
■ Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
■ IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
GENERAL DESCRIPTION
The Am79C971 controller is a single-chip 32-bit full-duplex, 10/100-Megabit per second (Mbps) highlyintegrated Etherne t system solution, designed to
address high-perfor mance syst em applicat ion requirements. It is a flexible bus mastering dev ice that can be
used in any application, including network-ready PCs
and bridge/router designs. The bus master architecture
provides high data throughput in the system and low
CPU and system bus utiliza tion. The Am79C971 co ntroller is fabricated with AMD’s advanced low-power
Complementary Metal Oxide Semiconductor (CMOS)
process to provide l ow operating and stand by current
for power sensitive applications.
The Am79C971 controller is a complete Ethernet node
integrated into a sin gle VLSI device. It contain s a bus
interface unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)compliant Media Access Controller (MAC), a large
Transmit FIFO and a large Receive FIFO, SRAMbased FIFO extension with support for up to 128K
bytes of external frame buffering, an IEEE 802.3u-compliant MII, an IEEE 802.3-compliant Twisted-P air T r ansceiver Media Attachment Unit (10BASE-T MAU), and
an IEEE 802.3-compliant Attachment Unit Interface
(AUI). Both proprietary full-duplex and IEEE 802.3
compliant half-duplex operation are supported on the
MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10Mbps operation is supported through the MII, AUI, and
10BASE-T MAU interfaces, and 100 Mbps operation is
supported th rough the MII. The 10BASE-T MAU interface includes an IEEE 802.3-compliant auto-negotiation implementation , whic h wi ll auto mati ca lly ne got iate
between half- and full-duplex with another IEEE 802.3compliant auto-negotiation 10BASE-T device.
The Am79C971 controller is register compatible with
the LANCE (Am7990) E thernet controller, the C-
mode for board-level production connectivity
test
■ Implements low-power management for critical
battery powered application and green PCs
— Includes two power-saving sleep modes
(sleep and snooze)
— Integrated Magic Packet™ technology
support for remote power of networked PCs
■ Software compatible with AMD PCnet Family
and LANCE/C-LANCE register and descriptor
architecture
■ Compatible with the existing PCnet Family
driver/diagnostic software
■ Available in 160-pin TQFP and 176-pin TQFP
packages
LANCE (Am79C90) Ether net controlle r, and all Ethernet controllers in the PCnet Family except ILACC
(Am79C900), including the PCnet-ISA controller
(Am79C960),PCnet-ISA+ controller (Am79C961) ,
PCnet-ISA II con troller (Am79C9 61A), PCnet- 32 controller (Am79C965), PCnet-PCI controller
(Am79C970), and PCnet-PCI II controller
(Am79C970A). The B uffer Management Unit supp orts
the LANCE and PCnet descriptor software models.
The 32-bit multiplexed bus interface unit provides a
direct interface to the PCI local bus, simplifying the
design of an Ethernet node in a PC system. The
Am79C971 controller provides the complete interface
to an Expansion ROM or Flash device allowing add-on
card designs with only a singl e load per PCI bus interface pin. With its built-in suppor t for both little and bi g
endian byte alignment, this controller also addresses
non-PC applications. The Am79C971 controller’s advanced CMOS design allows the bus interface to be
connected to eithe r a +5-V or a +3.3-V s ignalin g environment. A compliant IEEE 1149.1 JTAG test interface
for board-level testing is also provided, as well as a
NAND tree test structure for those systems that cannot
support the JTAG interface.
The Am79C971 controll er suppor ts au to-configuratio n
in the PCI configu ration space. Additional Am79C971
controller configuration parameters, including the
unique IEEE physical address, can be read from an external non-volatile memory (EEPROM) immediately following system reset.
The integrated Manchester encoder/decoder (MENDEC) eliminates the need for an external Serial Interface Adapter (SIA) in the system. The built-in GPSI
allows the MENDEC to be bypassed.
2Am79C971
In addition, the device provides programmable on-chip
LED drivers for trans mit , re ce ive, collis ion, r ecei ve polarity, link integrity, activity, link active, address match,
full-duplex, MII select, 100 Mbps, or jabber status. The
Am79C971 controller also provides an EADI to allow
external hardware address filtering in internetworking
applications and a receive frame tagging feature.
For power sensitive applications where low standby
current is desired, the device incorporates two sleep
functions to reduce overall system power consumption,
excellent for notebooks and green PCs. In conjunctio n
with these low power modes, the PCnet-FAST controller also has integrated functions to suppor t Magic
Packet technology, an inexpensive technology that allows remote wake up of networked PCs.
The controller has the capability to automatically select
either the MII, AUI, or Twisted-Pair transceiver. Only
one interface is active at any one time. Any of the n etwork interfaces can be programmed to operate in either
half-duplex or full-duplex mode (AUI full-duplex only
supports the 10BASE-F standard).
The dual T ransmit and Receive FIFOs optimize system
overhead, providing sufficient latency tolerance at 10
Mbps and for 100-Mbps sys tems where low laten cies
can be guaranteed during frame transmission and
reception.
In highly loaded 10-M bps sys tems, suc h as se r vers or
when using the controll er in a 100-Mbp s environment,
the additional frame buffering capabili ty provided by a
16-bit wide SRAM interface provides high performance
and high latency tolerance on the system bus and network.
The Am79C971 controller can use up to 128 Kbytes of
SRAM as an extension of its dual Transmit and Receive
FIFOs. When no SRAM is used, the Am7 9C971 con-
troller’s FIFOs are programmed to bypass the SRAM
interface.
IMPORT ANT NOTE: A “No SRAM configuration” is only
valid for 10Mb mode. In 100Mb mode, SRAM is mandatory and must always be used.
ISO/IEC 8802-3 and IEEE 802.3 will be used interchangeably when referring to half-duplex 10 Mbps networks. IEEE 802.3 or IE EE 802.3u will be used
interchangeably only when referring to half-duplex 100Mbps Ethernet networks, since the IEEE standard is
not ISO approved yet. Full-duplex is a proprietary standard and is not approved by IEEE or ISO.
Am79C9713
ORDERING INFORMATION
Standard Products
AMD standard produc ts are av ailable in sev eral pac kages and operating r anges. T he order number (Valid Combination) is f ormed
by a combination of the elements below.
Am79C971
K\V
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0° C to +70° C)
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL176)
SPEED OPTION
Not applicable
DEVICE NUMBER/DESCRIPTION
Am79C971
Single-Chip Full-Duplex 10/100 Mbps Ethernet
Controller for PCI Local Bus
Valid Combinations
Am79C971
KC\W,
VC\W
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
LED0LED0OLED1
LED1LED1OLED1
LED2LED2OLED1
LED3LED3OLED1
SLEEPSleep Mode INA1
XTAL1Crystal InputINA1
XTAL2Crystal OutputOXTAL1
EEPROM Interface
EECS Serial EEPROM Chip SelectOO61
EEDI Serial EEPROM Data InOLED1
EEDO Serial EEPROM Data OutINA1
EESK Serial EEPROM ClockIOLED1
Expansion ROM Interface
AS_EBOEAddress Strobe/Expansion Bus Output EnableOO61
EBCLKExpansion Bus ClockINA1
EBD[7:0]Expansion Bus Data [7:0]IOTS68
EBDA[15:8]Expansion Bus Data/Address [15:8]IOTS68
EBUA_EBA[7:0]
EBWEExpansion Bus Write EnableOO61
ERAMCSExpansion Bus RAM Chip SelectOO61
EROMCSExpansion Bus ROM Chip SelectOO61
Note:
1. Not including test features
Expansion Bus Upper Addres s /Expansion Bus Addres s
[7:0]
1
OO68
DriverNo. of Pins
Am79C97115
PIN DESIGNATIONS
Listed By Group
Pin NamePin FunctionType
Media Independent Interface (MII)
COLCollisionINA1
CRSCarrier SenseINA1
MDCManagement Data ClockOOMII21
MDIOManagement Data I/OIOTSMII1
RX_CLKReceive ClockINA1
RXD[3:0]Receive DataINA4
RX_DVReceive Data ValidINA1
RX_ERReceive ErrorINA1
TX_CLKTransmit ClockINA1
TXD[3:0]Transmit DataOOMII14
TX_ENTransmit Data EnableOOMII11
TX_ERTransmit ErrorOOMII11
Attachment Unit Interface (A UI)
CI±AUI Collis ionINA1
DI±AUI Data InINA1
DO±AUI Data OutODO1
The following table describes th e various type s of o utput drive rs used i n the Am79C9 71 contro ller . All I
values shown in the table apply to 5 V signaling.
I
OH
See the DC Characteristics section for the values ap-
OL
and
A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
DO, TDO, and TPO are differential output drivers. Their
characteristics and t he o ne of the XTAL output a re described in the DC Characteristics section.
Address and data ar e multi pl exed on the same bus in terface pins. During the fir st clock of a transaction,
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks, AD[31:0] contain data. Byte ordering is littl e endian by default. AD[07:0] are define d
as the least significant byte (LSB) and AD[31:24] are
defined as the most significant byte (MSB). For FIFO
data transfers, the Am79C971 controller can be programmed for big endian byte ordering. See CSR3, bit 2
(BSWP) for more details.
eration section for details. The Am79C971 controller
will support a clock frequency of 0 MHz after certain
precautions are taken to ensure data integrity. This
clock or a derivation i s not used to dr ive any network
functions.
When RST
testing.
is active, CLK is an inp ut for NAND tree
DEVSEL
Device Select Input/Output
The Am79C971 controller dr ives DEVSEL when it detects a transaction that selects the device as a target.
The device samples DEVSEL
claims a transaction that the Am79C971 controller has
initiated.
to detect if a target
During the address phase of the transaction, when the
Am79C971 controller is a bus master , AD[31:2] will address the active Double Word (DWord). The
Am79C971 controller alwa ys drives AD[1:0] to ’00’ dur-
ing the address phase indicating linear burst order.
When the Am79C971 controller is not a bus master, the
AD[31:0] lines are continuously monitored to determine
if an address match exists for slave transfers.
During the data phase of the transacti on, AD[31: 0] are
driven by the Am79C971 controller wh en performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the Am79C971 co ntroller when
performing bus master read and slave write operations.
When RST
testing.
is active, AD[31:0] are inputs for NAND tree
C/BE[3:0]
Bus Command and Byte Enables Input/Output
Bus command and byte enables are multiplexed on the
same bus interface pins. During the a ddress phase o f
the transaction, C /BE
During the data phase, C/BE
ables. The byte enables define which physical byte
lanes carry meaningful data. C/BE
(AD[07:0]) and C/BE
The function of the byte enables is ind ependen t of th e
byte ordering mode (BSWP, CSR3, bit 2).
When RST
tree testing.
is active, C/BE[3:0] are inputs for NAND
[3:0] define th e bus command.
[3:0] are used as byte en -
0 applies to byte 0
3 applies to byte 3 (AD[31:24 ]).
CLK
Clock Input
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
are defined with resp ect to this edge. The A m79C971
controller normally operates over a frequency range of
10 to 33 MHz on the PCI bus due to networking demands. See the Frequency Demands for Networ k Op-
When RST
testing.
is activ e, DEVS EL is an inp ut f or NAND tr ee
FRAME
Cycle Frame Input/Output
FRAME is driven by the Am79 C971 controll er when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME
transaction is beginning. FRAME
data transfers continue. FRAME
the final data phase o f a transaction. When the
Am79C971 controller is in slave mode, it samples
FRAME
tion.
When RST is active, FRAME is an input f or NAND tree
testing.
to determ ine the ad dress phas e of a tran sac-
is asser ted to indica te a bus
is asserted while
is deasserted before
GNT
Bus Grant Input
This signal indicates that the access to the bus has
been granted to the Am79C971 controller.
The Am79C971 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the Am79C971 controller,
the device will drive the AD[31:0], C/BE
lines.
When RST is active, GNT is an input for NAND tree
testing.
[3:0] and PAR
IDSEL
Initialization Device Select Input
This signal is used as a c hip sele ct for the Am79C97 1
controller duri ng configura tion read a nd write transactions.
When RST
testing.
1. Not including test features.
is active, IDSEL is an input for NAND tree
18Am79C971
INTA
Interrupt Request Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MCCINT, MPDTINT, MAPINT, MREINT, and STINT. Each
status flag has either a mask or an enable bit which allows for suppression of INTA
the flag meanings.
Table 1.Interrupt Flags
NameDescriptionMask BitInterrupt Bit
BABLBabbleCSR3, bit 14 CSR0, bit 14
EXDINT
IDON
JABJabberCSR4, bit 0CSR4, bit 1
MERRMemory ErrorCSR3, bit 11 CSR0, bit 11
MISSMissed Frame CSR3, bit 12 CSR0, bit 12
MFCO
MPINT
RCVCCO
RINT
SLPINTSleep Interrupt CSR5, bit 8CSR5, bit 9
SINTSystem ErrorCSR5, bit 10 CSR5, bit 11
TINT
TXSTRTTransmit Start CSR4, bit 2CSR4, bit 3
UINTUser InterruptCSR4, bit 7CSR4, bit 6
MCCIINT
MCCINT
MPDTINT
Excessive
Deferral
Initialization
Done
Missed Frame
Count Overflow
Magic Packet
Interrupt
Receive
Collision Count
Overflow
Receive
Interrupt
Transmit
Interrupt
Internal MII
Management
Command
Complete
Interrupt
MII
Management
Command
Complete
Interrupt
MII PHY Detect
Transition
Interrupt
assertio n. Table 1 shows
CSR5, bit 6CSR5, bit 7
CSR3, bit 8CSR0, bit 8
CSR4, bit 8CSR4, bit 9
CSR5, bit 3CSR5, bit 4
CSR4, bit 4CSR4, bit 5
CSR3, bit 10 CSR0, bit 10
CSR3, bit 9CSR0, bit 9
CSR7, bit 2CSR7, bit 3
CSR7, bit 4CSR7, bit 5
CSR7, bit 0CSR7, bit 1
Table 1.Interrupt Flags
NameDescriptionMask BitInterrupt Bit
MAPINT
MREINT
STINT
By default INTA
MII Auto-Poll
Interrupt
MII
Management
Frame Read
Error Interrupt
Software Timer
Interrupt
CSR7, bit 6CSR7, bit 7
CSR7, bit 8CSR7, bit 9
CSR7, bit 10 CSR7, bit 11
is an open-drain output. For applications that need a high-active edge-sensitive interrupt
signal, the INTA
pin can be configured f or this mode by
setting INTLEVEL (BCR2, bit 7) to 1.
When RST is active, INTA is the outp ut for NAND tree
testing.
IRDY
Initiator Ready Input/Output
IRDY indicates the ability of the initiator of the transaction to complete the current data phase. IRDY
in conjunct i on wi t h T RDY
both IRDY
and TRDY are asser ted simultaneously. A
. Wait states are inserted until
is used
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the Am79C971 c ontroll er is a bus mas ter, it asserts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. Durin g all read dat a
phases, the device asserts IRDY
to indicate that it is
ready to accept the data.
When the Am79C971 controller is the target of a trans-
action, it checks IRDY
during all write data phases to
determine if valid data is presen t on AD[31:0]. During
all read data phases, the device checks IRDY
to deter-
mine if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND tree
testing.
PAR
ParityInput/Output
Parity is even parity across AD[31:0] a nd C/BE[3:0].
When the Am79C971 controller is a bus master , it generates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C971 controller operates in slave mode, it checks
parity during ev ery address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.
When RST
testing.
is active, PA R is an input for NAND tree
Am79C97119
PERR
Parity Error Input/Output
During any slave write transaction and any master read
transaction, the Am79C971 contro ller asserts PE RR
when it detects a dat a pa rity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C971 control ler monit ors PERR
target reports a data parity error.
When RST is active, PERR is an in put for NAND tree
testing.
to see if the
REQ
Bus Request Input/Output
The Am79C971 controller asserts REQ pin as a signal
that it wishes to become a bus mas ter. REQ
high when the Am79C971 control ler does not request
the bus. During M a gi c Packet
not be driven.
When RST is active, REQ is an input for NAND tree
testing.
mode, the REQ pin will
is driven
RST
Reset
Input
When RST
troller performs an internal system reset of the type
H_RESET (HARDWARE_RESET, see section on RESET). RST
riods. While in the H_RESET state, the Am79C971
controller will disable or deassert all outputs. RST
be asynchronous to clock when asser ted or deasserted.
When RST
is asserte d low, then the Am79C971 con-
must be held for a minimum of 30 clock pe-
may
is active, NAND tree testing is enabled.
SERR
System Error Input/Output
During any slave transaction, the Am79C971 controller
asserts S ERR
and reporting of the error is enabled by setting PERREN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.
By default SERR
nent test, it can be programmed to be an active-high
totem-pole output.
When RST
testing.
when it detects a n add re ss p ar i ty er r or,
is an open-drain out put. For compo-
is active, SERR is an input for NAND tree
STOP
Stop Input/Output
In slave mode, the Am79C971 controller drives the
signal to inform the bus master to stop the cur-
STOP
rent transaction. In bus mas ter mode, the Am79C97 1
controller checks STOP
to disconnect the current transaction.
When RST is active, STOP is an input for NAND tree
testing.
to determine if the target wants
TRDY
Target Ready Input/Output
TRDY indicates the ability of the target of the transa ction to complete the current data phase. Wait states are
inserted until both IRDY
taneously. A data phase is completed on any clock
when both IRDY
When the Am79C971 controller is a bus master, it
checks TRD Y during all read data phases to determine
if vali d data is present on AD[31: 0]. Duri ng all write data
phases, the device checks TRDY
target is ready to accept the data.
When the Am79C971 controller is the target of a transaction, it asser ts TRDY
indicate that valid data is present on AD[31 :0]. Durin g
all write data phases, the device ass erts TRDY
cate that it is ready to accept the data.
When RST is active, TRDY is an input for NAND tree
testing.
and TRDY are asserted.
and TRDY are asserted simul-
to determine if th e
during all read data phases to
to indi-
Board Interface
Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12 first.
LED0
LED0 Output
This output is designed to directly drive an LED. By defaul t, LED 0
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The LED0
pin polarity is programmable, but by default it is active
LOW. Whe n the LED0
active LOW, the output is an open d rain driver. When
the LED0
the output is a totem pole driver.
Note: The LED0 pin is multiplexed with the EEDI pin.
When RST
testing.
indicates an ac tive link connection on the
pin polarity is programmed to
pin polar ity is progra mmed to act ive HIGH,
is active, LED0 is an input for NAND tree
LED1
LED1Output
This output is designed to directly drive an LED. By default, LED1
This pin can also be programmed to indicate other network status (see BCR5). T he LED1
grammable, but by default, it is active LOW. When the
LED1
output is an open drain driver. When the LED1
indicates receive activity on the network.
pin polarity is pro-
pin polarity is programmed to active LOW, the
pin po-
20Am79C971
larity is pr ogrammed to active HIGH, th e output is a
totem pole driver.
Note: The LED1 pin is multiplexed with the EESK and
SFBD pins.
The LED1
Detection to deter mine whe ther or not an EE PROM is
present at the Am79C971 controller interface. At the
last rising edge of CLK while RST
is sampled to determine the value of the EEDET bit i n
BCR19. It is important to maintain ad equate hold time
around the rising edge of the CLK at this time to ensure
a correctly sampled value. A sampled HIGH value
means that an EEPROM is present, and EEDET will be
set to 1. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to 0. See
the EEPROM Auto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead i n
order to resolve the EEDET setting.
When RST
testing.
WARNING: The input signal level of LED1 must b e
insured for correct EEPROM detection before the
deassertion of RST
pin is also used dur ing EEPROM Auto-
is active LOW , LED1
is active, LED1 is an input for NAND tree
.
LED2
LED2 Output
This output is designed to directly drive an LED. By default, LED2
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default it is active
LOW. Whe n the LED2
active LOW, the output is an open drain driver. When
the LED2
the output is a totem pole driver.
indicates correct receive polarity on the
pin polarity is programmed to
pin polar ity is progra mmed to act ive HIGH,
LED while an EEPROM is used in the system, then
buffering is required between the LED3
LED circuit. If an LED c ircuit were directl y attached t o
this pin, it would crea te an I
not be met by the serial EEPROM attached to this pin.
If no EEPROM is inclu ded in the system design, then
the LED3
without buffering. For more details regarding LED connection, see the section on LED Support.
Note: The LED3
SRD, MIIRXFRTGD pins.
When RST
testing.
signal may be directly connected to an LED
pin is multiplexed with the EEDO,
is active, LED3 is an input for NAND tree
OL requirement that could
pin and the
SLEEP
Sleep Input
When SLEEP is asser ted, the Am79C9 71 controller
performs an internal system reset of the H_RESET
type and then proceeds into a power savings mode. All
Am79C971 controller outputs will be placed in their
normal reset condition. All Am79C971 controller inputs
will be ignored except for the SLEEP
tem must refrain from star ting th e network operations
of the Am79C971 controller for 0.5 se conds following
the deasser tion o f the SLEEP
ternal analog circuits to stabilize.
For effects with the Magic Packet™ modes, se e the
Magic Packet section.
Both CLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP
effect.
The SLEEP pin should not be asserted during power
supply ramp up. If it is desired that SLEEP
at power supply ramp up, then the system must delay
the assertion of SLEEP
completion of hardware reset.
until three clock cycles after the
pin itself . The sys-
pin in order to allow in-
command to take
be asserted
Note: The LED2 pin is multiplexed with the SRDCLK
pin and the MIIRXFRTGE pins.
When RST
testing.
is active, LED2 is an input for NAND tree
LED3
LED3 Output
This output is designed to directly drive an LED. By default, LED3
This pin can also be programmed to indicate other network status (see BCR7). T he LED3
gramma ble, but by defaul t it is active LOW. When th e
LED3
output is an open d rain driver. When the LED3
larity is pr ogrammed to active HIGH, th e output is a
totem pole driver.
Special attention must be given to the external circuitry
attached to this pin. Whe n this pin is used to dri ve an
indicates tran smit activity on the network .
pin polarity is pro-
pin polarity is programmed to active LOW, the
pin po-
Am79C97121
WARNING: The SLEEP pin must not be left unconnected. It should be tied to VDD if the power saving
mode is not used.
Note: The SLEEP
When RST
testing.
is active, SLEEP is an input for NAND tree
pin is multiplexed with the EAR pin.
XTAL1
Crystal Oscillator In Input
The internal clock generator uses a 20-MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the cr ystal frequency. XTAL1
may alternatively be driven using an external 20- MHz
CMOS level clock signal. Refer to the section on Exter-nal Crystal Characte ristic s for more details. This clock
is always required whether or not the internal
10BASE-T/AUI ports are enabled. If the internal PHY is
not used, ±10% accuracy is sufficient for the clock
source.
Note: When the Am79C971 controller is in coma
mode, t here is an i nternal 2 2 k
ground. If an external source drives XTAL1, some
power consumption will be consumed driving this resistor. If XTAL1 is driven LOW at this time, power consumption will be minimized. In this case, XTAL1 must
remain active for at least 30 cycles after the as ser tion
of SLEEP
and deassertion of REQ.
Ω resistor fr om X TAL1 to
XTAL2
Crystal Oscillator Out Output
The internal clock generator uses a 20-MHz crystal that
is attached to the pins XT AL1 and XTAL2. The network
data rate is one-half of the cry stal frequenc y. If an external clock source is used on XTAL1, then XTAL2
should be left unconnected.
EEPROM Interface
EECS
EEPROM Chip Select Output
This pin is designed to directly interface to a serial EEPROM that uses the 93C46 EEPROM interface protocol. EECS is connected to the EEPROM ’s chip select
pin. It is controll ed by either the Am 79C971 controll er
during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
When RST
testing.
is active, EECS is an input for NAND tree
EEDI
EEPROM Data InOutput
This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EEDI is connecte d to the EEPROM’s data input
pin. It is controll ed by either the Am 79C971 controll er
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.
Note: The EEDI pin is multiplexed with the LED0
When RST
testing.
is active, EEDI is an input for NAND tree
pin.
EEDO
EEPROM Data Out Input
This pin is designed to di rectly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EEDO is connecte d to the EEPROM’s data output pin. It is controlled by either the Am79C971
controller during command portions of a read of the entire EEPROM, or indirectly by the host system by reading from BCR19, bit 0.
Note: The EEDO pin is multiplexed with the LED3,
MIIRXFRTGD, and SRD pins.
When RST
testing.
is active, EEDO is an input for NAND tree
EESK
EEPROM Serial clock Input/Output
This pin is designe d to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface protocol. EESK is connected to the EEPROM’s clock pin.
It is controlled by either the Am79C971 controller directly during a read of the entire EE PROM , or indire ctly
by the host system by writing to BCR19, bit 1.
Note: The EESK pin is multiplexed with the LED1
SFBD pins.
The EESK pin is also used during EEPROM AutoDetection to deter mine whe ther or not an EEPROM is
present at the Am79C971 controller interface. At the
rising edge of the last CLK edge while RST
EESK is sampled to determine the value of the EEDET
bit in BCR19. A sampled HIGH value means that an
EEPROM is present, and EEDET will be set to 1. A
sampled LOW value means that an EEPROM is no t
present, and EEDET will be set to 0. See the EEPROMAuto-Detection section for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead to resolve the EEDET setting.
When RST
testing.
WARNING: The input signal level of EESK must be
valid for correct EEPROM detection before the
deassertion of RST
is active, EESK is an inpu t for NAND tree
.
is asserted,
and
Expansion Bus Interface
EBUA_EBA[7:0]
Expansion Bus Upper Address/
Expansion Bus Address [7:0] Output
The EBUA_EBA[7:0] pins provide the least and most
significant bytes of address on the Expansion Bus. The
most significant addre ss byte (address bits [15:8] during SRAM accesses; ad dress bits [19:16] dur ing boot
device accesses) is valid on these pins at the beginning
of an SRAM or boot device access, at the rising edge
of AS_EBOE
externally in a D flip -flop. Durin g sub seque nt cy cles o f
an SRAM or boot device access, address bits [7:0] are
present on these pins.
All EBUA_EBA[7:0] outputs are forced to a constant
level to conserve power while no access on the Expansion Bus is being performed.
. This upper address byte must be sto re d
22Am79C971
EBDA[15:8]
Expansion Bus Data/Address [15:8] Input/Output
When ERAMCS is asserted, EBDA[15:8] contain the
data bits [15:8] for SRAM accesses. When EROMCS
asserted low, EBDA[15:8] contain address bits [15:8]
for boot device accesses.
The EBDA[15:8] signals are driven to a constant level
to conserve power while no access on the Expansion
Bus is being performed.
is
EBD[7:0]
Expansion Bus Data [7:0] Input/Output
The EBD[7:0] pins provide data bits [7:0] for RAM/ROM
accesses. The EBD[7:0] signals are internally f orced to
a constant level to co ns erv e po wer while no ac cess on
the Expansion Bus is being performed.
EROMCS
Expansion ROM Chip Select Output
EROMCS serves as the chip select for the boot device.
It is asserted low during the data phases of boot device
accesses.
ERAMCS
Expansion RAM Chip Select Output
ERAMCS is asserted during SRAM read and write operations on the expansion bus.
AS_EBOE
Address Strobe/Expansion Bus
Output Enable Output
AS_EBOE
upper address bits on the EBUA_EBA[7:0] pins and as
the output enable for the Expansion Bus.
As an address strobe, a rising edge on AS_EBOE
supplied at the beginning of SRAM and boot device
accesses. This rising edge provides a clock edge for a
‘374 D-type edge-triggered flip-flop which must store
the upper address byte dur ing Expansion Bus accesses for EPROM/Flash/SRAM.
AS_EBOE
and SRAM read operations on the expansion bus and
is deasser ted during boot device and SRAM wr ite
operations.
functions as the address strobe for the
is
is asserted active LOW during boot device
EBWE
Expansion Bus Write Enable Output
EBWE provides the wr ite enable for writ e accesse s to
the SRAM devices and/or Flash device.
EBCLK
Expansion Bus Clock Input
EBCLK may be used as the fundamental clock to drive
the Expansion Bus ac cess cycles. The a ctual inter nal
clock used to drive the Expansion Bus cycles depends
on the values of the EBCS and CLK_FAC settings in
BCR27. Refer to the SRAM Interface Bandwidth Requirements section for details on determining the required EBCLK frequency. If a clock source other than
the EBCLK pin is programmed (BCR27, bi ts 5:3 ) to be
used to run the Expans ion Bus interface, this input
should be tied to VDD through a 4.7 k
EBCLK is not used to drive the bus interface, inter nal
buffer management unit, or the network functions.
Ω resistor.
Media Independent Interface
TX_CLK
Transmit Clock Input
TX_CLK is a conti nuous clock input th at provides the
timing reference for the transfer of the TX_EN,
TXD[3:0], an d TX_ER signal s out of the Am 79C971
device. TX_CLK must provide a nibble rate clock (25%
of the network data rate). Hence, an MII transceiver operating at 10 Mbps must provid e a TX_CL K freq uency
of 2.5 MHz and an MII transceiver operating at 100
Mbps must provide a TX_CLK frequency of 25 MHz.
Note: The TX_CLK pin is multiplexed with the TXCLK
pin.
When RST
testing.
If the MII port is not selecte d, the TX_CLK pin can b e
left floating.
is active, TX_CLK is an input for NAND tree
TXD[3:0]
Transmit Data Output
TXD[3:0] is the nibble-wide MII transmit data bus. Valid
data is generated on TXD[3:0] on every TX_CLK rising
edge while TX_EN is asserted. While TX_EN is deasserted , TXD[3:0] values are dri ven to a 0. TXD[3:0]
transitions synchronous to TX_CLK rising edges.
Note: The TXD[0] pin is multiplexed with the TXDAT
pin.
When RST
testing.
If the MII port is not selected, the TXD[3:0] pins can be
left floating.
is activ e , TXD[3: 0] ar e input s f or NAN D tree
TX_EN
Transmit Enable Output
TX_EN indicates when the Am79C971 device is presenting valid transmit nibbles on the MII. While TX_EN
is asserted, the Am79C971 device generates TXD[3:0]
and TX_ER on TX_CLK rising edges. TX_EN is asserted with the first nibble of preamble and remains asserted throughout the duration of a packet until it is
deassert ed p rior to the first TX_CLK following the final
Am79C97123
nibble of the frame. TX_EN transitions synchronous to
TX_CLK rising edges.
nal PHY switches t he RX_CLK an d TX_CLK, it must
provide glitch-free clock pulses.
Note: The TX_EN pin is multiplexed with the TXEN
pin.
When RST
testing.
If the MII port is not selected, the TX_EN pin can be left
floating.
is active, TX_EN is an input for NAND tree
TX_ER
Transmit Error Output
TX_ER is an output that, if asserted while TX_EN is asserted , instruc ts the MII PHY device connecte d to the
Am79C971 device to transmit a code group error.
TX_ER is unused and is reserved for future use and will
always be driven to a logical zero.
When RST
testing.
If the MII port is not selected, the TX_ER pin can be left
floating.
is active, TX_ER is an input for NAND tree
COL
Collision Input
COL is an input that indicates that a collision has been
detected on the network medium.
Note: The RX_CLK pin is multiplexed with the RXCLK
pin.
When RST
testing.
If the MII por t is not se lected, the RX_CLK pi n can be
left floating.
is active, RX_CLK is an input for NAND tree
RXD[3:0]
Receive Data Input
RXD[3:0] is the nibble-wide MII receive data bus. Data
on RXD[3:0] is sampled on every rising edge of
RX_CLK while RX_DV is asserted. RXD[3:0] is ignored
while RX_DV is de-asserted.
When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Tagg ing is enabled (RXFRTG,
CSR7, bit 14) and the MII is not selected, the RXD[0]
pin becomes a data input pin for the Receive Frame
Tag (RXFRTGD). See the Receive Frame Tagging sec-
tion for details.
Note: The RXD[0] pin is multiplexed with the
RXFRTGD pin.
When RST
testing.
is activ e, RXD[3:0 ] are in puts f or NAN D tree
Note: The COL pin is multiplexed with the CLSN pin.
When RST
testing.
If the MII por t is not s elected, the CO L pin can be left
floating.
is active, COL is an input for NAND tree
CRS
Carrier Sense Input
CRS is an input that indicates that a non-idl e medium,
due either to transmit or receive activi ty, has been detected.
Note: The CRS pin is multiplexed with the RXEN pin.
When RST
testing.
If the MII port is not select ed, the CRS pin can be left
floating.
is active, CRS is an input for NAND tree
RX_CLK
Receive Clock Input
RX_CLK is a clock input that provides the timing reference for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C971 device. RX_CLK
must provide a nibble rate cl ock (25% of the networ k
data rate). Hence, an MII transceiver operating at 10
Mbps must provide an RX_ CLK freq uen cy of 2.5 MHz
and an MII transceiver operating at 100 Mbps must provide an RX_CLK frequency of 25 MHz. When the exter-
If the MII por t is not sel ected, th e RXS[3 :0] pin can b e
left floating.
RX_DV
Receive Data Valid Input
RX_DV is an input used to indicate tha t valid received
data is being presented o n the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am 79C971 device on the MII, RX_DV must be asser ted prior t o the
RX_CLK rising edge, when th e first nibble of the Start
of Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK,
when the last nibble of the CRC is driven on RXD[3:0].
RX_DV must then be deasserted pri or to th e RX_CLK
rising edge which follows this final nibble. RX_DV transitions are synchronous to RX_CLK rising edges.
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII i s not selected, the RX_DV pin becomes a data input enable pin for the Receive Frame
Tag (RXFRTGE). See the Receive Frame Tagging sec-
tion for details.
Note: The RX_DV pin is multiplexed with the
RXFRTGE pin.
When RST
testing.
is active, RX_DV is an input for NAND tree
24Am79C971
If the MII port is not selected, the RX_DV pin can be left
floating.
RX_ER
Receive Error Input
RX_ER is an input that indicates that the MII transceiver device has detected a coding error in the receive
frame currently being transferred on the RXD[3:0] pins.
When RX_ER is asser t ed while RX_DV is asser ted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Spec i al co de group s gen erate d
on RXD while RX_DV is deasserted are ignor ed (e.g.,
Bad SSD in TX and IDLE in T4). RX_ER transitions are
synchronous to RX_CLK rising edges.
Note: The RX_ER pin is multiplexed with the RXDAT
pin.
When RST
testing.
If the MII port is not selected, the RX_ER pin can be left
floating.
is active, RX_ER is an input for NAND tree
MDC
Management Data Clock Output
MDC is a non-continuous clock output t hat provides a
timing referenc e for bits on the MDIO p in. Duri ng MII
management por t operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management operations are in progress, MDC is driven LOW. The MDC is
derived from the external 20-MHz crystal.
Attachment Unit Interface
CI±
Collision In Input
CI± is a differential input pair sig nal ing the A m7 9C971
controller that a collision has been detected on the network media, indicated by the CI
with a 10-MHz pattern of sufficient amplitude and pulse
width to meet ISO 8802-3 (IEEE/ANSI 802.3 ) standards. CI
If the CI
gether.
± operates at pseudo ECL levels.
± pins are not used , they should be tied to-
± inputs being driven
DI±
Data In Input
DI
±is a diff erential input pair to the Am79C971 control-
ler carr ying Manche ster encoded data from the network. DI
If the DI
gether.
± operates at pseudo ECL levels.
± pins are not used, they should be tied to-
DO±
Data Out Output
DO± is a differential output pair from the Am79C971
controller for transmitting Manches te r enc ode d d ata t o
the network. DO
If the AUI is not used, DO
minimum power consumption.
± operates at pseudo ECL levels.
± should be le ft floating for
10BASE-T Interface
If the MII port is not selected, th e MDC pin can be left
floating.
MDIO
Management Data I/O Input/Output
MDIO is the bidirectional M II management por t data
pin. MDIO is an output during the header portion of the
management frame transfers and durin g the data portions of write transfers. MDIO is an input during the
data portions of read data transfers. When an operation
is not in progress on the management port, MDIO is not
driven. MDIO transitions from the Am79C971 controller
are synchronous to MDC Falling edges.
If the PHY is attached through an MII physical connector, then the MDIO pin should be externally pulled down
SS with a 10-kΩ ±5% resistor. If the PHY is on
to V
board, then the MDIO pin should be externally pulled
up to V
When RST is active, MDIO is an input for NAND tre e
testing.
CC with a 10-kΩ ±5% resistor.
RXD±
10BASE-T Receive Data Input
± are 10BASE-T por t differential rece ivers. If the
RXD
10BASE-T interface is not used in a design, RXD+ and
RXD- should be connected to each other.
TXD±
10BASE-T Transmit Data Output
TXD± are 10BASE-T port differential drivers.
TXP±
10BASE-T Pre-Distortion Control Output
These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.
General Purpose Serial Interface
CLSN
Collision Input
CLSN is an input that indicates a collision has occurred
on the network.
Note: The CLSN pin is multiplexed with the COL pin.
When RST
testing.
is active, CLSN is an input for NAND tree
Am79C97125
RXCLK
Receive Clock Input
RXCLK is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
TXEN
Transmit Enable Output
TXEN is an output that provides an enable signal for
transmission. Data on the TXDAT pin is not valid unless
the TXEN signal is HIGH.
Note: The RXCLK pin is multiplexed with the RX_CLK
pin.
When RST
testing.
is active, RXCLK is an input for NAND tree
RXDAT
Receive Data Input
RXDAT is an input. The rising edges of the RXCLK signal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
Note: The RXDAT pin is multiplexed with the RX_E R
pin.
When RST
testing.
is active, RXDAT is an input for NAND tree
RXEN
Receive Enable Input
RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.
Note: The RXEN pin is multiplexed with the CRS pin.
When RST
testing.
is active, RXEN is an input for NAND tr ee
TXCLK
Transmit Clock Input
TXCLK is an input that provides a clock signal for MAC
activity, both transmit and r ecei ve. The ri sing edges o f
the TXCLK can be used to validate TXDAT output data.
Note: The TXCLK pin is multiplexed with the TX_CLK
pin.
When RST
testing.
is active, TXCLK is an input for NAND tree
TXDAT
Transmit Data Output
TXDAT is an output tha t provides the ser ial bit stream
for transmission, including preamble, SFD, data, and
FCS field, if applicable.
Note: The TXDAT pin is multiplexed with the TXD[0]
pin.
When RST
testing.
is active, TXDAT is an input for NAND tree
Note: The TXEN pin is multiplexed with the TX_EN
pin.
When RST
testing.
is active, TXEN is an input for NAND tree
External Address Detection Interface
EAR
External Address Reject Low Input
The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR’d with the value on the EAR
pin. The EAR pin is defined as REJECT. The pin value
is OR’d with the internal address detection result to determine if th e current frame sho uld be a ccepted or rejected.
The EAR
be tied to VDD through a resistor.
Note: The EAR pin is multiplexed with the SLEEP pin.
When RST
testing.
pin must not be left unconnect ed, it should
is active, EAR is an input for NAND tree
SFBD
Start Frame-Byte Delimiter Output
For the Internal PHY during External Address
Detection:
An initial rising edge on the SFBD signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signa l, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns when operating at 10 Mbps) after
detecting the second “1” in the S FD (Start of F ra me Delimiter) of a rece ived frame. SFBD will subsequent ly
toggle every 4 bit times (1.25 MHz frequency when operating at 10 Mbps) with each rising edge indicating the
first bit of each subsequen t byte of the received serial
bit stream. See the EADI Rejection Timing with InternalPHY timing diagram for details. SFBD will be active
only during frame reception.
For the External PHY attached to the Media Independent Interface during External Address Detection:
An initial rising edge on the SFBD signal indicates that
a start of valid data is present on the RXD[3:0] pins.
SFBD will go high for one nibble time (400 ns when operating at 10 Mbps and 40 ns when operating at 100
Mbps) one RX_CLK perio d after RX_DV has been asserted and RX_ER is deasserted and the detection o f
26Am79C971
the SFD (Start of F rame Delimiter) of a received frame.
Data on the RXD[3:0] will be the start of the destination
address field. SFBD will subsequently toggle every nibble time (1.25 MHz frequency when operating at 10
Mbps and 12.5 MHz fr equenc y when o perating at 10 0
Mbps) indicating the first nibble of each subsequent
byte of the received nibble stream. The RX_CLK
should be used in con junction with the S FBD to latch
the correct data for external address matching. SFBD
will be active only during frame reception.
Note: The SFBD pin is multiplexed with the EESK and
pins.
LED1
When RST
testing.
is active, SFBD is an input for NAND tree
SRD
Serial Receive Data Input/Output
SRD is the decoded NRZ data from the net work. This
signal can be used for external address detection.
When the 10BASE-T port is selected, transitions on
SRD will only occur during receive activity. When the
AUI port is selected, transitions on SRD will occur during both transmit and receive activity.
When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Ta gging is enabled (RXFRTG,
CSR7, bit 14) and the MII is selected, the SRD pin becomes a data input pin for the Receive Frame Tag (MIIRXFRTGD). See the Receive Frame Tagging section
for details.
Note: When the MII port is selected, SRD will not generate transitions and receive data must be derived from
the Media Independent Interface RXD[3:0] pins.
Note also that the SRD pin is multiplexed with the
EEDO and LED3
When RST
testing.
pins.
is active, SRD is an input for NAND tree
SRDCLK
Serial Receive Data Clock Input/Output
Serial Rece ive Data is synchronou s with reference to
SRDCLK. When the 10BASE-T port is selected, transitions on SRDCLK will only occur during receive activity.
When the AUI port is selected, transitions on SRDCLK
will occur during both transmit and receive activity.
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the SRDCLK pin becomes a data input enable pin for the Rece ive Frame
Tag (M IIRXFRTGE). See the Receive Frame Tagging
section for details.
Note: When the MII port is selected, SRDCLK will not
generate transitions and the receive clock must be derived from the MII RX_CLK pin.
Note also that the SR DCLK pin i s multiplexed with the
pin.
LED2
When RST
tree testing.
is active, SRDCLK is an input for NAND
RXFRTGD
Receive Frame Tag Data Input
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is no t selected, the RXFRTGD pin
becomes a data i nput pin for the Recei ve Frame Tag.
See the Receive Frame Tagging section for details.
Note: The RXFRTGD pin is multiplexed with the
RXD[0] pin.
When RST
tree testing.
is active, RXFRTGD is an input for NAND
RXFRTGE
Receive Frame Tag Enable Input
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the Re ceive Frame Tagging secti on for de-
tails.
Note: The RXFRTGE pin is multiplexed with the
RX_DV pin.
When RST
tree testing.
is active, RXFRTGE is an input for NAND
MIIRXFRTGD
MII Receive Frame Tag Enable Input/Output
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is ena bled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGD pin
becomes a data i nput pin for the Recei ve Frame Tag.
See the Receive Frame Tagging section for details.
Note: The MIIRXFRTGD pin is multiplexed with the
SRD pin.
When RST
NAND tree testing.
is active, MIIRXFRTGD is an inpu t for
MIIRXFRTGE
MII Receive Frame Tag Enable Input/Output
When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the M II is selected, the MIIRXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the Re ceive Frame Tagging secti on for de-
tails.
Note: The MIIRXFRTGE pin is multiplexed with the
SRDCLK pin.
Am79C97127
When RST is active, MIIRXFRTGE is an input for
NAND tree testing.
IEEE 1149.1 (1990) Test Access Port
Interface
TCK
Test Clock Input
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull up resistor.
TDI
Test Data In Input
TDI is the test da ta input path t o the Am79C9 71 controller. The pin has an internal pull up resistor.
VDD_PLL
PLL Power (1 Pin) Power
There is one analog PLL +5 V supply pin. Specia l attention should be paid to the printed circuit board layout
to avoid excessive noise on this line. Refer to Appendix
B, Recommendation for Power and Ground Decoupling, for details.
VSS_PLL
PLL Ground (1 Pin) Power
There is one analog PLL groun d pin. Spe cial attentio n
should be paid to the printed circuit board layout to
avoid excessive noise on this line. Refer to Appendix B,
Recommendation for Power and Ground Decoupling,
for details.
TDO
Test Data Out Output
TDO is the test data output path from the Am79C971
controller. The pin is tri-stated when the JT A G port is inactive.
TMS
Test Mode Select Input
A serial input bit stream on the TMS pin is used to define the specif ic boundary scan test to be executed.
The pin has an internal pull up resistor.
Power Supply Pins
AVDDB
Analog Power (3 Pins) Power
There are thr ee analog +5 V sup ply pins that provide
power for the Twisted Pair and AUI drivers. Hence, they
are very noisy. Special attention should b e paid to the
printed circuit board layout to av oid e xcessive noise on
these lines. Refer to Appendix B, Recommendation forPower and Ground Decoupling, for details.
AVSSB
Analog Ground (1 Pins) Power
There is one analog ground pin that provides ground
for the Twi sted Pair and AUI drivers. Hence, it i s very
noisy. Special attention should be paid to the printed
circuit board layout to avoid excessive noise on these
lines. Refer to Appendix B, Recommendation for P owerand Ground Decoupling, for details.
VDDB
I/O Buffer Power (5 Pins) Power
There are five power supply pins tha t are used by the
input/output buffer drivers. All VDDB pins must be connected to a +5 V supply.
VSSB
I/O Buffer Ground (13 Pins) Power
There are thirteen ground pins that are used by the PCI
bus input/output buffer drivers.
VDD_PCI
PCI I/O Buffer Power (5 Pins) Power
There are five power supply pins tha t are used by the
PCI input/ou tput buffer drivers. In a sys tem with +5 V
signaling environment, all VDD_PCI pins must be connected to a +5 V supply. In a system with +3.3 V signaling environment, all VDD_PCI pins must be connected
to a +3.3 V supply.
VDD
Digital Power (4 Pins) Power
There are four power supply pins that are used by the
internal digital circuitry. All VDD pins must be connected to a +5 V supply.
VSS
Digital Ground (6 Pins) Power
There are six ground pins that are used by the internal
digital circuitry.
28Am79C971
BASIC FUNCTIONS
System Bus Interface
The Am79C971 controller is designed to operate as a
bus master during nor mal operations. Some slave I/O
accesses to t he Am79C971 controller are require d in
normal operations as well. Initialization of the
Am79C971 controller is achieved through a combination of PCI Configuration Space accesses, bus slave
accesses, bus master acces ses, and an op tional rea d
of a serial EEPROM that is performed by the
Am79C971 controller. The EEPROM read o peration is
performed through the 93C46 EEPROM interface. The
ISO 8802-3 (IEEE/A NSI 802.3) Ethernet A ddres s may
reside within the serial EEPROM. Some Am79C971
controller configuration registers may also be programmed by the EEPROM read operation.
The Address PROM, on-chip bo ard-configuration registers, and the Ether net contr oller register s occupy 32
bytes of address space. I/O an d memor y mapped I/O
accesses are supported. Base Address registers in the
PCI configuration sp ace allow locating the address
space on a wide variety of starting addresses.
For diskless stations, the Am79C971 controller supports a ROM or Flash-based (both referred to as the
Expansion ROM throughout this specification) boot device of up to 1 Mbyte in size. The host can map the boot
device to any memory address that aligns to a 1-Mbyte
boundary by modifyi ng the Expans ion ROM Base Address register in the PCI configuration space.
Software Interface
The software interface to the Am79C971 controller is
divided into three parts. One part is the PCI configuration registers used to identify the Am79C971 controller
and to setup the configuration of the device. The setup
information includes the I/O or memory mapped I/O
base address, mappin g of the Expansion ROM, an d
the routing of the Am79C971 controller interrupt cha nnel. This allows for a jumperless implementation.
The second por tion of the software interface is the d irect access to the I/O resources of the Am79C971 controller. The Am79C971 controller occup ies 32 bytes of
address space that must begin on a 32-byte block
boundary. The address space can be mapped into I/O
or memory space (memory mapped I/O). The I/O Base
Address Register i n th e P C I Configuration Space controls the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O
Base Address R egister controls the s tart addr ess of
the address space if it is mapped to memor y space.
The 32-byte address spac e is used by the so ftware to
program the Am79C971 control ler operating mode, to
enable and disable various features, to monitor operat-
ing status, and to request particular functions to be executed by the Am79C971 controller.
The third por tion of th e software interface is the d escriptor and buffer areas that are shared between the
software and the Am79C971 cont roller durin g normal
network oper ations. The desc riptor area b oundaries
are set by the software and do not chan ge dur ing normal network operations. There is one descriptor area
for receive activity and there is a separate area for
transmit activity. The descriptor space contains relocatable pointers to the networ k frame d ata, and it is u sed
to transfer frame status from the Am79C971 controll er
to the software. The buffer areas are locations that hold
frame data for transmission or that acce pt frame data
that has been received.
Network Interfaces
The Am79C971 controller can be connected to an
IEEE 802.3 or propri etar y networ k via one o f four network interfaces. The Media Independent Interface (MII)
provides an IEEE 802.3-complian t nibble-wide interface to an external 100- and/or 10 -Mbps transceiver
device. The Attachment Unit Interface (AUI) provides
an ISO 8802-3 (IEE E/ANSI 802.3) defi ned differential
interface. On-board MAU and or off-board MAU connection with or without a n AUI cable is supported. The
10BASE-T interface provides a twisted-pair Ethernet
port , which is ISO 8802-3 (IE EE/ANSI 802 .3)-compliant, and contains the auto-negotiation capability, which
is IEEE 802.3u-compliant. The General Purpose Serial
Interface (GPSI) allows bypassing the Manchester
Encoder/Decoder (MENDEC) and is functionally equivalent to the GPSI found on the LANCE.
While in auto-selection mode, the interface in use is determined by the Network P ort Manager . If the quiescent
state of the MII MDIO pin is HIGH, the MII is activated.
If the MII MDIO pin is LOW, the Am79C971 device
checks the link status on the 10BASE-T port. If the
10BASE-T link status is good, the 10BASE-T port is selected. If there is no active link status, then the device
assumes an AUI connec tion. The 10B ASE-T por t will
continue to monitor the link status while th e AUI is active. The software driver can override th is automatic
configuration at anytime by disabling the auto-selection
and forcing a network port to be attached to the internal
MAC. The GPSI port can onl y be enabled by disa bling
the auto-selection and manually selecting the GPSI as
the network port.
The Am79C971 controller suppor ts half-duplex and
full-duplex operation on all four network interfaces (i.e.,
AUI, 10BASE-T, GPSI, and MII).
Am79C97129
DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Sta tus
Registers (CSR), the Bu s Configuration Registers
(BCR), the Ad dress PROM (APROM) lo cations, and
the Expansion ROM. Table 2 shows the response of
the Am79C971 controller to each of the PCI commands
in slave mode.
Table 2. Slave Commands
C[3:0]CommandUse
0000
0001Special CycleNot used
0010I/O Read
0011I/O Write
0100Reserved
0101Reserved
0110Memory Read
0111Memo ry Write
1000Reserved
1001Reserved
1010
1011
1100
1101
1110
1111
Interrupt
Acknowledge
Configuration
Read
Configuration
Write
Memory Read
Multiple
Dual Addres s
Cycle
Memory Read
Line
Memory Write
Invalidate
Not used
Read of CSR, BCR, APROM,
and Reset registers
Write to CSR, BCR, and
APROM
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers
Read of the Expansion Bus
Memory mapped I/O write of
CSR, BCR, and APROM
Read of the Configuration
Space
Write to the Configuration
Space
Aliased to Memory Read
Not used
Aliased to Memory Read
Aliased to Memory Write
Slave Configuration Transfers
The host can access the Am79C971 PCI configuration
space with a configuration read or write command. The
Am79C971 controller will assert DEVSEL
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
during the
select the DWord location in the configuration space.
The Am79C971 controller ignores AD[10:8], because it
is a single function device. AD[31:11] are don’t care.
AD31
AD11
Don’t careDon’t care
AD10
AD8
AD7
AD2
DWord
index
AD1AD0
00
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, a nd 32-bit transfers are supported . DEVSEL
cles after the host has asserted FRAME
is asserted two clock cy-
. All
configuration cycles are of fixed length. The
Am79C971 controll er will asser t TRDY
on the third
clock of the data phase.
The Am79C971 controller does not support burst trans-
fers for access to configurati on space. When th e host
keeps FRAME
asserted for a second data phase, the
Am79C971 controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic r ead of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C971 control ler will ter minate the access on the
PCI bus with a disconnect/retry response.
The Am79C971 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardw ired to 1. The Am79C97 1 controller
is capable of detecting a configuration cycle even when
its address phas e immediate ly follows the data phas e
of a transaction to a different target without a ny idle
state in-between. There will be no contention on the
DEVSEL
Am79C971 controll er asser ts DEV SEL
clock after FRAME
, TRDY, and STOP signals, since the
on the second
is asserted (medium timing).
Slave I/O Transfers
After the Am79C971 co ntroller is c onfigured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monito r ing the PCI bus for
access to its CSR, BCR, or APROM locati ons. If configured for regular I/O mode, the Am79C971 contr oller
will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
The Am79C971 controller asserts DEVSEL
an address mat ch and the access is an I/O cycle. If
configured for memory mapped I/O mode, the
Am79C971 controller wil l look for an address that falls
within its 32 bytes of me mory address spa ce (star ting
from the memory mapped I/O base address). The
Am79C971 controll er asser ts DEVSEL
address match and the access is a memory cycle.
DEVSEL
asserted FRAME
is asserted two clock cycles after the host has
. See Figure 1 and Figure 2.
if it detects
if it detects an
30Am79C971
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