AMD Advanced Micro Devices AM79C971VCW, AM79C971KCW Datasheet

Am79C971

PCnet™-FAST
Single-Chip Full-Duplex 10/100 Mbps Ethernet Contr oller for PCI Local Bus

DISTINCTIVE CHARACTERISTICS

■ Single-chip Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) local
bus

— 32-bit glueless PCI host interface
— Supports PCI clock frequency fr om DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

from 15 MHz to 33 MHz

— High performance bus mastering

architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization

— PCI specification revision 2.1 compliant
— Supports PCI Subsystem/Subvendor ID/

Vendor ID pr ogramming through the
EEPROM interface

— Supports both PCI 5.0-V and 3.3-V signaling

environments

— Plug and Play compatible
— Supports an unlimited PCI burst length
— Big endian and little endian byte alignments

supported

■ Integrated 10BASE-T and 10BASE-2/5 (AUI)

Physical Layer Interface
— Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3

and Blue Book Ethernet-compliant solution

— Automatic Twisted-Pair receive polarity

detection and correction

— Internal 10BASE-T transceiver with Smart

Squelch to Twisted-Pair medium

— IEEE 802.3-compliant auto-negotiable

10BASE-T interface

■ Supports General Purpose Serial Interface

(GPSI)

■ Media Independent Interface (MII) for

connecting external 10- or 100-Megabit per
second (Mbps) transceivers

— IEEE 802.3-compliant MII
— Intelligent Auto-Poll™ external PHY status

monitor and interrupt

— Includes intelligent on-chip Network Port

Manager that provides auto-port selection
between MII, on-chip 10BASE-T port, and A UI
without software support

— Supports both auto-negotiable and non

auto-negotiable external PHYs

— Supports 10BASE-T, 100BASE-TX/FX,

100BASE-T4, and 100BASE-T2 IEEE 802.3­compliant MII PHYs at full- or half-duplex

■ Internal/external loopback capabilities on all

ports

■ Supports patented External Address Detection

Interface (EADI)
— Receive frame tagging support for inter-

networking applications

■ Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards

■ Full-duplex operation supported in AUI,

10BASE-T, MII, and GPSI ports with
independent Transmit (TX) and Receive (RX)
channels

■ Flexible buffer architecture

— Large independent internal TX and RX FIFOs
— SRAM-based FIFO buffer extension

supporting up to 128 kilobytes (Kbytes)

— 1/2 Gigabit per second (Gbps) internal data

bandwidth

— Programmable FIFO watermarks fo r both TX

and RX operations

— RX frame queuing for high latency PCI bus

host operation

— Programmable allocation of buffer space

between RX and TX queues

■ EEPROM interface supports jumperless design

and provides through-chip programming
— Supports full programmability of half-/full-

duplex operation f or external 100 Mbps PHYs
through EEPR OM mapping

■ Extensive LED status support

Publication# 20550 Rev: E Amendment: /0
Issue Date: May 2000

■ Supports up to 1 Megabyte (Mbyte) optional

Boot PROM and Flash for diskless node
application

■ Look-Ahead Packet Processing (LAPP) data

handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame

■ Includes Programma ble Inter Packet Gap (IPG)

to address less network aggressive MAC
controllers

■ Offers the Modified Back-Off algorithm to

address the Ethernet Capture Effect

■ IEEE 1149.1-compliant JTAG Boundary Scan

test access port interface and NAND tree test

GENERAL DESCRIPTION

The Am79C971 controller is a single-chip 32-bit full-du­plex, 10/100-Megabit per second (Mbps) highly­integrated Etherne t system solution, designed to
address high-perfor mance syst em applicat ion require­ments. It is a flexible bus mastering dev ice that can be
used in any application, including network-ready PCs
and bridge/router designs. The bus master architecture
provides high data throughput in the system and low
CPU and system bus utiliza tion. The Am79C971 co n­troller is fabricated with AMD’s advanced low-power
Complementary Metal Oxide Semiconductor (CMOS)
process to provide l ow operating and stand by current
for power sensitive applications.

The Am79C971 controller is a complete Ethernet node
integrated into a sin gle VLSI device. It contain s a bus
interface unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)­compliant Media Access Controller (MAC), a large
Transmit FIFO and a large Receive FIFO, SRAM­based FIFO extension with support for up to 128K
bytes of external frame buffering, an IEEE 802.3u-com­pliant MII, an IEEE 802.3-compliant Twisted-P air T r ans­ceiver Media Attachment Unit (10BASE-T MAU), and
an IEEE 802.3-compliant Attachment Unit Interface
(AUI). Both proprietary full-duplex and IEEE 802.3
compliant half-duplex operation are supported on the
MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10­Mbps operation is supported through the MII, AUI, and
10BASE-T MAU interfaces, and 100 Mbps operation is
supported th rough the MII. The 10BASE-T MAU inter­face includes an IEEE 802.3-compliant auto-negotia­tion implementation , whic h wi ll auto mati ca lly ne got iate
between half- and full-duplex with another IEEE 802.3­compliant auto-negotiation 10BASE-T device.

The Am79C971 controller is register compatible with
the LANCE (Am7990) E thernet controller, the C-

mode for board-level production connectivity
test

■ Implements low-power management for critical

battery powered application and green PCs
— Includes two power-saving sleep modes

(sleep and snooze)

— Integrated Magic Packet™ technology

support for remote power of networked PCs

■ Software compatible with AMD PCnet Family

and LANCE/C-LANCE register and descriptor
architecture

■ Compatible with the existing PCnet Family

driver/diagnostic software

■ Available in 160-pin TQFP and 176-pin TQFP

packages

LANCE (Am79C90) Ether net controlle r, and all Ether­net controllers in the PCnet Family except ILACC
(Am79C900), including the PCnet-ISA controller
(Am79C960),PCnet-ISA+ controller (Am79C961) ,
PCnet-ISA II con troller (Am79C9 61A), PCnet- 32 con­troller (Am79C965), PCnet-PCI controller
(Am79C970), and PCnet-PCI II controller
(Am79C970A). The B uffer Management Unit supp orts
the LANCE and PCnet descriptor software models.

The 32-bit multiplexed bus interface unit provides a
direct interface to the PCI local bus, simplifying the
design of an Ethernet node in a PC system. The
Am79C971 controller provides the complete interface
to an Expansion ROM or Flash device allowing add-on
card designs with only a singl e load per PCI bus inter­face pin. With its built-in suppor t for both little and bi g
endian byte alignment, this controller also addresses
non-PC applications. The Am79C971 controller’s ad­vanced CMOS design allows the bus interface to be
connected to eithe r a +5-V or a +3.3-V s ignalin g envi­ronment. A compliant IEEE 1149.1 JTAG test interface
for board-level testing is also provided, as well as a
NAND tree test structure for those systems that cannot
support the JTAG interface.

The Am79C971 controll er suppor ts au to-configuratio n
in the PCI configu ration space. Additional Am79C971
controller configuration parameters, including the
unique IEEE physical address, can be read from an ex­ternal non-volatile memory (EEPROM) immediately fol­lowing system reset.

The integrated Manchester encoder/decoder (MEN­DEC) eliminates the need for an external Serial Inter­face Adapter (SIA) in the system. The built-in GPSI
allows the MENDEC to be bypassed.

2 Am79C971

In addition, the device provides programmable on-chip
LED drivers for trans mit , re ce ive, collis ion, r ecei ve po­larity, link integrity, activity, link active, address match,
full-duplex, MII select, 100 Mbps, or jabber status. The
Am79C971 controller also provides an EADI to allow
external hardware address filtering in internetworking
applications and a receive frame tagging feature.

For power sensitive applications where low standby
current is desired, the device incorporates two sleep
functions to reduce overall system power consumption,
excellent for notebooks and green PCs. In conjunctio n
with these low power modes, the PCnet-FAST control­ler also has integrated functions to suppor t Magic
Packet technology, an inexpensive technology that al­lows remote wake up of networked PCs.

The controller has the capability to automatically select
either the MII, AUI, or Twisted-Pair transceiver. Only
one interface is active at any one time. Any of the n et­work interfaces can be programmed to operate in either
half-duplex or full-duplex mode (AUI full-duplex only
supports the 10BASE-F standard).

The dual T ransmit and Receive FIFOs optimize system
overhead, providing sufficient latency tolerance at 10
Mbps and for 100-Mbps sys tems where low laten cies

can be guaranteed during frame transmission and
reception.

In highly loaded 10-M bps sys tems, suc h as se r vers or
when using the controll er in a 100-Mbp s environment,
the additional frame buffering capabili ty provided by a
16-bit wide SRAM interface provides high performance
and high latency tolerance on the system bus and net­work.

The Am79C971 controller can use up to 128 Kbytes of
SRAM as an extension of its dual Transmit and Receive
FIFOs. When no SRAM is used, the Am7 9C971 con-

troller’s FIFOs are programmed to bypass the SRAM
interface.

IMPORT ANT NOTE: A “No SRAM configuration” is only
valid for 10Mb mode. In 100Mb mode, SRAM is man­datory and must always be used.

ISO/IEC 8802-3 and IEEE 802.3 will be used inter­changeably when referring to half-duplex 10 Mbps net­works. IEEE 802.3 or IE EE 802.3u will be used
interchangeably only when referring to half-duplex 100­Mbps Ethernet networks, since the IEEE standard is
not ISO approved yet. Full-duplex is a proprietary stan­dard and is not approved by IEEE or ISO.

Am79C971 3

ORDERING INFORMATION
Standard Products

AMD standard produc ts are av ailable in sev eral pac kages and operating r anges. T he order number (Valid Combination) is f ormed
by a combination of the elements below.

Am79C971

K\V

C

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0° C to +70° C)

PACKAGE TYPE

K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL176)

SPEED OPTION

Not applicable

DEVICE NUMBER/DESCRIPTION

Am79C971
Single-Chip Full-Duplex 10/100 Mbps Ethernet
Controller for PCI Local Bus

Valid Combinations

Am79C971

KC\W,

VC\W

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

4 Am79C971

BLOCK DIAGRAM

CLK
RST

AD[31:00]

C/BE[3:0]

PAR

FRAME

TRDY

IRDY

STOP

IDSEL

DEVSEL

REQ

GNT
PERR
SERR

INTA

SLEEP

PCI Bus
Interface

Unit

Buffer

Management

Unit

Expansion Bus Interface

Bus
Rcv

FIFO

Bus
Xmt

FIFO

FIFO

Control

MAC

Rcv

FIFO

MAC

Xmt

FIFO

Network

Port

Manager

Auto

Negotiation

EBUA_EBA[7:0]
EBDA[15:8]
EBD[7:0]
EROMCS
ERAMCS
AS_EBOE
EBWE
EBCLK

802.3
MAC
Core

Manchester

Encoder/

Decoder

(PLS) &

AUI Port

10BASE-T

MAU

GPSI

Port

MII

Port

EADI

Port

TXEN
TXCLK
TXDAT
RXEN
RXCLK
RXDAT
CLSN
TX_E
TXD[3:0]
TX_EN
TX_CLK
COL
RXD[3:0]
RX_ER
RX_CLK
RX_DV
CRS
MDC
MDIO

SRDCLK
SRD
SF/BD
EAR
RXFRTGD/MIIRXFRTGD
RXFRTGE/MIIRXFRTGE

XTAL1
XTAL2
DO+/­DI+/­CI+/-

TXD+/­TXP+/­RXD+/-

TCK

TMS

TDI

TDO

JTAG

Port

Control

93C46

EEPROM

Interface

LED

Control

EECS
EESK
EEDI
EEDO

LED0
LED1
LED2
LED3

20550D-1

Am79C971 5

TABLE OF CONTENTS

AM79C971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

CONNECTION DIAGRAM (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

CONNECTION DIAGRAM (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

PIN DESIGNATIONS (PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

PIN DESIGNATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PIN DESIGNATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Listed By Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Listed By Driver Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

AD[31:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

C/BE[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DEVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

GNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IDSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

INTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

IRDY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

PERR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LED0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

LED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

LED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EECS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EEDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EEDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EESK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EBUA_EBA[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

EBDA[15:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EBD[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EROMCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

ERAMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

AS_EBOE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EBWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

EBCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6 Am79C971

TX_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TXD[3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TX_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TX_ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

COL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

RX_CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

RXD[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

RX_DV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

RX_ER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

MDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CI

DI±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DO±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10BASE-T Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

RXD

TXD±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

TXP±. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5

CLSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

RXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RXDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RXEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

TXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

TXDAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

TXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

SFBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SRDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RXFRTGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RXFRTGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

MIIRXFRTGD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

MIIRXFRTGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AV DDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AV SSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VDD_PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VSS_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VDDB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VSSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VDD_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Am79C971 7

Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Receive Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Manchester Encoder/Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Twisted-Pair Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5

Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

External Address Detection Interface (EADI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Power Savings Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

The contents of the Device ID register is the same as the contents of CSR88. . . . . . . . . . . . . .100

NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

RAP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

REGISTER PROGRAMMING SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Am79C971 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

DC CHARACTERISTICS OV ER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE

SPECIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

SWITCHING CHARACTERISTICS: BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

SWITCHING CHARACTERISTICS: ATTACHMENT UNIT INTERFACE. . . . . . . . . . . . . . . . . . . . . .207

SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . .208

SWITCHING CHARACTERISTICS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . .209

SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . .210

KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

SWITCHING WAVEFORMS: EXPANSION BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

SWITCHING WAVEFORMS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

SWITCHING WAVEFORMS: ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . .221

SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .224

8 Am79C971

SWITCHING WAVEFORMS: GENERAL-PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . .226

SWITCHING WAVEFORMS: EXTERNAL ADDRESS DETECTION INTERFACE. . . . . . . . . . . . . .227

SWITCHING WAVEFORMS: RECEIVE FRAME TAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

PQR160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

PQL176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

AM79C971 COMPATIBLE MEDIA INTERFACE MODULES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

RECOMMENDATION FOR POWER AND GROUND DECOUPLING. . . . . . . . . . . . . . . . . . . . . . . .B-1

ALTERNATIVE METHOD FOR INITIALIZATION* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-1

LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

AUTO-NEGOTIATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E-1

AM79C971A PCNET-FAST 10/100 MBPS PCI ETHERNET CONTROLLER REV A.6 ERRATA . . F-1

Am79C971 9

RELATED AMD PRODUCTS

Part No. Description

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79865 100 Mbps Physical Data Transmitter (PDT)
An79866A 100 Mbps Physical Data Receiver (PDR)
Am79C870 Quad 100BASE-X Transceiver
Am79C871 Quad 100BASE-X Repeater Transceiver
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug n' Play support)
Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft® Plug n' Play support)
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses)
Am79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus
Am79C981 Integrated Multiport R epeater Plus™ (IMR+™)
Am79C987 Hardware Implemented Management Information Base™ (HIMIB™)

10 Am79C971

CONNECTION DIAGRAM (PQR160)

D

IDSEL

VDD
AD23
AD22

VSS
AD21
AD20

VDD_PCI

AD19
AD18

VSSB

AD17
AD16

C/BE2

FRAME

IRDY

TRDY

DEVSEL

STOP
VSSB

PERR

SERR

VDD_PCI

PAR

C/BE1

AD15
AD14
AD13
AD12

VSSB

AD11
AD10

VDD

AD9

AD8

VSS

C/BE0

AD7

AD6

VSSB

AD27

AD26

VDD_PCI

AD25

AD24

C/BE3

VSSB

160

159

158

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

157

414243444546474849505152535455565758596061626364656667687071727374757677787980

156

155

154

AD29

AD28

153

152

AD30

VDD

151

150

AD31

CLK

VSSB

REQ

GNT

149

148

147

146

145

PCnet™-

Am79C971 KC/W

Am79C971

VSS

144

RST

143

INTA

142

TDI

VDD_PCI

141

140

FAST

TDO

TMS

139

138

TCK

137

VSSB

EECS

136

135

VDDB

VDD_PLL

LED2/SRDCLK/MIIRXFRTGE

EESK/LED1/SFBD

EEDI/LED0

EEDO/LED3/SRD/MIIRXFRTG

CI+

CI-

DI+

134

133

131

130

129

128

127

132

69

126

AVDDB

DI-

125

124

DO+

DO-

123

122

AVSSB

121

120
119
118
117
116
115
114
113
112

111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

XTAL2
VSS_PLL
XTAL1
AVDDB
TXD+
TXP+
TXD­TXP­AVDDB
RXD+
RXD­VSS
MDIO
MDC
SLEEP/EAR
RXD3
RXD2
RXD1
RXD0/RXFRTGD
VDDB
RX_DV/RXFRTGE
RX_CLK/RXCLK
RX_ER/RXDAT
VSSB
TX_ER
TX_CLK/TXCLK
TX_EN/TXEN
VDDB
TXD0/TXDAT
TXD1
TXD2
TXD3
COL/CLSN
CRS/RXEN
VSSB
EBD0
EBD1
EBD2
EBD3
EBD4

AD5

AD4

AD3

Pin 1 is marked for orientation.

AD1

AD2

VDD_PCI

AD0

VSSB

EBWE

ERAMCS

AS_EBOE

EBROMCS

2055A-2

VSS

EBCLK

EBUA_EBA0

EBUA_EBA1

VSSB

VDDB

EBUA_EBA2

EBUA_EBA3

EBUA_EBA4

VDDB

EBDA8

EBUA_EBA5

EBUA_EBA6

EBUA_EBA7

EBDA9

EBDA10

EBDA11

VSSB

EBDA12

VDD

EBDA13

EBDA14

EBDA15

EBD6

EBD7

EBD5

VSSB

VSS

Am79C971 11

20550D-2

CONNECTION DIAGRAM (PQL176)

NCNCAD24

C/BE3

VSSB

AD25

VDD_PCI

AD26

AD27

AD28

AD29

AD30

VDD

AD31

176

175

174

173

172

171

170

169

168

167

166

165

164

NC
NC

IDSEL

VDD
AD23
AD22

VSS
AD21
AD20

VDD_PCI

AD19
AD18

VSSB

AD17
AD16

C/BE2

FRAME

IRDY

TRDY

DEVSEL

STOP

VSSB
PERR
SERR

VDD_PCI

PAR

C/BE1

AD15
AD14
AD13
AD12

VSSB

AD11
AD10

VDD

AD9
AD8

VSS

C/BE0

AD7
AD6

VSSB

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

163

REQ

GNT

VSSB

CLK

VSS

RST

162

161

160

159

158

157

PCnetª-

Am79C971 VC/W

Am79C971

INTA

VDD_PCI

156

155

TDI

154

TDO

TMS

153

152

FAST

VC/W

TCK

EECS

VSSB

EESK/LED1/SFBD

LED2/SRDCLK/MIIRXFRTGE

EEDI/LED0

151

150

149

148

147

146

EEDO/LED3/SRD/MIIRXFRTGD

VDDB

VDD_PLL

CI+

CI-

DI+

DI-

AVDDB

DO+

DO-

AVSSBNCNC

145

144

143

142

141

140

139

138

137

136

135

134

133

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

NC
NC
XTAL2
VSS_PLL
XTAL1
AVDDB
TXD+
TXP+
TXD­TXP­AVDDB
RXD+
RXD­VSS
MDIO
MDC
SLEEP/EAR
RXD3
RXD2
RXD1
RXD0/RXFRTGD
VDDB
RX_DV/RXFRTGE
RX_CLK/RXCLK
RX_ER/RXDAT
VSSB
TX_ER
TX_CLTXCLK
TX_EN/TXEN
VDDB
TXD0/TXDAT
TXD1
TXD2/RXEN
TXD3

99

COL/CLSN

98

CRS/RXEN

97

VSSB

96

EBD0

95

EBD1

94

EBD2

93

EBD3

92

EBD4

91

NC

90

NC

89

88

NC

NC

AD5

AD4

AD3

AD2

AD1

AD0

VDD_PCI

VSSB

ERAMCS

EBWE

AS_EBOE

EBROMCS

VSS

EBCLK

EBUA_EBA0

EBUA_EBA1

EBUA_EBA2

EBUA_EBA3

VSSB

VDDB

EBUA_EBA4

EBUA_EBA5

EBUA_EBA6

EBUA_EBA7

Pin 1 is marked for orientation.

12 Am79C971

VDDB

EBDA8

EBDA9

EBDA10

VSSB

EBDA11

EBDA12

EBDA13

VDD

EBDA14

EBDA15

EBD7

EBD6

VSSB

EBD5

VSS

NC

NC

20550D-3

PIN DESIGNATIONS (PQR16 0)
Listed By Pin Number

Pin

Pin

No.

Name

1 IDSEL 41 AD5 81 EBD4 121 AVSSB
2 VDD 42 AD4 82 EBD3 122 DO­3 AD23 43 AD3 83 EBD2 123 DO+
4 AD22 44 AD2 84 EBD1 124 AVDDB
5 VSS 45 VDD_PCI 85 EBD0 125 DI­6 AD21 46 AD1 86 VSSB 126 DI+
7 AD20 47 AD0 87 CRS/RXEN 127 CI­8 VDD_PCI 48 VSSB 88 COL/CLSN 128 CI+
9 AD19 49 ERAMCS 89 TXD3 129 VDD_PLL
10 AD18 50 EROMCS 90 TXD2 130 VDDB

11 VSSB 51 EBWE 91 TXD1 131
12 AD17 52 AS_EBOE 92 TXD0/TXDAT 132 EED1/LED0
13 AD16 53 EBCLK 93 VDDB 133
14 C/BE2 54 VSS 94 TX_EN/TXEN 134 EESK/LED1/SFBD

15 FRAME 55 EBUA_EBA0 95 TX_CLK/TXCLK 135 VSSB
16 IRDY 56 EBUA_EBA1 96 TX_ER 136 EECS
17 TRDY 57 EBUA_EBA2 97 VSSB 137 TCK
18 DEVSEL 58 EBUA_EBA3 98 RX_ER/RXDAT 138 TMS
19 STOP 59 VSSB 99 RX_CLK/RXCLK 139 TDO
20 VSSB 60 EBUA_EBA4 100 RX_DV/RXFRTGE 140 TDI
21 PERR 61 VDDB 101 VDDB 141 VDD_PCI
22 SERR 62 EBUA_EBA5 102 RXD0/RXFRTGD 142 INTA
23 VDD_PCI 63 EBUA_EBA6 103 RXD1 143 RST
24 PAR 64 EBUA_EBA7 104 RXD2 144 VSS
25 C/BE1 65 VDDB 105 RXD3 145 CLK
26 AD15 66 EBDA8 106 SLEEP/EAR 146 VSSB
27 AD14 67 EBDA9 107 MDC 147 GNT
28 AD13 68 EBDA10 108 MDIO 148 REQ
29 AD12 69 EBDA11 109 VSS 149 AD31
30 VSSB 70 VSSB 110 RXD- 150 VDD
31 AD11 71 EBDA12 111 RXD+ 151 AD30
32 AD10 72 EBDA13 112 AVDDB 152 AD29
33 VDD 73 VDD 113 TXP- 153 AD28
34 AD9 74 EBDA14 114 TXD- 154 AD27
35 AD8 75 EBDA15 115 TXP+ 155 AD26
36 VSS 76 EBD7 116 TXD+ 156 VDD_PCI
37 C/BE0 77 EBD6 117 AVDDB 157 AD25
38 AD7 78 VSSB 118 XTAL1 158 VSSB
39 AD6 79 EBD5 119 VSS_PLL 159 C/BE3
40 VSSB 80 VSS 120 XTAL2 160 AD24

Pin
No.

Pin
Name

Pin
No.

Pin
Name

Pin No.

Pin
Name

EEDO/LED3/SRD/
MIIRXFRTGD

LED2/SRDCLK/
MIIRXFRTGE

Am79C971 13

PIN DESIGNATIONS (PQL176)
Listed By Pin Number

Pin

Pin

No.

Name

1 NC 45 NC 89 NC 133 NC
2 NC 46 NC 90 NC 134 NC
3 IDSEL 47 AD5 91 EBD4 135 AVSSB
4 VDD 48 AD4 92 EBD3 136 DO­5 AD23 49 AD3 93 EBD2 137 DO+
6 AD22 50 AD2 94 EBD1 138 AVDDB
7 VSS 51 VDD_PCI 95 EBD0 139 DI­8 AD21 52 AD1 96 VSSB 140 DI+
9 AD20 53 AD0 97 CRS/RXEN 141 CI­10 VDD_PCI 54 VSSB 98 COL/CLSN 142 CI+
11 AD19 55 ERAMCS 99 TXD3 143 VDD_PLL
12 AD18 56 EROMCS 100 TXD2/RXEN 144 VDDB

13 VSSB 57 EBWE 101 TXD1 145
14 AD17 58 AS_EBOE 102 TXD0/TXDAT 146 EED1/LED0
15 AD16 59 EBCLK 103 VDDB 147
16 C/BE2 60 VSS 104 TX_EN/TXEN 148 EESK/LED1/SFBD

17 FRAME 61 EBUA_EBA0 105 TX_CLK/TXCLK 149 VSSB
18 IRDY 62 EBUA_EBA1 106 TX_ER 150 EECS
19 TRDY 63 EBUA_EBA2 107 VSSB 151 TCK
20 DEVSEL 64 EBUA_EBA3 108 RX_ER/RXDAT 152 TMS
21 STOP 65 VSSB 109 RX_CLK/RXCLK 153 TDO
22 VSSB 66 EBUA_EBA4 110 RX_DV/RXFRTGE 154 TDI
23 PERR 67 VDDB 111 VDDB 155 VDD_PCI
24 SERR 68 EBUA_EBA5 112 RXD0/RXFRTGD 156 INTA
25 VDD_PCI 69 EBUA_EBA6 113 RXD1 157 RST
26 PAR 70 EBUA_EBA7 114 RXD2 158 VSS
27 C/BE1 71 VDDB 115 RXD3 159 CLK
28 AD15 72 EBDA8 116 SLEEP/EAR 160 VSSB
29 AD14 73 EBDA9 117 MDC 161 GNT
30 AD13 74 EBDA10 118 MDIO 162 REQ
31 AD12 75 EBDA11 119 VSS 163 AD31
32 VSSB 76 VSSB 120 RXD- 164 VDD
33 AD11 77 EBDA12 121 RXD+ 165 AD30
34 AD10 78 EBDA13 122 AVDDB 166 AD29
35 VDD 79 VDD 123 TXP- 167 AD28
36 AD9 80 EBDA14 124 TXD- 168 AD27
37 AD8 81 EBDA15 125 TXP+ 169 AD26
38 VSS 82 EBD7 126 TXD+ 170 VDD_PCI
39 C/BE0 83 EBD6 127 AVDDB 171 AD25
40 AD7 84 VSSB 128 XTAL1 172 VSSB
41 AD6 85 EBD5 129 VSS_PLL 173 C/BE3
42 VSSB 86 VSS 130 XTAL2 174 AD24
43 NC 87 NC 131 NC 175 NC
44 NC 88 NC 132 NC 176 NC

Pin
No.

Pin
Name

Pin
No.

Pin
Name

Pin No.

Pin
Name

EEDO/LED3/SRD/
MIIRXFRTGD

LED2/SRDCLK/
MIIRXFRTGE

14 Am79C971

PIN DESIGNATIONS (PQR160, PQL176)
Listed By Group

Pin Name Pin Function Type
PCI Bus Interface

AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I NA 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Fram e IO STS6 1
GNT Bus Grant I NA 1
IDSEL Initialization Device Select I NA 1
INTA Interrupt O OD6 1
IRDY Initiator Ready IO STS6 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request O TS3 1
RST Reset I NA 1
SERR System Error IO OD6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1

Board Interface

LED0 LED0 O LED 1
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I NA 1
XTAL1 Crystal Input I NA 1
XTAL2 Crystal Output O XTAL 1
EEPROM Interface
EECS Serial EEPROM Chip Select O O6 1
EEDI Serial EEPROM Data In O LED 1
EEDO Serial EEPROM Data Out I NA 1
EESK Serial EEPROM Clock IO LED 1

Expansion ROM Interface

AS_EBOE Address Strobe/Expansion Bus Output Enable O O6 1
EBCLK Expansion Bus Clock I NA 1
EBD[7:0] Expansion Bus Data [7:0] IO TS6 8
EBDA[15:8] Expansion Bus Data/Address [15:8] IO TS6 8

EBUA_EBA[7:0]
EBWE Expansion Bus Write Enable O O6 1

ERAMCS Expansion Bus RAM Chip Select O O6 1
EROMCS Expansion Bus ROM Chip Select O O6 1

Note:

1. Not including test features

Expansion Bus Upper Addres s /Expansion Bus Addres s
[7:0]

1

O O6 8

Driver No. of Pins

Am79C971 15

PIN DESIGNATIONS
Listed By Group

Pin Name Pin Function Type
Media Independent Interface (MII)

COL Collision I NA 1
CRS Carrier Sense I NA 1
MDC Management Data Clock O OMII2 1
MDIO Management Data I/O IO TSMII 1
RX_CLK Receive Clock I NA 1
RXD[3:0] Receive Data I NA 4
RX_DV Receive Data Valid I NA 1
RX_ER Receive Error I NA 1
TX_CLK Transmit Clock I NA 1
TXD[3:0] Transmit Data O OMII1 4
TX_EN Transmit Data Enable O OMII1 1
TX_ER Transmit Error O OMII1 1

Attachment Unit Interface (A UI)

CI± AUI Collis ion I NA 1
DI± AUI Data In I NA 1
DO± AUI Data Out O DO 1

10BASE-T Interface

RXD+/RXD- Receive Differential Pair I NA 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2

General Purpose Serial Interface (GPSI)

CLSN Collision IO NA 1
RXCLK Receive Clock I NA 1
RXDAT Receive Data I NA 1
RXEN Receive Enable I NA 1
TXCLK Transmit Clock I NA 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I NA 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data IO LED 1
SRDCLK Serial Receive Data Clock IO LED 1

RXFRTGD/MIIRXFRTGD

RXFRTGE/MIIRXFRTGE

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I NA 1
TDI Test Data In I NA 1
TDO Test Data Out O TS6 1
TMS Test Mode Sele ct I NA 1

Note:

1. Not including test features.

Receive Frame Tag Data/MII Receive Frame
Tag Data

Receive Frame T ag Enable/MII Receive Fr ame
Tag Enable

1

I NA 1

I NA 1

Driver No. of Pins

16 Am79C971

PIN DESIGNATIONS
Listed By Group

Pin Name Pin Function Type
Power Suppli es

AVDDB Analog I/O Buffer Power P NA 3
AVSSB Analog I/O Buffer Ground P NA 1
VDD_PLL Analog PLL Power P NA 1
VSS_PLL Analog PLL Ground P NA 1
VDD Digital Power P NA 4
VSS Digital Ground P NA 6
VDDB I/O Buffer Power P NA 5
VSSB I/O Buffer Ground P NA 13
VDD_PCI PCI I/O Buffer Power P NA 5

Note:

1. Not including test features.

1

Driver No. of Pins

Listed By Driver Type

The following table describes th e various type s of o ut­put drive rs used i n the Am79C9 71 contro ller . All I

values shown in the table apply to 5 V signaling.

I

OH

See the DC Characteristics section for the values ap-

OL

and

A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
DO, TDO, and TPO are differential output drivers. Their
characteristics and t he o ne of the XTAL output a re de­scribed in the DC Characteristics section.

plying to 3.3 V signaling.

Name Type IOL (mA) IOH (mA) Load (pF)

LED LED 12 -0.4 50
OMII1 Totem Pole 4 -4 50
OMII2 Totem Pole 4 -4 390
O6 Totem Pole 6 -0.4 50
OD6 Open Drain 6 NA 50
STS6 Sustained Tri-State 6 -2 50
TS3 Tri-State 3 -2 50
TS6 Tri-State 6 -2 50
TSMII Tri-State 4 -4 470

Am79C971 17

PIN DESCRIPTIONS
PCI Interfa ce
AD[31:0]

Address and Data Input/Output

Address and data ar e multi pl exed on the same bus in ­terface pins. During the fir st clock of a transaction,
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks, AD[31:0] contain data. Byte or­dering is littl e endian by default. AD[07:0] are define d
as the least significant byte (LSB) and AD[31:24] are
defined as the most significant byte (MSB). For FIFO
data transfers, the Am79C971 controller can be pro­grammed for big endian byte ordering. See CSR3, bit 2
(BSWP) for more details.

eration section for details. The Am79C971 controller
will support a clock frequency of 0 MHz after certain
precautions are taken to ensure data integrity. This
clock or a derivation i s not used to dr ive any network
functions.

When RST
testing.

is active, CLK is an inp ut for NAND tree

DEVSEL

Device Select Input/Output

The Am79C971 controller dr ives DEVSEL when it de­tects a transaction that selects the device as a target.
The device samples DEVSEL
claims a transaction that the Am79C971 controller has
initiated.

to detect if a target

During the address phase of the transaction, when the
Am79C971 controller is a bus master , AD[31:2] will ad­dress the active Double Word (DWord). The
Am79C971 controller alwa ys drives AD[1:0] to ’00’ dur-
ing the address phase indicating linear burst order.
When the Am79C971 controller is not a bus master, the
AD[31:0] lines are continuously monitored to determine
if an address match exists for slave transfers.

During the data phase of the transacti on, AD[31: 0] are
driven by the Am79C971 controller wh en performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the Am79C971 co ntroller when
performing bus master read and slave write operations.

When RST
testing.

is active, AD[31:0] are inputs for NAND tree

C/BE[3:0]

Bus Command and Byte Enables Input/Output

Bus command and byte enables are multiplexed on the
same bus interface pins. During the a ddress phase o f
the transaction, C /BE
During the data phase, C/BE
ables. The byte enables define which physical byte
lanes carry meaningful data. C/BE
(AD[07:0]) and C/BE
The function of the byte enables is ind ependen t of th e
byte ordering mode (BSWP, CSR3, bit 2).

When RST
tree testing.

is active, C/BE[3:0] are inputs for NAND

[3:0] define th e bus command.

[3:0] are used as byte en -

0 applies to byte 0

3 applies to byte 3 (AD[31:24 ]).

CLK

Clock Input

This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
are defined with resp ect to this edge. The A m79C971
controller normally operates over a frequency range of
10 to 33 MHz on the PCI bus due to networking de­mands. See the Frequency Demands for Networ k Op-

When RST
testing.

is activ e, DEVS EL is an inp ut f or NAND tr ee

FRAME

Cycle Frame Input/Output

FRAME is driven by the Am79 C971 controll er when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME
transaction is beginning. FRAME
data transfers continue. FRAME
the final data phase o f a transaction. When the
Am79C971 controller is in slave mode, it samples
FRAME
tion.

When RST is active, FRAME is an input f or NAND tree
testing.

to determ ine the ad dress phas e of a tran sac-

is asser ted to indica te a bus

is asserted while

is deasserted before

GNT

Bus Grant Input

This signal indicates that the access to the bus has
been granted to the Am79C971 controller.

The Am79C971 controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the Am79C971 controller,
the device will drive the AD[31:0], C/BE
lines.

When RST is active, GNT is an input for NAND tree
testing.

[3:0] and PAR

IDSEL

Initialization Device Select Input

This signal is used as a c hip sele ct for the Am79C97 1
controller duri ng configura tion read a nd write transac­tions.

When RST
testing.

1. Not including test features.

is active, IDSEL is an input for NAND tree

18 Am79C971

INTA

Interrupt Request Output

An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC­CINT, MPDTINT, MAPINT, MREINT, and STINT. Each
status flag has either a mask or an enable bit which al­lows for suppression of INTA
the flag meanings.

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

BABL Babble CSR3, bit 14 CSR0, bit 14
EXDINT

IDON
JAB Jabber CSR4, bit 0 CSR4, bit 1

MERR Memory Error CSR3, bit 11 CSR0, bit 11
MISS Missed Frame CSR3, bit 12 CSR0, bit 12

MFCO

MPINT

RCVCCO

RINT
SLPINT Sleep Interrupt CSR5, bit 8 CSR5, bit 9

SINT System Error CSR5, bit 10 CSR5, bit 11
TINT
TXSTRT Transmit Start CSR4, bit 2 CSR4, bit 3

UINT User Interrupt CSR4, bit 7 CSR4, bit 6

MCCIINT

MCCINT

MPDTINT

Excessive
Deferral

Initialization
Done

Missed Frame
Count Over­flow

Magic Packet
Interrupt

Receive
Collision Count
Overflow

Receive
Interrupt

Transmit
Interrupt

Internal MII
Management
Command
Complete
Interrupt

MII
Management
Command
Complete
Interrupt

MII PHY Detect
Transition
Interrupt

assertio n. Table 1 shows

CSR5, bit 6 CSR5, bit 7

CSR3, bit 8 CSR0, bit 8

CSR4, bit 8 CSR4, bit 9

CSR5, bit 3 CSR5, bit 4

CSR4, bit 4 CSR4, bit 5

CSR3, bit 10 CSR0, bit 10

CSR3, bit 9 CSR0, bit 9

CSR7, bit 2 CSR7, bit 3

CSR7, bit 4 CSR7, bit 5

CSR7, bit 0 CSR7, bit 1

Table 1. Interrupt Flags

Name Description Mask Bit Interrupt Bit

MAPINT

MREINT

STINT

By default INTA

MII Auto-Poll
Interrupt

MII
Management
Frame Read
Error Interrupt

Software Timer
Interrupt

CSR7, bit 6 CSR7, bit 7

CSR7, bit 8 CSR7, bit 9

CSR7, bit 10 CSR7, bit 11

is an open-drain output. For applica­tions that need a high-active edge-sensitive interrupt
signal, the INTA

pin can be configured f or this mode by

setting INTLEVEL (BCR2, bit 7) to 1.

When RST is active, INTA is the outp ut for NAND tree
testing.

IRDY

Initiator Ready Input/Output

IRDY indicates the ability of the initiator of the transac­tion to complete the current data phase. IRDY
in conjunct i on wi t h T RDY
both IRDY

and TRDY are asser ted simultaneously. A

. Wait states are inserted until

is used

data phase is completed on any clock when both IRDY
and TRDY are asserted.

When the Am79C971 c ontroll er is a bus mas ter, it as­serts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. Durin g all read dat a
phases, the device asserts IRDY

to indicate that it is

ready to accept the data.
When the Am79C971 controller is the target of a trans-

action, it checks IRDY

during all write data phases to
determine if valid data is presen t on AD[31:0]. During
all read data phases, the device checks IRDY

to deter-

mine if the initiator is ready to accept the data.

When RST is active, IRDY is an input for NAND tree
testing.

PAR

Parity Input/Output

Parity is even parity across AD[31:0] a nd C/BE[3:0].
When the Am79C971 controller is a bus master , it gen­erates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C971 controller operates in slave mode, it checks
parity during ev ery address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.

When RST
testing.

is active, PA R is an input for NAND tree

Am79C971 19

PERR

Parity Error Input/Output

During any slave write transaction and any master read
transaction, the Am79C971 contro ller asserts PE RR
when it detects a dat a pa rity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C971 control ler monit ors PERR
target reports a data parity error.

When RST is active, PERR is an in put for NAND tree
testing.

to see if the

REQ

Bus Request Input/Output

The Am79C971 controller asserts REQ pin as a signal
that it wishes to become a bus mas ter. REQ
high when the Am79C971 control ler does not request
the bus. During M a gi c Packet
not be driven.

When RST is active, REQ is an input for NAND tree
testing.

 mode, the REQ pin will

is driven

RST

Reset
Input

When RST
troller performs an internal system reset of the type
H_RESET (HARDWARE_RESET, see section on RE­SET). RST
riods. While in the H_RESET state, the Am79C971
controller will disable or deassert all outputs. RST
be asynchronous to clock when asser ted or deas­serted.

When RST

is asserte d low, then the Am79C971 con-

must be held for a minimum of 30 clock pe-

may

is active, NAND tree testing is enabled.

SERR

System Error Input/Output

During any slave transaction, the Am79C971 controller
asserts S ERR
and reporting of the error is enabled by setting PER­REN (PCI Command register, bit 6) and SERREN (PCI
Command register, bit 8) to 1.

By default SERR
nent test, it can be programmed to be an active-high
totem-pole output.

When RST
testing.

when it detects a n add re ss p ar i ty er r or,

is an open-drain out put. For compo-

is active, SERR is an input for NAND tree

STOP

Stop Input/Output

In slave mode, the Am79C971 controller drives the

signal to inform the bus master to stop the cur-

STOP
rent transaction. In bus mas ter mode, the Am79C97 1

controller checks STOP
to disconnect the current transaction.

When RST is active, STOP is an input for NAND tree
testing.

to determine if the target wants

TRDY

Target Ready Input/Output

TRDY indicates the ability of the target of the transa c­tion to complete the current data phase. Wait states are
inserted until both IRDY
taneously. A data phase is completed on any clock
when both IRDY

When the Am79C971 controller is a bus master, it
checks TRD Y during all read data phases to determine
if vali d data is present on AD[31: 0]. Duri ng all write data
phases, the device checks TRDY
target is ready to accept the data.

When the Am79C971 controller is the target of a trans­action, it asser ts TRDY
indicate that valid data is present on AD[31 :0]. Durin g
all write data phases, the device ass erts TRDY
cate that it is ready to accept the data.

When RST is active, TRDY is an input for NAND tree
testing.

and TRDY are asserted.

and TRDY are asserted simul-

to determine if th e

during all read data phases to

to indi-

Board Interface

Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12 first.

LED0

LED0 Output

This output is designed to directly drive an LED. By de­faul t, LED 0
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The LED0
pin polarity is programmable, but by default it is active
LOW. Whe n the LED0
active LOW, the output is an open d rain driver. When
the LED0
the output is a totem pole driver.

Note: The LED0 pin is multiplexed with the EEDI pin.

When RST
testing.

indicates an ac tive link connection on the

pin polarity is programmed to

pin polar ity is progra mmed to act ive HIGH,

is active, LED0 is an input for NAND tree

LED1

LED1 Output

This output is designed to directly drive an LED. By de­fault, LED1
This pin can also be programmed to indicate other net­work status (see BCR5). T he LED1
grammable, but by default, it is active LOW. When the
LED1
output is an open drain driver. When the LED1

indicates receive activity on the network.

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

20 Am79C971

larity is pr ogrammed to active HIGH, th e output is a
totem pole driver.

Note: The LED1 pin is multiplexed with the EESK and
SFBD pins.

The LED1
Detection to deter mine whe ther or not an EE PROM is
present at the Am79C971 controller interface. At the
last rising edge of CLK while RST
is sampled to determine the value of the EEDET bit i n
BCR19. It is important to maintain ad equate hold time
around the rising edge of the CLK at this time to ensure
a correctly sampled value. A sampled HIGH value
means that an EEPROM is present, and EEDET will be
set to 1. A sampled LOW value means that an EE­PROM is not present, and EEDET will be set to 0. See
the EEPROM Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead i n
order to resolve the EEDET setting.

When RST
testing.

WARNING: The input signal level of LED1 must b e
insured for correct EEPROM detection before the
deassertion of RST

pin is also used dur ing EEPROM Auto-

is active LOW , LED1

is active, LED1 is an input for NAND tree

.

LED2

LED2 Output

This output is designed to directly drive an LED. By de­fault, LED2
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default it is active
LOW. Whe n the LED2
active LOW, the output is an open drain driver. When
the LED2
the output is a totem pole driver.

indicates correct receive polarity on the

pin polarity is programmed to

pin polar ity is progra mmed to act ive HIGH,

LED while an EEPROM is used in the system, then
buffering is required between the LED3
LED circuit. If an LED c ircuit were directl y attached t o
this pin, it would crea te an I
not be met by the serial EEPROM attached to this pin.
If no EEPROM is inclu ded in the system design, then
the LED3
without buffering. For more details regarding LED con­nection, see the section on LED Support.

Note: The LED3
SRD, MIIRXFRTGD pins.

When RST
testing.

signal may be directly connected to an LED

pin is multiplexed with the EEDO,

is active, LED3 is an input for NAND tree

OL requirement that could

pin and the

SLEEP

Sleep Input

When SLEEP is asser ted, the Am79C9 71 controller
performs an internal system reset of the H_RESET
type and then proceeds into a power savings mode. All
Am79C971 controller outputs will be placed in their
normal reset condition. All Am79C971 controller inputs
will be ignored except for the SLEEP
tem must refrain from star ting th e network operations
of the Am79C971 controller for 0.5 se conds following
the deasser tion o f the SLEEP
ternal analog circuits to stabilize.

For effects with the Magic Packet™ modes, se e the
Magic Packet section.

Both CLK and XTAL1 inputs must have valid clock sig­nals present in order for the SLEEP
effect.

The SLEEP pin should not be asserted during power
supply ramp up. If it is desired that SLEEP
at power supply ramp up, then the system must delay
the assertion of SLEEP
completion of hardware reset.

until three clock cycles after the

pin itself . The sys-

pin in order to allow in-

command to take

be asserted

Note: The LED2 pin is multiplexed with the SRDCLK
pin and the MIIRXFRTGE pins.

When RST
testing.

is active, LED2 is an input for NAND tree

LED3

LED3 Output

This output is designed to directly drive an LED. By de­fault, LED3
This pin can also be programmed to indicate other net­work status (see BCR7). T he LED3
gramma ble, but by defaul t it is active LOW. When th e
LED3
output is an open d rain driver. When the LED3
larity is pr ogrammed to active HIGH, th e output is a
totem pole driver.

Special attention must be given to the external circuitry
attached to this pin. Whe n this pin is used to dri ve an

indicates tran smit activity on the network .

pin polarity is pro-

pin polarity is programmed to active LOW, the

pin po-

Am79C971 21

WARNING: The SLEEP pin must not be left uncon­nected. It should be tied to VDD if the power saving
mode is not used.

Note: The SLEEP

When RST
testing.

is active, SLEEP is an input for NAND tree

pin is multiplexed with the EAR pin.

XTAL1

Crystal Oscillator In Input

The internal clock generator uses a 20-MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the cr ystal frequency. XTAL1
may alternatively be driven using an external 20- MHz
CMOS level clock signal. Refer to the section on Exter-
nal Crystal Characte ristic s for more details. This clock
is always required whether or not the internal
10BASE-T/AUI ports are enabled. If the internal PHY is

not used, ±10% accuracy is sufficient for the clock
source.

Note: When the Am79C971 controller is in coma
mode, t here is an i nternal 2 2 k
ground. If an external source drives XTAL1, some
power consumption will be consumed driving this resis­tor. If XTAL1 is driven LOW at this time, power con­sumption will be minimized. In this case, XTAL1 must
remain active for at least 30 cycles after the as ser tion
of SLEEP

and deassertion of REQ.

Ω resistor fr om X TAL1 to

XTAL2

Crystal Oscillator Out Output

The internal clock generator uses a 20-MHz crystal that
is attached to the pins XT AL1 and XTAL2. The network
data rate is one-half of the cry stal frequenc y. If an ex­ternal clock source is used on XTAL1, then XTAL2
should be left unconnected.

EEPROM Interface
EECS

EEPROM Chip Select Output

This pin is designed to directly interface to a serial EE­PROM that uses the 93C46 EEPROM interface proto­col. EECS is connected to the EEPROM ’s chip select
pin. It is controll ed by either the Am 79C971 controll er
during command portions of a read of the entire EE­PROM, or indirectly by the host system by writing to
BCR19, bit 2.

When RST
testing.

is active, EECS is an input for NAND tree

EEDI

EEPROM Data In Output

This pin is designed to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro­tocol. EEDI is connecte d to the EEPROM’s data input
pin. It is controll ed by either the Am 79C971 controll er
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.

Note: The EEDI pin is multiplexed with the LED0
When RST

testing.

is active, EEDI is an input for NAND tree

pin.

EEDO

EEPROM Data Out Input

This pin is designed to di rectly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro­tocol. EEDO is connecte d to the EEPROM’s data out­put pin. It is controlled by either the Am79C971
controller during command portions of a read of the en­tire EEPROM, or indirectly by the host system by read­ing from BCR19, bit 0.

Note: The EEDO pin is multiplexed with the LED3,
MIIRXFRTGD, and SRD pins.

When RST
testing.

is active, EEDO is an input for NAND tree

EESK

EEPROM Serial clock Input/Output

This pin is designe d to directly interface to a serial
EEPROM that uses the 93C46 EEPROM interface pro­tocol. EESK is connected to the EEPROM’s clock pin.
It is controlled by either the Am79C971 controller di­rectly during a read of the entire EE PROM , or indire ctly
by the host system by writing to BCR19, bit 1.

Note: The EESK pin is multiplexed with the LED1
SFBD pins.

The EESK pin is also used during EEPROM Auto­Detection to deter mine whe ther or not an EEPROM is
present at the Am79C971 controller interface. At the
rising edge of the last CLK edge while RST
EESK is sampled to determine the value of the EEDET
bit in BCR19. A sampled HIGH value means that an
EEPROM is present, and EEDET will be set to 1. A
sampled LOW value means that an EEPROM is no t
present, and EEDET will be set to 0. See the EEPROM
Auto-Detection section for more details.

If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead to re­solve the EEDET setting.

When RST
testing.

WARNING: The input signal level of EESK must be
valid for correct EEPROM detection before the
deassertion of RST

is active, EESK is an inpu t for NAND tree

.

is asserted,

and

Expansion Bus Interface
EBUA_EBA[7:0]

Expansion Bus Upper Address/
Expansion Bus Address [7:0] Output

The EBUA_EBA[7:0] pins provide the least and most
significant bytes of address on the Expansion Bus. The
most significant addre ss byte (address bits [15:8] dur­ing SRAM accesses; ad dress bits [19:16] dur ing boot
device accesses) is valid on these pins at the beginning
of an SRAM or boot device access, at the rising edge
of AS_EBOE
externally in a D flip -flop. Durin g sub seque nt cy cles o f
an SRAM or boot device access, address bits [7:0] are
present on these pins.

All EBUA_EBA[7:0] outputs are forced to a constant
level to conserve power while no access on the Expan­sion Bus is being performed.

. This upper address byte must be sto re d

22 Am79C971

EBDA[15:8]

Expansion Bus Data/Address [15:8] Input/Output

When ERAMCS is asserted, EBDA[15:8] contain the
data bits [15:8] for SRAM accesses. When EROMCS
asserted low, EBDA[15:8] contain address bits [15:8]
for boot device accesses.

The EBDA[15:8] signals are driven to a constant level
to conserve power while no access on the Expansion
Bus is being performed.

is

EBD[7:0]

Expansion Bus Data [7:0] Input/Output

The EBD[7:0] pins provide data bits [7:0] for RAM/ROM
accesses. The EBD[7:0] signals are internally f orced to
a constant level to co ns erv e po wer while no ac cess on
the Expansion Bus is being performed.

EROMCS

Expansion ROM Chip Select Output

EROMCS serves as the chip select for the boot device.
It is asserted low during the data phases of boot device
accesses.

ERAMCS

Expansion RAM Chip Select Output

ERAMCS is asserted during SRAM read and write op­erations on the expansion bus.

AS_EBOE

Address Strobe/Expansion Bus
Output Enable Output

AS_EBOE
upper address bits on the EBUA_EBA[7:0] pins and as
the output enable for the Expansion Bus.

As an address strobe, a rising edge on AS_EBOE
supplied at the beginning of SRAM and boot device
accesses. This rising edge provides a clock edge for a
‘374 D-type edge-triggered flip-flop which must store
the upper address byte dur ing Expansion Bus ac­cesses for EPROM/Flash/SRAM.

AS_EBOE
and SRAM read operations on the expansion bus and
is deasser ted during boot device and SRAM wr ite
operations.

functions as the address strobe for the

is

is asserted active LOW during boot device

EBWE

Expansion Bus Write Enable Output

EBWE provides the wr ite enable for writ e accesse s to
the SRAM devices and/or Flash device.

EBCLK

Expansion Bus Clock Input

EBCLK may be used as the fundamental clock to drive
the Expansion Bus ac cess cycles. The a ctual inter nal

clock used to drive the Expansion Bus cycles depends
on the values of the EBCS and CLK_FAC settings in
BCR27. Refer to the SRAM Interface Bandwidth Re­quirements section for details on determining the re­quired EBCLK frequency. If a clock source other than
the EBCLK pin is programmed (BCR27, bi ts 5:3 ) to be
used to run the Expans ion Bus interface, this input
should be tied to VDD through a 4.7 k

EBCLK is not used to drive the bus interface, inter nal
buffer management unit, or the network functions.

Ω resistor.

Media Independent Interface
TX_CLK

Transmit Clock Input

TX_CLK is a conti nuous clock input th at provides the
timing reference for the transfer of the TX_EN,
TXD[3:0], an d TX_ER signal s out of the Am 79C971
device. TX_CLK must provide a nibble rate clock (25%
of the network data rate). Hence, an MII transceiver op­erating at 10 Mbps must provid e a TX_CL K freq uency
of 2.5 MHz and an MII transceiver operating at 100
Mbps must provide a TX_CLK frequency of 25 MHz.

Note: The TX_CLK pin is multiplexed with the TXCLK
pin.

When RST
testing.

If the MII port is not selecte d, the TX_CLK pin can b e
left floating.

is active, TX_CLK is an input for NAND tree

TXD[3:0]

Transmit Data Output

TXD[3:0] is the nibble-wide MII transmit data bus. Valid
data is generated on TXD[3:0] on every TX_CLK rising
edge while TX_EN is asserted. While TX_EN is de­asserted , TXD[3:0] values are dri ven to a 0. TXD[3:0]
transitions synchronous to TX_CLK rising edges.

Note: The TXD[0] pin is multiplexed with the TXDAT
pin.

When RST
testing.

If the MII port is not selected, the TXD[3:0] pins can be
left floating.

is activ e , TXD[3: 0] ar e input s f or NAN D tree

TX_EN

Transmit Enable Output

TX_EN indicates when the Am79C971 device is pre­senting valid transmit nibbles on the MII. While TX_EN
is asserted, the Am79C971 device generates TXD[3:0]
and TX_ER on TX_CLK rising edges. TX_EN is as­serted with the first nibble of preamble and remains as­serted throughout the duration of a packet until it is
deassert ed p rior to the first TX_CLK following the final

Am79C971 23

nibble of the frame. TX_EN transitions synchronous to
TX_CLK rising edges.

nal PHY switches t he RX_CLK an d TX_CLK, it must
provide glitch-free clock pulses.

Note: The TX_EN pin is multiplexed with the TXEN
pin.

When RST
testing.

If the MII port is not selected, the TX_EN pin can be left
floating.

is active, TX_EN is an input for NAND tree

TX_ER

Transmit Error Output

TX_ER is an output that, if asserted while TX_EN is as­serted , instruc ts the MII PHY device connecte d to the
Am79C971 device to transmit a code group error.
TX_ER is unused and is reserved for future use and will
always be driven to a logical zero.

When RST
testing.

If the MII port is not selected, the TX_ER pin can be left
floating.

is active, TX_ER is an input for NAND tree

COL

Collision Input

COL is an input that indicates that a collision has been
detected on the network medium.

Note: The RX_CLK pin is multiplexed with the RXCLK
pin.

When RST
testing.

If the MII por t is not se lected, the RX_CLK pi n can be
left floating.

is active, RX_CLK is an input for NAND tree

RXD[3:0]

Receive Data Input

RXD[3:0] is the nibble-wide MII receive data bus. Data
on RXD[3:0] is sampled on every rising edge of
RX_CLK while RX_DV is asserted. RXD[3:0] is ignored
while RX_DV is de-asserted.

When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Tagg ing is enabled (RXFRTG,
CSR7, bit 14) and the MII is not selected, the RXD[0]
pin becomes a data input pin for the Receive Frame
Tag (RXFRTGD). See the Receive Frame Tagging sec-
tion for details.

Note: The RXD[0] pin is multiplexed with the
RXFRTGD pin.

When RST
testing.

is activ e, RXD[3:0 ] are in puts f or NAN D tree

Note: The COL pin is multiplexed with the CLSN pin.
When RST

testing.

If the MII por t is not s elected, the CO L pin can be left
floating.

is active, COL is an input for NAND tree

CRS

Carrier Sense Input

CRS is an input that indicates that a non-idl e medium,
due either to transmit or receive activi ty, has been de­tected.

Note: The CRS pin is multiplexed with the RXEN pin.
When RST

testing.

If the MII port is not select ed, the CRS pin can be left
floating.

is active, CRS is an input for NAND tree

RX_CLK

Receive Clock Input

RX_CLK is a clock input that provides the timing refer­ence for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C971 device. RX_CLK
must provide a nibble rate cl ock (25% of the networ k
data rate). Hence, an MII transceiver operating at 10
Mbps must provide an RX_ CLK freq uen cy of 2.5 MHz
and an MII transceiver operating at 100 Mbps must pro­vide an RX_CLK frequency of 25 MHz. When the exter-

If the MII por t is not sel ected, th e RXS[3 :0] pin can b e
left floating.

RX_DV

Receive Data Valid Input

RX_DV is an input used to indicate tha t valid received
data is being presented o n the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am 79C971 de­vice on the MII, RX_DV must be asser ted prior t o the
RX_CLK rising edge, when th e first nibble of the Start
of Frame Delimiter is driven on RXD[3:0], and must re­main asserted until after the rising edge of RX_CLK,
when the last nibble of the CRC is driven on RXD[3:0].
RX_DV must then be deasserted pri or to th e RX_CLK
rising edge which follows this final nibble. RX_DV tran­sitions are synchronous to RX_CLK rising edges.

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII i s not selected, the RX_DV pin be­comes a data input enable pin for the Receive Frame
Tag (RXFRTGE). See the Receive Frame Tagging sec-
tion for details.

Note: The RX_DV pin is multiplexed with the
RXFRTGE pin.

When RST
testing.

is active, RX_DV is an input for NAND tree

24 Am79C971

If the MII port is not selected, the RX_DV pin can be left
floating.

RX_ER

Receive Error Input

RX_ER is an input that indicates that the MII trans­ceiver device has detected a coding error in the receive
frame currently being transferred on the RXD[3:0] pins.
When RX_ER is asser t ed while RX_DV is asser ted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Spec i al co de group s gen erate d
on RXD while RX_DV is deasserted are ignor ed (e.g.,
Bad SSD in TX and IDLE in T4). RX_ER transitions are
synchronous to RX_CLK rising edges.

Note: The RX_ER pin is multiplexed with the RXDAT
pin.

When RST
testing.

If the MII port is not selected, the RX_ER pin can be left
floating.

is active, RX_ER is an input for NAND tree

MDC

Management Data Clock Output

MDC is a non-continuous clock output t hat provides a
timing referenc e for bits on the MDIO p in. Duri ng MII
management por t operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management opera­tions are in progress, MDC is driven LOW. The MDC is
derived from the external 20-MHz crystal.

Attachment Unit Interface
CI±

Collision In Input

CI± is a differential input pair sig nal ing the A m7 9C971
controller that a collision has been detected on the net­work media, indicated by the CI
with a 10-MHz pattern of sufficient amplitude and pulse
width to meet ISO 8802-3 (IEEE/ANSI 802.3 ) stan­dards. CI

If the CI
gether.

± operates at pseudo ECL levels.

± pins are not used , they should be tied to-

± inputs being driven

DI±

Data In Input

DI

± is a diff erential input pair to the Am79C971 control-

ler carr ying Manche ster encoded data from the net­work. DI

If the DI
gether.

± operates at pseudo ECL levels.

± pins are not used, they should be tied to-

DO±

Data Out Output

DO± is a differential output pair from the Am79C971
controller for transmitting Manches te r enc ode d d ata t o
the network. DO

If the AUI is not used, DO
minimum power consumption.

± operates at pseudo ECL levels.

± should be le ft floating for

10BASE-T Interface

If the MII port is not selected, th e MDC pin can be left
floating.

MDIO

Management Data I/O Input/Output

MDIO is the bidirectional M II management por t data
pin. MDIO is an output during the header portion of the
management frame transfers and durin g the data por­tions of write transfers. MDIO is an input during the
data portions of read data transfers. When an operation
is not in progress on the management port, MDIO is not
driven. MDIO transitions from the Am79C971 controller
are synchronous to MDC Falling edges.

If the PHY is attached through an MII physical connec­tor, then the MDIO pin should be externally pulled down

SS with a 10-kΩ ±5% resistor. If the PHY is on

to V
board, then the MDIO pin should be externally pulled
up to V

When RST is active, MDIO is an input for NAND tre e
testing.

CC with a 10-kΩ ±5% resistor.

RXD±

10BASE-T Receive Data Input

± are 10BASE-T por t differential rece ivers. If the

RXD
10BASE-T interface is not used in a design, RXD+ and
RXD- should be connected to each other.

TXD±

10BASE-T Transmit Data Output

TXD± are 10BASE-T port differential drivers.

TXP±

10BASE-T Pre-Distortion Control Output

These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.

General Purpose Serial Interface
CLSN

Collision Input

CLSN is an input that indicates a collision has occurred
on the network.

Note: The CLSN pin is multiplexed with the COL pin.
When RST

testing.

is active, CLSN is an input for NAND tree

Am79C971 25

RXCLK

Receive Clock Input

RXCLK is an input. The rising edges of the RXCLK sig­nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.

TXEN

Transmit Enable Output

TXEN is an output that provides an enable signal for
transmission. Data on the TXDAT pin is not valid unless
the TXEN signal is HIGH.

Note: The RXCLK pin is multiplexed with the RX_CLK
pin.

When RST
testing.

is active, RXCLK is an input for NAND tree

RXDAT

Receive Data Input

RXDAT is an input. The rising edges of the RXCLK sig­nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.

Note: The RXDAT pin is multiplexed with the RX_E R
pin.

When RST
testing.

is active, RXDAT is an input for NAND tree

RXEN

Receive Enable Input

RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.

Note: The RXEN pin is multiplexed with the CRS pin.
When RST

testing.

is active, RXEN is an input for NAND tr ee

TXCLK

Transmit Clock Input

TXCLK is an input that provides a clock signal for MAC
activity, both transmit and r ecei ve. The ri sing edges o f
the TXCLK can be used to validate TXDAT output data.

Note: The TXCLK pin is multiplexed with the TX_CLK
pin.

When RST
testing.

is active, TXCLK is an input for NAND tree

TXDAT

Transmit Data Output

TXDAT is an output tha t provides the ser ial bit stream
for transmission, including preamble, SFD, data, and
FCS field, if applicable.

Note: The TXDAT pin is multiplexed with the TXD[0]
pin.

When RST
testing.

is active, TXDAT is an input for NAND tree

Note: The TXEN pin is multiplexed with the TX_EN
pin.

When RST
testing.

is active, TXEN is an input for NAND tree

External Address Detection Interface
EAR

External Address Reject Low Input

The incoming frame will be checked against the inter­nally active address detection mechanisms and the re­sult of this check will be OR’d with the value on the EAR
pin. The EAR pin is defined as REJECT. The pin value
is OR’d with the internal address detection result to de­termine if th e current frame sho uld be a ccepted or re­jected.

The EAR
be tied to VDD through a resistor.

Note: The EAR pin is multiplexed with the SLEEP pin.
When RST

testing.

pin must not be left unconnect ed, it should

is active, EAR is an input for NAND tree

SFBD

Start Frame-Byte Delimiter Output
For the Internal PHY during External Address

Detection:

An initial rising edge on the SFBD signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signa l, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns when operating at 10 Mbps) after
detecting the second “1” in the S FD (Start of F ra me De­limiter) of a rece ived frame. SFBD will subsequent ly
toggle every 4 bit times (1.25 MHz frequency when op­erating at 10 Mbps) with each rising edge indicating the
first bit of each subsequen t byte of the received serial
bit stream. See the EADI Rejection Timing with Internal
PHY timing diagram for details. SFBD will be active
only during frame reception.

For the External PHY attached to the Media Inde­pendent Interface during External Address Detec­tion:

An initial rising edge on the SFBD signal indicates that
a start of valid data is present on the RXD[3:0] pins.
SFBD will go high for one nibble time (400 ns when op­erating at 10 Mbps and 40 ns when operating at 100
Mbps) one RX_CLK perio d after RX_DV has been as­serted and RX_ER is deasserted and the detection o f

26 Am79C971

the SFD (Start of F rame Delimiter) of a received frame.
Data on the RXD[3:0] will be the start of the destination
address field. SFBD will subsequently toggle every nib­ble time (1.25 MHz frequency when operating at 10
Mbps and 12.5 MHz fr equenc y when o perating at 10 0
Mbps) indicating the first nibble of each subsequent
byte of the received nibble stream. The RX_CLK
should be used in con junction with the S FBD to latch
the correct data for external address matching. SFBD
will be active only during frame reception.

Note: The SFBD pin is multiplexed with the EESK and

pins.

LED1
When RST

testing.

is active, SFBD is an input for NAND tree

SRD

Serial Receive Data Input/Output

SRD is the decoded NRZ data from the net work. This
signal can be used for external address detection.
When the 10BASE-T port is selected, transitions on
SRD will only occur during receive activity. When the
AUI port is selected, transitions on SRD will occur dur­ing both transmit and receive activity.

When the EADI is enabled (EADISEL, BCR2, bit 3) and
the Receive Frame Ta gging is enabled (RXFRTG,
CSR7, bit 14) and the MII is selected, the SRD pin be­comes a data input pin for the Receive Frame Tag (MI­IRXFRTGD). See the Receive Frame Tagging section
for details.

Note: When the MII port is selected, SRD will not gen­erate transitions and receive data must be derived from
the Media Independent Interface RXD[3:0] pins.

Note also that the SRD pin is multiplexed with the
EEDO and LED3

When RST
testing.

pins.

is active, SRD is an input for NAND tree

SRDCLK

Serial Receive Data Clock Input/Output

Serial Rece ive Data is synchronou s with reference to
SRDCLK. When the 10BASE-T port is selected, transi­tions on SRDCLK will only occur during receive activity.
When the AUI port is selected, transitions on SRDCLK
will occur during both transmit and receive activity.

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is selected, the SRDCLK pin be­comes a data input enable pin for the Rece ive Frame
Tag (M IIRXFRTGE). See the Receive Frame Tagging
section for details.

Note: When the MII port is selected, SRDCLK will not
generate transitions and the receive clock must be de­rived from the MII RX_CLK pin.

Note also that the SR DCLK pin i s multiplexed with the

pin.

LED2
When RST

tree testing.

is active, SRDCLK is an input for NAND

RXFRTGD

Receive Frame Tag Data Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is no t selected, the RXFRTGD pin
becomes a data i nput pin for the Recei ve Frame Tag.
See the Receive Frame Tagging section for details.

Note: The RXFRTGD pin is multiplexed with the
RXD[0] pin.

When RST
tree testing.

is active, RXFRTGD is an input for NAND

RXFRTGE

Receive Frame Tag Enable Input

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the MII is not selected, the RXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the Re ceive Frame Tagging secti on for de-
tails.

Note: The RXFRTGE pin is multiplexed with the
RX_DV pin.

When RST
tree testing.

is active, RXFRTGE is an input for NAND

MIIRXFRTGD

MII Receive Frame Tag Enable Input/Output

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is ena bled (RXFRTG, CSR7,
bit 14), and the MII is selected, the MIIRXFRTGD pin
becomes a data i nput pin for the Recei ve Frame Tag.
See the Receive Frame Tagging section for details.

Note: The MIIRXFRTGD pin is multiplexed with the
SRD pin.

When RST
NAND tree testing.

is active, MIIRXFRTGD is an inpu t for

MIIRXFRTGE

MII Receive Frame Tag Enable Input/Output

When the EADI is enabled (EADISEL, BCR2, bit 3), the
Receive Frame Tagging is enabled (RXFRTG, CSR7,
bit 14), and the M II is selected, the MIIRXFRTGE pin
becomes a data input enable pin for the Receive Frame
Tag. See the Re ceive Frame Tagging secti on for de-
tails.

Note: The MIIRXFRTGE pin is multiplexed with the
SRDCLK pin.

Am79C971 27

When RST is active, MIIRXFRTGE is an input for
NAND tree testing.

IEEE 1149.1 (1990) Test Access Port Interface

TCK

Test Clock Input

TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull up resistor.

TDI

Test Data In Input

TDI is the test da ta input path t o the Am79C9 71 con­troller. The pin has an internal pull up resistor.

VDD_PLL

PLL Power (1 Pin) Power

There is one analog PLL +5 V supply pin. Specia l at­tention should be paid to the printed circuit board layout
to avoid excessive noise on this line. Refer to Appendix

B, Recommendation for Power and Ground Decou­pling, for details.

VSS_PLL

PLL Ground (1 Pin) Power

There is one analog PLL groun d pin. Spe cial attentio n
should be paid to the printed circuit board layout to
avoid excessive noise on this line. Refer to Appendix B,

Recommendation for Power and Ground Decoupling,

for details.

TDO

Test Data Out Output

TDO is the test data output path from the Am79C971
controller. The pin is tri-stated when the JT A G port is in­active.

TMS

Test Mode Select Input

A serial input bit stream on the TMS pin is used to de­fine the specif ic boundary scan test to be executed.
The pin has an internal pull up resistor.

Power Supply Pins
AVDDB

Analog Power (3 Pins) Power

There are thr ee analog +5 V sup ply pins that provide
power for the Twisted Pair and AUI drivers. Hence, they
are very noisy. Special attention should b e paid to the
printed circuit board layout to av oid e xcessive noise on
these lines. Refer to Appendix B, Recommendation for
Power and Ground Decoupling, for details.

AVSSB

Analog Ground (1 Pins) Power

There is one analog ground pin that provides ground
for the Twi sted Pair and AUI drivers. Hence, it i s very
noisy. Special attention should be paid to the printed
circuit board layout to avoid excessive noise on these
lines. Refer to Appendix B, Recommendation for P ower
and Ground Decoupling, for details.

VDDB

I/O Buffer Power (5 Pins) Power

There are five power supply pins tha t are used by the
input/output buffer drivers. All VDDB pins must be con­nected to a +5 V supply.

VSSB

I/O Buffer Ground (13 Pins) Power

There are thirteen ground pins that are used by the PCI
bus input/output buffer drivers.

VDD_PCI

PCI I/O Buffer Power (5 Pins) Power

There are five power supply pins tha t are used by the
PCI input/ou tput buffer drivers. In a sys tem with +5 V
signaling environment, all VDD_PCI pins must be con­nected to a +5 V supply. In a system with +3.3 V signal­ing environment, all VDD_PCI pins must be connected
to a +3.3 V supply.

VDD

Digital Power (4 Pins) Power

There are four power supply pins that are used by the
internal digital circuitry. All VDD pins must be con­nected to a +5 V supply.

VSS

Digital Ground (6 Pins) Power

There are six ground pins that are used by the internal
digital circuitry.

28 Am79C971

BASIC FUNCTIONS
System Bus Interface

The Am79C971 controller is designed to operate as a
bus master during nor mal operations. Some slave I/O
accesses to t he Am79C971 controller are require d in
normal operations as well. Initialization of the
Am79C971 controller is achieved through a combina­tion of PCI Configuration Space accesses, bus slave
accesses, bus master acces ses, and an op tional rea d
of a serial EEPROM that is performed by the
Am79C971 controller. The EEPROM read o peration is
performed through the 93C46 EEPROM interface. The
ISO 8802-3 (IEEE/A NSI 802.3) Ethernet A ddres s may
reside within the serial EEPROM. Some Am79C971
controller configuration registers may also be pro­grammed by the EEPROM read operation.

The Address PROM, on-chip bo ard-configuration reg­isters, and the Ether net contr oller register s occupy 32
bytes of address space. I/O an d memor y mapped I/O
accesses are supported. Base Address registers in the
PCI configuration sp ace allow locating the address
space on a wide variety of starting addresses.

For diskless stations, the Am79C971 controller sup­ports a ROM or Flash-based (both referred to as the
Expansion ROM throughout this specification) boot de­vice of up to 1 Mbyte in size. The host can map the boot
device to any memory address that aligns to a 1-Mbyte
boundary by modifyi ng the Expans ion ROM Base Ad­dress register in the PCI configuration space.

Software Interface

The software interface to the Am79C971 controller is
divided into three parts. One part is the PCI configura­tion registers used to identify the Am79C971 controller
and to setup the configuration of the device. The setup
information includes the I/O or memory mapped I/O
base address, mappin g of the Expansion ROM, an d
the routing of the Am79C971 controller interrupt cha n­nel. This allows for a jumperless implementation.

The second por tion of the software interface is the d i­rect access to the I/O resources of the Am79C971 con­troller. The Am79C971 controller occup ies 32 bytes of
address space that must begin on a 32-byte block
boundary. The address space can be mapped into I/O
or memory space (memory mapped I/O). The I/O Base
Address Register i n th e P C I Configuration Space con­trols the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O
Base Address R egister controls the s tart addr ess of
the address space if it is mapped to memor y space.
The 32-byte address spac e is used by the so ftware to
program the Am79C971 control ler operating mode, to
enable and disable various features, to monitor operat-

ing status, and to request particular functions to be ex­ecuted by the Am79C971 controller.

The third por tion of th e software interface is the d e­scriptor and buffer areas that are shared between the
software and the Am79C971 cont roller durin g normal
network oper ations. The desc riptor area b oundaries
are set by the software and do not chan ge dur ing nor­mal network operations. There is one descriptor area
for receive activity and there is a separate area for
transmit activity. The descriptor space contains relocat­able pointers to the networ k frame d ata, and it is u sed
to transfer frame status from the Am79C971 controll er
to the software. The buffer areas are locations that hold
frame data for transmission or that acce pt frame data
that has been received.

Network Interfaces

The Am79C971 controller can be connected to an
IEEE 802.3 or propri etar y networ k via one o f four net­work interfaces. The Media Independent Interface (MII)
provides an IEEE 802.3-complian t nibble-wide inter­face to an external 100- and/or 10 -Mbps transceiver
device. The Attachment Unit Interface (AUI) provides
an ISO 8802-3 (IEE E/ANSI 802.3) defi ned differential
interface. On-board MAU and or off-board MAU con­nection with or without a n AUI cable is supported. The
10BASE-T interface provides a twisted-pair Ethernet
port , which is ISO 8802-3 (IE EE/ANSI 802 .3)-compli­ant, and contains the auto-negotiation capability, which
is IEEE 802.3u-compliant. The General Purpose Serial
Interface (GPSI) allows bypassing the Manchester
Encoder/Decoder (MENDEC) and is functionally equiv­alent to the GPSI found on the LANCE.

While in auto-selection mode, the interface in use is de­termined by the Network P ort Manager . If the quiescent
state of the MII MDIO pin is HIGH, the MII is activated.
If the MII MDIO pin is LOW, the Am79C971 device
checks the link status on the 10BASE-T port. If the
10BASE-T link status is good, the 10BASE-T port is se­lected. If there is no active link status, then the device
assumes an AUI connec tion. The 10B ASE-T por t will
continue to monitor the link status while th e AUI is ac­tive. The software driver can override th is automatic
configuration at anytime by disabling the auto-selection
and forcing a network port to be attached to the internal
MAC. The GPSI port can onl y be enabled by disa bling
the auto-selection and manually selecting the GPSI as
the network port.

The Am79C971 controller suppor ts half-duplex and
full-duplex operation on all four network interfaces (i.e.,
AUI, 10BASE-T, GPSI, and MII).

Am79C971 29

DETAILED FUNCTIONS
Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Sta tus
Registers (CSR), the Bu s Configuration Registers
(BCR), the Ad dress PROM (APROM) lo cations, and
the Expansion ROM. Table 2 shows the response of
the Am79C971 controller to each of the PCI commands
in slave mode.

Table 2. Slave Commands

C[3:0] Command Use

0000

0001 Special Cycle Not used

0010 I/O Read

0011 I/O Write

0100 Reserved
0101 Reserved

0110 Memory Read

0111 Memo ry Write

1000 Reserved
1001 Reserved

1010

1011

1100

1101

1110

1111

Interrupt
Acknowledge

Configuration
Read

Configuration
Write

Memory Read
Multiple

Dual Addres s
Cycle

Memory Read
Line

Memory Write
Invalidate

Not used

Read of CSR, BCR, APROM,
and Reset registers

Write to CSR, BCR, and
APROM

Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers
Read of the Expansion Bus

Memory mapped I/O write of
CSR, BCR, and APROM

Read of the Configuration
Space

Write to the Configuration
Space

Aliased to Memory Read

Not used

Aliased to Memory Read

Aliased to Memory Write

Slave Configuration Transfers

The host can access the Am79C971 PCI configuration
space with a configuration read or write command. The
Am79C971 controller will assert DEVSEL
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]

during the

select the DWord location in the configuration space.
The Am79C971 controller ignores AD[10:8], because it
is a single function device. AD[31:11] are don’t care.

AD31
AD11

Don’t care Don’t care

AD10
AD8

AD7
AD2

DWord
index

AD1 AD0

00

The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, a nd 32-bit trans­fers are supported . DEVSEL
cles after the host has asserted FRAME

is asserted two clock cy-

. All
configuration cycles are of fixed length. The
Am79C971 controll er will asser t TRDY

on the third

clock of the data phase.
The Am79C971 controller does not support burst trans-

fers for access to configurati on space. When th e host
keeps FRAME

asserted for a second data phase, the

Am79C971 controller will disconnect the transfer.
When the host tries to access the PCI configuration

space while the automatic r ead of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C971 control ler will ter minate the access on the
PCI bus with a disconnect/retry response.

The Am79C971 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardw ired to 1. The Am79C97 1 controller
is capable of detecting a configuration cycle even when
its address phas e immediate ly follows the data phas e
of a transaction to a different target without a ny idle
state in-between. There will be no contention on the
DEVSEL
Am79C971 controll er asser ts DEV SEL
clock after FRAME

, TRDY, and STOP signals, since the

on the second

is asserted (medium timing).

Slave I/O Transfers

After the Am79C971 co ntroller is c onfigured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monito r ing the PCI bus for
access to its CSR, BCR, or APROM locati ons. If con­figured for regular I/O mode, the Am79C971 contr oller
will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
The Am79C971 controller asserts DEVSEL
an address mat ch and the access is an I/O cycle. If
configured for memory mapped I/O mode, the
Am79C971 controller wil l look for an address that falls
within its 32 bytes of me mory address spa ce (star ting
from the memory mapped I/O base address). The
Am79C971 controll er asser ts DEVSEL
address match and the access is a memory cycle.
DEVSEL
asserted FRAME

is asserted two clock cycles after the host has

. See Figure 1 and Figure 2.

if it detects

if it detects an

30 Am79C971