AMD Advanced Micro Devices AM79C970AVCW, AM79C970AKCW, AM79C970AKC Datasheet
PRELIMINARY
Am79C970A
PCnetTM-PCI II Single-Chip Full-Duplex Ethernet Controller
for PCI Local Bus Product
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller for the Peripheral Component Interconnect (PCI) local bus
Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
Direct interface to the PCI local bus (Revision
2.0 compliant)
High-performance 32-bit Bus Master architec-
ture with integrated DMA buffer Management
Unit for low CPU and bus utilization
Software compatible with AMD PCnet Family,
LANCE/C-LANCE, and Am79C900 ILACC register and descriptor architecture
Compatible with PCnet Family driver software
Full-duplex operation for increased network
bandwidth
Big endian and little endian byte alignments
supported
3.3 V/5 V signaling for PCI bus interface
Low-power CMOS design with two sleep
modes allows reduced power consumption for
critical battery powered applications and Green
PCs
Integrated Magic PacketTMsupport for remote
wake up of Green PCs
Individual 272-byte transmit and 256-byte receive FIFOs provide frame buffering for increased system latency and support the
following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit pad-
ding (individually programmable)
— Automatic runt frame rejection
— Automatic selection of received collision frames
Microwire EEPROM interface supports
jumperless design and provides through-chip
programming
Supports optional Boot PROM for diskless
node applications
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
end of receive frame
Integrated Manchester Encoder/Decoder
Provides Integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with automatic
port selection
Automatic Twisted-Pair receive polarity detection and automatic correction of the receive
polarity
Optional byte padding to long-word boundary
on receive
Dynamic transmit FCS generation programmable on a frame-by-frame basis
Internal/external loopback capabilities
Supports the following types of network inter-
faces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium
JTAG Boundary Scan (IEEE 1149.1) test access
port interface and NAND Tree test mode for
board-level production connectivity test
Supports LANCE General Purpose Serial Interface (GPSI)
Supports External Address Detection Interface
(EADI)
4 programmable LEDs for status indication
132-pin PQFP package
Advanced
Micro
Devices
GENERAL DESCRIPTION
The 32-bit PCnet-PCI II single-chip full-duplex Ethernet
controller is a highly integrated Ethernet system solution
designed to address high-performance system application requirements. It is a flexible bus-mastering device
that can be used in any application, including networkready PCs, printers, fax modems, and bridge/router de-
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
signs. The bus-master architecture provides high data
throughput in the system and low CPU and system bus
utilization. The PCnet-PCI II controller is fabricated with
AMD’s advanced low-power CMOS process to
provide low operating and standby current for power
sensitive applications.
Publication# 19436 Rev. A Amendment/+1
Issue Date: April 1995
AMD
P R E L I M I N A R Y
The PCnet-PCI II controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a DMA buffer management unit, an IEEE
802.3-compliant Media Access Control (MAC) function,
individual 272-byte transmit and 256-byte receive
FIFOs, an IEEE 802.3-compliant Attachment Unit
Interface (AUI) and Twisted-Pair Transceiver Media
Attachment Unit (10BASE-T MAU) that can both
operate in either half-duplex or full-duplex mode.
The PCnet-PCI II controller is register compatible with
the LANCE (Am7990) Ethernet controller, the
C-LANCE (Am79C90) Ethernet controller, the ILACC
(Am79C900) Ethernet controller, and all Ethernet
controllers in the PCnet Family, including the
PCnet-ISA controller (Am79C960), PCnet-ISA+
controller (Am79C961), PCnet-ISA II controller
(Am79C961A), PCnet-32 controller (Am79C965),
PCnet-PCI controller (Am79970), and the PCnet-SCSI
controller (Am79C974). The buffer management unit
supports the C-LANCE, ILACC, and PCnet descriptor
software models. The PCnet-PCI II controller is
software compatible with the Novell
NE2100 and
NE1500 Ethernet adapter card architectures.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to PCI local bus applications, simplifying
the design of an Ethernet node in a PC system. The
PCnet-PCI II controller provides the complete interface
to an Expansion ROM, allowing add-on card designs
with only a single load per PCI bus interface pin. With its
built-in support for both little and big endian byte alignment, this controller also addresses proprietary non-PC
applications. The PCnet-PCI II controller’s
advanced CMOS design allows the bus interface to be
connected to either a 5 V or a 3.3 V signaling environment. Both NAND Tree and JTAG test interfaces
are provided.
The PCnet-PCI II controller supports automatic
configuration in the PCI configuration space. Additional
PCnet-PCI II configuration parameters, including the
unique IEEE physical address, can be read from an external non-volatile memory (Microwire EEPROM) immediately following system reset.
The controller has the capability to automatically select
either the AUI port or the Twisted-Pair transceiver. Only
one interface is active at any one time. Both network interfaces can be programmed to operate in either halfduplex or full-duplex mode. The individual transmit and
receive FIFOs optimize system overhead, providing sufficient latency during frame transmission and reception,
and minimizing intervention during normal network error
recovery. The integrated Manchester encoder/decoder
(MENDEC) eliminates the need for an external Serial Interface Adapter (SIA) in the system. The built-in General
Purpose Serial Interface (GPSI) allows the MENDEC to
be by-passed. In addition, the device
provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity, activity, or jabber status. The PCnet-PCI II controller also
provides an External Address Detection Interface
(EADI) to allow fast external hardware address filtering
in internetworking applications.
For power sensitive applications where low stand-by
current is desired, the device incorporates two Sleep
functions to reduce over-all system power consumption,
excellent for notebooks and Green PCs. In conjunction
with these low power modes, the PCnet-PCI II controller
also has integrated functions to support Magic Packet,
an inexpensive technology that allows remote wake up
of Green PCs.
2
Am79C970A
BLOCK DIAGRAM
CLK
RST
AD[31:00]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
LOCK
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
NOUT
SLEEP
PCI Bus
Interface
Unit
P R E L I M I N A R Y
Rcv
FIFO
Xmt
FIFO
FIFO
Control
GPSI
802.3
Port
MAC
Core
EADI
Port
Manchester
Encoder/
Decoder
(PLS) & AUI
Port
10BASE-T
MAU
AMD
DXCVR
TXEN
TXCLK
TXDAT
RXEN
RXCLK
RXDAT
CLSN
SRDCLK
SRD
SF/BD
EAR
XTAL1
XTAL2
DO+/DI +/CI+/-
TXD+/TXP+/RXD+/-
LNKST
TCK
TMS
TDI
TDO
JTAG
Port
Control
Buffer
Management
Unit
Microwire
EEPROM
Interface
LED
Control
Expansion
ROM
Interface
EECS
EESK
EEDI
EEDO
LED1
LED2
LED3
ERA[7:0]
ERD[7:0]
ERACLK
EROE
19436A-1
3Am79C970A
AMD
P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELATED PRODUCTS 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONNECTION DIAGRAM 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESIGNATIONS 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Pin Number 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Group 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Listed By Driver Type 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interface 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Interface 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire EEPROM Interface 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Serial Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Address Detection Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 Test Access Port Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Pins 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BASIC FUNCTIONS 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Interface Function 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interface 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Network Interfaces 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DETAILED FUNCTIONS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Bus Interface Unit 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Configuration Transfers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave I/O Transfers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Transfers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exclusive Access 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Cycle Termination 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect When Busy 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect Of Burst Transfer 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect When Locked 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error Response 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Bus Interface Unit 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Acquisition 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Master DMA Transfers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Non-Burst Read Transfer 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Burst Read Transfer 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Non-Burst Write Transfer 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Burst Write Transfer 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Initiated Termination 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect With Data Transfer 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect Without Data Transfer 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Abort 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Am79C970A
P R E L I M I N A R Y
AMD
Master Initiated Termination 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preemption During Non-Burst Transaction 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preemption During Burst Transaction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Abort 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity Error Response 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Parity Error Handling 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Block DMA Transfers 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor DMA Transfers 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO DMA Transfers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Burst FIFO DMA Transfers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst FIFO DMA Transfers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management Unit 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Re-Initialization 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suspend 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor Rings 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Table Entry 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor Table Entry 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Access Control 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit and Receive Message Data Encapsulation 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Destination Address Handling 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Access Management 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Medium Allocation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Handling 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Operation 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Function Programming 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Generation 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit FCS Generation 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Exception Conditions 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Carrier 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Late Collision 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SQE Test Error 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Operation 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Function Programming 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Matching 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Pad Stripping 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive FCS Checking 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Exception Conditions 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopback Operation 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T-MAU Loopback Modes 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Loopback Features 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Magic Packet Mode 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manchester Encoder/Decoder 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Crystal Characteristics 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Drive Characteristics 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MENDEC Transmit Path 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Timing and Operation 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Path 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Signal Conditioning 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5Am79C970A
AMD
P R E L I M I N A R Y
Clock Acquisition 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Tracking 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carrier Tracking and End of Message 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Decoding 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Tolerance Definition 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Attachment Unit Interface 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Termination 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detection 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted-Pair Transceiver 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Transmit Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Receive Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Test Function 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polarity Detection and Reversal 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface Status 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Collision Detection Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Quality Error Test Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jabber Function 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface Connection 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full-Duplex Operation 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full-Duplex Link Status LED Support 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Serial Interface 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Address Detection Interface 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion ROM Interface 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Microwire Interface 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic EEPROM Read Operation 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Auto-Detection 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Access to the Microwire Interface 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM-programmable Registers 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM MAP 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Support 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Savings Modes 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 Test Access Port Interface 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Circuit 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP Finite State Machine 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Instructions 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Register and Decoding Logic 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Register 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Data Registers 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND Tree Testing 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H_RESET 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S_RESET 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Access 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Resources 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address PROM Space 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Register 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Word I/O Mode 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Word I/O Mode 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USER ACCESSIBLE REGISTERS 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Am79C970A
P R E L I M I N A R Y
AMD
PCI Vendor ID 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Device ID Register 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Command Register 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Status Register 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Revision ID Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Programming Interface Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Sub-Class Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Base-Class Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Latency Timer Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Header Type Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI I/O Base Address Register 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Memory Mapped I/O Base Address Register 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Expansion ROM Base Address Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Line Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Interrupt Pin Register 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI MIN_GNT Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI MAX_LAT Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAP Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAP: Register Address Port 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR0: PCnet-PCI II Controller Controller Status Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR1: Initialization Block Address 0 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR2: Initialization Block Address 1 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR3: Interrupt Masks and Deferral Control 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR4: Test and Features Control 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR5: Extended Control and Interrupt 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR6: RX/TX Descriptor Table Length 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR8: Logical Address Filter 0 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR9: Logical Address Filter 1 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR10: Logical Address Filter 2 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR11: Logical Address Filter 3 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR12: Physical Address Register 0 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR13: Physical Address Register 1 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR14: Physical Address Register 2 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR15: Mode 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR16: Initialization Block Address Lower 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR17: Initialization Block Address Upper 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR18: Current Receive Buffer Address Lower 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR19: Current Receive Buffer Address Upper 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR20: Current Transmit Buffer Address Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR21: Current Transmit Buffer Address Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR22: Next Receive Buffer Address Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR23: Next Receive Buffer Address Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR24: Base Address of Receive Descriptor Ring Lower 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR25: Base Address of Receive Descriptor Ring Upper 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR26: Next Receive Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR27: Next Receive Descriptor Address Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR28: Current Receive Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR29: Current Receive Descriptor Address Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR30: Base Address of Transmit Descriptor Ring Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR31: Base Address of Transmit Descriptor Ring Upper 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR32: Next Transmit Descriptor Address Lower 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR33: Next Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR34: Current Transmit Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR35: Current Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7Am79C970A
AMD
P R E L I M I N A R Y
CSR36: Next Next Receive Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR37: Next Next Receive Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR38: Next Next Transmit Descriptor Address Lower 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR39: Next Next Transmit Descriptor Address Upper 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR40: Current Receive Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR41: Current Receive Status 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR42: Current Transmit Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR44: Next Receive Byte Count 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR45: Next Receive Status 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR46: Poll Time Counter 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR47: Polling Interval 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR58: Software Style 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR60: Previous Transmit Descriptor Address Lower 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR61: Previous Transmit Descriptor Address Upper 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR62: Previous Transmit Byte Count 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR63: Previous Transmit Status 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR64: Next Transmit Buffer Address Lower 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR65: Next Transmit Buffer Address Upper 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR66: Next Transmit Byte Count 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR67: Next Transmit Status 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR72: Receive Descriptor Ring Counter 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR74: Transmit Descriptor Ring Counter 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR76: Receive Descriptor Ring Length 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR78: Transmit Descriptor Ring Length 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR80: DMA Transfer Counter and FIFO Watermark Control 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR82: Bus Activity Timer 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR84: DMA Address Register Lower 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR85: DMA Address Register Upper 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR86: Buffer Byte Counter 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR88: Chip ID Register Lower 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR89: Chip ID Register Upper 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR94: Transmit Time Domain Reflectometry Count 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR100: Bus Timeout 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR112: Missed Frame Count 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR114: Receive Collision Count 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR122: Advanced Feature Control 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR124: Test Register 1 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR0: Master Mode Read Active 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR1: Master Mode Write Active 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR2: Miscellaneous Configuration 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR4: Link Status LED (LNKST) 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR5: LED1 Status 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR6: LED2 Status 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR7: LED3 Status 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR9: Full-Duplex Control 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR16: I/O Base Address Lower 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR16: I/O Base Address Upper 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR18: Burst and Bus Control Register 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR19: EEPROM Control and Status 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR20: Software Style 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR21: Interrupt Control 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR22: PCI Latency Register 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Block 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RLEN and TLEN 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Am79C970A
P R E L I M I N A R Y
AMD
RDRA and TDRA 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LADRF 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PADR 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptors 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD0 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD1 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD2 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMD3 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptors 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD0 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD1 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD2 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMD3 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER SUMMARY 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATING 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATING RANGES 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC CHARACTERISTICS 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING CHARACTERISTICS 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface 174. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI 176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EADI 177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KEY TO SWITCHING WAVEFORMS 178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING TEST CIRCUITS 178. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING WAVEFORMS 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Interface 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Interface 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EADI 190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PHYSICAL DIMENSIONS 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX A: PCnet-PCI II Compatible Media Interface Modules A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10BASE-T Filters and Transformers A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUI Isolation Transformers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC/DC Converters A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manufacturer Contact Information A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B: Recommendation For Power And Ground Decoupling B-1. . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX C: Alternative Method For Initialization C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX D: Look-Ahead Packet Processing Concept D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction of the LAPP Concept D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outline of the LAPP Flow D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LAPP Software Requirements D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9Am79C970A
AMD
P R E L I M I N A R Y
LAPP Rules for Parsing of Descriptors D-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Some Examples of LAPP Descriptor Interaction D-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Size Tuning D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
An Alternative LAPP Flow—the TWO Interrupt Method D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX E: PCnet-PCI II and PCnet-PCI Differences E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
New Features E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Register Bit Changes E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Space E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Configuration Registers E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor E-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List Of Pin Changes E-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Am79C970A
P R E L I M I N A R Y
RELATED PRODUCTS
Part No. Description
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
TM
)
(ILACC)
TM
(HIMIBTM)
Plug n’ Play support)
Am79C900 Integrated Local Area Communications Controller
Am79C940 Media Access Controller for Ethernet (MACE
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft
Am79C961A PCnet-ISA II Single-Chip Full-Duplex Ethernet Controller (with Microsoft
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 486 and VL buses)
Am79C970 PCnet-PCI II Single-Chip Ethernet Controller for PCI Local Bus
Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C981 Integrated Multiport Repeater Plus
TM
(IMR+TM)
Am79C987 Hardware Implemented Management Information Base
AMD
Plug n’ Play support)
11Am79C970A
AMD
P R E L I M I N A R Y
CONNECTION DIAGRAM – 132-PIN PQFP
AD28
AD29
VSSB
AD30
AD31
TDO
REQ
VSS
TMS
GNT
VDD
CLK
RST
VSS
132
131
130
129
128
127
126
125
124
123
122
121
120
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
TDI
IDSEL
VSS
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
343536373839404142434445464748495051525354555657585960616263646566
119
Am79C970A
PCnet-PCI II
TCK
118
INTA
117
RESERVED
116
SLEEP
EECS
115
114
VSS
113
EESK/LED1/SFBD
EEDI/LNKST
112
111
EEDO/LED3/SRD
VDD
110
109
AVDD2
CI+
108
107
CI-
106
DI+
105
DI-
104
AVDD1
DO+
103
102
DO-
101
AVSS1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXD-
TXP-
AVDD4
RXD+
RXD-
VSS
LED2/SRDCLK
ERD0/RXDAT
ERD1/RXCLK
VDD
ERD2/RXEN
VSS
ERD3/CLSN
ERD4/TXCLK
VSS
ERD5
ERD6/TXEN
VDD
ERD7/TXDAT
ERA0
ERA1
VSS
ERA2
ERA3
ERA4
ERA5
VSS
Pin 1 is marked for orientation
RESERVED = Don't connect
Pin 1 is marked for orientation.
RESERVED = Don’t connect
12
PAR
AD15
AD14
AD13
AD12
VSSB
C/BE1
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
AD5
VSSB
AD4
AD3
AD2
AD1
VSSB
AD0
EAR
VDD
EROE
VSS
VSS
ERACLK
DXCVR/NOUT
ERA7
ERA6
19436A-2
Am79C970A
P R E L I M I N A R Y
CONNECTION DIAGRAM – 144-PIN TQFP
NC
NC
AD28
AD29
VSSB
AD30
AD31
TDO
REQ
VSS
TMS
GNT
VDD
CLK
RST
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
NC
VDDB
AD27
AD26
VSSB
AD25
AD24
C/BE3
VDD
TDI
IDSEL
VSSB
AD23
AD22
VSSB
AD21
AD20
VDDB
AD19
AD18
VSSB
AD17
AD16
C/BE2
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
VSS
PERR
SERR
VDDB
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
129
PCnet-PCI II
Am79C970AVC
49
50
51
52
TCK
128
53
INTA
127
54
RESERVED
SLEEP
EECS
VSS
126
125
124
123
55
56
57
58
EESK/LED1/SFBD
EEDI/LNKST
122
121
59
60
EED0/LED3/SRD
120
61
VDD
119
62
AVDD2
CI+
118
117
63
64
CI-
116
65
DI+
115
66
DI-
114
67
AVDD1
DO+
113
112
68
69
DI-
111
70
AVSS1
NC
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
71
72
AMD
NC
NC
XTAL2
AVSS2
XTAL1
AVDD3
TXD+
TXP+
TXD-
TXP-
AVDD4
RXD+
RXD-
VSS
LED2/SRDCLK
ERD0/RXDAT
ERD1/RXCLK
VDD
ERD2/RXEN
VSS
ERD3/CLSN
ERD4/TXCLK
VSS
ERD5
ERD6/TXEN
VDD
ERD7/TXDAT
ERA0
ERA1
VSS
ERA2
ERA3
ERA4
ERA5
VSS
NC
NC
PAR
AD15
AD14
AD13
VSSB
C/BE1
Pin 1 is marked for orientation.
RESERVED = Don’t connect
AD12
AD11
AD10
VSSB
AD9
AD8
VDDB
C/BE0
AD7
AD6
AD5
VSSB
AD4
AD3
AD2
AD1
VSSB
AD0
NC
VSS
EROE
DXCVR/NOUT
VSS
ERACLK
EAR
VDD
ERA7
ERA6
NC
19436A-3
13Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Pin Number
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 VDDB 34 PAR 67 VSS 100 AVSS1
2 AD27 35 C/BE1 68 ERA5 101 DO-
3 AD26 36 AD15 69 ERA4 102 DO+
4 VSSB 37 VSSB 70 ERA3 103 AVDD1
5 AD25 38 AD14 71 ERA2 104 DI-
6 AD24 39 AD13 72 VSS 105 DI+
7 C/BE3 40 AD12 73 ERA1 106 CI-
8 VDD 41 AD11 74 ERA0 107 CI+
9 TDI 42 AD10 75 ERD7/TXDAT 108 AVDD2
10 IDSEL 43 VSSB 76 VDD 109 VDD
11 VSS 44 AD9 77 ERD6/TXEN 110 EEDO/LED3/SRD
12 AD23 45 AD8 78 ERD5 111 EEDI/LNKST
13 AD22 46 VDDB 79 VSS 112 EESK/LED1/SFBD
14 VSSB 47 C/BE0 80 ERD4/TXCLK 113 VSS
15 AD21 48 AD7 81 ERD3/CLSN 114 EECS
16 AD20 49 AD6 82 VSS 115 SLEEP
17 VDDB 50 VSSB 83 ERD2/RXEN 116 RESERVED
18 AD19 51 AD5 84 VDD 117 INTA
19 AD18 52 AD4 85 ERD1/RXCLK 118 TCK
20 VSSB 53 AD3 86 ERD0/RXDAT 119 VSS
21 AD17 54 AD2 87 LED2/SRDCLK 120 RST
22 AD16 55 VSSB 88 VSS 121 CLK
23 C/BE2 56 AD1 89 RXD- 122 VDD
24 FRAME 57 AD0 90 RXD+ 123 GNT
25 IRDY 58 EAR 91 AVDD4 124 TMS
26 TRDY 59 VDD 92 TXP- 125 VSS
27 DEVSEL 60 EROE 93 TXD- 126 REQ
28 STOP 61 VSS 94 TXP+ 127 TDO
29 LOCK 62 DXCVR/NOUT 95 TXD+ 128 AD31
30 VSS 63 VSS 96 AVDD3 129 AD30
31 PERR 64 ERACLK 97 XTAL1 130 VSSB
32 SERR 65 ERA7 98 AVSS2 131 AD29
33 VDDB 66 ERA6 99 XTAL2 132 AD28
14
Am79C970A
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I N/A 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Frame IO STS6 1
GNT Bus Grant I N/A 1
IDSEL Initialization Device Select I N/A 1
INTA Interrupt IO TS6 1
IRDY Initiator Ready IO STS6 1
LOCK Bus Lock I N/A 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request IO TS3 1
RST Reset I N/A 1
SERR System Error IO TS6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1
Board Interface
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I N/A 1
XTAL1 Crystal Input I N/A 1
XTAL2 Crystal Output O XTAL 1
Microwire EEPROM Interface
EECS Microwire Serial EEPROM Chip Select O O6 1
EEDI Microwire Serial EEPROM Data In O LED 1
EEDO Microwire Address EEPROM Data Out I N/A 1
EESK Microwire Serial PROM Clock IO LED 1
Expansion ROM Interface
ERA[7:0] Expansion ROM Address Bus O O6 8
ERACLK Expansion ROM Address Clock O O6 1
ERD[7:0] Expansion ROM Data Bus I N/A 8
EROE Expansion ROM Output Enable O O6 1
15Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 132-PIN PQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
Attachment Unit Interface (AUI)
CI+/CI- AUI Collision Differential Pair I N/A 2
DI+/DI- AUI Data In Differential Pair I N/A 2
DO+/DO- AUI Data Out Differential Pair O DO 2
DXCVR Disable Transceiver O O6 1
10BASE-T Interface
LNKST Link Status O LED 1
RXD+/RXD- Receive Differential Pair I N/A 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2
General Purpose Serial Interface (GPSI)
CLSN Collision I N/A 1
RXEN Receive Enable I N/A 1
RXDAT Receive Data I N/A 1
RXCLK Receive Clock I N/A 1
TXCLK Transmit Clock I N/A 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1
External Address Detection Interface (EADI)
EAR External Address Reject Low I N/A 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data O LED 1
SRDCLK Serial Receive Data Clock O LED 1
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK Test Clock I N/A 1
TDI Test Data In I N/A 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I N/A 1
Test Interface
NOUT NAND Tree Test Output O O6 1
Power Supplies
AV
AV
V
V
V
V
DD
SS
DD
SS
DDB
SSB
Analog Power P N/A 4
Analog Ground P N/A 2
Digital Power P N/A 6
Digital Ground P N/A 12
I/O Buffer Power P N/A 4
I/O Buffer Ground P N/A 8
16
Am79C970A
P R E L I M I N A R Y
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Pin Number
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 NC 37 NC 73 NC 109 NC
2 VDDB 38 PAR 74 VSS 110 AVSS1
3 AD27 39 C/BE1 75 ERA5 111 DO-
4 AD26 40 AD15 76 ERA4 112 DO+
5 VSSB 41 VSSB 77 ERA3 113 AVDD1
6 AD25 42 AD14 78 ERA2 114 DI-
7 AD24 43 AD13 79 VSS 115 DI+
8 C/BE3 44 AD12 80 ERA1 116 CI-
9 VDD 45 AD11 81 ERA0 117 CI+
10 TDI 46 AD10 82 ERD7/TXDAT 118 AVDD2
11 IDSEL 47 VSSB 83 VDD 119 VDD
12 VSSB 48 AD9 84 ERD6/TXEN 120 EEDO/LED3/SRD
13 AD23 49 AD8 85 ERD5 121 EEDI/LNKST
14 AD22 50 VDDB 86 VSS 122 EESK/LED1/SFBD
15 VSSB 51 C/BE0 87 ERD4/TXCLK 123 VSS
16 AD21 52 AD7 88 ERD3/CLSN 124 EECS
17 AD20 53 AD6 89 VSS 125 SLEEP
18 VDDB 54 VSSB 90 ERD2/RXEN 126 Reserved
19 AD19 55 AD5 91 VDD 127 INTA
20 AD18 56 AD4 92 ERD1/RXCLK 128 TCK
21 VSSB 57 AD3 93 ERD0/RXDAT 129 VSS
22 AD17 58 AD2 94 LED2/SRDCLK 130 RST
23 AD16 59 VSSB 95 VSS 131 CLK
24 C/BE2 60 AD1 96 RXD- 132 VDD
25 FRAME 61 AD0 97 RXD+ 133 GNT
26 IRDY 62 EAR 98 AVDD4 134 TMS
27 TRDY 63 VDD 99 TXP- 135 VSS
28 DEVSEL 64 EROE 100 TXD- 136 REQ
29 STOP 65 VSS 101 TXP+ 137 TDO
30 LOCK 66 DXCVR/NOUT 102 TXD+ 138 AD31
31 VSS 67 VSS 103 AVDD3 139 AD30
32 PERR 68 ERACLK 104 XTAL1 140 VSSB
33 SERR 69 ERA7 105 AVSS2 141 AD29
34 VDDB 70 ERA6 106 XTAL2 142 AD28
35 NC 71 NC 107 NC 143 NC
36 NC 72 NC 108 NC 144 NC
AMD
NC - Indicates no connect
17Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
AD[31:0] Address/Data Bus IO TS3 32
C/BE[3:0] Bus Command/Byte Enable IO TS3 4
CLK Bus Clock I N/A 1
DEVSEL Device Select IO STS6 1
FRAME Cycle Frame IO STS6 1
GNT Bus Grant I N/A 1
IDSEL Initialization Device Select I N/A 1
INTA Interrupt IO TS6 1
IRDY Initiator Ready IO STS6 1
LOCK Bus Lock I N/A 1
PAR Parity IO TS3 1
PERR Parity Error IO STS6 1
REQ Bus Request IO TS3 1
RST Reset I N/A 1
SERR System Error IO TS6 1
STOP Stop IO STS6 1
TRDY Target Ready IO STS6 1
Board Interface
LED1 LED1 O LED 1
LED2 LED2 O LED 1
LED3 LED3 O LED 1
SLEEP Sleep Mode I N/A 1
XTAL1 Crystal Input I N/A 1
XTAL2 Crystal Output O XTAL 1
Microwire EEPROM Interface
EECS Microwire Serial EEPROM Chip Select O O6 1
EEDI Microwire Serial EEPROM Data In O LED 1
EEDO Microwire Address EEPROM Data Out I N/A 1
EESK Microwire Serial PROM Clock IO LED 1
Expansion ROM Interface
ERA[7:0] Expansion ROM Address Bus O O6 8
ERACLK Expansion ROM Address Clock O O6 1
ERD[7:0] Expansion ROM Data Bus I N/A 8
EROE Expansion ROM Output Enable O O6 1
18
Am79C970A
P R E L I M I N A R Y
AMD
PIN DESIGNATIONS – 144-PIN TQFP
Listed By Group
Pin Name Pin Function Type Driver No. of Pins
PCI Bus Interface
Attachment Unit Interface (AUI)
CI+/CI- AUI Collision Differential Pair I N/A 2
DI+/DI- AUI Data In Differential Pair I N/A 2
DO+/DO- AUI Data Out Differential Pair O DO 2
DXCVR Disable Transceiver O O6 1
10BASE-T Interface
LNKST Link Status O LED 1
RXD+/RXD- Receive Differential Pair I N/A 2
TXD+/TXD- Transmit Differential Pair O TDO 2
TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2
General Purpose Serial Interface (GPSI)
CLSN Collision I N/A 1
RXEN Receive Enable I N/A 1
RXDAT Receive Data I N/A 1
RXCLK Receive Clock I N/A 1
TXCLK Transmit Clock I N/A 1
TXDAT Transmit Data O O6 1
TXEN Transmit Enable O O6 1
External Address Detection Interface (EADI)
EAR External Address Reject Low I N/A 1
SFBD Start Frame Byte Delimiter O LED 1
SRD Serial Receive Data O LED 1
SRDCLK Serial Receive Data Clock O LED 1
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK Test Clock I N/A 1
TDI Test Data In I N/A 1
TDO Test Data Out O TS6 1
TMS Test Mode Select I N/A 1
Test Interface
NOUT NAND Tree Test Output O O6 1
Power Supplies
AV
AV
V
V
V
V
DD
SS
DD
SS
DDB
SSB
Analog Power P N/A 4
Analog Ground P N/A 2
Digital Power P N/A 6
Digital Ground P N/A 12
I/O Buffer Power P N/A 4
I/O Buffer Ground P N/A 8
19Am79C970A
AMD
P R E L I M I N A R Y
PIN DESIGNATIONS
Listed By Driver Type
The next table describes the various types of drivers that
are used in the PCnet-PCI II controller:
Name Type IOL (mA) IOH (mA) Load (pF)
LED LED 12 -0.4 50
O6 Totem Pole 6 -0.4 50
OD6 Open Drain 6 N/A 50
STS6 Sustained Tri-State
TS3 Tri-State 3 -2 50
TS6 Tri-State 6 -2 50
All IOL and IOH values shown in the table above apply to
5 V signaling. See the section “DC Characteristics” for
the values applying to 3.3 V signaling.
TM
DO, TDO and TPO are differential output drivers. The
characteristic of these and the XTAL output are described in the section “DC Characteristics”.
A sustained tri-state signal is a low active signal that is
driven high for one clock period before it is left floating.
6-250
20
Am79C970A
P R E L I M I N A R Y
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C970A K C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and Formed in a Tray
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQB132)
V = Thin Quad Flat Pack (PDL144)
°C to +70°C)
Valid Combinations
AM79C970A
DEVICE NUMBER/DESCRIPTION
Am79C970A
PCnet-PCI II Single-Chip Full-Duplex Controller
for PCI Local Bus
KC, KC\W, VC,
VC\W
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
SPEED OPTION
Not Applicable
Valid Combinations
21Am79C970A
AMD
P R E L I M I N A R Y
PIN DESCRIPTION
PCI Interface
AD[31:0]
Address and Data Input/Output
Address and data are multiplexed on the same bus interface pins. During the first clock of a transaction
AD[31:0] contain a physical address (32 bits). During
the subsequent clocks AD[31:0] contain data. Byte ordering is little endian by default. AD[7:0] are defined as
least significant byte and AD[31:24] are defined as the
most significant byte. For FIFO data transfers, the
PCnet-PCI II controller can be programmed for big
endian byte ordering. See CSR3, bit 2 (BSWP) for
more details.
During the address phase of the transaction, when the
PCnet-PCI II controller is a bus master, AD[31:2] will
address the active Double Word (DWord). The
PCnet-PCI II controller always drives AD[1:0] to ‘00’ during the address phase indicating linear burst order.
When the PCnet-PCI II controller is not a bus master,
the AD[31:0] lines are continuously monitored to determine if an address match exists for slave transfers.
During the data phase of the transaction, AD[31:0] are
driven by the PCnet-PCI II controller when performing
bus master write and slave read operations. Data on
AD[31:0] is latched by the PCnet-PCI II controller when
performing bus master read and slave write operations.
When RST is active, AD[31:0] are inputs for NAND
tree testing.
C/BE[3:0]
Bus Command and Byte Enables Input/Output
Bus command and byte enables are multiplexed on the
same bus interface pins. During the address phase of
the transaction, C/BE[3:0] define the bus command.
During the data phase C/BE[3:0] are used as byte enables. The byte enables define which physical byte
lanes carry meaningful data. C/BE0 applies to byte 0
(AD[7:0]) and C/BE3 applies to byte 3 (AD[31:24]). The
function of the byte enables is independent of the byte
ordering mode (BSWP, CSR3, bit 2).
When RST is active, C/BE[3:0] are inputs for NAND
tree testing.
CLK
Clock Input
This clock is used to drive the system bus interface and
the internal buffer management unit. All bus signals are
sampled on the rising edge of CLK and all parameters
are defined with respect to this edge. The PCnet-PCI II
controller operates over a range of 0 MHz to 33 MHz.
This clock is not used to drive the network functions.
When RST is active, CLK is an input for NAND
tree testing.
DEVSEL
Device Select Input/Output
The PCnet-PCI II controller drives DEVSEL when it
detects a transaction that selects the device as a target.
The device samples DEVSEL to detect if a target
claims a transaction that the PCnet-PCI II controller
has initiated.
When RST is active, DEVSEL is an input for NAND
tree testing.
FRAME
Cycle Frame Input/Output
FRAME is driven by the PCnet-PCI II controller when it
is the bus master to indicate the beginning and duration
of a transaction. FRAME is asserted to indicate a bus
transaction is beginning. FRAME is asserted while data
transfers continue. FRAME is deasserted before the final data phase of a transaction. When the PCnet-PCI II
controller is in slave mode, it samples FRAME to determine the address phase of transaction.
When RST is active, FRAME is an input for NAND
tree testing.
GNT
Bus Grant Input
This signal indicates that the access to the bus has been
granted to the PCnet-PCI II controller.
The PCnet-PCI II controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts GNT
without an active REQ from the PCnet-PCI II controller,
the device will drive the AD[31:0], C/BE[3:0] and
PAR lines.
When RST is active, GNT is an input for NAND
tree testing.
IDSEL
Initialization Device Select Input
This signal is used as a chip select for the
PCnet-PCI II controller during configuration read and
write transactions.
When RST is active, IDSEL is an input for NAND
tree testing.
22
Am79C970A
P R E L I M I N A R Y
INTA
Interrupt Request Input/Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT and UINT. Each status
flag has either a mask or an enable bit which allows for
suppression of INTA assertion. The flags have the
following meaning:
Table 1. Interrupt Flags
BABL Babble
EXDINT Excessive Deferral
IDON Initialization Done
JAB Jabber
MERR Memory Error
MISS Missed Frame
MFCO Missed Frame Count Overflow
MPINT Magic Packet Interrupt
RCVCCO Receive Collision Count Overflow
RINT Receive Interrupt
SLPINT Sleep Interrupt
SINT System Error
TINT Transmit Interrupt
TXSTRT Transmit Start
UINT User Interrupt
By default INTA is an open-drain output. For applications that need a high-active edge sensitive interrupt
signal, the INTA pin can be configured for this mode by
setting INTLEVEL (BCR2, bit 7) to ONE.
When RST is active, INTA is an input for NAND
tree testing.
IRDY
Initiator Ready Input/Output
IRDY indicates the ability of the initiator of the transaction to complete the current data phase. IRDY is used in
conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it asserts IRDY during all write data phases to indicated that
valid data is present on AD[31:0]. During all read data
phases the device asserts IRDY to indicate that it is
ready to accept the data.
When the PCnet-PCI II controller is the target of a transaction, it checks IRDY during all write data phases to determine if valid data is present on AD[31:0]. During all
AMD
read data phases the device checks IRDY to determine
if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND
tree testing.
LOCK
Lock Input
In slave mode, LOCK is an input to the PCnet-PCI II controller. A bus master can lock the device to guarantee an
atomic operation that requires multiple transactions.
The PCnet-PCI II controller will never assert LOCK as
a master.
When RST is active, LOCK is an input for NAND
tree testing.
PAR
Parity Input/Output
Parity is even parity across AD[31:0] and C/BE[3:0].
When the PCnet-PCI II controller is a bus master, it generates parity during the address and write data phases.
It checks parity during read data phases. When the
PCnet-PCI II controller operates in slave mode, it
checks parity during every address phase. When it is the
target of a cycle, it checks parity during write data
phases and it generates parity during read data phases.
When RST is active, PAR is an input for NAND
tree testing.
PERR
Parity Error Input/Output
During any slave write transaction and any master read
transaction, the PCnet-PCI II controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to ONE. During any master write transaction the PCnet-PCI II controller monitors PERR to see if
the target reports a data parity error.
When RST is active, PERR is an input for NAND
tree testing.
REQ
Bus Request Input/Output
The PCnet-PCI II controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the PCnet-PCI II controller does not
request the bus.
When RST is active, REQ is an input for NAND
tree testing.
RST
Reset Input
When RST is asserted low, then the PCnet-PCI II controller performs an internal system reset of the type
23Am79C970A
AMD
H_RESET (HARDWARE_RESET). RST must be held
for a minimum of 30 clock periods. While in the H_RESET state, the PCnet-PCI II controller will disable or
deassert all outputs. RST may be asynchronous to CLK
when asserted or deasserted. It is recommended that
the deassertion be synchronous to guarantee clean and
bounce free edge.
When RST is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the NOUT
output (pin 62).
P R E L I M I N A R Y
SERR
System Error Input/Output
During any slave transaction, the PCnet-PCI II controller
asserts SERR when it detects an address parity error
and reporting of the error is enabled by setting PERREN
(PCI Command register, bit 6) and SERREN (PCI Command register, bit 8) to ONE.
By default SERR is an open-drain output. For component test it can be programmed to be an active-high totem-pole output.
When RST is active, TRDY is an input for NAND
tree testing.
Board Interface
LED1
LED1 Output
This output is designed to directly drive an LED. By default, LED1 indicates receive activity on the network.
This pin can also be programmed to indicate other
network status (see BCR5). The LED1 pin polarity is
programmable, but by default, it is active LOW.
Note that the LED1 pin is multiplexed with the EESK and
SFBD pins.
LED2
LED2 Output
This output is designed to directly drive an LED. By default, LED2 indicates correct receive polarity on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR6). The LED2
pin polarity is programmable, but by default, it is
active LOW.
When RST is active, SERR is an input for NAND
tree testing.
STOP
Stop Input/Output
In slave mode, the PCnet-PCI II controller drives the
STOP signal to inform the bus master to stop the current
transaction. In bus master mode, the PCnet-PCI II controller checks STOP to determine if the target wants to
disconnect the current transaction.
When RST is active, STOP is an input for NAND
tree testing.
TRDY
Target Ready Input/Output
TRDY indicates the ability of the target of the transaction
to complete the current data phase. TRDY is used in
conjunction with IRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it
checks TRDY during all read data phases to determine if
valid data is present on AD[31:0]. During all write data
phases the device checks TRDY to determine if the target is ready to accept the data.
When the PCnet-PCI II controller is the target of a transaction, it asserts TRDY during all read data phases to indicate that valid data is present on AD[31:0]. During all
write data phases the device asserts TRDY to indicate
that it is ready to accept the data.
Note that the LED2 pin is multiplexed with the
SRDCLK pin.
LED3
LED3 Output
This output is designed to directly drive an LED. By default, LED3 indicates transmit activity on the network.
This pin can also be programmed to indicate other network status (see BCR7). The LED3 pin polarity is programmable, but by default, it is active LOW.
Note that the LED3 pin is multiplexed with the EEDO
and SRD pins.
Special attention must be given to the external circuitry
attached to this pin. When this pin is used to drive an
LED while an EEPROM is used in the system, then buffering is required between the LED3 pin and the LED circuit. If an LED circuit were directly attached to this pin, it
would create an I
by the serial EEPROM attached to this pin. If no
EEPROM is included in the system design, then the
LED3 signal may be directly connected to an LED without buffering. For more details regarding LED connection, see the section “LED Support”.
OL requirement that could not be met
SLEEP
Sleep Input
When SLEEP is asserted, the PCnet-PCI II controller
performs an internal system reset of the S_RESET type
and then proceeds into a power savings mode. All
PCnet-PCI II controller outputs will be placed in their
normal reset condition. All PCnet-PCI II controller inputs
24
Am79C970A
P R E L I M I N A R Y
will be ignored except for the SLEEP pin itself. Deassertion of SLEEP results in wake-up. The system must refrain from starting the network operations of the
PCnet-PCI II controller device for 0.5 s following the
deassertion of the SLEEP signal in order to allow internal analog circuits to stabilize.
Both CLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP command to
take effect.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the assertion of SLEEP until three clock cycles after the completion of a hardware reset operation.
The SLEEP pin must not be left unconnected. It should
be tied to VDD, if the power savings mode is not used.
XTAL1
Crystal Oscillator In Input
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. XTAL1
may alternatively be driven using an external 20 MHz
CMOS level clock signal. Refer to the section “External
Crystal Characteristics” for more details.
Note that when the PCnet-PCI II controller is in coma
mode, there is an internal 22 kΩ resistor from XTAL1 to
ground. If an external source drives XTAL1, some
power will be consumed driving this resistor. If XTAL1 is
driven LOW at this time power consumption will be minimized. In this case, XTAL1 must remain active for at
least 30 cycles after the assertion of SLEEP and
deassertion of REQ.
XTAL2
Crystal Oscillator Out Output
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. If an external clock source is used on XTAL1, then XTAL 2 should
be left unconnected.
Microwire EEPROM Interface
EECS
EEPROM Chip Select Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EECS is connected to the Microwire EEPROM chip select pin. It is controlled by either the PCnet-PCI II controller during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
AMD
EEDI
EEPROM Data In Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDI is connected to the Microwire EEPROM data input
pin. It is controlled by either the PCnet-PCI II controller
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.
Note that the EEDI pin is multiplexed with the
LNKST pin.
EEDO
EEPROM Data Out Input
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDO is connected to the Microwire EEPROM data output pin. It is controlled by either the PCnet-PCI II controller during command portions of a read of the entire
EEPROM, or indirectly by the host system by reading
from BCR19, bit 0.
Note that the EEDO pin is multiplexed with the LED3
and SRD pins.
EESK
EEPROM Serial clock Input/Output
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EESK is connected to the Microwire EEPROM clock pin.
It is controlled by either the PCnet-PCI II controller directly during a read of the entire EEPROM, or indirectly
by the host system by writing to BCR19, bit 1.
Note that the EESK pin is multiplexed with the LED1 and
SFBD pins.
The EESK pin is also used during EEPROM Auto-detection to determine whether or not an EEPROM is present
at the PCnet-PCI II controller Microwire interface. At the
rising edge of CLK during the last clock during which
RST is asserted, EESK is sampled to determine the
value of the EEDET bit in BCR19. A sampled HIGH
value means that an EEPROM is present, and EEDET
will be set to ONE. A sampled LOW value means that an
EEPROM is not present, and EEDET will be cleared to
ZERO. See the section “EEPROM Auto-Detection” for
more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in order to resolve the EEDET setting.
25Am79C970A
AMD
P R E L I M I N A R Y
Expansion ROM Interface
ERA[7:0]
Expansion ROM Address Output
These pins provide the address to the Expansion ROM.
When EROE is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion ROM
address. They must be latched externally. When EROE
is asserted and ERACLK is low, ERA[7:0] contain the
lower 8 bits of the Expansion ROM address.
All ERA outputs are forced to a constant level to conserve power while no access to the Expansion ROM
is performed.
ERACLK
Expansion ROM Address Clock Output
When EROE is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion
ROM address. ERACLK is used to latch the address
bits externally. Both ’373 (transparent latch) and ’374
(D flip-flop) types of address latch are supported.
ERD[7:0]
Expansion ROM Data Input
Data from the Expansion ROM is transferred on
ERD[7:0]. When EROE is high, the ERD[7:0] inputs are
internally disabled and can be left floating.
Note that the ERD[7:0] pins are multiplexed with the
GPSI interface.
EROE
Expansion ROM Output Enable Output
This signal is asserted when the Expansion ROM
is read.
Attachment Unit Interface
±
CI
Collision In Input
CI± is a differential input pair signaling the PCnet-PCI II
controller that a collision has been detected on the network media, indicated by the CI± inputs being driven
with a 10 MHz pattern of sufficient amplitude and pulse
width to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at pseudo ECL levels.
DI±
Data In Input
DI± is a differential input pair to the PCnet-PCI II controller carrying Manchester encoded data from the network.
Operates at pseudo ECL levels.
DO±
Data Out Output
DO± is a differential output pair from the PCnet-PCI II
controller for transmitting Manchester encoded data to
the network. Operates at pseudo ECL levels.
DXCVR
Disable Transceiver Output
The DXCVR signal is provided to power down an external transceiver or DC-to-DC converter in designs that
provide more than one network connection.
The polarity of the asserted state of the DXCVR output is
controlled by DXCVRPOL (BCR2, bit 4). By default, the
DXCVR output is high when asserted. When the
10BASE-T interface is the active network port, the
DXCVR output is always deasserted. When the AUI or
GPSI interface is the active network port, the assertion
of the DXCVR output is controlled by the setting of
DXCVRCTL (BCR2, bit 5).
Note that the DXCVR pin is multiplexed with the
NOUT pin.
Twisted Pair Interface
LNKST
Link Status Output
This output is designed to directly drive an LED. By default, LNKST indicates an active link connection on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The
LNKST pin polarity is programmable, but by default, it is
active LOW.
Note that the LNKST pin is multiplexed with the
EEDI pin.
RXD±
10BASE-T Receive Data Input
10BASE-T port differential receivers.
TXD±
10BASE-T Transmit Data Output
10BASE-T port differential drivers.
TXP±
10BASE-T Pre-Distortion Control Output
These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.
General Purpose Serial Interface
CLSN
Collision Input
CLSN is an input, indicating that a collision has occurred
on the network.
Note that the CLSN pin is multiplexed with the ERD3 pin.
RXCLK
Receive Clock Input
RXCLK is an input. Rising edges of the RXCLK signal
are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.
26
Am79C970A
P R E L I M I N A R Y
Note that the RXCLK pin is multiplexed with the
ERD1 pin.
RXDAT
Receive Data Input
RXDAT is an input. Rising edges of the RXCLK signal
are used to sample the data on the RXDAT input whenever the RXEN input is HIGH.
Note that the RXDAT pin is multiplexed with the
ERD0 pin.
RXEN
Receive Enable
Input
RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.
Note that the RXEN pin is multiplexed with the
ERD2 pin.
TXCLK
Transmit Clock Input
TXCLK is an input, providing a clock signal for MAC activity, both transmit and receive. Rising edges of the
TXCLK can be used to validate TXDAT output data.
Note that the TXCLK pin is multiplexed with the
ERD4 pin.
TXDAT
Transmit Data Output
TXDAT is an output, providing the serial bit stream for
transmission, including preamble, SFD data and FCS
field, if applicable. TXDAT floats when the GPSI interface is not enabled.
Note that the TXDAT pin is multiplexed with the
ERD7 pin.
TXEN
Transmit Enable Output
TXEN is an output, providing an enable signal for transmission. Data on the TXDAT pin is not valid unless the
TXEN signal is HIGH. TXEN should have an external
pull-down resistor attached (e.g. 3.3 kΩ) to ensure the
output is held inactive until the GPSI interface
is enabled.
Note that the TXEN pin is multiplexed with the ERD6 pin.
External Address Detection Interface
EAR
External Address Reject Low Input
The incoming frame will be checked against the internally active address detection mechanisms and the
AMD
result of this check will be ORd with the value on the
EAR pin. The EAR pin is defined as REJECT. The pin
value is “OR”ed with the internal address detection result to determine if the current frame should be accepted
or rejected.
The EAR pin is internally pulled-up and can be left unconnected, if the EADI interface is not used.
SFBD
Start Frame—Byte Delimiter Output
An initial rising edge on the SFBD signal indicates that a
start of frame delimiter has been detected. The serial bit
stream will follow on the SRD signal, commencing with
the destination address field. SFBD will go high for 4 bit
times (400 ns) after detecting the second ONE in the
SFD (Start of Frame Delimiter) of a received frame.
SFBD will subsequently toggle every 400 ns (1.25 MHz
frequency) with each rising edge indicating the first bit of
each subsequent byte of the received serial bit stream.
SFBD will be inactive during frame transmission.
Note that the SFBD pin is multiplexed with the EESK
and LED1 pins.
SRD
Serial Receive Data Output
SRD is the decoded NRZ data from the network. This
signal can be used for external address detection. When
the 10BASE-T port is selected, transitions on SRD will
only occur during receive activity. When the AUI or GPSI
port is selected, transitions on SRD will occur during
both transmit and receive activity.
Note that the SRD pin is multiplexed with the EEDO and
LED3 pins.
SRDCLK
Serial Receive Data Clock Output
Serial Receive Data is synchronous with reference to
SRDCLK. When the 10BASE-T port is selected, transitions on SRDCLK will only occur during receive activity.
When the AUI or GPSI port is selected, transitions
on SRDCLK will occur during both transmit and
receive activity.
Note that the SRDCLK pin is multiplexed with the
LED2 pin.
IEEE 1149.1 Test Access Port Interface
TCK
Test Clock Input
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10 MHz.
TCK has an internal pull-up resistor. The TCK input
27Am79C970A
AMD
P R E L I M I N A R Y
operates in the same signaling environment as the PCI
bus interface.
TDI
Test Data In Input
TDI is the test data input path to the PCnet-PCI II controller. The pin has an internal pull-up resistor. The TDI
input operates in the same signaling environment as the
PCI bus interface.
TDO
Test Data Out Output
TDO is the test data output path from the PCnet-PCI II
controller. The pin is tri-stated when the JTAG port is inactive. The TDO output operates in the same signaling
environment as the PCI bus interface.
TMS
Test Mode Select Input
A serial input bit stream on the TMS pin is used to define
the specific boundary scan test to be executed. The pin
has an internal pull-up resistor. The TMS input operates
in the same signaling environment as the PCI
bus interface.
Test Interface
NOUT
NAND Tree Out Output
When RST is asserted, the results of the NAND tree
testing can be observed on the NOUT pin.
Note that the NOUT pin is multiplexed with the
DXCVR pin.
avoid excessive noise on these lines. Refer to
Appendix B and the PCnet Family Board Design and
Layout Recommendations application note (PID
#19595A) for details.
AV
SS
Analog Ground (2 Pins) Power
There are two analog ground pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on these lines. Refer to Appendix B and
the PCnet Family Board Design and Layout
Recommendations application note (PID #19595A)
for details.
V
DD
Digital Power (6 Pins) Power
There are six power supply pins that are used by the internal digital circuitry. All V
pins must be connected to
DD
a +5 V supply.
V
DDB
I/O Buffer Power (4 Pins) Power
There are four power supply pins that are used by the
PCI bus input/output buffer drivers. In a system with 5 V
signaling environment, all V
pins must be connected
DDB
to a +5 V supply. In a system with 3.3 V signaling
nvironment, all V
pins must be connected to a
DDB
+3.3 V supply.
V
SS
Digital Ground (12 Pins) Ground
There are 12 ground pins that are used by the internal
digital circuitry.
Power Supply Pins
AV
DD
Analog Power (4 Pins) Power
There are four analog +5 V supply pins. Special attention should be paid to the printed circuit board layout to
28
Am79C970A
V
SSB
I/O Buffer Ground (8 Pins) Ground
There are 8 ground pins that are used by the PCI bus input/output buffer drivers.
P R E L I M I N A R Y
BASIC FUNCTIONS
System Bus Interface Function
The PCnet-PCI II controller is designed to operate as a
bus master during normal operations. Some slave I/O
accesses to the PCnet-PCI II controller are required in
normal operations as well. Initialization of the
PCnet-PCI II controller is achieved through a combination of PCI Configuration Space accesses, bus slave accesses, bus master accesses and an optional read of a
serial EEPROM that is performed by the PCnet-PCI II
controller. The EEPROM read operation is performed
through the Microwire interface. The ISO 8802-3
(IEEE/ANSI 802.3) Ethernet Address may reside within
the serial EEPROM. Some PCnet-PCI II controller configuration registers may also be programmed by the
EEPROM read operation.
The Address PROM, on-chip bus-configuration registers, and the Ethernet controller registers occupy 32
bytes of address space. Both, I/O and memory mapped
I/O access are supported. Base Address registers in the
PCI configuration space allow locating the address
space on a wide variety of starting addresses.
For diskless stations, the PCnet-PCI II controller supports an Expansion ROM of up to 64 Kbytes in size. The
host can map the Expansion ROM to any memory address that aligns to a 64K boundary by modifying the
Expansion ROM Base Address register in the PCI configuration space.
Software Interface
The software interface to the PCnet-PCI II controller is
divided into three parts. One part is the PCI configuration registers. They are used to identify the PCnet-PCI II
controller, and are also used to setup the configuration
of the device. The setup information includes the I/O or
memory mapped I/O base address, mapping of the
Expansion ROM and the routing of the PCnet-PCI II
controller interrupt channel. This allows for a
jumperless implementation.
The second portion of the software interface is the direct
access to the I/O resources of the PCnet-PCI II controller. The PCnet-PCI II controller occupies 32 bytes of ad-
AMD
dress space that must begin on a 32-byte block
boundary. The address space can be mapped into both
I/O or memory space (memory mapped I/O). The I/O
Base Address Register in the PCI Configuration Space
defines the start address of the address space if it is
mapped to I/O space. The Memory Mapped I/O Base
Address Register defines the start address of the address space if it is mapped to memory space. The
32-byte address space is used by the software to program the PCnet-PCI II controller operating mode, enable and disable various features, monitor operating
status, and request particular functions to be executed
by the PCnet-PCI II controller.
The third portion of the software interface is the descriptor and buffer areas that are shared between the software and the PCnet-PCI II controller during normal
network operations. The descriptor area boundaries are
set by the software and do not change during normal
network operations. There is one descriptor area for receive activity and there is a separate area for transmit
activity. The descriptor space contains relocatable
pointers to the network frame data and it is used to transfer frame status from the PCnet-PCI II controller to the
software. The buffer areas are locations that hold frame
data for transmission or that accept frame data that has
been received.
Network Interfaces
The PCnet-PCI II controller can be connected to an
802.3 network via one of three network interfaces. The
Attachment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection. The General Purpose Serial Interface
(GPSI) allows bypassing the Manchester Encoder/Decoder (MENDEC).
The PCnet-PCI II controller implements half or full-duplex Ethernet over all three network interfaces.
29Am79C970A
AMD
DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
P R E L I M I N A R Y
(BCR), the Address PROM (APROM) locations and the
Expansion ROM. The table below shows the response
of the PCnet-PCI II controller to each of the PCI com-
mands in slave mode.
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
Table 2. Slave Commands
C[3:0] Command Use
0000 Interrupt Acknowledge Not Used
0001 Special Cycle Not Used
0010 I/O Read Read of CSR, BCR and APROM
0011 I/O Write Write to CSR, BCR and APROM
0100 Reserved
0101 Reserved
0110 Memory Read Memory Mapped I/O Read of CSR, BCR and APROM
Read of the Expansion ROM
0111 Memory Write Memory Mapped I/O Write of CSR, BCR and APROM
Dummy Write to the Expansion ROM
1000 Reserved
1001 Reserved
1010 Configuration Read Read of the Configuration Space
1011 Configuration Write Write to the Configuration Space
1100 Memory Read Multiple Aliased to Memory Read
1101 Dual Address Cycle Not Used
1110 Memory Read Line Aliased to Memory Read
1111 Memory Write Invalidate Aliased to Memory Write
Slave Configuration Transfers
The host can access the PCnet-PCI II controller PCI
configuration space with a configuration read or write
command. The PCnet-PCI II controller will assert
DEVSEL during the address phase when IDSEL is asserted, AD[1:0] are both ZERO, and the access is a configuration cycle. AD[7:2] select the DWord location in the
configuration space. The PCnet-PCI II controller ignores AD[10:8], because it is a single function device.
AD[31:11] are don’t care.
The active bytes within a DWord are determined by the
byte enable signals. 8-bit, 16-bit and 32-bit transfers are
supported. DEVSEL is asserted two clock cycles after
the host has asserted FRAME. All configuration cycles
are of fixed length. The PCnet-PCI II controller will assert TRDY on the 4th clock of the data phase.
The PCnet-PCI II controller does not support burst
transfers for access to configuration space. When the
AD31 — AD11 AD10 — AD8 AD7 — AD2 AD1 AD0
Don’t care Don’t care DWord index 0 0
host keeps FRAME asserted for a second data phase,
the PCnet-PCI II controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET is on-going, the PCnet-PCI II controller will
terminate the access on the PCI bus with a disconnect/
retry response.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
bit 7), which is hardwired to ONE. The PCnet-PCI II controller is capable of detecting a configuration cycle even
when its address phase immediately follows the data
phase of a transaction to a different target without any
idle state in-between. There will be no contention on
the DEVSEL, TRDY and STOP signals, since the
PCnet-PCI II controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
30
Am79C970A
Loading...