AMD Advanced Micro Devices AM79C961AKCW, AM79C961AKC Datasheet
PRELIMINARY
Am79C961A
PCnet™-ISA II Jumperless, Full Duplex Single-Chip
Ethernet Controller for ISA
DISTINCTIVE CHARACTERISTICS
■
Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
■
Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
■
Supports full duplex operation on the
10BASE-T, AUI, and GPSI ports
■
Direct interface to the ISA or EISA bus
■
Pin compatible to Am79C961 PCnet-ISA+
Jumperless Single-Chip Ethernet Controller
■
Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
■
Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
■
Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
■
Dynamic transmit FCS generation
programmable on a frame-by-frame basis
■
Single +5 V power supply
■
Internal/external loopback capabilities
■
Supports 8K, 16K, 32K, and 64K Boot PROMs or
Flash for diskless node applications
■
Supports Microsoft’s Plug and Play System
configuration for jumperless designs
■
Supports staggered AT bus drive for reduced
noise and ground bounce
■
Supports 8 interrupts on chip
■
Look Ahead Packet Processing (LAPP)
allows protocol analysis to begin before
end of receive frame
■
Supports 4 DMA channels on chip
■
Supports 16 I/O locations
■
Supports 16 boot PROM locations
■
Provides integrated Attachment Unit Interface
(AUI) and 10B ASE-T transceiver with 2 modes of
port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
■
Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
■
Supports bus-master, programmed I/O, and
shared-memory architectures to fit in any PC
application
■
Supports edge and level-sensitive interrupts
■
DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
■
JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
■
Integrated Manchester Encoder/Decoder
■
Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
■
Supports LANCE General Purpose Serial
Interface (GPSI)
■
132-pin PQFP package
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 19364 Rev: A Amendment/+3
Issue Date: September 1996
PRELIMINARY
GENERAL DESCRIPTION
The PCnet-ISA II controller, a single-chip Ethernet controller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly
integrated 132-pin VLSI device is specifically designed
to reduce parts count and cost, and addresses applications where higher system throughput is desired. The
PCnet-ISA II controller is fabricated with AMD’s
advanced low-power CMOS process to provide low
standby current for power sensitive applications.
The PCnet-ISA II controller can be configured into one
of three different architecture modes to suit a particular
PC application. In the Bus Master mode, all transfers
are performed using the integrated DMA controller.
This configuration enhances system performance by
allowing the PCnet-ISA II controller to bypass the platform DMA controller and directly address the full 24-bit
memory space. The implementation of Bus Master
mode allows minimum parts count for the majority of
PC applications. The PCnet-ISA II can also be configured as a Bus Slave with either a Shared Memory or
Programmed I/O architecture for compatibility with
low-end machines, such as PC/XTs that do not support
Bus Masters, and high-end machines that require local
packet buffering for increased system latency.
The PCnet-ISA II controller is designed to directly interface with the ISA or EISA system bus. It contains an
ISA Plug and Play bus interf ace unit, DMA Buffer Management Unit, 802.3 Media Access Control function,
individual 136-byte transmit and 128-byte receive
FIFOs, IEEE 802.3 defined Attachment Unit Interface
(AUI), and a Twisted Pair Transceiver Media Attachment Unit. Full duplex network operation can be
enabled on any of the device’s network ports. The
PCnet-ISA II controller is also register compatible with
the LANCE (Am7990) Ethernet controller and
PCnet-ISA. The DMA Buffer Management Unit supports the LANCE descriptor software model. External
remote boot and Ethernet physical address PROMs
and Electrically Erasable Proms are also supported.
This advanced Ethernet controller has the built-in
capability of automatically selecting either the AUI port
or the Twisted Pair transceiver. Only one interface is
active at any one time. The individual 136-byte transmit
and 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission and reception, and minimizing intervention
during normal network error recovery. The integrated
Manchester encoder/decoder eliminates the need for
an external Serial Interface Adapter (SIA) in the node
system. If support for an external encoding/decoding
scheme is desired, the embedded General Purpose
Serial Interface (GPSI) allows direct access to/from the
MAC. In addition, the device provides programmable
on-chip LED drivers for transmit, receive, collision,
receive polarity, link integrity and activity, or jabber
status. The PCnet-ISA II controller also provides an
External Address Detection InterfaceTM (EADITM) to
allow external hardware address filtering in internetworking applications.
RELATED PRODUCTS
Part No. Description
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C981 Integrated Multiport Repeater Plus (IMR+)
Am79C987 Hardware Implemented Management Information Base (HIMIB)
Am79C940 Media Access Controller for Ethernet (MACE)
Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961 PCnet-ISA Jumperless Single-Chip Ethernet Controller (for ISA bus)
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386, 486, VL local buses)
Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet-SCSI Combination Single-Chip Ethernet and SCSI Controller (for PCI bus)
2 Am79C961A
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in se ver al packages and operating r anges. The order number (Valid Combination) is f ormed
by a combination of:
AM79C961A K C \W
ALTERNATE PACKAGING OPTION
\W=Trimmed and Formed (PQB132)
OPTIONAL PROCESSING
Blank=Standard Processing
TEMPERATURE RANGE
C=Commercial (0
P ACKA GE TYPE (per Prod. Nomenclature/16-038)
K=Molded Carrier Ring Plastic Quad Flat Pack
(PQB132)
SPEED
Not Applicable
°C to +70°C)
DEVICE NUMBER/DESCRIPTION
Am79C961A
PCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA
Valid Combinations
AM79C961A KC, KC\W
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
Am79C961A 3
PRELIMINARY
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
RELATED PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
STANDARD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CONNECTION DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN DESIGNATIONS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
LISTED BY PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PIN DESCRIPTIONS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
IEEE P996 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BOARD INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PLUG AND PLAY ISA CARD STATE TRANSITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
BLOCK DIAGRAM: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CONNECTION DIAGRAMS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PIN DESCRIPTIONS: BUS SLAVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PIN DESCRIPTIONS: NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
AUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
TWISTED PAIR INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PIN DESCRIPTIONS: POWER SUPPLIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
CONNECTION DIAGRAM (TQFP 144). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PIN DESCRIPTIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PIN DESCRIPTIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . . . . . . .34
LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
IMPORTANT NOTE ABOUT THE EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AUTO-CONFIGURATION PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
INITIATION KEY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
ISOLATION PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
HARDWARE PROTOCOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
SOFTWARE PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
PLUG AND PLAY CARD CONTROL REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . .45
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
AMD DEVICE DRIVER COMPATIBLE EEPROM BYTE MAP . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PLUG AND PLAY REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
PCNET-ISA II’S LEGACY BIT FEATURE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
P
LUG & PLAY REGISTER LOCATIONS DETAILED DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VENDOR DEFINED BYTE (PNP 0XF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
CHECKSUM FAILURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
USE WITHOUT EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
EXTERNAL SCAN CHAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4 Am79C961A
PRELIMINARY
FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
OPTIONAL IEEE ADDRESS PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
EISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DMA TRANSFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
1. INITIALIZATION BLOCK DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2. DESCRIPTOR DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3. FIFO DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
BUFFER MANAGEMENT UNIT (BMU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
REINITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
DESCRIPTOR RINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
DESCRIPTOR RINGS ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
MEDIA ACCESS CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION. . . . . . . . . . . . . . . . . . . . . . . .61
MANCHESTER ENCODER/DECODER (MENDEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DATA DECODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
JITTER TOLERANCE DEFINITION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ATTACHMENT UNIT INTERFACE (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
POLARITY DETECTION AND REVERSAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
COLLISION DETECT FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . .69
JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
POWER DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
FULL DUPLEX OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
EADI (EXTERNAL ADDRESS DETECTION INTERFACE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
GPSI (GENERAL PURPOSE SERIAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
OTHER DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
POWER SAVING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
ACCESS OPERATIONS (SOFTWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Am79C961A 5
PRELIMINARY
I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
I/O REGISTER ACCESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
IEEE ADDRESS ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
BOOT PROM ACCESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
STATIC RAM ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
BUS CYCLES (HARDWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ADDRESS PROM CYCLES EXTERNAL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ADDRESS PROM CYCLES USING EEPROM DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
ETHERNET CONTROLLER REGISTER CYCLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
TRANSMIT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TRANSMIT FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
AUTOMATIC PAD GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
TRANSMIT FCS GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
TRANSMIT EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
RECEIVE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
RECEIVE FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AUTOMATIC PAD STRIPPING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
RECEIVE FCS CHECKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
RECEIVE EXCEPTION CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
MAGIC PACKET OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
MAGIC PACKET MODE ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
MAGIC PACKET RECEIVE INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
LOOPBACK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
PCNET-ISA II CONTROLLER REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
REGISTER ACCESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
RAP: REGISTER ADDRESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
CONTROL AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
CSR0: PCnet-ISA II Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
CSR4: Test and Features Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
CSR5: Control 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
CSR6: RCV/XMT Descriptor Table Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
CSR8: Logical Address Filter, LADRF[15:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
CSR9: Logical Address Filter, LADRF[31:16]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
CSR10: Logical Address Filter, LADRF[47:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
CSR11: Logical Address Filter, LADRF[63:48]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
CSR15: Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
CSR16: Initialization Block Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
CSR18-19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
CSR20-21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
CSR22-23: Next Receive Buffer Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR24-25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR26-27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR28-29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR30-31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR34-35: Current Transmit Descriptor Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR36-37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR38-39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
CSR40-41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
6 Am79C961A
PRELIMINARY
CSR42-43: Current Transmit Status and Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR44-45: Next Receive Status and Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR47: Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR48-49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR50-51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
CSR52-53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR54-55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR56-57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR58-59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR60-61: Previous Transmit Descriptor Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR62-63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR64-65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR66-67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
CSR70-71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR76: Receive Ring Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
CSR84-85: DMA Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR88-89: Chip ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR94: Transmit Time Domain Reflectometry Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CSR96-97: Bus Interface Scratch Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR98-99: Bus Interface Scratch Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR104-105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR108-109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR112: Missed Frame Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
ISA BUS CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
ISACSR0: Master Mode Read Active/SRAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
ISACSR1: Master Mode Write Active/SRAM Address Pointer . . . . . . . . . . . . . . . . . . . . . . .104
ISACSR2: Miscellaneous Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
ISACSR4: LED0 Status (Link Integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
ISACSR5: LED1
ISACSR6: LED2 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
ISACSR7: LED3 Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
ISACSR8: Software Configuration Register (Read-Only Register) . . . . . . . . . . . . . . . . . . . .110
ISACSR9: Miscellaneous Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
RDRA and TDRA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
LADRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
PADR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
RMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
RMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
TMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
TMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
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TMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
TMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Ethernet Controller Registers (Accessed via RDP Port). . . . . . . . . . . . . . . . . . . . . . . . . . . .117
REGISTER SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port). . . . . . . . . . . . . . . . . .118
SYSTEM APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
ISA Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Compatibility Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Shared Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Optional Address PROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Boot PROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Static RAM Interface (for Shared Memory Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
AUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10BASE-T Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
OPERATING RANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . .124
SWITCHING CHARACTERISTICS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE . . . . . . . . . . . . . . . . .130
SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE . . . . . . . . . . . . . . . .130
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE. . . . . . . . . . . . .134
SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE. . . . . . . . . . . .134
SWITCHING CHARACTERISTICS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . .135
SWITCHING CHARACTERISTICS: GPSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
SWITCHING CHARACTERISTICS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
SWITCHING WAVEFORMS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
SWITCHING WAVEFORMS: SHARED MEMORY MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
SWITCHING WAVEFORMS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
SWITCHING WAVEFORMS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
SWITCHING WAVEFORMS: AUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
SWITCHING WAVEFORMS: 10BASE-T INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
PQB132 Plastic Quad Flat Pack Trimmed and Formed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
PQB132 Molded Carrier Ring Plastic Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
APPENDIX A: PCNET-II COMPATIBLE MEDIA INTERFACE MODULES. . . . . . . . . . . . . . . . . . . . . . . .172
PCnet-ISA II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . .172
PCnet-ISA II Compatible AUI Isolation Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
PCnet-ISA II Compatible DC/DC Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
APPENDIX B: LAYOUT RECOMMENDATIONS FOR REDUCING NOISE. . . . . . . . . . . . . . . . . . . . . . . .174
DECOUPLING LOW-PASS R/C FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
Digital Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
Analog Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
AVSS1 and AVDD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
AVSS2 and AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
AVSS2 and AVDD2/AVDD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
APPENDIX C: SAMPLE PLUG AND PLAY CONFIGURATION RECORD . . . . . . . . . . . . . . . . . . . . . . . .176
SAMPLE CONFIGURATION FILE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
APPENDIX D: ALTERNATIVE METHOD FOR INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
8 Am79C961A
PRELIMINARY
APPENDIX E: INTRODUCTION OF THE LOOK AHEAD PACKET PROCESSING
(LAPP) CONCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Outline of the LAPP Flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
SETUP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
FLOW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
LAPP Enable Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
LAPP Enable Rules for Parsing of Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
APPENDIX F: SOME CHARACTERISTICS OF THE XXC56 SERIAL EEPROM . . . . . . . . . . . . . . . . . . .188
SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE . . . . . . . . . . .188
INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Am79C961A 9
PRELIMINARY
BLOCK DIAGRAM: BUS MASTER MODE
AEN
[3, 5–7]
DACK
DRQ[3, 5–7]
IOCHRDY
IOCS16
IOR
IOW
IRQ[3, 4, 5, 9,
10, 11, 12]
MASTER
MEMR
MEMW
REF
RESET
SBHE
BALE
SD[0-15]
LA[17-23]
SA[0-19]
ISA Bus
Interface
Unit
Buffer
Management
Unit
RCV
FIFO
XMT
FIFO
FIFO
Control
802.3
MAC
Core
Encoder/
Decoder
(PLS) &
AUI Port
10BASE-T
MAU
Private
Bus
Control
DXCVR/EAR
CI+/–
DI+/–
XTAL1
XTAL2
DO+/–
RXD+/–
TXD+/–
TXPD+/–
IRQ15/APCS
BPCS
LED[0–3]
PRDB[0–7]
SLEEP
SHFBUSY
EEDO
EEDI
EESK
EECS
EEPROM
DVDD[1-7]
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
Interface
Unit
JTAG
Port
Control
TDO
TMS
TDI
TCK
19364A-1
10 Am79C961A
PRELIMINARY
CONNECTION DIAGRAMS: BUS MASTER MODE
DVDD2
TCK
TMS
TDO
TDI
EECS
BPCS
SHFBUSY
PRDB0/EESK
PRDB1/EEDI
PRDB2/EEDO
PRDB3
DVSS2
PRDB4
PRDB5
PRDB6
PRDB7
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
47
48
49
116
50
DVSS3
1
2MASTER
3DRQ7
4DRQ6
5DRQ5
6DVSS10
7DACK7
8DACK6
9DACK5
10LA17
11LA18
12LA19
13LA20
14DVSS4
15LA21
16LA22
17LA23
18SBHE
19DVDD3
20SA0
21SA1
22SA2
23DVSS5
24SA3
25SA4
26SA5
27SA6
28SA7
29SA8
30SA9
31DVSS6
32SA10
33SA11
34
35
36
37
39
42
43
44
45
Top Side View
46
DVDD1
LED0
115
114
51
52
LED1
DVSS1
113
112
53
54
LED2
LED3
111
110
55
DXCVR/EAR
109
AVDD2
CI+
108
107
59
58
CI–
106
60
DI+
105
61
DI–
104
62
AVDD1
DO+
103
102
63
64
DO–
101
65
AVSS1
100
XTAL299
AVSS298
XTAL197
AVDD396
TXD+95
TXPD+94
TXD–93
TXPD–92
AVDD491
RXD+90
RXD–89
DVSS1388
SD1587
SD786
SD1485
SD684
DVSS983
SD1382
SD581
SD1280
SD479
DVDD778
SD1177
SD376
SD1075
SD274
DVSS873
SD972
SD171
SD870
SD069
SLEEP68
DVDD667
66
SA12
DVDD4
SA13
SA1438SA15
SA1640SA1741SA18
DVSS7
SA19
AEN
IOCHRDY
MEMR
MEMW
DVSS11
IRQ15/APCS
IRQ12/FLASHWE
IRQ11
DVDD5
IRQ10
IOCS16
IRQ356IRQ457IRQ5
BALE
REF
DRQ3
DACK3
DVSS12
IOR
IOW
IRQ9
RESET
Am79C961A 11
19364A-2
PRELIMINARY
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Pin Number
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1 DVSS3 34 DVDD4 67 DVDD6 100 AVSS1
2 MASTER
3 DRQ7 36 SA13 69 SD0 102 DO+
4 DRQ6 37 SA14 70 SD8 103 AVDD1
5 DRQ5 38 SA15 71 SD1 104 DI–
6 DVSS10 39 DVSS7 72 SD9 105 DI+
7DACK7 40 SA16 73 DVSS8 106 CI–
8DACK6 41 SA17 74 SD2 107 CI+
9DACK5 42 SA18 75 SD10 108 AVDD2
10 LA17 43 SA19 76 SD3 109 DXCVR/EAR
11 LA18 44 AEN 77 SD11 110 LED3
12 LA19 45 IOCHRDY 78 DVDD7 111 LED2
13 LA20 46 MEMW 79 SD4 112 DVSS1
14 DVSS4 47 MEMR 80 SD12 113 LED1
15 LA21 48 DVSS11 81 SD5 114 LED0
16 LA22 49 IRQ15/APCS 82 SD13 115 DVDD1
17 LA23 50 IRQ12/FlashWE 83 DVSS9 116 PRDB7
18 SBHE 51 IRQ11 84 SD6 117 PRDB6
19 DVDD3 52 DVDD5 85 SD14 118 PRDB5
20 SA0 53 IRQ10 86 SD7 119 PRDB4
21 SA1 54 IOCS16 87 SD15 120 DVSS2
22 SA2 55 BALE 88 DVSS13 121 PRDB3
23 DVSS5 56 IRQ3 89 RXD– 122 PRDB2/EEDO
24 SA3 57 IRQ4 90 RXD+ 123 PRDB1/EEDI
25 SA4 58 IRQ5 91 AVDD4 124 PRDB0/EESK
26 SA5 59 REF 92 TXPD– 125 SHFBUSY
27 SA6 60 DVSS12 93 TXD– 126 BPCS
28 SA7 61 DRQ3 94 TXPD+ 127 EECS
29 SA8 62 DACK3 95 TXD+ 128 TDI
30 SA9 63 IOR 96 AVDD3 129 TDO
31 DVSS6 64 IOW 97 XTAL1 130 TMS
32 SA10 65 IRQ9 98 AVSS2 131 TCK
33 SA11 66 RESET 99 XTAL2 132 DVDD2
35 SA12 68 SLEEP 101 DO–
12 Am79C961A
PRELIMINARY
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Pin Number
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
AEN 44 DVSS12 60 LED2 111 SA6 27
AVDD1 103 DVSS13 88 LED3 110 SA7 28
AVDD2 108 DVSS2 120 MASTER
AVDD3 96 DVSS3 1 MEMR 47 SA9 30
AVDD4 91 DVSS4 14 MEMW 46 SBHE 18
AVSS1 100 DVSS5 23 PRDB0/EESK 124 SD0 69
AVSS2 98 DVSS6 31 PRDB1/EEDI 123 SD1 71
BALE 55 DVSS7 39 PRDB2/EEDO 122 SD10 75
BPCS 126 DVSS8 73 PRDB3 121 SD11 77
CI– 106 DVSS9 83 PRDB4 119 SD12 80
CI+ 107 DXCVR/EAR 109 PRDB5 118 SD13 82
DACK3 62 EECS 127 PRDB6 117 SD14 85
DACK5 9 IOCHRDY 45 PRDB7 116 SD15 87
DACK6 8 IOCS16 54 REF 59 SD2 74
DACK7 7 IOR 63 RESET 66 SD3 76
DI– 104 IOW 64 RXD– 89 SD4 79
DI+ 105 IRQ10 53 RXD+ 90 SD5 81
DO– 101 IRQ11 51 SA0 20 SD6 84
DO+ 102 IRQ12/FlashWE 50 SA1 21 SD7 86
DRQ3 61 IRQ15/APCS 49 SA10 32 SD8 70
DRQ5 5 IRQ3 56 SA11 33 SD9 72
DRQ6 4 IRQ4 57 SA12 35 SHFBUSY 125
DRQ7 3 IRQ5 58 SA13 36 SLEEP 68
DVDD1 115 IRQ9 65 SA14 37 TCK 131
DVDD2 132 LA17 10 SA15 38 TDI 128
DVDD3 19 LA18 11 SA16 40 TDO 129
DVDD4 34 LA19 12 SA17 41 TMS 130
DVDD5 52 LA20 13 SA18 42 TXD– 93
DVDD6 67 LA21 15 SA19 43 TXD+ 95
DVDD7 78 LA22 16 SA2 22 TXPD– 92
DVSS1 112 LA23 17 SA3 24 TXPD+ 94
DVSS10 6 LED0 114 SA4 25 XTAL1 97
DVSS11 48 LED1 113 SA5 26 XTAL2 99
2 SA8 29
Am79C961A 13
PRELIMINARY
PIN DESIGNATIONS: BUS MASTER MODE
Listed by Group
Pin Name Pin Function I/O Driver
ISA Bus Interface
AEN
BALE
ACK[3, 5–7]
D
DRQ[3, 5–7]
IOCHRDY
IOCS16
IOR
IOW
IRQ[3, 4, 5, 9, 10, 11, 12, 15]
LA[17-23]
MASTER
MEMR
MEMW
REF
RESET
SA[0 –19]
SBHE
SD[0 –15]
Board Interfaces
IRQ15/APCS
BPCS
DXCVR/EAR
LED0
LED1
LED2
LED3
PRDB[3–7]
SLEEP
XTAL1
XTAL2
SHFBUSY
PRDB(0)/EESK
PRDB(1)/EEDI
PRDB(2)/EEDO
EECS
Address Enable
Bus Address Latch Enable
DMA Acknowledge
DMA Request
I/O Channel Ready
I/O Chip Select 16
I/O Read Select
I/O Write Select
Interrupt Request
Unlatched Address Bus
Master Transfer in Progress
Memory Read Select
Memory Write Select
Memory Refresh Active
System Reset
System Address Bus
System Byte High Enable
System Data Bus
IRQ15 or Address PROM Chip Select
Boot PROM Chip Select
Disable Transceiver
LED0/LNKST
LED1/SFBD/RCV A CT
LED2/SRD/RXDATPOL
LED3/SRDCLK/XMTACT
PROM Data Bus
Sleep Mode
Crystal Input
Crystal Output
Read access from EEPROM in process
Serial Shift Clock
Serial Shift Data In
Serial Shift Data Out
EEPROM Chip Select
I/O
I/O
O
O
I/O
O
O
O
I/O
I/O
I/O
O
O
I/O
O
O
O
O
I/O
O
I/O
I/O
I/O
O
I
I
I
TS3
OD3
OD3
I
I
TS3/OD3
TS3
OD3
TS3
TS3
I
I
TS3
TS3
TS3
TS1
TS1
TS1
TS2
TS2
TS2
TS2
TS1
I
I
14 Am79C961A
PRELIMINARY
PIN DESIGNATIONS: BUS MASTER MODE (continued)
Listed by Group
Pin Name Pin Function I/O Driver
Attachment Unit Interface (AUI)
CI±
DI±
DO±
Twisted Pair Transceiver Interface (10BASE-T)
RXD±
TXD±
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
TDI
TDO
TMS
Power Supplies
AVDD
AVSS
DVDD
DVSS
10BASE-T Predistortion Control
Collision Inputs
Receive Data
Transmit Data
10BASE-T Receive Data
10BASE-T T r ansmit Data
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Analog Power [1-4]
Analog Ground [1-2]
Digital Power [1-7]
Digital Ground [1-13]
I
I
O
I
O
O
I
I
O
I
TS2
Output Driver Types
Name Type IOL (mA) IOH (mA) pF
TS1 Tri-State 4 –1 50
TS2 Tri-State 12 –4 50
TS3 Tri-State 24 –3 120
OD3 Open Drain 24 –3 120
Am79C961A 15
PRELIMINARY
PIN DESCRIPTION: BUS MASTER MODE
These pins are part of the bus master mode. In order to
understand the pin descriptions, definition of some
terms from a draft of IEEE P996 are included.
IEEE P996 Terminology
Alternate Master: Any device that can take control of
the bus through assertion of the MASTER signal. It has
the ability to generate addresses and bus control signals in order to perform bus operations. All Alter nate
Masters must be 16 bit devices and drive SBHE.
Bus Ownership: The Current Master possesses bus
ownership and can assert any bus control, address and
data lines.
Current Master: The Permanent Master, Temporary
Master or Alternate Master which currently has ownership of the bus.
Permanent Master: Each P996 bus will hav e a de vice
known as the Permanent Master that provides certain
signals and bus control functions as described in Section 3.5 (of the IEEE P996 spec.), “P ermanent Master”.
The Permanent Master function can reside on a Bus
Adapter or on the backplane itself.
Temporary Master: A de vice that is capable of generating a DMA request to obtain control of the bus and
directly asserting only the memory and I/O strobes
during bus transfer. Addresses are generated by the
DMA device on the Permanent Master.
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus perf orms
an I/O access to the device.
Input
BALE
Used to latch the LA20–23 address lines.
DACK 3, 5-7
DMA Acknowledge
Asserted LOW when the Permanent Master acknowledges a DMA request. When DACK is asserted the
PCnet-ISA II controller becomes the Current Master by
asserting the MASTER signal.
Input
DRQ 3, 5-7
DMA Request
When the PCnet-ISA II controller needs to perform a
DMA transfer, it asserts DRQ. The Permanent Master
acknowledges DRQ with the assertion of DACK. When
the PCnet-ISA II does not need the bus it desserts
DRQ. The PCnet-ISA II provides for fair bus bandwidth
sharing between two bus mastering devices on the ISA
bus through an adaptive delay which is inserted
Input/Output
between back-to-back DMA requests. See the
Back-to-Back DMA Requests section for details.
Because of the operation of the Plug and Play registers, the DMA Channels on the PCnet-ISA II must be
attached to the specific DRQ and DACK signals on the
PC/AT bus as indicated by the pin names.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA II controller is being accessed,
IOCHRDY HIGH indicates that valid data exists on the
data bus for reads and that data has been latched for
writes. When the PCnet-ISA II controller is the Current
Master on the ISA bus, it extends the b us cycle as long
as IOCHRDY is LOW.
Input/Output
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive the IOCS16 pin LOW
to indicate that the chip supports a 16-bit operation at
this address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
The PCnet-ISA II controller follows the IEEE P996 specification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no dependency on IOR, or IOW ; howe ver, some PC/A T clone systems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since
data is moved by memory cycles there is virtually no performance loss incurred by running 8-bit I/O and compatibility problems are virtually eliminated. The PCnet-ISA II
controller can be configured to run 8-bit-only I/O by
clearing Bit 0 in Plug and Play register F0.
Output
IOR
I/O Read
IOR is driven LOW by the host to indicate that an Input/
Output Read operation is taking place. IOR is only v alid
if the AEN signal is LOW and the external address
matches the PCnet-ISA II controller’s predefined I/O
address location. If valid, IOR indicates that a slave
read operation is to be performed.
Input
IOW
I/O Write
IOW is driven LOW b y the host to indicate that an Input/
Output Write operation is taking place. IO W is only valid
if AEN signal is LOW and the external address matches
the PCnet-ISA II controller’s predefined I/O address
location. If valid, IOW indicates that a slave write operation is to be performed.
Input
16 Am79C961A
PRELIMINARY
IRQ 3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.
All status flags have a mask bit which allows for suppression of IRQ assertion. These flags have the
following meaning:
BABL Babble
RCVCCO Receive Collision Count Overflow
JAB Jabber
MISS Missed Frame
MERR Memory Error
MPCO Missed Packet Count Overflow
RINT Receive Interrupt
IDON Initialization Done
TXDATSTRT Transmit Start
Because of the operation of the Plug and Play registers, the interrupts on the PCnet-ISA II must be
attached to specific IRQ signals on the PC/AT bus.
Output
LA17-23
Unlatched Address Bus
The unlatched address bus is driven by the PCnet-ISA
II controller during bus master cycle.
The functions of these unlatched address pins will
change when GPSI mode is invoked. The following
table shows the pin configuration in GPSI mode. Please
refer to the section on General Purpose Serial Interface
for detailed information on accessing this mode.
Pin
Number
10 LA17 RXDAT
11 LA18 SRDCLK
12 LA19 RXCRS
13 LA20 CLSN
15 LA21 STDCLK
16 LA22 TXEN
17 LA23 TXDAT
Pin Function in Bus
Master Mode
Input/Output
Pin Function in
GPSI Mode
MASTER
Master Mode
This signal indicates that the PCnet-ISA II controller
has become the Current Master of the ISA bus. After
the PCnet-ISA II controller has received a DMA
Acknowledge (DACK) in response to a DMA Request
Input/Output
(DRQ), the Ethernet controller asserts the MASTER
signal to indicate to the Permanent Master that the
PCnet-ISA II controller is becoming the Current Master.
MEMR
Memory Read
MEMR goes LOW to perform a memory read operation.
Input/Output
MEMW
Memory Write
MEMW goes LOW to perform a memory write
operation.
Input/Output
REF
Memory Refresh
When REF is asserted, a memory refresh is active. The
PCnet-ISA II controller uses this signal to mask inadvertent DMA Acknowledge assertion during memory
refresh periods. If DACK is asserted when REF is
active, D ACK assertion is ignored. REF is monitored to
eliminate a bus arbitration problem observed on some
ISA platforms.
Input
RESET
Reset
When RESET is asserted HIGH the PCnet-ISA II controller performs an internal system reset. RESET must
be held for a minimum of 10 XTAL1 periods before
being deasserted. While in a reset state , the PCnet-ISA
II controller will tristate or deassert all outputs to predefined reset levels. The PCnet-ISA II controller resets
itself upon power-up.
Input
SA0-19
System Address Bus
This bus contains address information, which is stable
during a bus operation, regardless of the source.
SA17-19 contain the same values as the unlatched
address LA17-19. When the PCnet-ISA II controller is
the Current Master, SA0-19 will be driven actively.
When the PCnet-ISA II controller is not the Current
Master, the SA0-19 lines are continuously monitored to
determine if an address match exists for I/O slave
transfers or Boot PROM accesses.
Input/Output
SBHE
System Byte High Enable
This signal indicates the high byte of the system data
bus is to be used. SBHE is driven by the PCnet-ISA II
controller when performing bus mastering operations.
Input/Output
SD0-15
System Data Bus
These pins are used to transfer data to and from the
PCnet-ISA II controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA II control-
Input/Output
Am79C961A 17
PRELIMINARY
ler when performing bus master writes and slave read
operations. Likewise, the data on SD0-15 is latched by
the PCnet-ISA II controller when performing bus
master reads and slave write operations.
Board Interface
IRQ12/FlashWE
Flash Write Enable
Optional interface to the Flash memory boot PROM
Write Enable.
Output
IRQ15/APCS
Address PROM Chip Select
When programmed as APCS in Plug and Play Register
F0, this signal is asserted when the external Address
PROM is read. When an I/O read operation is
performed on the first 16 bytes in the PCnet-ISA II controller’s I/O space, APCS is asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA II controller buffers the contents of the
PROM data bus and drives them on the lower eight bits
of the System Data Bus.
When programmed to IRQ15 (default), this pin has the
same function as IRQ 3, 4, 5, 9, 10, 11, or 12.
Output
BPCS
Boot PROM Chip Select
This signal is asserted when the Boot PROM is read. If
SA0-19 lines match a predefined address block and
MEMR is active and REF inactive , the BPCS signal will
be asserted. The outputs of the external Boot PROM
drive the PROM Data Bus. The PCnet-ISA II controller
buffers the contents of the PROM data bus and drives
them on the lower eight bits of the System Data Bus.
Output
DXCVR/EAR
Disable T ransceiver/
External Address Reject
This pin can be used to disable external transceiver
circuitry attached to the AUI interface when the internal
10BASE-T port is active. The polarity of this pin is set
by the DXCVRP bit (PnP register 0xF0, bit 5). When
DXCVRP is cleared (default), the DXCVR pin is driven
HIGH when the Twisted Pair port is active or SLEEP
mode has been entered and driven LOW when the A UI
port is active. When DXCVRP is set, the DXCVR pin is
driven LOW when the Twisted Pair por t is active or
SLEEP mode has been entered and driven HIGH when
the AUI port is active.
Input/Output
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the internally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and
timing of this signal).
LEDO-3
LED Drivers
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section
Bus Configuration Registers
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0
continues to indicate 10BASE-T Link Status.
LED EADI Function
1 SF/BD
2 SRD
3 SRDCLK
Output
The ISA
) and they are active LO W.
PRDB3-7
Private Data Bus
This is the data bus for the Boot PROM and the
Address PROM.
Input/Output
PRDB2/EEDO
Private data bus bit 2/Data Out
A multifunction pin which serves as PRDB2 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA OUT from the EEPROM.
Input/Output
PRDB1/EEDI
Private data bus bit 1/Data In
A multifunction pin which serves as PRDB1 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA In to the EEPROM.
Input/Output
PRDB0/EESK
Private data bus bit 0/
Serial Clock
A multifunction pin which serves as PRDB0 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become Serial Clock to the EEPROM.
Input/Output
18 Am79C961A
PRELIMINARY
SHFBUSY
Shift Busy
This pin indicates that a read from the exter nal
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to V
through a 10K Ω pull-up resistor.
Input/Output
CC
EECS
EEPROM CHIP SELECT
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
Output
SLEEP
Sleep
When SLEEP pin is asserted (active LOW), the
PCnet-ISA II controller performs an internal system
reset and proceeds into a power savings mode. All
Input
outputs will be placed in their normal reset condition.
All PCnet-ISA II controller inputs will be ignored except
for the SLEEP
in the device waking up. The system must delay the
starting of the network controller by 0.5 seconds to
allow internal analog circuits to stabilize.
pin itself. Deassertion of SLEEP results
XTAL1
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on Exter nal
Crystal Characteristics for more details.
Input
XTAL2
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Output
Am79C961A 19
PRELIMINARY
Power up
RESET_DRV
Set CSN = 0
State Active Commands
State Active Commands
Reset
Isolation
Wait for Key
Set RD_DATA Port
Serial Isolation
Wake[CSN]
Wait for Key
State Active Commands
Sleep
Lose serial location OR
(WAKE <> CSN)
no active commands
Initiation Key
Reset
Wait for Key
Wake[CSN]
Set CSN
WAKE <> CSN
Config
State Active Commands
Reset
Wait for Key
Wake[CSN]
Resource Data
Status
Logical Device
I/O Range Check
Activate
Configuration Registers
Notes:
1. CSN = Card Select Number.
2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to
zero. All logical devices are set to their power-up configuration values.
3. The Wait for Key command causes a state transition from the current state to Wait for Key.
Plug and Play ISA Card State Transitions
20 Am79C961A
PRELIMINARY
BLOCK DIAGRAM: BUS SLAVE MODE
AEN
IOCHRDY
RCV
FIFO
802.3
MAC
Core
DXCVR/EAR
IOR
IOW
IRQ[3, 4, 5, 9,
10, 11, 12]
IOCS16
MEMR
MEMW
REF
RESET
SA[0-15]
SBHE
SD[0-15]
SMA
SLEEP
BPAM
SMAM
SHFBUSY
EEDO
EEDI
EESK
EECS
ISA Bus
Interface
Unit
Buffer
Management
Unit
EEPROM
Interface
Unit
XMT
FIFO
FIFO
Control
Encoder/
Decoder
(PLS) &
AUI Port
10BASE-T
MAU
Private
Bus
Control
JTAG
Port
Control
CI+/DI+/-
XTAL1
XTAL2
DO+/-
RXD+/TXD+/-
TXPD+/-
IRQ15/APCS
BPCS
LED[0-3]
PRAB[0-15]
PRDB[0-7]
OE
SR
SRWE
TDO
TMS
TDI
TCK
DVDD[1-7]
DVSS[1-13]
AVDD[1-4]
AVSS[1-2]
19364A-3
Am79C961A 21
PRELIMINARY
CONNECTION DIAGRAMS: BUS SLAVE MODE
DVDD2
TCK
TMS
TDO
TDI
EECS
BPCS
SHFBUSY
PRDB0/EESK
PRDB1/EEDI
PRDB2/EEDO
PRDB3
DVSS2
PRDB4
PRDB5
PRDB6
PRDB7
131
130
129
128
127
126
125
124
123
122
121
120
44
45
46
119
118
117
116
Top Side View
47
48
49
50
DVSS3
132
1
2SMA
3SA0
4SA1
5SA2
6DVSS10
7SA3
8SA4
9SA5
10SA6
11SA7
12SA8
13SA9
14DVSS4
15SA10
16SA11
17SA12
18SBHE
19DVDD3
20PRAB0
21PRAB1
22PRAB2
23DVSS5
24PRAB3
25PRAB4
26PRAB5
27PRAB6
28PRAB7
29PRAB8
30PRAB9
31DVSS6
32PRAB10
33PRAB11
34
35
36
37
39
42
43
DVDD1
LED0
115
114
51
52
LED1
DVSS1
113
112
53
54
LED2
LED3
111
110
55
DXCVR/EAR
109
AVDD2
CI+
108
107
59
58
CI–
106
60
DI+
105
61
DI–
104
62
AVDD1
103
63
DO+
102
64
DO–
101
65
AVSS1
100
XTAL299
AVSS298
XTAL197
AVDD396
TXD+95
TXPD+94
TXD–93
TXPD–92
AVDD491
RXD+90
RXD–89
DVSS1388
SD1587
SD786
SD1485
SD684
DVSS983
SD1382
SD581
SD1280
SD479
DVDD778
SD1177
SD376
SD1075
SD274
DVSS873
SD972
SD171
SD870
SD069
SLEEP68
DVDD667
66
DVDD4
PRAB12
PRAB13
PRAB1438PRAB15
SA1340SA1441SA15
DVSS7
AEN
SRWE
MEMR
MEMW
IOCHRDY
DVSS11
APCS/IRQ15
IRQ11
SRCS/IRQ12
22 Am79C961A
IRQ10
DVDD5
BPAM
IOCS16
REF
IRQ356IRQ457IRQ5
SROE
SMAM
DVSS12
IOR
IOW
IRQ9
RESET
19364A-4
PRELIMINARY
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Pin Number
Pin # Name Pin # Name Pin # Name
1 DVSS3
2 46 MEMW 90
3 47 MEMR
4 48 DVSS11 92
5 49 IRQ15 93
6 50 IRQ12 94
7 51 IRQ11 95
8 52 DVDD5 96
9 53 IRQ10 97
10 54 IOCS16
11 55 BP
12 56 IRQ3 100
13 SA9
14 58 IRQ5 102
15 59 REF
16 60 DVSS12 104
17 61 SR
18 62 SMAM
19 63 IOR
20 64 IO
21 65 IRQ9 109
22 66 RESET 110
23 67 DVDD6 111
24 68 SLEEP
25 69 SD0 113
26 70 SD8 114
27 71 SD1 115 DVDD1
28 72 SD9 116
29 73 DVSS8 117
30 74 SD2 118
31 75 SD10 119
32 76 SD3 120
33 77 SD11 121
34 78 DVDD7 122
35 79 SD4 123
36 80 SD12 124
37 PRAB14
38 82 SD13 126
39 83 DVSS9 127
40 84 SD6 128
41 85 SD14 129
42 86 SD7 130
43 87 SD15 131
44 88 DVSS13 132
SMA
SA0
SA1
SA2
DVSS10
SA3
SA4
SA5
SA6
SA7
SA8
DVSS4
SA10
SA11
SA12
SBHE
DVDD3
PRAB0
PRAB1
PRAB2
DVSS5
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
DVSS6
PRAB10
PRAB11
DVDD4
PRAB12
PRAB13
PRAB15
DVSS7
SA13
SA14
SA15
WE
SR
AEN
45 IOCHRDY 89 RXD-
91
98
AM 99
57 IRQ4 101
103
OE 105
106
107
W 108
112
81 SD5 125
RXD+
AVDD4
TXPD-
TXD-
TXPD+
TXD+
AVDD3
XTAL1
AVSS2
XTAL2
AVSS1
DO-
DO+
AVDD1
DI-
DI+
CI-
CI+
AVDD2
DXCVR/EAR
LED3
LED2
DVSS1
LED1
LED0
PRDB7
PRDB6
PRDB5
PRDB4
DVSS2
PRDB3
PRDB2/EEDO
PRDB1/EEDI
PRDB0/EESK
SHFBUSY
BPCS
EECS
TDI
TDO
TMS
TCK
DVDD2
Am79C961A 23
PRELIMINARY
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Pin Name
Name Pin# Name Pin# Name Pin#
AEN
AVDD1
AVDD2
AVDD3
AVDD4
AVSS1
AVSS2
AM
BP
BPCS
CI-
CI+
DIDI+
DO-
DO+
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
DVDD6
DVDD7
DVSS1
DVSS10
DVSS11
DVSS12
DVSS13
DVSS2
DVSS3
DVSS4
DVSS5
DVSS6
DVSS7
DVSS8
DVSS9
DXCVR/EAR
EECS
IOCHRDY
IOCS16
IOR
IOW
IRQ10
IRQ11
IRQ12
44 IRQ15 49 SA13
103 IRQ3 56 41
108 IRQ4 57 42
96 IRQ5 58 5
91 IRQ9 65 7
100 LED0
98 LED1
55 LED2
126 LED3
106 MEMR
107 MEMW
104 PRAB0 20 18
105 PRAB1 21 69
101 PRAB10 32 71
102 PRAB11 33 75
115 PRAB12 35 77
132 PRAB13 36 80
19 PRAB14 37 82
34 PRAB15 38 85
52 PRAB2 22 87
67 PRAB3 24 74
78 PRAB4 25 76
112 PRAB5 26 79
6 PRAB6 27 SD5
48 PRAB7 28 84
60 PRAB8 29 86
88 PRAB9 30 70
120 PRDB0/DO 124 72
1 PRDB0/D1 123 125
14 PRDB0/SCLK 122 68
23 PRDB3 121 2
31 PRDB4 119 62
39 PRDB5 118 61
73 PRDB6 117 43
83 PRDB7 116 131
109 REF
127 RESET 66 129
45 RXD- 89 130
54 RXD+ 90 93
63 SA0 3 95
64 SA1 4 92
53 SA10 15 94
51 SA11 16 97
50 SA12 17 99
40
SA14
SA15
SA2
SA3
114 8
113 9
111 10
110 11
47 12
46 13
59 128
SA4
SA5
SA6
SA7
SA8
SA9
SBHE
SD0
SD1
SD10
SD11
SD12
SD13
SD14
SD15
SD2
SD3
SD4
81
SD6
SD7
SD8
SD9
SHFBUSY
SLEEP
SMA
SMAM
SROE
SRWE
TCK
TDI
TDO
TMS
TXD-
TXD+
TXPD-
TXPD+
XTAL1
XTAL2
24 Am79C961A
PRELIMINARY
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Group
Pin Name Pin Function I/O Driver
ISA Bus Interface
AEN Address Enable I
IOCHRDY I/O Channel Ready O OD3
IOCS16
IOR
W I/O Write Select I
IO
IRQ[3, 4, 5, 9, 10, 11, 12, 15] Interrupt Request O TS3/OD3
MEMR
MEMW
REF Memory Refresh Active I
RESET System Reset I
SA[0–15] System Address Bus I
SBHE
SD[0–15] System Data Bus I/O TS3
Board Interfaces
IRQ15/APCS
BPCS
AM Boot PROM Address Match I
BP
DXCVR/EAR
LED0
LED1
LED2
LED3
PRAB[0–15] PRivate Address Bus I/O TS3
PRDB[3–7] PRivate Data Bus I/O TS1
SLEEP
SMA
SMAM
OE Static RAM Output Enable O TS3
SR
WE Static RAM Write Enable O TS1
SR
XTAL1 Crystal Oscillator Input I
XTAL2 Crystal Oscillator OUTPUT O
SHFBUSY Read access from EEPROM in process O
PRDB(0)/EESK Serial Shift Clock I/O
PRDB(1)/EEDI Serial Shift Data In I/O
PRDB(2)/EEDO Serial Shift Data Out I/O
EECS EEPROM Chip Select O
I/O Chip Select 16 O OD3
I/O Read Select I
Memory Read Select I
Memory Write Select I
System Byte High Enable I
IRQ15 or Address PROM Chip Select O TS1
Boot PROM Chip Select O TS1
Disable Transceiver I/O TS1
LED0/LNKST O TS2
LED1/SFBD/RCV A CT O TS2
LED2/SRD/RXDATD01 O TS2
LED3/SRDCLK/XMTACT O TS2
Sleep Mode I
Slave Mode Architecture I
Shared Memory Address Match I
Am79C961A 25
PRELIMINARY
PIN DESIGNATIONS: BUS SLAVE MODE
Listed by Group
Pin Name Pin Function I/O Driver
Attachment Unit Interface (AUI)
CI±
DI±
DO±
Twisted Pair Transceiver Interface (10BASE-T)
RXD±
TXD±
TXPD±
IEEE 1149.1 Test Access Port Interface (JTAG)
TCK
TDI
TDO
TMS
Power Supplies
AVDD
AVSS
DVDD
DVSS
10BASE-T Predistortion Control
Collision Inputs
Receive Data
Transmit Data
10BASE-T Receive Data
10BASE-T T r ansmit Data
Test Data Input
Test Data Output
Test Mode Select
Analog Power [1-4]
Analog Ground [1-2]
Digital Power [1-7]
Digital Ground [1-13]
Test Clock
I
I
O
I
O
O
I
I
O
I
TS2
Output Driver Types
Name Type I
TS1 Tri-State 4 –1 50
TS2 Tri-State 12 –4 50
TS3 Tri-State 24 –3 120
OD3 Open Drain 24 –3 120
(mA) IOH (mA) pF
OL
26 Am79C961A
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