AMD Am79C930 User Manual

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PRELIMINARY

Am79C930

PCnet™-Mobile
Single-Chip Wireless LAN Media Access Controller

DISTINCTIVE CHARACTERISTICS

Capable of supporting the IEEE 802.11 standard
(draft)

Supports the Xircom Netwave™ media access
control (MAC) protocols

Supports MAC layer functions
Individual 8-byte transmit and 15-byte receive

FIFOs
Integrated intelligent 80188 processor for MAC

layer functions
Glueless PCMCIA bus interface conforming to

PC Card standard—Feb. 1995
Full PCMCIA software interface support for PC

Card standard—Feb. 1995
Glueless ISA (IEEE P996) bus interface with full

support for Plug and Play release 1.0a
Glueless SRAM interface for MAC operations,

supporting up to 128 Kbytes of memory
Glueless Flash memory interface, supporting

up to 128 Kbytes of non-volatile memory for
MAC control code, PCMCIA configuration

parameters, and ISA Plug and Play
configuration parameters

Provides integrated Transceiver Attachment
Interface (TAI), supporting Frequency-Hopping
Spread Spectrum, Direct Sequence Spread
Spectrum, and infrared physical-layer
interfaces

Antenna diversity selection support
Fabricated with submicron CMOS technology

with low operating current
Supports dual 3 V and 5 V supply applications
Low-power mode allows reduced power

consumption for critical battery-powered
applications

144-pin Thin Quad Flat Pack (TQFP) package
available for space-critical applications, such as
PCMCIA

JTAG Boundary Scan (IEEE 1149.1) test access
port for board-level production test

GENERAL DESCRIPTION

PCnet-Mobile (Am79C930) is the first in a series of mo­bile networking products in AMD’s PCnet family. The
Am79C930 device is the first single-chip wireless LAN
media access controller (MAC) supporting the IEEE

802.11 (draft) standard and the Xircom Netwave™
MAC protocols. The Am79C930 device is designed to
have a flexible protocol engine to allow for industry
standard and proprietary protocols. Protocol firmware
for Xircom Netwave and IEEE 802.11 (draft) MAC pro­tocols are supplied by AMD. It is pin-compatible with
the PCMCIA bus or the ISA (Plug and Play) bus
through a pin-strapping option.

The Am79C930 device contains a PCMCIA/ISA bus
interface unit (BIU), a MAC control unit, and a

Publication# 20183 Rev: BAmendment/0
Issue Date: April 1997

This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.

transceiver attachment interface (TAI). The TAI sup­ports frequency-hopping spread spectrum, direct
sequence spread spectrum, and infrared physical layer
interfaces. In addition, a power down function has been
incorporated to provide low standby current for power­sensitive applications.

The Am79C930 device provides users with a media ac­cess controller that has flexibility (i.e., bus interface,
protocol, and physical layer support) to allow the
design of multiple products using a single device. By
having all the necessary MAC functions on a single
chip, users only need to add memory and the physical
layer in order to deliver a fully functional wireless LAN
connection.

1

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.

AM79C930 V C

DEVICE NUMBER/DESCRIPTION

Am79C930
Single-Chip Wireless LAN Media Access Controller

\W

OPTIONAL PROCESSING

\W = Trimmed and Formed in a Tray

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

PACKAGE TYPE

V = 144-Pin Thin Quad Flat Pack (PQT144)

SPEED

Not Applicable

Valid Combinations

Am79C930 VC\W

Valid Combinations

Valid combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

2 Am79C930

BLOCK DIAGRAM
PCMCIA Mode

PRELIMINARY

MOE

MWE

MA 16–0

MD 7–0

XCE

SCE

FCE

USER6–0

A14–0

D7–0

REG

CE1

OE

IORD

IOWR

RESET

WE

WAIT

INPACK

IREQ

STSCHG

PMX2–1

Bus

Interface

Unit

(PCMCIA)

CA16–8

CAD 7–0

INT1

ALE

WR

SRDY

UCS

LCS

RESET

MAC

Control

Unit

(80188 core)

DRQ0
DRQ1

INT0

JTAG

Control

Block

Transceiver

Attachment

Interface

TRST

TMS/T3
TDI/T1
TDO/T2

RXCIN
ANTSLT

ANTSLT

SAR6–0
ADIN2–1
ADREF
RXDATA

RXC
SDCLK

SDDATA
SDSEL3–1
TXCMD

TXCMD
TXMOD

TXDATA

TXDATA
RXPE
TXPE
HFPE

HFCLK

LFPE

LFCLK

FDET
LNK
ACT

CLKIN

TEST

PWRDWN

20183B-1

Am79C930 3

BLOCK DIAGRAM
Bus Interface Unit

IREQ

A14–0 or

LA23–17, SA16–0

D7–0

PRELIMINARY

MD[7:0] MA[16:0]

System

Interrupt

Generator

Address Buffer

Data Buffer

Bus
Multi­plexer

Latch

CA16
ALE

CA15–8

CAD7–0

PCMCIA

or

ISA Control Signals

CLKIN

SIR0
SIR1

...

SIR7

Slave

Control

PCMCIA

and ISA
Memory

and I/O

PCMCIA

Config Registers

Plug and Play

Control Module

ISA Memory Base

ISA I/O Base

80188

Interrupt
Generator

MIR0
MIR1

...

MIR15

Slave

Control

and

Arbitration

for

Memory

Interface

Bus

MOE

MWE

UCS

LCS

SRDY

XCE

FCE

TAICE

SCE

INT1

RESET

20183B-2

4 Am79C930

PRELIMINARY

BLOCK DIAGRAM
Transceiver Attachment Interface Unit

IRQ

MD[7:0]

TAICE

Slave

Control

MA[4:0]

DRQ[1:0]

RXCSEL

RXCIN

Interrupt

Generator

TIR0

TIR31

Slave

Control

Memory

Interface

Bus I/O

and DMA

DPLL

TCR0

TCR...TIR...

TCR31

C

M
U
X

Empty

Transceiver Interface

Unit Control

TX

FIFO

8

Bytes

P->S S->P

MUX

C
R
C

MUX

FIFO

Bytes

SFD

Detect

Transceiver
Control
Signals

RX

15

C
R
C

FDET

Count

Phylen

RESET

CLKIN

÷80
÷40

÷5
÷10
÷20

M
U
X

Sleep

BIAS

Suppress

RXD
TXD
TXC

RXC

20183B-3

Am79C930 5

AMD

P R E L I M I N A R Y

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BLOCK DIAGRAM 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Interface Unit 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transceiver Attachment Interface Unit 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA BLOCK DIAGRAM 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA CONNECTION DIAGRAM 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA PIN SUMMARY 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Number 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA PIN LIST 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Name 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA PIN FUNCTION SUMMARY 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Pin Summary 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA PLUG AND PLAY BLOCK DIAGRAM 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONNECTION DIAGRAM 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Plug And Play 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA PLUG AND PLAY PIN LIST 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Number 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Listed By Pin Name 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA PLUG AND PLAY PIN SUMMARY 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTIONS 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pins with Internal Pull Up or Pull Down Devices 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Configuration Pins 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Host System Interface Pins 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Bus Interface 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA (IEEE P996) Bus interface 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Interface Pins 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Pins 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Management Pins 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAI Interface Pins 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other Pins 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 Test Access Port Pins 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply Pins 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Power Supply Pins 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Power Supply Pins 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multi-Function Pins 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 1: USER2/LA19 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 2: USER3/SA16 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

Am79C930

P R E L I M I N A R Y

AMD

Pin 3: USER4/LA17 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 45: STSCHG/BALE 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 90: USER0/RFRSH 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 91: USER1/IRQ12/EXTCTS/EXINT188 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 92: USER7/IRQ11 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 94: RXC/IRQ10/EXTA2DST 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 95: USER6/IRQ5/EXTSDF 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 96: USER5/IRQ4/EXTCHBSY 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 98: ACT 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 100: LNK 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 101: SDCLK 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 102: SDDATA 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 103: SDSEL3 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 105: SDSEL2 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 107: SDSEL1 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 115: TXC 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 118: LFPE 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 120: HFPE 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 122: RXPE 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 126: TXCMD 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 129: TXPE 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 131: TXMOD 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 132: ANTSLT 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 141: ANTSLT/LA23 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 142: TXCMD/LA21 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 143: TXDATA/LA20 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin 144: LLOCKE/SA15 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FUNCTIONAL DESCRIPTION 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Functions 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Bus Interface Function 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Bus Interface Function 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Interface Function 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Network Interface Function 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Functions 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Level Description 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Interface Unit 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Interface 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA (IEEE P996) Plug and Play Interface 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Interface 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Embedded 80188 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Media Access Management 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Medium Allocation 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRAM Memory Management 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flash Memory Management 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transceiver Attachment Interface Unit Management 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7Am79C930

AMD

P R E L I M I N A R Y

Bus Interface Unit Interaction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transceiver Attachment Interface Unit 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX FIFO 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Power Ramp Control 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am79C930-based TX Power Ramp Control . 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transceiver-Based TX Power Ramp Control . 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX CRC Generation 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Status 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Start of Frame Delimiter Detection 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX Data Parallelization 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX FIFO 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX CRC Checking 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX Status Reporting 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Ordering 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RSSI A/D Unit 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Physical Header Accommodation 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Bias Control 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baud Determination Logic 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clear Channel Assessment Logic 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Antenna Diversity Logic 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TXC As Input 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 Test Access Port Interface 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boundary Scan Circuit 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAP FSM 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supported Instructions 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Register and Decoding Logic 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boundary Scan Register (BSR) 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other Data Registers 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Saving Modes 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Down Function 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applicability to IEEE 802.11 Power Down Modes 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software Access 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am79C930 System Interface Resources 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Mode Resources 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Attribute Memory Resources. 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA I/O Resources. 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Plug and Play Mode Resources 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Plug and Play Memory Resources 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Plug and Play I/O Resources. 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Plug and Play Register Set. 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC Firmware Resources 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC (80188 core) Memory Resources 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC (80188 core) Memory Resources Restrictions 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC (80188 core) Interrupt Channel Allocation 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC (80188 core) DMA Channel Allocation 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DMA Channel Allocation In The 80188 Core 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loopback Operation 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

Am79C930

P R E L I M I N A R Y

AMD

LED Support 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET Methods 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET Pin 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWRESET (SIR0[7]) 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CORESET (SIR0[6]) 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA COR SRESET 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA PnP RESET 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SRES (TIR0[5]) 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER DESCRIPTIONS 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Interface Registers (SIR space) 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR0: General Configuration Register (GCR) 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR1: Bank Switching Select Register (BSS) 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR2: Local Memory Address Register [7:0] (LMA) 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR3: Local Memory Address Register [14:8] (LMA) 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR4: I/O Data Port A (IODPA) 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR5: I/O Data Port B (IODPB) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR6: I/O Data Port C (IODPC) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SIR7: I/O Data Port D (IODPD) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC Interface Registers (MIR Space) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR0: Processor Interface Register (PIR) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR1: Power Up Clock Time [3:0] (PUCT) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR2: Power Down Length Count [7:0] (PDLC) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR3: Power Down Length Count [15:8] (PDLC) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR4: Power Down Length Count [22:16] (PDLC) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR5: Free Count [7:0] (FCNT) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR6: Free Count [15:8] (FCNT) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR7: Free Count [23:16] (FCNT) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR8: Flash Wait States 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR9: TCR Mask STSCHG Data 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR10: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR11: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR12: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR13: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR14: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MIR15: Reserved 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transceiver Attachment Interface Registers (TIR Space) 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR0: Network Control 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR1: Network Status 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR2: Serial Device 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR3: Fast Serial Port Control 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR4: Interrupt Register 1 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR5: Interrupt Register 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR6: Interrupt Unmask Register 1 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR7: Interrupt Unmask Register 2 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR8: Transmit Control 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR9: Transmit Status 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9Am79C930

AMD

P R E L I M I N A R Y

TIR10: TX FIFO Data Register 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR11: Transmit Sequence Control 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR12: Byte Count Register LSB 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR13: Byte Count Register MSB 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR14: Byte Count Limit LSB 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR15: Byte Count Limit MSB 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR16: Receiver Control 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR17: Receive Status Register 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR18: RX FIFO Data Register 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR19: Reserved 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR20: CRC32 Correct Byte Count LSB 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR21: CRC32 Correct Byte Count MSB 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR22: CRC8 Correct Byte Count LSB 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR23: CRC8 Correct Byte Count MSB 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR24: TCR Index Register 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR25: Configuration Data Port 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR26: Antenna Diversity and A/D Control 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR27: Serial Approximation Register 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR28: RSSI Lower Limit 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR29: USER Pin Data 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR30: Test Dummy Register 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIR31: TEST 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAI Configuration Register space (TCR) 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR0: Network Configuration 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR1: Transmit Configuration 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR2: Clock Recovery 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR3: Receive Configuration 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR4: Antenna Diversity Timer 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR5: TX Ramp Up Timing 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR6: TX Ramp Down Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR7: Pin Data A 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR8: Start Delimiter LSB 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR9: Start Delimiter CSB 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR10: Start Delimiter MSB 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR11: Interrupt Register 3 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR12: Interrupt Unmask Register 3 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR13: Pin Configuration A 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR14: Pin Configuration B 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR15: Pin Configuration C 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR16: Baud Detect Start 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR17: Baud Detect Lower Limit 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR18: Baud Detect Upper Limit. 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR19: Baud Detect Accept Count for Carrier Sense 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR20: Baud Detect Accept Count for Stop Diversity 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR21: Baud Detect Ratio 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR22: Baud Detect Accept Count 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR23: Baud Detect Fail Count 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

Am79C930

P R E L I M I N A R Y

AMD

TCR24: RSSI Sample Start 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR25: RSSI Configuration 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR26: Reserved 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR27: TIP LED Scramble 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR28: Clear Channel Assessment Configuration 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR29: Reserved 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR30: Pin Function and Data Rate 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TCR31: Device Revision 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA CCR Registers and PCMCIA CIS Space 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Card Configuration and Status Register 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Card Information Structure (CIS) 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGES 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V Am79C930 DC Characteristics 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 V Am79C930 DC Characteristics 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 DC Characteristics (5.0 and 3.3 V) 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGES 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC CHARACTERISTICS 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 and 3.3 V PCMCIA Interface AC Characteristics 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA MEMORY READ ACCESS 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA MEMORY WRITE ACCESS 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA I/O READ ACCESS 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA I/O WRITE ACCESS 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 AND 3.3 V ISA INTERFACE AC CHARACTERISTICS 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA ACCESS 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V MEMORY BUS INTERFACE AC CHARACTERISTICS 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY BUS READ ACCESS 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY BUS WRITE ACCESS 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 V MEMORY BUS INTERFACE AC CHARACTERISTICS 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY BUS READ ACCESS 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY BUS WRITE ACCESS 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V TAI INTERFACE AC CHARACTERISTICS 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 V TAI INTERFACE AC CHARACTERISTICS 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 AND 3.3 V USER PROGRAMMABLE PINS AC CHARACTERISTICS 146. . . . . . . . . . . . . . . . . . . . . . . .

5.0 AND 3.3 V IEEE 1149.1 INTERFACE AC CHARACTERISTICS 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ANALOG-TO-DIGITAL (A/D) CONVERTER CHARACTERISTICS 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11Am79C930

AMD

P R E L I M I N A R Y

TIMING WAVEFORMS 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCMCIA Bus Interface Waveforms 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISA Bus Interface Waveforms 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Bus Interface Waveforms 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLOCK WAVEFORMS 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAI WAVEFORMS 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PROGRAMMABLE INTERFACE WAVEFORMS 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 INTERFACE WAVEFORMS 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AC TEST REFERENCE WAVEFORMS 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V PCMCIA AC Test Reference Waveform 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 V PCMCIA AC Test Reference Waveform 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V NON-PCMCIA AC Test Reference Waveform 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 V NON-PCMCIA AC Test Reference Waveform 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PHYSICAL DIMENSIONS 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDIX A: Typical Am79C930 System Application A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Configuration A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame Transmission A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame Reception A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

Am79C930

PCMCIA CONNECTION DIAGRAM

LLOCKE

TXDATA

TXCMD

ANTSLT

VDDU2

VDD5

AVDD

ADREF

AVSS

PRELIMINARY

ADIN2

ADIN1

PWRDWN

ANTSLT

TXMOD

VSST

TXPE

FDET

VSSTXCMD

VDDT

RXCIN

RXSDATA

RXPE

TXDATA

HFPE

HFCLK

LFPE

LFCLK

VSST

TXC

SAR6

SAR5

SAR4

SAR3

SAR2

SAR1

USER2
USER3
USER4

VDDM

XCE

MA11

VSSM

MA9
MA8

MA13

MWE

MA14
MA16
MA15
MA12

VDDM

V

MA7
MA6
MA5

VSSM

MA4
MA3
MA2
MA1
MA0
MD0
MD1

VDDM

MD2
MD3

VSSM

MD4
MD5
MD6
MD7

119

118

117

116

132

131

130

129

128

127

126

125

124

123

144

143

142

141

140

139

138

137

136

135

134

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

CC

16
17

18
19

20
21
22
23
24
25
26
27
28

29
30
31
32
33
34

35
36

4243444546474849505152

40

373839

41

133

Am79C930

53

54

55

122

121

120

62

57

56

61

59

60

58

115

63

64

66

65

111

114

113

112

110

109

108
107
106
105

104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

69

68

70

67

72

71

SAR0

SDSEL1

VSST

SDSEL2

VDDT

SDSEL3

ADDATA
SDCLK

LNK

VSST

ACT

VDDU1
USER5
USER6
RXC
VSSU1
USER7
USER1
USER0
V

CC

TDI
TRST
TMS
TDO
TCK
PMX1
PMX2

TEST

CLK20
PCMCIA
D3
D4
VSSP
D5
D6
D7

MA10

Notes:

Pin 1 is marked for orientation.
NC = No Connection

MOE

SCE

FCE

D2D1D0

VSSP

STSCHG

A0

A1

A2

A3

INPACK

WAIT

A4

REG

A7

A12

VDDP

SS

V

A5

RESET

A6

IREQ

WE

A14

A13

A8

IORD

IOWR

A9

A11OEA10

CE1

20183B-4

Am79C930 13

PRELIMINARY

PCMCIA PIN SUMMARY
Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 USER2 37 MA10 73 D7 109 SAR1
2 USER3 38 MOE
3 USER4 39 SCE
4 VDDM 40 FCE
5 XCE

41 D2 77 D4 113 SAR5
6 MA11 42 D1 78 D3 114 SAR6
7 VSSM 43 D0 79 PCMCIA 115 TXC
8 MA9 44 VSSP 80 CLK20 116 VSST
9 MA8 45 STSCHG

10 MA13 46 A0 82 PMX2 118 LFPE
11 MWE 47 A1 83 PMX1 119 HFCLK
12 MA14 48 REG 84 TCK 120 HFPE
13 MA16 49 A2 85 TDO 121 TXDATA
14 MA15 50 INP

ACK 86 TMS 122 RXPE
15 MA12 51 A3 87 TRST 123 RXDATA
16 VDDM 52 W
17 V

CC

53 A4 89 V

AIT 88 TDI 124 RXCIN

18 MA7 54 A7 90 USER0 126 TXCMD
19 MA6 55 VDDP 91 USER1 127 V
20 MA5 56 A12 92 USER7 128 FDET
21 VSSM 57 V

SS

22 MA4 58 RESET 94 RXC 130 VSST
23 MA3 59 A5 95 USER6 131 TXMOD
24 MA2 60 A6 96 USER5 132 ANTSLT
25 MA1 61 IREQ
26 MA0 62 WE
27 MD0 63 A14 99 VSST 135 ADIN2
28 MD1 64 A13 100 LNK 136 AVSS
29 VDDM 65 A8 101 SDCLK 137 ADREF
30 MD2 66 IO

WR 102 SDDATA 138 AVDD
31 MD3 67 IORD
32 VSSM 68 A9 104 VDDT 140 VDDU2
33 MD4 69 A11 105 SDSEL2
34 MD5 70 OE 106 VSST 142 TXCMD
35 MD6 71 A10 107 SDSEL1
36 MD7 72 CE1 108 SAR0 144 LLOCKE

74 D6 110 SAR2
75 D5 111 SAR3
76 VSSP 112 SAR4

81 TEST 117 LFCLK

CC

125 VDDT

SS

93 VSSU1 129 TXPE

97 VDDU1 133 PWRDWN
98 ACT 134 ADIN1

103 SDSEL3 139 VDD5

141 ANTSLT

143 TXDATA

14 Am79C930

PRELIMINARY

PCMCIA PIN LIST
Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

A0 46 HFPE 120 OE 70 TXMOD 131
A1 47 INP
A10 71 IORD
A11 69 IO
A12 56 IREQ
A13 64 LFCLK 117 REG
A14 63 LFPE
A2 49 LLOCKE 144 RXC 94 USER5 96
A3 51 LNK
A4 53 MA0 26 RXDATA 123 V
A5 59 MA1 25 RXPE
A6 60 MA10 37 SAR0 108 VDD5 139
A7 54 MA11 6 SAR1 109 VDDM 4
A8 65 MA12 15 SAR2 110 VDDM 16
A9 68 MA13 10 SAR3 111 VDDM 29
A

CT 98 MA14 12 SAR4 112 VDDP 55
ADIN1 134 MA15 14 SAR5 113 VDDT 104
ADIN2 135 MA16 13 SAR6 114 VDDT 125
ADREF 137 MA2 24 SCE
ANTSLT 132 MA3 23 SDCLK 101 VDDU2 140
ANTSL

T 141 MA4 22 SDDATA 102 V
AVDD 138 MA5 20 SDSEL1
AVSS 136 MA6 19 SDSEL2
CE1

72 MA7 18 SDSEL3 103 VSSM 21
CLK20 80 MA8 9 STSCHG
D0 43 MA9 8 TCK 84 VSSP 44
D1 42 MD0 27 TDI 88 VSSP 76
D2 41 MD1 28 TDO 85 VSST 99
D3 78 MD2 30 TEST
D4 77 MD3 31 TMS 86 VSST 116
D5 75 MD4 33 TRST
D6 74 MD5 34 TXC 115 VSSU1 93
D7 73 MD6 35 TXCMD
FCE
FDET

40 MD7 36 TXCMD 142 USER7 92

128 MOE 38 TXDATA 121 WE 62

HFCLK 119 MWE

ACK 50 PCMCIA 79 TXPE 129

67 PMX1 83 USER0 90

WR 66 PMX2 82 USER1 91

61 PWRDWN 133 USER2 1

48 USER3 2

118 RESET 58 USER4 3

100 RXCIN 124 USER6 95

CC

122 V

CC

39 VDDU1 97

SS

107 V

SS

105 VSSM 7

45 VSSM 32

81 VSST 106

87 VSST 130

126 WAIT 52

11 TXDATA 143 XCE 5

17
89

57

127

Am79C930 15

PRELIMINARY

PCMCIA PIN FUNCTION SUMMARY
PCMCIA Pin Summary

No. of

Pins Pin Name Pin Function Pin Style

15 A14–A0 PCMCIA address bus lines I

8 D7–D0 PCMCIA data bus lines TS2
1 RESET PCMCIA bus RESET line I

1 CE1

1 OE

1 WE

1 REG

1 INP

1 W

1 IORD

1 IO

1 IREQ

1 STSCHG
1 PCMCIA PCMCIA mode—selects PCMCIA or ISA Plug and Play mode I
1 PWRDWN Powerdown—indicates that device is in the power down mode TP1

17 MA16–0

8 MD7–0

1 FCE

1 SCE

1 XCE

1 MOE

1 MWE

1 TCK Test Clock—this is the clock signal for IEEE 1149.1 testing I
1 TDI Test Data In—this is the data input signal for IEEE 1149.1 testing I

ACK

AIT Wait—used to delay the termination of the current PCMCIA cycle TS2

WR

Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write
accesses

Output Enable—used to enable the output drivers of the Am79C930 device for
PCMCIA Read accesses

Write Enable—used to indicate that the current PCMCIA cycle is a write access I
REG—used to indicate that the current PCMCIA cycle is to the Attribute

Memory space of the Am79C930 device
Input Acknowledge—used to indicate that the Am79C930 device will respond

to the current I/O read cycle

I/O Read—this signal is asserted by the PCMCIA host system whenever an
I/O read operation occurs

I/O Write—this signal is asserted by the PCMCIA host system whenever an
I/O write operation occurs

Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software

Status Change—PCMCIA output used only for WAKEUP signaling PTS1

Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design

Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design

Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface

SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface

eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)

Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus

Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus

TS1

PTS3

TP1

TS1

TP1

TP1

TP1

TP1

TP1

I

I

I

I

16 Am79C930

PRELIMINARY

PCMCIA PIN FUNCTION SUMMARY (continued)
PCMCIA Pin Summary (continued)

No. of

Pins Pin Name Pin Function Pin Style

1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing TS1
1 TMS Test Mode Select—this is the test mode select for IEEE 1149.1 testing I
1 TRST
1 USER7 User-programmable pin PTS3
1 RXC Receive Clock—provides decode receive clock PTS3

1 TEST

1 CLKIN

2 PMX1–2 Power Management Xtal—32-kHz Xtal input for sleep timer reference I/XO
1 TXC Transmit Clock—may be configured either as input or output TS1

1 LFPE

1 LFCLK Low Frequency Clock—a reference signal for the transceiver synthesizer TS1
1 LLOCKE Low Frequency Synthesizer Lock—a programmable signal PTS1

1 HFPE

1 HFCLK High Frequency Clock—a reference signal for the transceiver synthesizer TS1
2 ANTSLT, ANTSL
2 TXCMD, TXCMD Transmit Command—used to select the transmit path in the transceiver TP1, PTS1

1 TXPE

2 TXDATA, TXD
1 TXMOD Transmit Modulation Enable—enables the modulation of transmit data TP1
1 RXPE Receive Power Enable—enables the receive function of the transceiver PTS1
1 RXDATA Receive Data—accepts receive data in NRZ format from the transceiver I
1 FDET Frame Detect—start of frame delimiter detection indication TS1
1 RXCIN Receive Clock Input—optional clock input that allows for an external PLL IPU
1 SDCLK Serial Data Clock—clock output used to access serial peripheral devices PTS1
1 SDDATA Serial Data Data—data pin used to access serial peripheral devices PTS1
3 SDSEL3–SDSEL1 Serial Data Select—chip select outputs used to select serial peripheral devices PTS1
1 ACT Activity LED—output capable of driving an LED PTS2
1 LNK Link LED—output capable of driving an LED PTS2

1 ADREF

7 SAR6–SAR0

Test Reset—this is the reset signal for IEEE 1149.1 testing I

Test pin—when asserted, this pin places the Am79C930 device into a
nonstandard factory-only test mode

Clock input to drive BIU, 80188 core, and TAI, supplying network data rate
information

Low Frequency Power Enable—used to power up the low-frequency section of
the transceiver

High Frequency Power Enable—used to power up the high-frequency section
of the transceiver

T Antenna Select—used to select between two antennas PTS1

Transmit Power Enable—used to power up the transmit section of the
transceiver

ATA Transmit Data—supplies the transmit data stream to the transceiver TP1, PTS1

A/D Reference—an input that can be used to set the analog reference voltage
for the internal A/D converter

Serial Approximation Register—supplies the value of the serial approximation
register used in the A/D converter

PTS1

PTS1

TP1

TS1

I

I

I

Am79C930 17

PRELIMINARY

PCMCIA PIN FUNCTION SUMMARY (continued)
PCMCIA Pin Summary (continued)

No. of

Pins Pin Name Pin Function Pin Style

2 ADIN1–2 Comparator—A/D comparator inputs TS1
12 V
13 GND Ground I

CC

7 USER0–USER6

Power I

User-definable I/O pins with direct accessibility and control through TCR and
TIR registers

PTS3, PTS1

Output Driver Types

Name Type I

TP1 Totem pole 4 mA –4 mA 50 pF
TS1 Tri-state 4 mA –4 mA 50 pF

TS2 Tri-state 24 mA –4 mA 120 pF
PTS1 User-programmable tri-state 4 mA –4 mA 50 pF
PTS2 User-programmable tri-state 12 mA –4 mA 50 pF
PTS3 User-programmable tri-state 24 mA –4 mA 120 pF

OD2 Open drain 24 mA –4 mA 120 pF

XO Xtal amplifier output NA NA 50 pF

OL

I

OH

Input Types

Name Type Size of Pullup Size of Pulldown

I Input NA NA
IPU Input with internal pullup device >50K Ω
IPD Input with internal pulldown device NA >50K Ω

Load

NA

18 Am79C930

PRELIMINARY

ISA PLUG AND PLAY BLOCK DIAGRAM

MOE

MWE

MA 16–0

MD 7–0

XCE

SCE

FCE

LA23–17
SA126–0

SD7–0

AEN

BALE

MEMR

IOR

IOW

RESET

MEMW

IOCHRDY

IRQ(X)

RFRSH

PMX2–1

Bus

Interface Unit

(ISA

Plug and Play)

CA16–18
CAD 7–0

INT1

ALE

WR

SRDY

UCS

LCS

RESET

IEEE

802.11
MAC

Control Unit

(80188 core)

DRQ0
DRQ1

INT0

RESET

JTAG

Control

Block

IEEE

802.11

Network

Interface Unit

TRST

TMS/T3
TDI/T1
TDO/T2

RXCIN
ANTSLT

ANTSLT

SAR6–0
ADIN2–1
ADREF
RXDATA

RXC
SDCLK

SDDATA
SDSEL3–1
TXCMD

TXCMD
TXMOD

TXDATA

TXDATA
RXPE
TXPE
HFPE

HFCLK

LFPE

LFCLK

FDET
LNK
ACT

CLK20

TEST

PWRDWN

20183B-5

Am79C930 19

PRELIMINARY

ISA PLUG AND PLAY CONNECTION DIAGRAM

SA15

LA20

LA21

LA23

VDDU2

VDD5

AVDD

ADREF

AVSS

ADIN2

ADIN1

PWRDWN

ANTSLT

TXMOD

VSST

TXPE

FDET

VSSTXCMD

VDDT

RXCIN

RXSDATA

RXPE

TXDATA

HFPE

HFCLK

LFPE

LFCLK

VSST

TXC

SAR6

SAR5

SAR4

SAR3

SAR2

SAR1

LA19

SA16

LA17

VDDM

XCE

MA11

VSSM

MA9
MA8

MA13

MWE

MA14
MA16
MA15
MA12

VDDM

V
MA7
MA6
MA5

VSSM

MA4
MA3
MA2
MA1
MA0

MD0
MD1

VDDM

MD2
MD3

VSSM

MD4
MD5
MD6
MD7

119

118

117

116

63

6465666768

115

132

131

130

129

128

127

126

125

124

123

144

143

142

141

140

139

138

137

136

135

134

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

CC

16
17

18
19

20
21
22
23
24
25
26
27
28

29
30
31
32
33
34

35
36

424344454647484950

40

373839

41

133

Am79C930

51

545553

52

122

121

120

56575859606162

114

113

111

112

697071

110

109

72

108
107
106
105

104
103

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

SAR0

SDSEL1

VSST

SDSEL2

VDDT

SDSEL3

ADDATA
SDCLK

LNK

VSST

ACT

VDDU1
IRQ4
IRQ5
IRQ10
VSSU1
IRQ11
IRQ12

RFRSH

V

CC

TDI
TRST
TMS
TDO
TCK
PMX1
PMX2

TEST

CLK20
PCMCIA
SD3
SD4
VSSP
SD5
SD6
SD7

SA0

SA1

SA2

SA3

SA4

MA10

MOE

SCE

FCE

SD2

SD1

SD0

BALE

VSSP

AEN

LA22

SA7

IOCHRDY

Notes:

Pin 1 is marked for orientation.
NC = No Connection

20 Am79C930

SA12

VDDP

SS

V

SA5

RESET

SA6

IRQ9

SA14

MEMW

SA13

SA8

IOW

IOR

SA9

SA11

SA10

MEMR

LA18

20183B-6

PRELIMINARY

ISA PLUG AND PLAY PIN LIST
Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 LA19 37 MA10 73 SD7 109 SAR1
2 SA16 38 MOE
3 LA17 39 SCE
4 VDDM 40 FCE
5 XCE

41 SD2 77 SD4 113 SAR5
6 MA11 42 SD1 78 SD3 114 SAR6
7 VSSM 43 SD0 79 PCMCIA 115 TXC
8 MA9 44 VSSP 80 CLK20 116 VSST
9 MA8 45 BALE 81 TEST

10 MA13 46 SA0 82 PMX2 118 LFPE
11 MWE 47 SA1 83 PMX1 119 HFCLK
12 MA14 48 AEN 84 TCK 120 HFPE
13 MA16 49 SA2 85 TDO 121 TXDATA
14 MA15 50 LA22 86 TMS 122 RXPE
15 MA12 51 SA3 87 TRST 123 RXDATA
16 VDDM 52 IOCHRDY 88 TDI 124 RXCIN
17 V

CC

53 SA4 89 V

18 MA7 54 SA7 90 RFRSH
19 MA6 55 VDDP 91 IRQ12 127 V
20 MA5 56 SA12 92 IRQ11 128 FDET
21 VSSM 57 V

SS

22 MA4 58 RESET 94 IRQ10 130 VSST
23 MA3 59 SA5 95 IRQ5 131 TXMOD
24 MA2 60 SA6 96 IRQ4 132 ANTSLT
25 MA1 61 IRQ9 97 VDDU1 133 PWRDWN
26 MA0 62 MEMW
27 MD0 63 SA14 99 VSST 135 ADIN2
28 MD1 64 SA13 100 LNK
29 VDDM 65 SA8 101 SDCLK 137 ADREF
30 MD2 66 IOW 102 SDDATA 138 AVDD
31 MD3 67 IOR 103 SDSEL3
32 VSSM 68 SA9 104 VDDT 140 VDDU2
33 MD4 69 SA11 105 SDSEL2
34 MD5 70 MEMR
35 MD6 71 SA10 107 SDSEL1
36 MD7 72 LA18 108 SAR0 144 SA15

74 SD6 110 SAR2
75 SD5 111 SAR3
76 VSSP 112 SAR4

117 LFCLK

CC

125 VDDT
126 TXCMD

SS

93 VSSU1 129 TXPE

98 ACT 134 ADIN1

136 AVSS

139 VDD5

141 LA23

106 VSST 142 LA21

143 LA20

Am79C930 21

PRELIMINARY

ISA PLUG AND PLAY PIN LIST
Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

ACT 98 MA11 6 SA1 47 SDSEL2 105
ADIN1 134 MA12 15 SA10 71 SDSEL3
ADIN2 135 MA13 10 SA11 69 TCK 84
ADREF 137 MA14 12 SA12 56 TDI 88
AEN 48 MA15 14 SA12 56 TDO 85
ANTSLT 132 MA16 13 SA13 64 TEST
AVDD 138 MA2 24 SA14 63 TMS 86
AVSS 136 MA3 23 SA15 144 TRST
BALE 45 MA4 22 SA16 2 TXC 115
CLK20 80 MA5 20 SA2 49 TXCMD
FCE
FDET

40 MA6 19 SA3 51 TXDATA 121

128 MA7 18 SA4 53 TXMOD 131
HFCLK 119 MA8 9 SA5 59 TXPE
HFPE
IOCHRDY 52 MD0 27 SA7 54 V
IOR
IO

W 66 MD2 30 SA9 68 VDDM 4

120 MA9 8 SA6 60 V

CC

CC

67 MD1 28 SA8 65 VDD5 139

IRQ10 94 MD3 31 SAR0 108 VDDM 16
IRQ11 92 MD4 33 SAR1 109 VDDM 29
IRQ12 91 MD5 34 SAR2 110 VDDP 55
IRQ4 96 MD6 35 SAR3 111 VDDT 104
IRQ5 95 MD7 36 SAR4 112 VDDT 125
IRQ9 61 MEMR
LA17 3 MEMW
LA18 72 MOE
LA19 1 MWE

70 SAR5 113 VDDU1 97
62 SAR6 114 VDDU2 140
38 SCE 39 V
11 SD0 43 V

SS

SS

LA20 143 PCMCIA 79 SD1 42 VSSM 7
LA21 142 PMX1 83 SD2 41 VSSM 32
LA22 50 PMX2 82 SD3 78 VSSP 44
LA23 141 PWRDWN 133 SD4 77 VSSP 76
LFCLK 117 RESET
LFPE
LNK

118 RFRSH 90 SD6 74 VSST 106

100 RXCIN 124 SD7 73 VSST 116

58 SD5 75 VSST 99

MA0 26 RXDATA 123 SDCLK 101 VSST 130
MA1 25 RXPE
MA10 37 SA0 46 SDSEL1

122 SDDATA 102 VSSU1 93

107 XCE 5

103

126

129

127

81

87

17
89

57

22 Am79C930

PRELIMINARY

ISA PLUG AND PLAY PIN SUMMARY

No. of

Pins Pin Name Pin Function Pin Style

7 LA23–LA17 ISA upper address bus lines I

17 SA16–SA0 ISA lower address bus lines I

8 SD7–SD0 ISA data bus lines TS2
1 RESET

1 MEMR

1 MEMW
1 AEN Address Enable—used to indicate that the current ISA bus I/O address is valid I
1 BALE
1 IOCHRDY I/O Channel Ready—used to delay the termination of the current ISA bus cycle TS2
1 IOR

1 IOW

6 IRQ4, 5, 9, 10, 11, 12
1 RFRSH

1 PCMCIA PCMCIA mode—selects PCMCIA or ISA Plug and Play mode I
1 PWRDWN Powerdown—indicates that device is in the power down mode TP1

17 MA16–0

8 MD7–0

1 FCE

1 SCE

1 XCE

1 MOE

1 MWE
1 TCK Test Clock—this is the clock signal for IEEE 1149.1 testing I

1 TDI Test Data In—this is the data input signal for IEEE 1149.1 testing I
1 TDO Test Data Out—this is the data output signal for IEEE 1149.1 testing TS1
1 TMS Test Mode Select—this is the test mode select for IEEE 1149.1 testing I
1 TRST

1 TEST

1 CLKIN
2 PMX1–2 Power Management Xtal—32-kHz Xtal input for sleep timer reference I/XO

RESET input I
Memory Read—used to enable the output drivers of the Am79C930 device for

ISA bus memory read accesses
Memory Write—used to indicate that the current ISA bus cycle is a memory

write access

Bus Address Latch Enable—used to indicate that the ISA address lines are
valid

I/O Read—this signal is asserted by the ISA host system whenever an I/O read
operation occurs

I/O Write—this signal is asserted by the ISA host system whenever an I/O write
operation occurs

Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software

Refresh—indicates that the current ISA bus cycle is a refresh operation I

Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design

Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design

Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface

SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface

eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)

Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus

Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus

Test Reset—this is the reset signal for IEEE 1149.1 testing I
Test pin—when asserted, this pin places the Am79C930 device into a

non-IEEE 1149.1 test mode
Clock input to drive BIU, 80188 core, and TAI, supplying network data rate

information

PTS3/OD2

TP1

TS1

TP1

TP1

TP1

TP1

TP1

I

I

I

I

I

I

I

Am79C930 23

PRELIMINARY

ISA PLUG AND PLAY PIN SUMMARY (continued)

No. of

Pins Pin Name Pin Function Pin Style

1 TXC Transmit Clock—may be configured either as input or output TS1
1 LFPE
1 LFCLK Low Frequency Clock—a reference signal for the transceiver synthesizer TS1
1 HFPE
1 HFCLK High Frequency Clock—a reference signal for the transceiver synthesizer TS1

1 ANTSLT Antenna Select—used to select between two antennas PTS1
1 TXCMD

1 TXPE
1 TXDATA Transmit Data—supplies the transmit data stream to the transceiver TP1

1 TXMOD
1 RXPE
1 RXDATA Receive Data—accepts receive data in NRZ format from the transceiver I
1 FDET
1 RXCIN Receive Clock Input—optional clock input that allows for an external PLL IPU
1 SDCLK Serial Data Clock—clock output used to access serial peripheral devices PTS1
1 SDDATA Serial Data Data—data pin used to access serial peripheral devices PTS1
3 SDSEL3
1 A

–SDSEL1 Serial Data Select—chip select outputs used to select serial peripheral devices PTS1

CT Activity LED—output capable of driving an LED PTS2

1 LNK
1 ADREF

7 SAR6–SAR0
2 ADIN1–2 Comparator—A/D comparator inputs TS1

12 V

CC

13 GND Ground I

Low Frequency Power Enable—used to power up the low-frequency section of
the transceiver

High Frequency Power Enable—used to power up the high-frequency section
of the transceiver

PTS1

PTS1

Transmit Command—used to select the transmit path in the transceiver TP1
Transmit Power Enable—used to power up the transmit section of the

transceiver

TP1

Transmit Modulation Enable—enables the modulation of transmit data TP1
Receive Power Enable—enables the receive function of the transceiver PTS1

Frame Detect—start of frame delimiter detection indication TS1

Link LED—output capable of driving an LED PTS2
A/D Reference—an input that can be used to set the analog reference voltage

for the internal A/D converter
Serial Approximation Register—supplies the value of the serial approximation

register used in the A/D converter

TS1

Power I

I

Output Driver Types

Name Type I

OL

TP1 Totem pole 4 mA –4 mA 50 pF
TS1 Tri-state 4 mA –4 mA 50 pF

TS2 Tri-state 24 mA –4 mA 120 pF
PTS1 User-programmable tri-state 4 mA –4 mA 50 pF
PTS2 User-programmable tri-state 12 mA –4 mA 50 pF
PTS3 User-programmable tri-state 24 mA –4 mA 120 pF

OD2 Open drain 24 mA –4 mA 120 pF

XO Xtal amplifier Output NA NA

I

OH

Input Types

Name Type Size of Pullup Size of Pulldown

I Input NA NA
IPU Input with internal pullup device >50K Ω
IPD Input with internal pulldown device NA >50K Ω

24 Am79C930

load

NA

P R E L I M I N A R Y

PIN DESCRIPTIONS
Pins with Internal Pull Up or Pull

Down Devices

Several pins of the Am79C930 device include internal
pull up or pull down devices. With the exception of the
RESET pin, these pins are fully programmable as inputs
or outputs when the PCMCIA mode has been selected.
A subset of these pins is programmable when the ISA
Plug and Play mode has been selected. These pins will
come up after RESET in the high impedance state with
the pull up or pull down device actively determining the
value of the pin, unless an external driving source
overdrives the pull up or pull down device. VINITDN
bit (MIR9[2]) is used to turn off all pull up and pull
down devices.

The following list indicates those pins that contain pull
up and pull down devices:

PCMCIA Mode Internal Device Size of Internal

Pin Name Type Device

USER[6]/IRQ5 pull up > 100K Ω
USER[5]/IRQ4 pull up > 100K Ω
USER[4]/LA17 pull up > 100K Ω
USER[3]/SA16 pull up > 100K Ω
USER[2]/LA19 pull up > 100K Ω

USER[1]/IRQ12 pull down > 100K Ω

USER[0]/RFRSH pull down > 100K Ω

LLOCKE/SA15 pull down > 100K Ω

ANTSLT/LA23 pull up > 100K Ω
TXDATA/LA20 pull up > 100K Ω

TXCMD/LA21 pull down > 100K Ω

RXC/IRQ10 pull up > 100K Ω

USER7/IRQ11 pull up > 100K Ω

LFPE pull up > 100K Ω
HFPE pull up > 100K Ω
RXPE pull up > 100K Ω

ANTSLT pull down > 100K Ω

TXCMD pull up > 100K Ω

TXPE pull up > 100K Ω

SDCLK pull up > 100K Ω

SDDATA pull up > 100K Ω

SDSEL[3] pull up > 100K Ω
SDSEL[2] pull up > 100K Ω
SDSEL[1] pull up > 100K Ω

ACT pull up > 100K Ω
LNK pull up > 100K Ω

TXMOD pull up > 100K Ω

STSCHG/BALE pull up > 100K Ω

TXC pull up > 100K Ω

AMD

Following the RESET operation, the Am79C930 firm­ware or driver software should appropriately program
the D bits of TIR and TCR registers, and then set the FN
and EN bits of TIR and TCR registers to set the values
and directions of each of these programmable pins.
Once these operations have been performed, the soft­ware should then program the INITDN bit of MIR9 in or­der to disable all of the pull up and pull down devices.
Unused programmable pins should be programmed for
output mode, or may be left in the default high imped­ance state if an external pull down or pull up device is left
connected to the pin. Unused programmable pins must
not be programmed for input mode with no external
source (pull-device or driver) connected and the INITDN
bit of MIR9 set to a 1, since this could lead to unaccept­able levels of power consumption by the Am79C930 de­vice. For more information on programmable pins, see
the Multi-Function Pins section.

Configuration Pins
PCMCIA

PCMCIA/ISA Bus Interface Select

The value of this pin will asynchronously determine the
operating mode of the Am79C930 device, regardless of
the state of the RESET pin and regardless of the state of
the CLKIN pin. If the PCMCIA pin is tied to VCC, then the
Am79C930 controller will be programmed for PCMCIA
Bus Mode. If the PCMCIA pin is tied to VSS, then the
Am79C930 controller will be programmed for ISA Plug
and Play Bus Interface Mode.

Input

25Am79C930

AMD

P R E L I M I N A R Y

The functionality of the following pins is determined, at
least in part, by the connection of the PCMCIA pin:

PCMCIA Mode ISA Plug and Play Mode

Pin Name Pin Name

USER6 USER6/IRQ5
USER5 USER5/IRQ4
USER4 LA17
USER3 SA16
USER2 LA19
USER1 USER1/IRQ12
USER0 RFRSH

A[14:0] SA[14:0]

LLOCKE SA15

D[7:0] SD[7:0]

CE1 LA18

OE MEMR

WE MEMW

REG AEN

TXDATA LA20

TXCMD LA21

INPACK LA22

ANTSLT LA23

WAIT IOCHRDY

STSCHG BALE

IORD IOR

IOWR IOW

IREQ IRQ9

RXC RXC/IRQ10

USER7 USER7/IRQ11

Host System Interface Pins

PCMCIA Bus Interface

A14–0

Address Bus

Signals A0 through A14 are address-bus-input lines.
Signal A0 is always used because the data interface to
the Am79C930 is only 8-bits wide.

Input

CE1

Card Enable

CE1 is an active low card enable input signal. CE1 is
used to enable even-numbered word address bytes. A0
is used to select between the even and odd numbered
bytes within the addressed word.

Input

D7–0

Data Bus

Signals D7 through D0 are the bidirectional data bus for
PCMCIA. The most significant bit is D7.

Input/Output

OE

Output Enable

OE is an active low-output-enable input signal. OE is
used to gate memory read data from the Am79C930 de­vice onto the PCMCIA data bus. OE should be deas­serted during memory write cycles to the Am79C930
device. OE is used for Common memory accesses and
Attribute memory accesses.

Input

INPACK

Input Acknowledge

The INPACK signal is an active low signal. INPACK is
asserted when the Am79C930 device is selected and
the Am79C930 device can respond to an I/O read cycle
at the address currently on the address bus. This signal
is used by the host to control the enable of any input data
buffer between the card and the CPU. This signal will be
inactive until the card is configured.

Output

IORD

I/O Read

IORD is an active low signal. IORD is asserted by the
host system to indicate to the Am79C930 device that a
read from the Am79C930’s I/O space is being per­formed. The Am79C930 device will not respond to the
IORD signal until it has been configured for I/O opera­tion by the system.

Input

IOWR

I/O Write

IOWR is an active low signal. IOWR is asserted by the
host system to indicate to the Am79C930 device that a
write to the Am79C930’s I/O space is being performed.
The Am79C930 device will not respond to the IOWR sig­nal until it has been configured for I/O operation by
the system.

Input

IREQ

Interrupt Request

IREQ is an active low signal. IREQ is asserted by the
Am79C930 device to indicate to the host that software
service is required. IREQ can operate in the pulse mode
or level mode of operation as defined in the PCMCIA
specification. In pulse mode of operation, an interrupt is
signaled by the Am79C930 device by asserting a low­going pulse of at least 0.5 microseconds (µs). In pulse
mode of operation, the inactive state (i.e., HIGH output)
is driven, not floated. In level mode of operation, an in­terrupt is signaled by the Am79C930 device by assert­ing a LOW level. In level mode of operation, the inactive
state (i.e., HIGH output) is driven, not floated.

Output

26

Am79C930

P R E L I M I N A R Y

Function Mode REG CE1 IORD IOWR A0 OE WE D7–0

Standby mode X H X X X X X High-Z
Common Memory Read Even Byte H L H H L L H Even Byte
Common Memory Read Odd Byte H L H H H L H Odd Byte
Common Memory Write Even Byte H L H H L H L Even Byte
Common Memory Write Odd Byte H L H H H H L Odd Byte
Attribute Memory Read Even Byte L L H H L L H Even Byte
Attribute Memory Read Odd Byte L L H H H L H Odd Byte
Attribute Memory Write Even Byte L L H H L H L Even Byte
Attribute Memory Write Odd Byte L L H H H H L Odd Byte
I/O Read Even Byte L L L H L H H Even Byte
I/O Read Odd Byte L L L H H H H Odd Byte
I/O Write Even Byte L L H L L H H Even Byte
I/O Write Odd Byte L L H L H H H Odd Byte

REG

Attribute Memory Select

REG is an active low-input signal that selects among At­tribute memory and Common memory in the Am79C930
device and the Am79C930-based PCMCIA card. When
REG is asserted, then the current access is to Attribute
memory or I/O. When REG is not asserted, then the cur­rent access is to Common memory.

Input

device from the PCMCIA data bus. WE should be deas­serted during memory read cycles to the Am79C930.
WE is used for Common memory accesses and Attrib­ute memory accesses.

ISA (IEEE P996) Bus interface

LA23–17, SA16–0

Address Bus

AMD

Signals SA0 through SA16 and LA17 through LA23

RESET

Reset

RESET is an active high-input signal that clears the
Card Configuration Option Register CCOR) and places
the Am79C930 device into an unconfigured (PCMCIA­Memory-Only Interface) state. This pin also causes a
RESET to be asserted to each of the Am79C930 core
function units (i.e., PCMCIA interface, CPU, and Trans­ceiver Attachment Interface).

Input

are address-bus-input lines which enable direct address
of up to 16 Mbytes of memory space in an ISA-based
Am79C930 design. Signal SA0 is always used, because
the data interface to the Am79C930 is only 8-bits wide.

SD7–0

Data Bus

Signals SD7 through SD0 are the bidirectional data bus
for ISA. The most significant bit is SD7.

Input/Output

Input

STSCHG

Status Change

The STSCHG signal is an active low signal. STSCHG as
implemented in the Am79C930 device is only used for
the PCMCIA WAKEUP indication. The CHANGED bit
and the SIGCHG bit of the Card Configuration and
Status Register (CCSR) are not supported by the
Am79C930 device. The Pin Replacement Register is
not supported by the Am79C930 device.

Output

WAIT

Extend Bus Cycle

The WAIT signal is an active low signal. WAIT is as­serted by the Am79C930 device to delay completion of
the access cycle currently in progress.

Output

WE

Write Enable

WE is an active low write-enable input signal. WE is
used to strobe memory write data into the Am79C930

Input

AEN

Address Enable

AEN is driven LOW by the ISA host to indicate when an
I/O address is valid.

Input

BALE

Bus Address Latch Enable

BALE is driven by the ISA host to indicate when the ad­dress signal lines are valid.

Input

IOCHRDY

I/O Channel Ready

The IOCHRDY signal is deasserted by the Am79C930
device at the beginning of a memory access in order
to delay completion of the memory access cycle then
in progress. The IOCHRDY signal is reasserted by
the Am79C930 device when the memory access
is completed.

Output

27Am79C930

AMD

P R E L I M I N A R Y

IOR

I/O Read

The IOR signal is made active by the ISA host in order to
read data from the Am79C930 device’s I/O space.

Input

IOW

I/O Write

The IOW signal is made active by the ISA host in order to
write data to the Am79C930 device’s I/O space.

Input

MEMR

Memory Read

The MEMR signal is made active by the ISA host in
order to read data from the Am79C930 device’s
memory space.

Input

MEMW

Memory Write

The MEMW signal is made active by the ISA host in
order to write data to the Am79C930 device’s
memory space.

Input

IRQ[4,5,9–12]

Interrupt Request

IRQ[x] is asserted by the Am79C930 device to indicate
to the host that software service is required. IRQ[x] is
held at the inactive level when no interrupt is requested.
Only one of the six IRQ[x] lines may be selected for use
at any one time. IRQ[x] outputs may be programmed for
edge or level operation. Edge or level programming is
part of the ISA Plug and Play initialization procedure.
When edge programming has been selected, then the
selected IRQ[x] pin is
an active interrupt request, and the selected IRQ[x] pin

driven

is
quest. When level programming has been selected,
then the selected IRQ[x] pin is driven to a LOW level and
the selected IRQ pin is
interrupt request (i.e., open drain operation). “Unused”
(i.e., unselected) IRQ[x] lines will be held in a
high impedance state, even when interrupt service
is requested.

to a low level to indicate an inactive interrupt re-

driven

to a HIGH level to indicate

floated

to indicate an inactive

Output

RESET

Reset

RESET is an active high input signal. When driven to a
HIGH level, RESET causes the Am79C930 device to
immediately place all ISA bus outputs into a high imped­ance state. This pin also causes a RESET to be as­serted to each of the Am79C930 core function units (i.e.,
ISA interface state machine, 80188, and Transceiver
Attachment Interface).

Input

RFRSH

Refresh

The RFRSH signal is made active by the ISA host to in­dicate that the current bus cycle is a refresh operation.

Input

Memory Interface Pins

MA16–0

Memory Address Bus

Signals MA0 through MA16 are address-bus-output
lines which enable direct address of up to 128 Kbytes of
SRAM memory and 128 Kbytes of Flash memory in a
Am79C930-based application. The Am79C930 device
will drive these signals to Access memory locations
within the SRAM or the Flash memory.

Output

FCE

Flash Memory Chip Enable

FCE is an active low chip enable output signal. FCE is
used to activate the Flash memory device’s control logic
and input buffers during accesses on the memory
interface bus.

Output

MD7–0

Memory Data Bus

Signals MD7 through MD0 are the bidirectional data bus
for the SRAM and the Flash memory. The most signifi­cant bit is MD7.

Input/Output

MOE

Memory Output Enable

MOE is an active low output that is used to gate the out­puts of the SRAM and Flash memory device’s during
read cycles.

Output

SCE

SRAM Chip Enable

SCE is an active low chip enable output signal. SCE
is used to activate the SRAM device’s control logic and
input buffers during accesses on the memory
interface bus.

Output

MWE

Memory Write Enable

MWE is an active low output that is used to latch address
and data information in the SRAM and Flash memory
devices during write cycles. Address information for
SRAM and Flash memory write cycles is valid on the
MA16–0 pins at the falling edge of MWE. Data informa­tion for SRAM and Flash memory write cycles is valid on
the MD7–0 pins at the rising edge of MWE.

Output

XCE

eXtra Chip Enable

XCE is an active low chip enable output signal. XCE is
used to activate a peripheral device’s control logic and
input buffers during accesses on the memory interface
bus. XCE is activated by appropriate signaling from the
80188 embedded core. XCE may not be activated
through the system interface. Sixteen bytes of address
range are allotted for use with the XCE signal.

Output

28

Am79C930

P R E L I M I N A R Y

Clock Pins

CLKIN

System Clock

CLKIN is the clock input for the Am79C930 device’s
logic functions. CLKIN is used to drive the CLKIN input
of the embedded 80188 core. The BIU section uses the
CLKOUT signal from the 80188 embedded core as a
reference. The register interface portions of the TAI use
the CLKIN signal as a reference. The TAI uses a divided
version of this clock to obtain a reference clock for data
transmission, where the divisor value is selectable
through a register; this allows different data rates to be
set. The TAI DPLL clock recovery circuit will use a refer­ence clock that is 20 times the selected data rate, when­ever the ECLK bit of the Receiver Configuration
Register (TCR3) is set to a 0. This DPLL reference
clock is also derived from the CLKIN signal. When the
ECLK bit is set to 1, the TAI DPLL is not used, and the
incoming receive data stream is clocked with the RXCIN
signal. The highest frequency allowed at the CLKIN in­put is 40 MHz.

Input

PMX[1–2]

Power Management Crystal

PMX[1–2] are the reference crystal inputs for the clock
that drives the power management logic. The nominal
frequency for this crystal input is 32 kHz.

Input/Output

RXCIN

Receive Clock In

RXCIN is the reference clock input for the receive data
stream entering the Am79C930 device when the ECLK
bit of TCR2 is set to a 1. Rising edges of the RXCIN input
will mark valid sample points for the data arriving at the
RXDATA input.

Input

RXC

Receive Clock Out

RXC is the reference clock output for the receive data
stream that is derived either from the DPLL or from the
RXCIN pin, depending on the selected Am79C930 de­vice configuration. This clock is provided for test pur­poses only. This function is only available when the
Am79C930 device is programmed for the PCMCIA
mode of operation.

Output

TXC

Transmit Clock

TXC is the clock reference for data transmission at the
network interface. Some systems may require that the
Am79C930 device deliver the transmit data with a clock
for reference. In such systems, the TXC pin may be
configured as an output and the TXC signal will be
generated by the Am79C930 device as a derivative from
the CLKIN input. TXDATA will change on falling edges

Input/Output

AMD

of TXC, allowing ample setup and hold time for valid
sampling of TXDATA with the rising edge of TXC.

Some systems may require that the Am79C930 device
deliver the transmit data according to a clock reference
that is external to the Am79C930 device. In such sys­tems, the TXC pin may be configured as an input.
TXDATA will change on falling edges of TXC, allowing
ample setup and hold time for valid sampling of
TXDATA with the rising edge of TXC.

System Management Pins
PWRDWN

Power Down

PWRDWN is an active high output that indicates that the
Am79C930 device has been placed into a low power
mode to conserve power. While PWRDWN is asserted,
the internal clock that is routed to the 80188 embedded
core and the network interface (TAI section) has been
halted. PCMCIA CCRs and SIRs are still active while in
the low power mode.

Output

USER[0–6]

User-Definable Pins

USER[0–6] are pins that are controlled directly through
TIR and TCR registers. These pins may serve as out­puts, inputs or as I/O through the use of high-impedance
control and data bits in TIR and TCR registers. These
pins are available only in PCMCIA mode.

Note: Some of the TAI interface pins are similarly

programmable, thereby allowing some user-defined
functionality when using the ISA Plug and Play mode
of operation.

TAI Interface Pins

Input/Output

ANTSLT

Antenna Select

ANTSLT is an active high output that indicates to the
transceiver which antenna should be utilized for both
transmission and reception. ANTSLT allows for selec­tion among two possible antennas.

Output

ANTSLT

Antenna Select

ANTSLT is an active low output that is the logical inverse
of the ANTSLT output. This signal is only available when
the Am79C930 device is configured for the PCMCIA
mode of operation.

Output

FDET

Frame Detect

FDET is an active low output that indicates when the
Am79C930 device has located the Start of Frame De­limiter in the receive or transmit data stream. This signal

Output

29Am79C930

AMD

is deasserted when the RESET pin is issued or the CRC
reset bit is set to 1 (SIR0); when the TXS bit is set to 1
(TIR8) or the RXS bit is set to 1 (TIR16); when TXRES
bit set to 1 (TIR8), or the RXRES bit is set to 1 (TIR16), or
the SRES bit is set to 1 (TIR0).

P R E L I M I N A R Y

HFCLK

High Frequency Clock

HFCLK provides a reference clock for a transceiver syn­thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one-half the clock rate of the CLKIN sig­nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. HFCLK will be
LOW whenever the HFPE signal is inactive.

Output

HFPE

High Frequency Power Enable

HFPE is an active low output that is used to power up the
high-frequency VCO section of the transceiver. This pin
is directly controllable through a TAI register and is also
programmable as an I/O with read capability.

Output

LFCLK

Low Frequency Clock

LFCLK provides a reference clock for a transceiver syn­thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one half the clock rate of the CLKIN sig­nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. LFCLK will be
LOW whenever the LFPE signal is inactive.

Output

PLL is used for clock recovery, then the RXDATA input
will expect valid data at rising edges of the RXCIN input.
External versus internal PLL use is determined through
the setting of the ECLK bit in TCR2.

RXPE

Receiver Power Enable

RXPE is an active low output that is used to power up the
receive section of the transceiver. This pin is directly
controllable through a TAI register and is also program­mable as an I/O with read capability.

Output

TXCMD

Transmit Command

TXCMD is an active low output that is used to enable the
transceiver’s transmission onto the medium. When
TXCMD is low, the transceiver should enable its trans­mission function and disable its receive function. When
TXCMD is high, the transceiver should disable its
transmission function and return to receive functionality.
This pin is directly controlled by the transmit state
machine in the TAI and the TXCMD bit of TIR11. The
timing of the TXCMD signal is programmable from a TAI
register. The polarity of this pin is programmable from a
TAI register.

Output

TXCMD

Transmit Command

TXCMD is an active high output that is the logical in­verse of the TXCMD output. This signal is only available
when the Am79C930 device is configured for the
PCMCIA mode of operation.

Output

LFPE

Low Frequency Power Enable

LFPE is an active low output that is used to power up the
low-frequency synthesizer section of the transceiver.
This pin is directly controllable through a TAI register
and is also programmable as an I/O with read capability.

Output

LLOCKE

Synthesizer Lock

LLOCKE is a general-purpose input that can be used to
convey a transceiver’s synthesizer lock signal to the
80188 embedded controller. The value of the LLOCKE
pin is readable at a register bit in the TIR register space.

Input

RXDATA

Receive Data

RXDATA is an input that accepts the serial bit stream for
reception, including Preamble, SFD, PHY header, MAC
header, Data and FCS field. The RXDATA input stream
is expected to be NRZ data. Clock recovery is per­formed internal to the Am79C930 device. If an external

30

Input

Am79C930

TXDATA

Transmit Data

TXDATA is an output that provides the serial bit stream
for transmission, including preamble, SFD, PHY
header, MAC header, data and FCS field, or a subset
thereof. Data delivered from the MAC to the transceiver
is valid at the rising edge of TXC and changes on the fall­ing edge of TXC. The value of the TXDATA pin is pro­grammable to 1, 0, or “last bit transmitted” whenever the
transmit circuit is idle and during ramp up and ramp
down of the transceiver’s transmit circuits.

Output

TXDATA

Transmit Data

TXDATA is an output that is the logical inverse of the
TXDATA output. This signal is only available when the

Am79C930 device is configured for the PCMCIA mode
of operation. The value of the TXDATA pin is 0 when­ever the transmit circuit is idle and during ramp up and
ramp down of the transmitter.

Output