AMD Advanced Micro Devices AM79C90JC, AM79C90PC, AM79C90JCTR Datasheet

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PRELIMINARY

Am79C90

CMOS Local Area Network Controller for Ethernet
(C-LANCE)

DISTINCTIVE CHARACTERISTICS

Compatible with Ethernet and IEEE 802.3
10BASE-5 Type A, and 10BASE-2 Type B,
“Cheapernet,” 10BASE-T

Easily interfaced with 80x86, 680x0, Am29000

™

Z8000

microprocessors



On-board DMA and buffer management, 64-byte
Receive, 48-byte Transmit FIFOs

24-bit-wide linear addressing (Bus Master Mode)
Network and packet error reporting

,

Back-to-back packet reception with as little as

0.5 µ s interframe spacing
Diagnostic Routines

—Internal/external loopback
—CRC logic check
—Time domain reflectometer

Low power consumption for power-sensitive
applications

Completely software- and hardware-compatible with
AMD’s LANCE device (Am7990) (see Appendix A)

GENERAL DESCRIPTION

The Am79C90 CMOS Local Area Network Controller
for Ethernet (C-LANCE) is a 48-pin VLSI device de­signed to greatly simplify interfacing a microcomputer or
minicomputer to an IEEE 802.3/Ethernet Local Area
Network. The C-LANCE, in conjunction with the
Am7992B Serial Interface Adapter (SIA), Am7996 or
Am79C98 and Am79C100 Transceiver, and closely
coupled local memory and microprocessor, is intended

BLOCK DIAGRAM

Parallel

Bus

Interface

C-LANCE/

CPU

Control

Bus

Interface

Station

Address

Detection

Local CPU Interface

DAL15:0

A23:16

BM
1/BUSAKO

BM

INTR

HOLD

HLDA

ALE/AS

CS

ADR

AS

D

DALO

DALI

READ

0/BYTE

READY
RESET

to provide the user with a complete interface module for
an Ethernet network. The Am79C90 is designed using
a scalable CMOS technology and is compatible with a
variety of microprocessors. On-board DMA, advanced
buffer management, and extensive error reporting and
diagnostics facilitate design and improve system
performance.

DMA/Data

Path Control

Retry
Logic

Microprogram

Store

Serial I/O

Interface

RX
RCLK
TX
TCLK
CLSN
TENA
RENA

17881C-1

Am7992B SIA Interface

Publication# 17881 Rev: CAmendment/0
Issue Date: January 1998

This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.

1

AMD

P R E L I M I N A R Y

RELATED AMD PRODUCTS

Part No. Description

Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver
Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+)

TM

TM

(ILACCTM)

)

Am79C900 Integrated Local Area Communications Controller
Am79C940 Media Access Controller for Ethernet (MACE
Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)



Am79C961 PCnet-ISA Single-Chip Ethernet Controller (with Microsoft

Plug n’ Play support)
Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386DX, 486 and VL buses)
Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C98 Twisted-Pair Ethernet Transceiver (TPEX)

TM

Am79C981 Integrated Multiport Repeater Plus
Am79C987 Hardware Implemented Management Information Base

(IMR+TM)

TM

(HIMIBTM)

CONNECTION DIAGRAMS

DIP PLCC

1

V

SS

DAL7
DAL6
DAL5
DAL4
DAL3
DAL2

DAL1
DAL0

READ

INTR

DALI

DALO

DAS

BM0/BYTE

BM1/BUSAKO

HOLD/BUSRQ

ALE/AS

HLDA

ADR

READY

RESET

V

CS

SS

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Note:

Pin 1 is marked for orientation.

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

17881B-2

V

DD

DAL8
DAL9
DAL10
DAL11
DAL12
DAL13
DAL14
DAL15
A16
A17

A18
A19

A20
A21

A22
A23
RX

RENA
TX
CLSN
RCLK
TENA
TCLK

NC

NC
DAL2
DAL3
DAL4
DAL5
DAL6
DAL7

VSS

VDD
DAL8
DAL9

DAL10
DAL11
DAL12

NC

NC

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

DAL1

DAL0

NC

NC

READ

7

29

DAL13

INTR

6

30

DAL14

DALI

5

31

DAL15

4

32

DALO

NC

3

33

A16

A17

NC

DAS

NCNCBM1/BUSRQ

BM0/BYTE

1

67

68

36

NC

37

66

38

NC

298

35

342728

A18

A19

65

39

A20

64

40

A21

HOLD/BUSRQ

ALE/AS

63

41

42

A22

A23

HLDA

62

61

43

RX

17881B-3

NC

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

RENA

NC

CS

NC
NC
ADR

READY
RESET

NC
NC
VSS
TCLK
TENA

RCLK
CLSN
TX
NC
NC

2

Am79C90

PRELIMINARY

TYPICAL ETHERNET/CHEAPERNET NODE

Ethernet

Local

CPU

Cheapernet

Local

CPU

Local

Memory

Local Bus

Local

Memory

Local Bus

Am79C90
C-LANCE

Am79C90

C-LANCE

DTE

DTE

Am7992B

SIA

Am7992B

SIA

AUI

Cable

Am7996

Transceiver

Power

Supply

MAU

Am7996

Transceiver

Power

Supply

Ethernet Coax

TAP

RG58A/U or
RG58C/U
BNC “T”

Typical Ethernet 10BASE-T Node

Local

CPU

Local

CPU

Local

Memory

Local Bus

Local

Memory

Local Bus

Am79C90
C-LANCE

Am79C90
C-LANCE

DTE

Am7992B

SIA

DTE

Am7992B

SIA

AUI

Cable

MAU

Am79C98

Am79C100

Power

Supply

Am79C98

Am79C100

Twisted-Pair

AUI—Attachment Unit Interface DTE—Data Terminal Equipment MAU—Medium Attachment Unit

Twisted-Pair

17881C-4

Am79C90 3

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed
by a combination of the elements below.

AM79C90 P C

DEVICE NUMBER/DESCRIPTION

Am79C90
CMOS Local Area Network Controller for Ethernet

B

OPTIONAL PROCESSING

Blank=Standard Processing
TR=Tape and Reel Packaging

OPERATING CONDITIONS

C = Commercial (0°C to +70°C)

PACKAGE TYPE

P=48-Pin Plastic DIP (PD 048)
J=68-Pin Plastic Leaded Chip Carrier (PL 068)

SPEED

Not Applicable

Valid Combinations

AM79C90 PC, JC, JCTR

Valid Combinations

Valid combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

4 Am79C90

PRELIMINARY

PIN DESCRIPTION
A16–A23

High Order Address Bus (Output, Three-State)

Additional address bits to access a 24-bit address.
These lines are driven as a Bus Master only.

ADR

Register Address Port Select (Input)

When the C-LANCE is a Slave, ADR indicates which of
the two register ports is selected. ADR LOW selects
register data port; ADR HIGH selects register address
port. ADR must be valid throughout the data portion of
the bus cycle and is only used by the C-LANCE when

is LOW.

CS

ALE/AS

Address Latch Enable (Output, Three-State)

Used to demultiplex the DAL lines and define the
address portion of the bus cycle. This l/O pin is pro­grammable through bit (01) of CSR3.

As ALE (CSR3 (01), ACON = 0), the signal transitions
from a HIGH to a LOW during the address portion of
the transfer and remains LOW during the data portion.
ALE can be used by a Slave device to control a latch on
the bus address lines. When ALE is HIGH, the latch is
open, and when ALE goes LOW, the latch is closed.

(CSR3 (01), ACON = 1), the signal pulses LOW

As AS
during the address portion of the bus transaction. The
LOW-to-HlGH transition of AS can be used by a Slave
device to strobe the address into a register.

The C-LANCE drives the ALE/AS line only as a Bus
Master.

BM0/BYTE, BM

(Output, Three-State)

The two pins are programmable through bit (00) of
CSR3.

0, BM1—If CSR3 (00) BCON = 0

BM
PIN 15 = BM0 (Output, Three-State) (48-Pin DlPs)
PIN 16 = BM1 (Output, Three-State) (48-Pin DlPs)

BM0, BM1 (Byte Mask). This indicates that the byte(s)
on the DAL are to be read or written during this bus
transaction. The C-LANCE drives these lines only as a
Bus Master. It ignores the Byte Mask lines when it is a
Bus Slave and assumes word transfers.

1

/BUSAKO

Byte selection using Byte Mask is done as described
by the following table:

BM

1

LOW LOW Whole Word

LOW HIGH Upper Byte
HlGH LOW Lower Byte
HlGH HIGH None

BYTE, B
PIN 15 = BYTE (Output, Three-State) (48-Pin DlPs)
PIN 16 = BUSAKO (Output) (48-Pin DIPs)

Byte selection may also be done using the BYTE line
and DAL00 line, latched during the address portion of
the bus cycle. The C-LANCE drives BYTE only as a
Bus Master and ignores it when a Bus Slave selection
is done (similar to BM0, BM1). Byte selection is done
as outlined in the following table:

B
is not requesting the bus and it receives HLDA,
BUSAKO will be driven LOW. If the C-LANCE is re­questing the bus when it receives HLDA, BUSAKO will
remain HIGH.

USAKO—If CSR3 (00) BCON = 1

BYTE DAL

LOW LOW Whole Word

LOW HIGH Illegal Condition
HlGH LOW Lower Byte
HlGH HIGH Upper Byte

USAKO is a bus request daisy chain output. If the chip

BM

0

00

Selection

Selection

Byte Swapping

In order to be compatible with the variety of 16-bit mi­croprocessors available to the designer, the C-LANCE
may be programmed to swap the position of the upper­and lower-order bytes on data involved in transfers with
the internal FIFOs.

Byte swapping is done when BSWP = 1. The most
significant byte of the word in this case will appear on
DAL lines 7–0 and the least significant byte on DAL
lines 15–8.

When BYTE = H (indicating a byte transfer) the table in­dicates on which part of the 16-bit data bus the actual
data will appear.

Whenever byte swap is activated, the only data that is
swapped is data traveling to and from the Transmit/
Receive FIFOs.

Am79C90 5

PRELIMINARY

Mode Bits

Signal Line

BYTE = L and
DAL00 = L

BYTE = L and
DAL00 = H

BYTE = H and
DAL00 = H

BYTE = H and
DAL00 = L

BSWP = 0

and BCON = 1

Word Word

Illegal Illegal

Upper Byte Lower Byte

Lower Byte Upper Byte

BSWP = 1

and BCON = 1

CLSN

Collision (Input)

A logical input that indicates that a collision is occurring
on the channel.

CS

Chip Select (Input)

Indicates, when asserted, that the C-LANCE is the
Slave device of the data transfer. CS
throughout the data portion of the bus cycle. CS must
not be asserted when HLDA is LOW.

must be valid

DAL00–DAL15

Data/Address Lines (Input/Output, Three-State)

The time multiplexed Address/Data bus. During the ad­dress portion of a memory transfer, DAL00–DAL15
contains the lower 16 bits of the memory address. The
upper 8 bits of address are contained in A16–A23.

During the data portion of a memory transfer, DAL00–
DAL15 contains the read or write data, depending on
the type of transfer.

The C-LANCE drives these lines as a Bus Master and
as a Bus Slave.

D

ALI

Data/Address Line In (Output, Three-State)

An external bus transceiver control line. D
serted when the C-LANCE reads from the DAL lines. It
will be LOW during the data portion of a READ transfer
and remain HIGH for the entire transfer if it is a WRITE.
DALI is driven only when C-LANCE is a Bus Master.

D

ALO

Data/Address Line Out (Output, Three-State)

An external bus transceiver control line. D
serted when the C-LANCE drives the DAL lines. DALO
will be LOW only during the address portion if the trans­fer is a READ. It will be LOW for the entire transfer if the
transfer is a WRITE. DALO is driven only when
C-LANCE is a Bus Master.

ALI is as-

ALO is as-

DAS

Data Strobe (Input/Output, Three-State)

Defines the data portion of the bus transaction. D
high during the address portion of a bus transaction
and low during the data portion. The LOW-to-HlGH
transition can be used by a Slave device to strobe bus
data into a register. DAS is driven only as a Bus Master.

AS is

HLDA

Bus Hold Acknowledge (Input)

A response to HOLD
to the chip’s assertion of HOLD, the chip is the Bus
Master.

During Bus Master operation, the C-LANCE waits for

A to be deasserted HIGH before reasserting

HLD
HOLD LOW. This insures proper bus handshake under
all situations.

. When HLDA is LOW in response

HOLD/BUSRQ

Bus Hold Request (Output, Open Drain)

Asserted by the C-LANCE when it requires access to
memory. HOLD
transaction. The function of this pin is programmed
through bit (00) of CSR3. Bit (00) of CSR3 is cleared
when RESET is asserted.

When CSR3 (00) BCON = 0
PIN 17 = HOLD

(Output Open Drain and input sense) (48-Pin DIPs)
When CSR3 (00) BCON = 1
PIN 17 = BUSRQ (I/O Sense, Open Drain) (48-Pin DlPs)
If the C-LANCE wants to use the bus, it looks at HOLD/

BUSRQ; if it is HIGH the C-LANCE can pull it LOW and
request the bus. If it is already LOW, the C-LANCE
waits for it to go inactive-HlGH before requesting the
bus.

is held LOW for the entire ensuing bus

INTR

Interrupt (Output, Open Drain)

An attention signal that indicates, when active, that one
or more of the following CSR0 status flags is set: BABL,
MERR, MISS, RINT, TINT or IDON. INTR
bit 06 of CSR0 (INEA = 1). INTR remains asserted until
the source of Interrupt is removed.

is enabled by

RCLK

Receive Clock (Input)

A 10 MHz square wave synchronized to the Receive
data and only active while receiving an Input Bit
Stream.

6 Am79C90

PRELIMINARY

READ

(Input/Output, Three-State)

Indicates the type of operation to be performed in the
current bus cycle. This signal is an output when the
C-LANCE is a Bus Master.

High—Data is taken off the DAL lines by the

C-LANCE.

Low—Data is placed on the DAL lines by the

C-LANCE.

The signal is an input when the C-LANCE is a Bus
Slave.

High—Data is placed on the DAL lines by the

C-LANCE.

Low—Data is taken off the DAL lines by the

C-LANCE.

READY

(Input/Output, Open Drain)

When the C-LANCE is a Bus Master, READ
asynchronous acknowledgment from the bus memory
that it will accept data in a WRITE cycle or that it has
put data on the DAL lines in a READ cycle.

As a Bus Slave, the C-LANCE asserts READY when it
has put data on the DAL lines during a READ cycle or
is about to take data off the DAL lines during a write
cycle. READY is a response to DAS and will return High
after DAS has gone High. READY is an input when the
C-LANCE is a Bus Master and an output when the
C-LANCE is a Bus Slave.

Y is an

RENA

Receive Enable (Input)

A logical input that indicates the presence of carrier on
the channel.

RESET

Reset (Input)

Reset causes the C-LANCE to cease operation, clear
its internal logic, force all three-state buffers to the high­impedance state, and enter an idle state with the stop
bit of CSR0 set. It is recommended that a 3.3 k Ω pullup
resistor be connected to this pin.

RX

Receive (Input)

Receive Input Bit Stream.

TCLK

Transmit Clock (Input)

10 MHz clock.

TENA

Transmit Enable (Output)

Transmit Output Bit Stream enable. When asserted, it
enables valid transmit output (TX).

TX

Transmit (Output)

Transmit Output Bit Stream.

V

DD

Power Supply Pin +5 V ± 5%

It is recommended that 0.1 µ F and 10 µ F decoupling
capacitors be used between V

V

SS

Ground

Pin 1 and 24 (48-Pin DlPs) should be connected
together externally, as close to the chip as possible.

DD

and V

SS

.

Am79C90 7

AMD

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

The parallel interface of the CMOS Local Area Network
Controller for Ethernet (C-LANCE) has been designed
to be “friendly” or easy to interface to a variety of popular
microprocessors. These microprocessors include the
Am29000, 80x86, 680x0, Z8000 and LSI-11. The
C-LANCE has a 24-bit wide linear address space when
it is in the Bus Master Mode. A programmable mode of
operation allows byte addressing in one of two ways:
aByte/Word control signal compatible with the 80x86
and Z8000 or an Upper Data Strobe and Lower Data

Address

Bits

16–23

A16–A23

CPU

DAL0–DAL15

ALE

Data and

Address

Bits 0–15

Buffer

Buffer

Strobe signal compatible with microprocessors such as
the 68000. A programmable polarity on the Address
Strobe signal eliminates the need for external logic. The
C-LANCE interfaces with both multiplexed and de­multiplexed data busses and features control signals for
address/data bus transceivers. The C-LANCE is pin-for­pin compatible with AMD’s LANCE device (Am7990).
Please refer to Appendix B for a complete comparison
between the C-LANCE and LANCE devices.

Control

A16–A23

DAL0 – DAL15

Buffer

ALE

A16–A23

DAL0–DAL15A16–A23Control

Figure 1. C-LANCE/CPU Interfacing Multiplexed Bus

Latch

Decoder

C-LANCE

ALE

ADR

CS

17881B-5

8

Am79C90

Data Bus

P R E L I M I N A R Y

Address

Bus

Data/Address
Bits 0-15

A0–A15

Latch

A16–A23

Buffer

A0–A23

Decode

ALE
Address

Bits 16-23

C-LANCE

CS

Figure 2. C-LANCE/CPU Interfacing Demultiplexed Bus

AMD

17881B-6

During initialization, the CPU loads the starting address
of the initialization block into two internal control regis­ters. The C-LANCE has four internal control and status
registers (CSR0, 1, 2, 3) which are used for various
functions, such as the loading of the initialization block
address, and programming different modes and status
conditions. The host processor communicates with the
C-LANCE during the initialization phase, for demand
transmission, and periodically to read the status bits fol­lowing interrupts. All other transfers to and from the
memory are automatically handled as DMA.

Interrupts to the microprocessor are generated by the
C-LANCE upon:

completion of its initialization routine
the reception of a packet
the transmission of a packet
transmitter timeout error
a missed packet
memory error

The cause of the interrupt is ascertained by reading
CSR0. Bit (06) of CSR0, (INEA), enables or disables
interrupts to the microprocessor. In systems where poll­ing is used in place of interrupts, bit (07) of CSR0,
(INTR), indicates an interrupt condition.

The basic operation of the C-LANCE consists of two dis­tinct modes: transmit and receive. In the transmit mode,
the C-LANCE chip directly accesses data (in a transmit
buffer) in memory. It prefaces the data with a preamble,
start frame delimiter (SFD), and calculates and appends
a 32-bit CRC. On transmission, the first byte of data

loads into the 48-byte Transmit FIFO; the C-LANCE
then begins to transmit preamble while simultaneously
loading the rest of the packet into Transmit FIFO for
transmission.

In the receive mode, packets are sent via the Am7992B
SlA to the C-LANCE. The packets are loaded into the
64-byte Receive FIFO for preparation of automatic
downloading into buffer memory. A CRC is calculated
and compared with the CRC appended to the data pack­et. If the calculated CRC does not agree with the packet
CRC, an error bit is set.

Addressing

Packets can be received using three different destina­tion addressing schemes: physical, logical and
promiscuous.

The first type is a full comparison of the 48-bit destina­tion address in the packet with the node address that
was programmed into the C-LANCE during an initializa­tion cycle. There are two types of logical addresses.
One is group type mask where the 48-bit address in the
packet is put through a hash filter to map the 48-bit
physical addresses into 1 of 64 logical groups. If any of
these 64 groups have been preselected as the logical
address, then the 48-bit address is stored in main mem­ory. At this time, a look up is performed by the host com­puter comparing the 48-bit incoming address with the
pre-stored 48-bit logical address. This mode can be
useful if sending packets to all of a particular type of de­vice simultaneously (i.e., send a packet to all file servers
or all printer servers). Additional details on logical ad­dressing can be found in the INITIALIZATION section

9Am79C90

AMD

P R E L I M I N A R Y

under “Logical Address Filter.” The second logical ad­dress is a broadcast address where all nodes on the net­work receive the packet. The last receive mode of
operation is referred to as “promiscuous mode” in which
a node will accept all packets on the medium regardless
of their destination address.

Collision Detection and Implementation

The Ethernet and IEEE 802.3 CSMA/CD network ac­cess algorithms are implemented completely within the
C-LANCE. In addition to listening for a clear medium be­fore transmitting, Ethernet handles collisions in a prede­termined way. Should two transmitters attempt to seize
the medium at the same time, they will collide and the
data on the medium will be garbled. The transmitting
nodes listen while they transmit, detect the collision,
then continue to transmit for a predetermined length of
time to “jam” the network and ensure that all nodes have
recognized the collision. The transmitting nodes then
delay a random amount of time according to the Ether­net “truncated binary backoff” algorithm in order that the
colliding nodes do not try to repeatedly access the net­work at the same time. The C-LANCE also offers a se­lectable Modified Backoff Algorithm for better
performance on busy networks. Up to 16 attempts to ac­cess the network are made by the C-LANCE before re­porting an error due to excessive collisions.

Error Reporting and Diagnostics

Extensive error reporting is provided by the C-LANCE.
Error conditions reported relate either to the network as
a whole or to individual data packets. Network-related
errors are recorded as flags in the CSRs and are exam­ined by the CPU following interrupt. Packet-related er­rors are written into descriptor entries corresponding to
the packet.

System errors include:

Babbling Transmitter
—Transmitter attempting to transmit more than

1518 bytes, excluding preamble and start frame

delimiter
Collision
—Collision detection circuitry nonfunctional
Missed Packet
—Insufficient buffer space
Memory timeout
—Memory response failure

Packet-related errors:

CRC
—Invalid data
Framing
—Packet did not end on a byte boundary

Overflow/Underflow
—Indicates abnormal latency in servicing a DMA

request
Buffer
—Insufficient buffer space available

The C-LANCE performs several diagnostic routines
which enhance the reliability and integrity of the system.
These include a CRC check and two loop back modes
(internal/external). Errors may be introduced into the
system to check error detection logic. A Time Domain
Reflectometer is incorporated into the C-LANCE to aid
system designers in locating faults in the Ethernet physi­cal medium. Shorts and opens manifest themselves in
reflections which are sensed by the TDR.

10

Am79C90

P R E L I M I N A R Y

Transmit Descriptor for 1st Data Buffer
Transmit Descriptor for 2nd Data Buffer
Transmit Descriptor for 3rd Data Buffer

Transmit Descriptor for Nth Data Buffer

Receive Descriptor for 1st Data Buffer
Receive Descriptor for 2nd Data Buffer
Receive Descriptor for 3rd Data Buffer

Receive Descriptor for Nth Data Buffer

AMD

Initialization
Block

Transmit
Descriptor
Ring
(4 words
per entry)

Receive
Descriptor
Ring
(4 words
per entry)

Transmit Data Buffer #1
Transmit Data Buffer #2
Transmit Data Buffer #3

Transmit Data Buffer #N
Receive Data Buffer #1
Receive Data Buffer #2
Receive Data Buffer #3

Receive Data Buffer #N

Figure 2-1. C-LANCE/Processor Memory Interface

Transmit
Data
Buffers

Receive
Data
Buffers

17881B-7

11Am79C90

AMD

C-LANCE CSR Registers

Pointer to Initialization Block

Initialization
Block

Mode of Operation
Physical Address
Logical Address Filter

Pointer to Receive Ring
Number of Receive Entries (N)
Pointer to Transmit Ring
Number of Transmit Entries (M)

P R E L I M I N A R Y

Receive Descriptor Ring

Address of Receive Buffer 1
Buffer 1 Status
Buffer 1 Byte Count
Buffer 1 Message Count

Transmit Descriptor Ring

Address of Transmit Buffer 1
Buffer 1 Status
Buffer 1 Byte Count
Buffer 1 Error Status

Receive Buffer

Data

Packet

1

Data

2
2
2
2

N
N
N
N

2
2
2
2

Packet

2

Data

Packet

N

Transmit Buffer

Data

Packet

1

Data

Packet

2

Figure 2-2. C-LANCE Memory Management

Buffer Management

A key feature of the C-LANCE and its on-board DMA
channel is the flexibility and speed of communication
between the C-LANCE and the host microprocessor
through common memory locations. The basic organi­zation of the buffer management is a circular queue of
tasks in memory called descriptor rings as shown in
Figures 2-1 and 2-2. There are separate descriptor rings
to describe transmit and receive operations. Up to 128
tasks may be queued up on a descriptor ring awaiting
execution by the C-LANCE. Each entry in a descriptor
ring holds a pointer to a data memory buffer and an entry
for the length of the data buffer. Data buffers can be
chained or cascaded to handle a long packet in multiple
data buffer areas. The C-LANCE searches the descrip­tor rings in a “lookahead” manner to determine the next
empty buffer in order to chain buffers together or to han­dle back-to-back packets. As each buffer is filled,

M
M
M
M

Data

Packet

M

17881B-8

the“own” bit is reset, allowing the host processor to
process the data in the buffer.

C-LANCE Interface

CSR bits such as ACON, BCON and BSWP are used for
programming the pin functions used for different inter­facing schemes. For example, ACON is used to pro­gram the polarity of the Address Strobe signal
(ALE/AS).

BCON is used for programming the pins, for handling
either the BYTE/WORD method for addressing word or­ganized, byte addressable memories where the BYTE
signal is decoded along with the least significant ad­dress bit to determine upper or lower byte, or an explicit
scheme in which two signals labeled as BYTE MASK
(BM0 and BM1) indicate which byte is addressed. When

12

Am79C90

P R E L I M I N A R Y

the BYTE scheme is chosen, the BM1 pin can be used
for performing the function BUSAKO.

BCON is also used to program pins for different DMA
modes. In a daisy chain DMA scheme, 3 signals are
used (BUSRQ, HLDA, BUSAKO). In systems using a
DMA controller for arbitration, only HOLD and HLDA are
used.

C-LANCE in Bus Slave Mode

The C-LANCE enters the Bus Slave Mode whenever CS
becomes active. This mode must be entered whenever
writing or reading the four status control registers
(CSR0, CSR1, CSR2, and CSR3) and the Register Ad­dress Pointer (RAP). RAP and CSR0 may be read or
written to at anytime, but the C-LANCE must be stopped
(by setting the stop bit in CSR0) for CSR1, CSR2, and
CSR3 access.

Read Sequence (Slave Mode)

At the beginning of a read cycle, CS, READ, and DAS
are asserted. ADR must be valid at this time. (If ADR is a
“1,” the contents of RAP are placed on the DAL lines.
Otherwise the contents of the CSR register addressed
by RAP are placed on the DAL lines.) After the data on
the DAL lines become valid, the C-LANCE asserts
READY, CS, READ, DAS, and ADR must remain stable
throughout the cycle. Refer to Figure 3.

AMD

Write Sequence (Slave Mode)

This cycle is similar to the read cycle, except that during
this cycle, READ is not asserted (READ is LOW). The
DAL buffers are tristated which configures these lines as
inputs. The assertion of READY by C-LANCE indicates
to the memory device that the data on the DAL lines
have been stored by C-LANCE in its appropriate CSR
register. CS, READ, DAS, ADR and DAL 15:00 must re­main stable throughout the write cycle. Refer to
Figure4.

Note: Setting the STOP bit in the C-LANCE will gener­ate a C-LANCE reset, which will cause all bus control
output signals (including

READY

) to float. To guarantee
slave write timing when the STOP bit is being set in
CSR0, the C-LANCE will latch the STOP bit and will wait
for the slave cycle to complete before resetting itself and
floating the output signals.

C-LANCE in Bus Master Mode

All data transfers from the C-LANCE in the bus Master
mode are timed by ALE, DAS, and READY. The auto­matic adjustment of the C-LANCE cycle by the READY
signal allows synchronization with variable cycle time
memory due either to memory refresh or to dual port ac­cess. Transfers are a minimum of 600 ns in length ex­cept for the first transfer of a bus mastership period in
which the minimum is 700 ns. Transfers can be in­creased in 100ns increments.

13Am79C90

AMD

DAL0–DAL15

DAS

READ

READY

(Output from

C-LANCE)

HOLD

P R E L I M I N A R Y

Read Data

See
Note 1

O.D.

CS

ADR

Note:

1. There are two types of delays which depend on which internal register is accessed.
Type 1 refers to access of CSR0, CSR3 and RAP.
Type 2 refers to access of CSR1 and CSR2 which are longer than Type 1 delay.

Figure 3. Bus Slave Read Timing

17881B-9

14

Am79C90

DAL0–DAL15

DAS

READ

READY

(Output from

C-LANCE)

HOLD

CS

P R E L I M I N A R Y

AMD

Write Data

O.D.

ADR

Figure 4. Bus Slave Write Timing

Read Sequence (Master Mode)

A read cycle is begun by placing a valid address on
DAL00 – DAL15 and A16 – A23. The BYTE MASK sig­nals are asserted to indicate a word, upper byte or lower
byte memory reference. READ indicates the type of cy­cle. ALE or AS is pulsed, and the trailing edge of either
can be used to latch addresses. DAL00 – DAL15 go into
a 3-state mode, and DAS falls LOW to signal the begin­ning of the memory access. The memory responds by
placing READY LOW to indicate that the DAL lines have
valid data. The C-LANCE then latches memory data on
the rising edge of DAS, which in turn ends the memory
cycle and READY returns HIGH. Refer to Figure 5-1.

17881B-10

The bus transceiver controls, DALI and DALO, are used
to control the bus transceivers. DALI directs data toward
the C-LANCE, and DALO directs data or addresses
away from the C-LANCE. During a read cycle, DALO
goes inactive before DALI becomes active to avoid
“spiking” of the bus transceivers.

Write Sequence (Master Mode)

The write cycle is similar to the read cycle except that the
DAL00 – DAL15 lines change from containing ad­dresses to data after either ALE or AS goes inactive.
After data is valid on the bus, DAS goes active. Data to
memory is held valid after DAS goes inactive. Refer to
Figure 5-2.

15Am79C90

AMD

TCLK

HOLD

HLDA

A16–A23

BM0, BM1

ALE

P R E L I M I N A R Y

T

WAIT

T0

0

T1 T2 T3 T4 T5 T6

100 200 300 400 500

Address, BM0, BM1

600

700

O.D.

DAS

READY

DAL0–DAL15

(Read)

DALO

(Read)

DALI

(Read)

READ

(Read)

Address

Data In

Figure 5-1. Bus Master Read Timing (Single DMA Cycle)

17881B-11

16

Am79C90

TCLK

HOLD

HLDA

A16–A23

BM0, BM1

ALE

P R E L I M I N A R Y

T

WAIT

T0

0 100 200 300 400 500 600

T1 T2 T3 T4 T5 T6

Address, BM0, BM1

AMD

700

O.D.

DAS

READY

DAL0–DAL15

(Write)

DALO

(Write)

DALI

(Write)

READ

(Write)

Address

Data Out

Figure 5-2. Bus Master Write Timing (Single DMA Cycle)

17881B-12

17Am79C90

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P R E L I M I N A R Y

Differences Between Ethernet Versions 1
and 2

a.Version 2 specifies that the collision detect of the

transceiver must be activated during the inter­packet gap time.

b.Version 2 specifies some network management

functions, such as reporting the occurrence of colli­sions, retries and deferrals.

c.Version 2 specifies that when transmission is ter-

minated, the differential transmit lines are driven to
0 volt differentially (half step).

Differences Between IEEE 802.3 and
Ethernet

a.IEEE 802.3 specifies a 2-byte length field rather

than a type field. The length field (802.3) describes
the actual amount of data in the frame.

b.IEEE 802.3 allows the use of a PAD field in the

data section of a frame, while Ethernet specifies
the minimum packet size at 64 bytes. The use of a
PAD allows the user to send and receive packets
which have less than 46 bytes of data.

A list of significant differences between Ethernet and
IEEE 802.3 at the physical layer include the following:

IEEE 802.3 Ethernet

End of Transmission Half Step Full Step (Rev 1)
State or

Half Step (Rev 2)
Common Mode Voltage ±5.5 V 0 – +5 V
Common Mode CurrentLess than 1 mA 1.6 mA ±40%
Receive±, Collision±
Input Threshold ±160 mV ±175 mV
Fault Protection 16 V 0 V

18

Am79C90

P R E L I M I N A R Y

PROGRAMMING

This section defines the Control and Status Registers
and the memory data structures required to program the
Am79C90 (C-LANCE).

Programming the Am79C90 (C-LANCE)

The Am79C90 (C-LANCE) is designed to operate in an
environment that includes close coupling with local
memory and microprocessor (HOST). The Am79C90
C-LANCE is programmed by a combination of registers
and data structures resident within the C-LANCE and
memory registers. There are four Control and Status
Registers (CSRs) within the C-LANCE which are pro­grammed by the HOST device. Once enabled, the
C-LANCE has the ability to access memory locations to
acquire additional operating parameters.

The Am79C90 has the ability to do independent buffer
management as well as transfer data packets to and
from the Ethernet. There are three memory structures
accessed by the Chip:

Initialization Block—12 words in contiguous mem­ory starting on a word boundary. It also contains
the operating parameters necessary for device op­eration. The initialization block is comprised of:

—Mode of Operation
—Physical Address
—Logical Address Mask
—Location to Receive and Transmit Descriptor

Rings

—Number of Entries in Receive and Transmit

Descriptor Rings

Receive and Transmit Descriptor Rings—Two ring
structures, one for incoming and outgoing packets.
Each entry in the rings is 4 words long and each
entry must start on a quadword boundary. The De­scriptor Rings are comprised of:

—The address of a data buffer
—The length of that data buffer
—Status information associated with the buffer
Data Buffers—Contiguous portions of memory

reserved for packet buffering. Data buffers may
begin on arbitrary byte boundaries.

In general, the programming sequence of the C-LANCE
may be summarized as:

Program the C-LANCE’s CSRs by a host device to
locate an initialization block in memory. The byte
control, byte address, and address latch enable
modes are also defined here.

AMD

The C-LANCE loads itself with the information con­tained within the initialization block.

The C-LANCE accesses the descriptor rings for
packet handling.

CONTROL AND STATUS REGISTERS

There are four Control and Status Registers (CSRs) on
the chip. The CSRs are accessed through two bus ad­dressable ports, an address port (RAP) and a data port
(RDP).

Accessing the Control and Status
Registers

The CSRs are read (or written) in a two step operation.
The address of the CSR to be accessed is written into
the RAP during a bus slave transaction. During a subse­quent bus slave transaction, the data being read from
(or written into) the RDP is read from (or written into) the
CSR selected in the RAP.

Once written, the address in RAP remains unchanged
until rewritten.

To distinguish the data port from the address port, a dis­crete input pin is provided.

ADR Input Pin Port

L Register Data Port (RDP)

H Register Address Port (RAP)

Register Data Port (RDP)

CSR DATA

17881B-13

Bit Name Description

15:00 CSR Data Writing data into RDP writes the data

into the CSR selected in RAP. Read­ing the data from the RDP reads the
data from the CSR selected in RAP.
CSR

1, CSR2 and CSR3 are acces-

sible only when the STOP bit of
CSR

0 is set.

If the STOP bit is not set while at­tempting to access CSR
CSR

3, the C-LANCE will return

READY, but a READ operation will
return undefined data. WRITE op­eration is ignored.

1, CSR2 or

015

19Am79C90