AMD Am79C874 Service Manual

DATA SHEET

Am79C874

NetPHY™-1LP Low Power 10/100-TX/FX Ethernet Transceiver

DISTINCTIVE CHARACTERISTICS

■ 10/100BASE-TX Ethernet PHY device with 100BASE-FX fiber optic support

■ Typical power consumption of 0.3 W

■ Sends/receives data reliably over cable lengths

greater than 130 meters

■ MII mode supports 100BASE-X and 10BASE-T

■ 7-Wire (General Purpose Serial Interface (GPSI))

mode supports 10BASE-T

■ Three PowerWise™ management modes (from 300 mW typical)

— Power down: only management responds

Typical power = 3 mW

— Unplugged: no cable, no receive clock

Typical power = 100 mW

— Idle wire: no wire signal, no receiver power

Typical power = 285 mW; MAC saves over 100 mW

GENERAL DESCRIPTION

The Am79C874 NetPHY-1LP device provides the physical (PHY) layer and transceiver functions for one 10/100 Mbps Ethernet port. It delivers the dual benefits of CMOS low power consumption and small package size. Operating at 3.3 V, it consumes only 0.3 W. Three power management modes provide options for even lower power consumption levels. The small 12x12 mm 80-pin PQL package conserves valuable board space on adapter cards, switch uplinks, and embedded Ethernet applications.

The NetPHY-1LP 10/100 Mbps Ethernet PHY device is IEEE 802.3 compliant. It can receive and transmit data reliably at over 130 meters. It includes on-chip input filtering and output waveshaping for unshielded twisted pair operation without requiring external filters or chokes. The NetPHY-1LP device can use 1:1 isolation transformers or 1.25:1 isolation transformers. 1.25:1 isolation transformers provide 20% lower transmit power consumption. A PECL interface is available for 100BASE-FX applications.

Interface to the Media Access Controller (MAC) layer is established via the standard Media Independent Interface (MII), a 5-bit symbol interface, or a 7-wire (GPSI)

■ Supports 1:1 or 1.25:1 transmit transformer

— Using a 1.25:1 ratio saves 20% transmit

power consumption

— No external filters or chokes required

■ Waveshaping – no external filter required

■ Full and half-duplex operation with full-featured

Auto-Negotiation function

■ LED indicators: Link, TX activity, RX activity, Collision, 10 Mbps, 100 Mbps, Full or Half Duplex

■ MDIO/MDC operates up to 25 MHz

■ Automatic Polarity Detection

■ Built-in loopback and test modes

■ Single 3.3-V power supply with 5-V I/O tolerance

■ 12 mm x 12 mm 80-pin TQFP package

■ Support for industrial temperature

(-40°C to +85°C)

interface. Auto-Negotiation determines the network speed and full or half-duplex operation. Automatic polarity correction is performed during Auto-Negotiation and during 10BASE-T signal reception.

Multiple LED pins are provided for front panel status feedback. One option is to use two bi-color LEDs to show when the device is in 100BASE-TX or 10BASE-T mode (by illuminating), Half or Full Duplex (by the color), and when data is being received (by blinking). Individual LEDs can indicate link detection, collision detection, and data being transmitted.

The NetPHY-1LP device needs only one external 25MHz oscillator or crystal because it uses a dual-speed clock synthesizer to generate all other required clock domains. The receiver has an adaptive equalizer/DC restoration circuit for accurate clock/data recovery from the 100BASE-TX signal.

The NetPHY-1LP device is available in the commercial (0°C to +70°C) or industrial (-40°C to +85°C) temperature ranges. The industrial temperature range is well suited to environments, such as enclosures with restricted air flow or outdoor equipment.

Always check www.amd.com for the latest information.

Publication# 22235 Rev: K Issue Date: May 2005

BLOCK DIAGRAM

DATA SHEET

MAC

MII Data Interface

MDC/MDIO

Interface

MII Serial Management Interface and Registers

PHYAD[4:0]

PCS

Framer

Carrier Detect

4B/5B

Clock Recovery

Link Monitor

Signal Detect

10BASE-T

100BASE-X

Control/Status

PLL Clk Generator

Test LED Control

XTL+

XTL- CLK

PMA

25 MHz

20 MHz

TEST LED

Drivers

TP_PMD

MLT-3

BLW

Stream Cipher

10TX

10RX

25 MHz

100TX

100RX

RX FLP

Auto-

Negotiation

Mux

TX+

TX-

RX+

RX-

Transformer

22236G-1

2 Am79C874 22235K

CONNECTION DIAGRAM

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PCSBP

ISODEF

ISO

TGND1

REFCLK

CLK25

BURN_IN

RST PWRDN PLLVCC

PLLGND

OGND1

OVDD1

PHYAD[4]/10RXD-

PHYAD[3]/10RXD+

PHYAD[2]/10TXD++

PHYAD[1]/10TXD+

PHYAD[0]/10TXD-

GPIO[0]/10TXD--/7Wire

GPIO[1]/TP125

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

TVCC2

TVCC1

DATA SHEET

TX-

TX+

TGND2

XTL+

XTL-

REFVCC

IBREF

REFGND

FXT-

FXT+

Am79C874

NetPHY-1LP

TEST2

TEST1/FXR+

TEST0/FXR-

EQGND

RX+

RX-

TEST3/SDI+

RPTR

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

EQVCC ADPVCC LEDDPX/LEDTXB LEDSPD[1]/LEDTXA/CLK25EN ANEGA TECH_SEL[0] TECH_SEL[1] TECH_SEL[2] CRVVCC CRVGND OGND2 OVDD2 LEDLNK/LED_10LNK/LED_PCSBP_SD LEDTX/LEDBTB LEDRX/LEDSEL LEDCOL/SCRAM_EN LEDSPD[0]/LEDBTA/FX_SEL INTR CRS/10CRS COL/10COL

MDC

MDIO

RXD[3]

RXD[2]

VDD1

RXD[1]

DGND1

RXD[0]/10RXD

RX_DV

TX_ER/TXD[4]

RX_ER/RXD[4]

RX_CLK/10RXCLK

TX_CLK/10TXCLK/PCSBP_CLK

VDD2

TXD[1]

DGND2

TXD[0]/10TXD

TX_EN/10TXEN

TXD[2]

TXD[3]

22236G-2

22235K Am79C874 3

DATA SHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

AM79C874

C/I/D/F

ALTERNATE PACKAGING OPTION

Not Applicable

TEMPERATURE RANGE

C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) D = Lead-free commercial (0°C to +70°C) F = Lead-free industrial (-40°C to +85°C)

PACKAGE TYPE

V = 80-Pin Thin Plastic Quad Flat Pack (PQT 80)

SPEED OPTION

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C874 NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver

Valid Combinations

AM79C874 VC

AM79C874 VI

AM79C874 VD

AM79C874 VF

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

4 Am79C874 22235K

DATA SHEET

RELATED AMD PRODUCTS

Table 1. Related AMD Products

Part No. Description

Integrated Controllers

Am79C973B/ Am79C975B

Am79C976 PCnet-PRO™ 10/100 Mbps PCI Ethernet PCI Controller

Am79C978A PCnet-Home™ Single-Chip 1/10 Mbps PCI Home Networking Controller

Physical Layer Devices (Single-Port)

Am79C901A HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY

Physical Layer Devices (Multi-Port)

Am79C875 NetPHY™-4LP Low Power Quad10/100-TX/FX Ethernet Transceiver

PCnet-FAS T™ III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY

22235K Am79C874 5

DATA SHEET

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

LIST OF FIGURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Media Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

MII/7-Wire (GPSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

LED Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

7-Wire (GPSI) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5B Symbol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

100BASE-X Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4B/5B Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Link Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

MLT-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Adaptive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Baseline Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Clock/Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

PLL Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Clock and Crystal Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

10BASE-T Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Twisted Pair Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Twisted Pair Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Reverse Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Auto-Negotiation and Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Far-End Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

SQE (Heartbeat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

LED Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Power Savings Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Selectable Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Unplugged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Idle Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PHY CONTROL AND MANAGEMENT BLOCK (PCM BLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

. . . . .29

6 Am79C874 22235K

DATA SHEET

Description of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Bad Management Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Reserved Registers (Registers 8-15, 20, 22, 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Commercial (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Industrial (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

System Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

MLT-3 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

MII Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

GPSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

PQT80 (measured in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

ERRATA FOR REVISION [B.7] SILICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Revision [B.7] Errata Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Errata for NetPHY-1LP [B.7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

B7 Errata 1- Advanced LED Mode Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

B7 Errata 2 - Auto-Negotiation ACK Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

B7 Errata 3 - Missing or Distorted /T/R/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

REVISION SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

22235K Am79C874 7

LIST OF FIGURES

Figure 1. FXT± and FXR± Termination for 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 2. MLT-3 Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 3. TX± and RX± Termination for 100BASE-TX and 10BASE-T . . . . . . . . . . . . . . . . . . .22

Figure 4. 10BASE-T Transmit /Receive Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 5. Standard LED Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 6. Advanced LED Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 7. PHY Management Read and Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 8. MLT-3 Receive Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 9. MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio . . . . . . . . . . . . . . . . . .45

Figure 10. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio . . . . . . . . . . . . . . .45

Figure 11. Near-End 100BASE-TX Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 12. 10BASE-T Waveform With 1:1 Transformer Ratio . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 13. PECL Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 14. Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 15. MLT-3 Test Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 16. Management Bus Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 17. Management Bus Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 18. 100 Mbps MII Transmit Start of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 19. 100 Mbps Transmit End of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 20. 100 Mbps MII Receive Start of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 21. 100 Mbps MII Receive End of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 22. 10 Mbps MII Transmit Start of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 23. 10 Mbps MII Transmit End of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 24. 10 Mbps MII Receive Start of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 25. 10 Mbps MII Receive End of Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 26. GPSI Receive Timing - Start of Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 27. GPSI Receive Timing - End of Reception (Last Bit = 0) . . . . . . . . . . . . . . . . . . . . . .55

Figure 28. GPSI Receive Timing - End of Reception (Last Bit = 1) . . . . . . . . . . . . . . . . . . . . . .56

Figure 29. GPSI Collision Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 30. GPSI Transmit Timing - Start of Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 31. GPSI Transmit 10TXCLK and 10TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 32. Test Load for 10RXD, 10CRS, 10RXCLK, 10TXCLK and 10COL . . . . . . . . . . . . . .57

DATA SHEET

8 Am79C874 22235K

DATA SHEET

LIST OF TABLES

Table 1. Related AMD Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 2. Pin Designations Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 3. Pin Description Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 4. MII Pins that Relate to 10 Mbps 7-Wire (GPSI) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 5. Code-Group Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 6. Speed and Duplex Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 7. Standard LED Mode and Advanced LED Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 8. Duplex LED Status Configuration in Advanced LED Mode1 . . . . . . . . . . . . . . . . . . . . . . .27

Table 9. Activity LED Configuration in Advanced LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 10. Clause 22 Management Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 11. PHY Address Setting Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 12. Supported Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 13. Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 14. MII Management Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 15. MII Management Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 16. PHY Identifier 1 Register (Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 17. PHY Identifier 2 Register (Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 18. Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 19. Auto-Negotiation Link Partner Ability Register in Base Page Format (Register 5) . . . . . .35

Table 20. Auto-Negotiation LInk Partner Ability Register in Next Page Format (Register 5) . . . . . .35

Table 21. Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 22. Auto-Negotiation Next Page Advertisement Register (Register 7) . . . . . . . . . . . . . . . . . .36

Table 23. Miscellaneous Features Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 24. Interrupt Control/Status Register (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 25. Diagnostic Register (Register 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 26. Power/Loopback Register (Register 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 27. Mode Control Register (Register 21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 28. Disconnect Counter (Register 23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 29. Receive Error Counter Register (Register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 30. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 31. System Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 32. MLT-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 33. MII Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 34. 100 Mbps MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 35. 100 Mbps MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 36. 10 Mbps MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 37. 10 Mbps MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 38. 10 Mbps GPSI Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 39. 10 Mbps GPSI Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 40. 10 Mbps GPSI Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 41. 10 Mbps GPSI Collision Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 42. 10 Mbps GPSI Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 43. GPSI Transmit 10TXCLK and 10TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 44. Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

22235K Am79C874 9

DATA SHEET

PIN DESIGNATIONS

Table 2. Pin Designations Listed by Pin Number

Pin No. Pin Name

1 PCSBP 21 MDIO 41 COL/10COL 61 RPTR

2 ISODEF 22 MDC 42 CRS/10CRS 62 TEST3/SDI+

3 ISO 23 RXD[3] 43 INTR 63 RX-

4 TGND1 24 RXD[2] 44

5REFCLK 25RXD[1] 45

6 CLK25 26 RXD[0]/10RXD 46 LEDRX

7 BURN_IN 27 VDD1 47 LEDTX

8RST

9 PWRDN 29 RX_DV 49 OVDD2 69 FXT+

10 PLLVCC 30 RX_CLK/10RXCLK 50 OGND2 70 FXT-

11 PLLGND 31 RX_ER/RXD[4] 51 CRVGND 71 REFGND

12 OGND1 32 TX_ER/TXD[4] 52 CRVVCC 72 IBREF

13 OVDD1 33

14 PHYAD[4]/10RXD- 34 TX_EN/10TXEN 54 TECH_SEL[1] 74 XTL-

15 PHYAD[3]/10RXD+ 35 DGND2 55 TECH_SEL[0] 75 XTL+

16 PHYAD[2]/10TXD++ 36 VDD2 56 ANEGA 76 TGND2

17 PHYAD[1]/10TXD+ 37 TXD[0]/10TXD 57

18 PHYAD[0]/10TXD- 38 TXD[1] 58 LEDDPX/LEDTXB 78 TX-

G P I O [ 0 ] / 1 0 T X D - - /

7Wire

20 GPIO[1]/TP125 40 TXD[3] 60 EQVCC 80 TVCC2

No. Pin Name

28 DGND1 48

TX_CLK/10TXCLK/ PCSBP_CLK

39 TXD[2] 59 ADPVCC 79 TVCC1

Pin No. Pin Name Pin No. Pin Name

LEDSPD[0] LEDBTA/FX_SEL

LEDCOL/ SCRAM_EN

LEDLNK LED_10LNK/ LED_PCSBP_SD

53 TECH_SEL[2] 73 REFVCC

LEDSPD[1] LEDTXA/CLK25EN

/LEDSEL 66 TEST0/FXR-

/LEDBTB 67 TEST1/FXR+

64 RX+

65 EQGND

68 TEST2

77 TX+

10 Am79C874 22235K

DATA SHEET

PIN DESCRIPTIONS

The following table describes terms used in the pin descriptions.

Table 3. Pin Description Terminology

Term Description

Input Digital input to the PHY

Analog Input Analog input to the PHY

Output Digital output from the PHY

Analog Output Analog output from the PHY

High Impedance Tri-state capable output from the PHY

Pull-Up

Pull-Down

PHY has internal pull-up resistor. NC=HIGH

PHY has internal pull-down resistor. NC=LOW

Media Connections

TX± Transmitter Outputs Analog Output

The TX± pins are the differential transmit output pair. The TX± pins transmit 10BASE-T or MLT-3 signals depending on the state of the link of the port. If the TX± pins are not used, they can be left unconnected.

RX± Receiver Input Analog Input

The RX± pins are the differential receive input pair. The RX± pins can receive 10BASE-T or MLT-3 signals depending on the state of the link of the port. If the RX± pins are not used, they can be connected to each other with standard resistor termination.

FXT± FX Transmit Analog Output

These pins are not connected in 10/100BASE-TX mode.

When FX_SEL come the PECL level transmit output for 100BASE-FX.

TEST0/FXRTest Output/FX Receive -Analog Output/Input

When BURN_IN (Pin 7) is pulled high, this pin serves as a test mode output monitor pin.

When FX_SEL a PECL level negative receive input for 100BASE-FX.

This pin can be left unconnected when the device is operating in 100BASE-TX or 10BASE-T mode.

TEST1/FXR+ Test Output/FX Receive +Analog Output/Input

When BURN_IN (Pin 7) is pulled high, this pin serves as a test mode output monitor pin.

(Pin 44) is pulled low, these pins be-

(Pin 44) is pulled low, this pin becomes

When FX_SEL

(Pin 44) is pulled low, this pin becomes

a PECL level positive receive input for 100BASE-FX.

This pin can be left unconnected when the device is operating in 100BASE-TX or 10BASE-T mode.

TEST3/SDI+ FX Transceiver Signal Detect Analog Output/Input

When BURN_IN (Pin 7) is pulled high, this pin serves as a test mode output monitor pin.

This pin is not connected in 10/100BASE-TX mode.

When FX_SEL

(Pin 44) is pulled low, this pin becomes the Signal Detect input from the Fiber-Optic transceiver. When the signal quality is good, the SDI+ pin should be driven high.

MII/7-Wire (GPSI) Signals

RXD[3:0] MII Receive Data Output, High Impedance

The data is synchronous with RX_CLK when RX_DV is active. When the 7-wire 10BASE-T interface operation is enabled (GPIO[0]= HIGH), RXD[0] will serve as the 10 MHz serial data output.

RX_DV Receive Data Valid Output, High Impedance

RX_DV is asserted when the NetPHY-1LP device is presenting recovered nibbles on RXD[3:0]. This includes the preamble through the last nibble of the data stream on RXD[3:0]. In 100BASE-X mode, the /J/K/ is considered part of the preamble; thus RX_DV is asserted when /J/K/ is detected. In 10BASE-T mode, RX_DV is asserted (and data is presented on RXD[3:0]) when the device detects valid preamble bits. RX_DV is synchronized to RX_CLK.

RX_CLK/10RXCLK Receive Clock Output, High Impedance

A continuous clock (which is active while LINK is established) provides the timing reference for RX_DV, RX_ER, and RXD[3:0] signals. It is 25 MHz in 100BASE-TX/FX and 2.5 MHz in 10BASE-T. To further reduce power consumption of the overall system, the device provides an optional mode enabled through MII Register 16, bit 0 in which RX_CLK is held inactive (low) when no data is received. If RX_CLK is needed when LINK is not established, the NetPHY-1LP must be placed into digital loopback or force the link via register 21, bits 13 or 14.

When 7-wire 10BASE-T mode is enabled, this pin will provide a 10 MHz clock. RX_CLK is high impedance when the ISO pin is enabled

RX_ER/RXD[4] Receive Error Output, High Impedance

When RX_ER is active high, it indicates an error has been detected during frame reception.

22235K Am79C874 11

DATA SHEET

This pin becomes the highest-order bit of the receive 5bit code group in PCS bypass (PCSBP=HIGH) mode. This output is ignored in 10BASE-T operation.

TX_ER/TXD[4] Transmit Error Input

When TX_ER is asserted, it will cause the 4B/5B encoding process to substitute the transmit error codegroup /H/ for the encoded data word.

This pin becomes the higher-order bit of the transmit 5bit code group in PCS bypass (PCSBP=HIGH) mode. This input is ignored in the 10BASE-T operation.

TX_CLK/10TXCLK/PCSBPCLK Transmit Clock Output, High Impedance

A free-running clock which provides timing reference for TX_EN, TX_ER, and TXD[3:0] signals. It is 25 MHz in 100BASE-TX/FX and 2.5 MHz in 10BASE-T.

When 7-wire GPSI mode is enabled, this pin will provide a 10 MHz transmit clock for 10BASE-T operation. When the cable is unplugged, the 10TXCLK ceases operation.

When working in PCSBP mode, this pin will provide a 25 MHz clock for 100BASE-TX operation, and 20 MHZ clock for 10BASE-T operation. TX_CLK is high impedance when the ISO pin is enabled.

TX_EN/10TXEN Transmit Enable Input

The TX_EN pin is asserted by the MAC to indicate that data is present on TXD[3:0].

When 7-wire 10BASE-T mode is enabled, this pin is the transmit enable signal.

TXD[3:1] Transmit Data Input

The MAC will source TXD[3:1] to the PHY. The data will be synchronous with TX_CLK when TX_EN is asserted. The PHY will clock in the data based on the rising edge of TX_CLK.

TXD[0]/10TXD Transmit Data[0]/10 Mbps Transmit Data Input

The MAC will source TXD[0] to the PHY. The data will be synchronous with TX_CLK when TX_EN is asserted. The PHY will clock in the data based on the rising edge TX_CLK.

When 7-wire 10BASE-T mode is enabled, this pin will transmit serial data.

COL/10COL Collision Output, High Impedance

COL is asserted high when a collision is detected on the media. COL is also used for the SQE test function in 10BASE-T mode.

10COL is asserted high when a collision is detected during 7-wire interface mode.

CRS/10CRS Carrier Sense Output, High Impedance

CRS is asserted high when twisted pair media is nonidle. This signal is used for both 10BASE-T and 100BASE-X. In full duplex mode, CRS responds only to RX activity. In half duplex mode, CRS responds to both RX and TX activity.

10CRS is used as the carrier sense output for the 7-wire interface mode.

Miscellaneous Functions

PCSBP PCS Bypass Input, Pull-Down

The 100BASE-TX PCS as well as scrambler/descrambler will be bypassed when PCSBP is pulled high via a 1-4.7 kΩ resistor. TX_ER will become TXD[4] and RX_ER will become RXD[4].

In 10 Mbps PCS bypass mode, the MII signals are not valid. The signals that interface to the MAC (i.e., DECPC 21143) are located on pins 14 to 19. The signals are defined as follows:

— 10RXD± are the differential receive outputs to

the MAC.

— 10TXD± are the differential transmit inputs from

the MAC.

— 10TXD++/10TXD-- are the differential pre-

emphasis transmit outputs from the MAC.

When left unconnected, the device operates in MII or GPSI mode.

ISODEF Isolate Default Input, Pull-Down

This pin is used when multiple PHYs are connected to a single MAC. When it is pulled high via a 1-4.7 kΩ resistor, the MII interface will be high impedance. The status of this pin will be latched into MII Register 0, bit 10 after reset.

When this pin is left unconnected, the default condition of the MII output pins are not in the high impedance state.

ISO Isolate Input, Pull-Down

The MII output pins will become high impedance when ISO is pulled high via a 1-4.7 kΩ resistor. However, the MII input pins will still respond to data. This allows multiple PHYs to be attached to the same MII interface. The same isolate condition can also be achieved by asserting MII Register 0, bit 10. In repeater mode, ISO will not tri-state the CRS pin.

When this pin is left unconnected, the MII output pins are not in the high impedance state.

12 Am79C874 22235K

DATA SHEET

REFCLK Clock Input Input, Pull-Down

This pin connects to a 25-MHz + with a 40% to 60% duty cycle. When a crystal input is used, this pin should be pulled low via a 1 kΩ resistor.

XTL± Crystal Inputs Analog Input

These pins should be connected to a 25-MHz crystal. The crystal should be parallel resonant and have a frequency stability of + of +

50 ppm. REFCLK (Pin 5) should be pulled low

when the crystal is used as a clock source.

These pins may be left unconnected when REFCLK is used as a clock source.

CLK25 25 MHz Clock Output

When the CLK25EN provides a continuous 25 MHz clock to the MAC.

BURN_IN Test Enable Input, Pull-Down

When pulled high via a 1-4.7 kΩ resistor, this pin forces the NetPHY-1LP device into Burn-in mode for reliability assurance control. When left unconnected the device operates normally.

TEST2 Test Output Analog Output

When BURN_IN (pin 7) is pulled high, this pin serves as a test mode output monitor pin. TEST2 can be left unconnected when the device is operating.

RST Reset Input, Pull-Up

A LOW input forces the NetPHY-1LP device to a known reset state. The chip can also be reset through internal power-on-reset or MII Register 0, bit 15.

PWRDN Power Down Input, Pull-Down

If this pin is pulled high via a 1-4.7 kΩ resistor on the rising edge of reset, the device will power down the analog modules and reset the digital circuits. However, the device will still respond to MDC/MDIO data. The same power-down state can also be achieved through the MII Register 0, bit 11. However, the device will respond activity on the PWRDN pin even when bit 11 is not set.

When left unconnected, the device operates normally.

This pin can be pulled down anytime during normal operation to enter Power Down mode.

PHYAD[4:0] PHY Address Input/Output, Pull-Up

These pins allow 32 configurable PHY addresses. The PHYAD will also determine the scramble seed, which

100 ppm and a frequency tolerance

pin is pulled low, the CLK25 pin

50 ppm clock source

helps to reduce EMI when there are multiple ports switching at the same time (repeater/switch applications). Each pin should either be pulled low via a 1 kΩ

− 4.7 kΩ resistor (set bit to zero) or left unconnected (set bit to 1) in order to achieve the desired PHY address. New address changes take effect after a reset has been issued, or at power up.

In PCS bypass mode, PHYAD[4:0] and GPIO[1:0] serves as 10BASE-T serial input and output.

Note: In GPSI mode, the PHYAD pins must be set to addresses other than 00h.

GPIO[0]/10TXD--/7Wire General Purpose I/O 0 Input/Output, Pull-Up

If this pin is pulled low via a 1-4.7 kΩ resistor, on the rising edge of reset, the device will operate in 10BASE-T 7-wire (GPSI) mode. If this pin is left unconnected during the rising edge of reset, the device will operate in standard MII mode.

After the reset operation has completed, this pin can function as an input or an output (dependent on the value of GPIO[0] DIR (MII Register 16, bit 6). If MII Register 16, bit 6 is set HIGH, GPIO[0] is an input. The input value on the GPIO[0] pin will be reflected in MII Register 16, bit 7 – GPIO[0] Data. If MII Register 16, bit 6 is set LOW, GPIO[0] is an output. The value of MII Register 16, bit 7 will be reflected on the GPIO[0] output pin.

GPIO[1]/TP125 General Purpose I/O 1 Input/Output, Pull-Down

If this pin is pulled high via a 1-4.7 kΩ resistor, on the rising edge of reset, the device will be enabled for use with a 1.25:1 transmit ratio transformer. If this pin is left unconnected during the rising edge of reset, the device will be enabled for use with a 1:1 transmit ratio transformer.

After the reset operation has completed, this pin can function as an input or an output (dependent on the value of GPIO[1] DIR – MII Register 16, bit 8). If MII Register 16, bit 8 is set HIGH, GPIO[1] is an input. The input value on the GPIO[1] pin will be reflected in MII Register 16, bit 9 – GPIO[1] Data. If MII Register 16, bit 8 is set LOW, GPIO[1] is an output. The value of MII Register 16, bit 9 will be reflected on the GPIO[1] output pin.

MDIO Management Data Input/Output Pull-Down

This pin is a bidirectional data interface used by the MAC to access management registers within the NetPHY-1LP device. This pin has an internal pull-down, therefore, it requires a 1.5 kΩ pull-up resistor as specified in IEEE 802.3 when interfaced with a MAC. This pin can be left unconnected when management is not used.

22235K Am79C874 13

DATA SHEET

MDC Management Data Clock Input

This clock is sourced by the MAC and is used to synchronize MDIO data. When management is not used, this pin should be tied to ground.

INTR Interrupt Output, High Impedance

This pin is used to signal an interrupt to the MAC. The pin will be forced high or low (normally high impedance) to signal an interrupt depending upon the value of the INTR_LEVL bit, MII Register 16, bit 14. The events which trigger an interrupt can be programmed via the Interrupt Control Register (Register 17).

TECH_SEL[2:0] Technology Select Input, Pull-Up

The Technology Select pins, in conjunction with the ANEGA pin, set the speed and duplex configurations for the device on the rising edge of reset. These capabilities are reflected in MII Register 1 and MII Register

4. Table 6 lists the possible configurations for the device. If the input is listed as LOW, the pin should be pulled to ground via a 1-4.7 kΩ resistor on the rising edge of reset. If the input is listed as HIGH, the pin can be left unconnected.

Note: By using resistors to hard wire the TECH_SEL[2:0] pins and the ANEGA pin, using the MDC/MDIO management interface pins becomes optional. The device’s speed, duplex, and auto-negotiation capabilities are set via hardware. If the management interface is used, the registers cannot be set to a higher capability than the hard-wired setting. The highest capabilities are Full Duplex, 100 Mbps, and Auto-Negotiation enabled.

ANEGA Auto-Negotiation Ability Input, Pull-Up

When this pin is pulled to ground via a 1-4.7 kΩ resistor, on the rising edge of reset, Auto-Negotiation is disabled. When this pin is left unconnected, on the rising edge of reset, Auto-Negotiation is enabled. Note that this pin acts in conjunction with Tech_Sel[2:0] on the rising edge of reset. Refer to Table 3 to determine the desired configuration for the device.

In 100BASE-FX mode, ANEGA should be pulled to ground.

RPTR Repeater Mode Input

This pin should be tied to ground via a 1-4.7 kΩ resistor if repeater mode is to be disabled. When this pin is pulled high via a 1-4.7 kΩ resistor, repeater mode will be enabled. Repeater mode can also enabled via MII Register 16, bit 15. In this mode, the port is set to Half Duplex and SQE is not performed.

LED Port Pins

LEDRX/LED_SEL Receive LED/LED Configuration Select

Input/Output, Pull-Up

When this pin is pulled low via a 1 kΩ resistor, on the rising edge of reset, the advanced LED configuration is enabled. If there is no pull-down resistor present, on the rising edge of reset, the standard LED configuration is enabled.

After the rising edge of reset this pin controls the Receive LED. This pin toggles between high and low when data is received. When the device is operating in the standard LED mode, refer to Figure 5 in the LED Port Configuration section. When the device is operating in the advanced LED mode, refer to Table 9 and Figure 6 in the LED Port Configuration section.

LEDCOL Collision LED/Scrambler Enable

When this pin is pulled low via a 1-kΩ resistor, on the rising edge of reset, the scrambler/descrambler is disabled. If no pull-down resistor is present, on the rising edge of reset, the scrambler/descrambler is enabled.

After the rising edge of reset this pin controls the Collision LED. This pin toggles between high and low when there is a collision in half-duplex operation. In fullduplex operation this pin is inactive. When the device is operating in the standard LED mode, refer to Figure 5 in the LED Port Configuration section. When the device is operating in the advanced LED mode, see Figure 6.

LEDLNK Link LED/7-Wire Link LED/PCSBP Signal Detect

When a link is established in 100BASE-X or 10BASE-T mode, this pin will assume a logic low level.

When a link is established in 7-Wire mode, this pin will assume a logic high level.

When in PCS Bypass mode, this pin assumes a logic high level indicating Signal Detect.

Refer to Figure 4 in the LED Port Configuration section if the device is operating in the standard LED mode. See Figure 5 if the device is operating in the advanced LED mode.

/SCRAM_EN

Input/Output, Pull-Up

/LED_10LNK/LED_PCSBP_SD

Output

14 Am79C874 22235K

DATA SHEET

Note: If 7-Wire mode is chosen the polarity of the LED should be reversed and the cathode of the LED should be tied to ground.

LEDSPD[0] 100 Mbps Speed LED/Advanced LED/Fiber Select

When this pin is pulled low via a 1 kΩ resistor, on the rising edge of reset, the device will be enabled for 100BASE-FX operation. When no pull-down resistor is present, on the rising edge of reset, the device will be enabled for 100BASE-TX or 10BASE-T operation.

When the standard LED configuration is enabled (see LEDRX 100 Mbps speed LED. A logic low level indicates 100 Mbps operation. A logic high level indicates 10 Mbps operation. Refer to Figure 5 in the LED Port Configura- tion section to determine the correct polarity of the LED.

When the advanced LED configuration is enabled, this pin works in conjunction with LEDTX Refer to Table 7 and Figure 6 in the LED Port Configu- ration section to determine the correct polarity of the bidirectional LED.

LEDTX Transmit LED/Advanced LED Output

When the standard LED configuration is enabled (see LEDRX transmit LED. This pin toggles between high and low when data is transmitted. Refer to Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED.

When the advanced LED configuration is enabled, this pin works in conjunction with LEDSPD[0] FX_SEL LED Port Configuration section to determine the correct polarity of the bi-directional LED.

LEDSPD[1] 10 Mbps Speed LED/Advanced LED/25 MHz Clock

Enable Input/Output, Pull-Up

When this pin is pulled low via a 1 kΩ resistor, on the rising edge of reset, the device will output a 25 MHz clock on CLK25 (pin 6). When no pull-down resistor is present, on the rising edge of reset, CLK25 is inactive.

When the standard LED configuration is enabled (see LEDRX 10 Mbps speed LED. A logic low level indicates 10 Mbps operation. A logic high level indicates 100 Mbps operation. Refer to Figure 5 in the LED Port Configura- tion section to determine the correct polarity of the LED.

When the advanced LED configuration is enabled, this pin works in conjunction with LEDDPX

58). Refer to Table 8 and Figure 6 in the LED Port Con-

/LEDBTA/FX_SEL

Input/Output, Pull-Up

/LEDSEL pin description), this pin serves as the

/LEDBTB (pin 47).

/LEDBTB

/LEDSEL pin description), this pin serves as the

/LEDBTA/

(pin 44). Refer to Table 7 and Figure 6 in the

/LEDTXA/CLK25EN

/LEDSEL pin description), this pin serves as the

/LEDTXB (pin

figuration section to determine the correct polarity of the bi-directional LED.

LEDDPX Duplex LED/Advanced LED Output

When the standard LED configuration is enabled (see LEDRX duplex LED. A logic low level indicates full duplex operation. A logic high level indicates half duplex operation. See Figure 5 in the LED Port Configuration section to determine the correct polarity of the LED.

When the advanced LED configuration is enabled, this pin works in conjunction with LEDSPD[1] CLK25EN LED Port Configuration section to determine the correct polarity of the bi-directional LED.

/LEDTXB

/LEDSEL description), this pin serves as the

LEDTXA/

(pin 57). Refer to Table 8 and Figure 6 in the

Bias

IBREF Reference Bias Resistor Analog

This pin must be tied to an external 10.0 kΩ (1%) resistor which should be connected to ground. The 1% resistor provides the bandgap reference voltage.

Note: This signal trace should be short and not close to other signals.

Power and Ground

PLLVCC, OVDD1, OVDD2, VDD1, VDD2, CRVVCC, ADPVCC, EQVCC, REFVCC, TVCC1, TVCC2 Power Pins Power

These pins are 3.3 V power for sections of the NetPHY-1LP device as follows:

PLLVCC is power for the PLL; OVDD1 and OVDD2 are power for the I/O; VDD1 and VDD2 are power for the digital logic; CRVVCC is power for clock recovery; ADPVCC and EQVCC are power for the equalizer; REFVCC is power for the bandgap reference; and TVCC1 and TVCC2 are power for the transmit driver.

PLLGND, OGND1, OGND2, DGND1, DGND2, CRVGND, EQGND, REFGND, TGND1, TGND2 Ground Pins Power

These pins are ground for the power pins as follows:

PLLGND is ground for PLLVCC; OGND is ground for OVDD; DGND is ground for VDD; CRVGND is ground for CRVVCC and ADPVCC; EQGND is ground for EQVCC; REFGND is ground for REFVCC; and TGND is ground for TVCC.

Note: Bypass capacitors of 0.1 μF between the power and ground pins are recommended. The four areas where the capacitors must be very close to the pins (within 3 mm) are the PLL (pins 10 and 11), Clock Recovery (pins 51 and 52), Equalizer (pins 60 and 65), and Bandgap Reference (pins 71 and 73) areas. The other bypass capacitors should be placed as close to the pins as possible.

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DATA SHEET

FUNCTIONAL DESCRIPTION

The NetPHY-1LP device integrates the 100BASE-X PCS, PMA, and PMD functions and the 10BASE-T Manchester ENDEC and transceiver functions in a single chip for Ethernet 10 Mbps and 100 Mbps operations. It performs 4B/5B, MLT3, NRZI, and Manchester encoding and decoding, clock and data recovery, stream cipher scrambling/descrambling, adaptive equalization, line transmission, carrier sense and link integrity monitor, Auto-Negotiation, and MII management functions. It provides an IEEE 802.3u compatible Media Independent Interface (MII) to communicate with an Ethernet Media Access Controller (MAC). Selection of 10 Mbps or 100 Mbps operation is based on settings of internal Serial Management Interface registers or determined by the on-chip Auto-Negotiation logic. The device can be set to operate either in full-duplex mode or half-duplex mode for either 10 Mbps or 100 Mbps.

The NetPHY-1LP device communicates with a repeater, switch, or MAC device through either the Media Independent Interface (MII) or the 10 Mbps 7-wire (GPSI) interface.

The NetPHY-1LP device consists of the following functional blocks:

■ MII Mode

■ 7-Wire (GPSI) Mode

■ PCS Bypass (5B Symbol) Mode

■ 100BASE-X Block including:

— Transmit Process

— Receive Process

— 4B/5B Encoder and Decoder

— Scrambler and Descrambler

— Link Monitor

—MLT-3

— Adaptive Equalizer

— Baseline Wander Compensation

— Clock/Data Recovery

— PLL Clock Synthesizer

■ 10BASE-T Block including:

— Transmit Process

— Receive Process

— Interface Status

— Collision Detect

— Jabber

— Reverse Polarity Detection and Correction

■ Auto-Negotiation and miscellaneous functions including:

— Auto-Negotiation

— Parallel Detection

— Far-End Fault

— SQE (Heartbeat)

— Loopback Operation

— Reset

■ LED Port Configuration

■ Power Savings Mechanisms including:

— Selectable Transformer

— Power Down

— Unplugged

— Idle Wire

■ PHY Control and Management

Modes of Operation

The MII/GPSI/5B Symbol interface provides the data path connection between the NetPHY-1LP transceiver and the Media Access Controller (MAC), repeater, or switch. The MDC and MDIO pins are responsible for communication between the NetPHY-1LP transceiver and the station management entity (STA). The MDC and MDIO pins can be used in any mode of operation.

MII Mode

The purpose of the MII mode is to provide a simple, easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to make the differences between various media transparent to the MAC sublayer.

The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer.

■ TXD (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to TX_CLK. For each TX_CLK period which TX_EN is asserted, TXD[3:0] are accepted for transmission by the PHY.

■ TX_CLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TX_EN, TXD, and TX_ER signals.

■ TX_EN (transmit enable) input from the MAC reconciliation sublayer to indicate nibbles are being presented on the MII for transmission on the physical medium. TX_ER (transmit coding error) transitions synchronously with respect to TX_CLK. If TX_ER is asserted for one or more clock periods, and TX_EN is asserted, the PHY will emit one or more symbols that are not part of the valid data delimiter set somewhere in the frame being transmitted.

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DATA SHEET

■ RXD (receive data) is a nibble (4 bits) of data that is sampled by the reconciliation sublayer synchronously with respect to RX_CLK. For each RX_CLK period which RX_DV is asserted, RXD[3:0] are transferred from the PHY to the MAC reconciliation sublayer.

■ RX_CLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock (during LINK only) that provides the timing reference for the transfer of the RX_DV, RXD, and RX_ER signals.

■ RX_DV (receive data valid) input from the PHY to indicate the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconciliation sublayer, RX_DV must encompass the frame starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter.

■ RX_ER (receive error) transitions synchronously with respect to RX_CLK. RX_ER will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being received by the PHY.

■ CRS (carrier sense) is asserted by the PHY when either the transmit or receive medium is non-idle and deasserted by the PHY when the transmit and receive medium are idle.

7-Wire (GPSI) Mode

7-Wire (GPSI) mode uses the existing MII pins, but data is transferred only on TXD[0] and RXD[0]. This mode is used in a General Purpose Serial Interface (GPSI) configuration for 10BASE-T. If the GPIO[0] pin is LOW at the rising edge of reset, then GPSI mode is selected. For this configuration, TX_CLK runs at 10 MHz. When the cable is unplugged, 10TXCLK ceases operation. Note that 7-wire mode does not define the use of Auto-Negotiation or MDC/MDIO.

The MII pins that relate to 7-wire (GPSI) mode are shown in the following table. The unused input pins in this mode should be tied to ground through a 1 kΩ resistor. The RPTR pin must be connected to GND.

Table 4. MII Pins that Relate to 10 Mbps 7-Wire

(GPSI) mode

MII Pin Name 7-Wire (GPSI)

TX_CLK/10TXCLK Transmit Clock

TXD[0]/10TXD Transmit Serial Data Stream

TXD[3:1] Not used

TX_EN/10TXEN Transmit Enable

TX_ER Not used

RX_CLK/10RXCLK Receive Clock

RXD[0] /10RXD Receive Serial Data Stream

RXD[3:1] Not used

COL/10COL Collision Detect

Table 4. MII Pins that Relate to 10 Mbps 7-Wire

(GPSI) mode (continued)

MII Pin Name 7-Wire (GPSI)

RX_ER Not used

CRS/10CRS Carrier Sense Detect

Note: CRS ends one and one-half bit times after the last data bit. The effect is one or two dribbling bits on every packet. All MACs truncate packets to eliminate the dribbling bits. The only noticeable effect is that all CRC errors are recorded as framing errors.

Use the TECH_SEL[2:0] to select the desired 10BASET operation.

5B Symbol Mode

The purpose of the 5B Symbol mode is to provide a way for the MAC to do the 4B/5B encoding/decoding and scrambling/descrambling in 100 Mbps operation.

In 10 Mbps operation, the MII signals are not used. Instead, the NetPHY-1LP device operates as a 10BASE-T transceiver, providing received data to the MAC over a serial differential pair (see PCSBP pin). The MAC uses two serial differential pairs to provide transmit data to the NetPHY-1LP device, where the two differential pairs are combined in the NetPHY-1LP device to compensate for inter-symbol interference on the twisted pair medium.

100BASE-X Block

The functions performed by the device include encoding of MII 4-bit data (4B/5B), decoding of received code groups (5B/4B), generating carrier sense and collision detect indications, serialization of code groups for transmission, de-serialization of serial data upon reception, mapping of transmit, receive, carrier sense, and collision at the MII interface, and recovery of clock from the incoming data stream. It offers stream cipher scrambling and descrambling capability for 100BASETX applications.

In the transmit data path for 100 Mbps, the NetPHY-1LP transceiver receives 4-bit (nibble) wide data across the MII at 25 million nibbles per second. For 100BASE-TX applications, it encodes and scrambles the data, serializes it, and transmits an MLT-3 data stream to the media via an isolation transformer. For 100BASE-FX applications, it encodes and serializes the data and transmits a Pseudo-ECL (PECL) data stream to the fiber optic transmitter. See Figure 1.

In the receive data path for 100 Mbps, the NetPHY-1LP transceiver receives an MLT-3 data stream from the network. For 100BASE-TX, it then recovers the clock from the data stream, de-serializes the data stream, and descrambles/decodes the data stream (5B/4B) before presenting it at the MII interface.

22235K Am79C874 17

Am79C874

NetPHY-1LP

TEST1/FXR+

TEST0/FXR-

TEST3/SDI+

ANEGA

3.3 V

69 Ω

183 Ω 183 Ω

1 kΩ

69 Ω

82.5 Ω

DATA SHEET

3.3 V

0.1 μF

3.3 V

0.01 μF

130 Ω

82.5 Ω 130 Ω 130 Ω

82.5 Ω

HFBR/HFCT-5903

3.3 V MT-RJ

5 RD+ 4 RD-

3 SD+

FXT-

FXT+

FX_SEL

1 kΩ

130 Ω 130 Ω

Figure 1. FXT± and FXR± Termination for 100BASE-FX

For 100BASE-FX operation, the NetPHY-1LP device receives a PECL data stream from the fiber optic transceiver and decodes that data stream.

The 100BASE-X block consists of the following subblocks:

— Transmit Process — Receive Process — 4B/5B Encoder and Decoder — Scrambler/Descrambler — Link Monitor — Far End Fault Generation and Detection &

Code-Group Generator

— MLT-3 encoder/decoder with Adaptive

Equalization — Baseline Restoration — Clock Recovery

Transmit Process

The transmit process generates code-groups based on the transmit control and data signals on the MII. This process is also responsible for frame encapsulation into a Physical Layer Stream, generating the collision signal based on whether a carrier is received simultaneously during transmission and generating the Carrier Sense CRS and Collision COL signals at the MII. The transmit process is implemented in compliance with the

10 TD9 TD+

22236G-3

transmit state diagram as defined in Clause 24 of the IEEE 802.3u specification.

The NetPHY-1LP device transmit function converts synchronous 4-bit data nibbles from the MII to a 125Mbps differential serial data stream. The entire operation is synchronous to a 25-MHz clock and a 125-MHz clock. Both clocks are generated by an on-chip PLL clock synthesizer that is locked to an external 25-MHz clock source.

In 100BASE-FX mode, the NetPHY-1LP device will bypass the scrambler. The output data is an NRZI PECL signal. This PECL level signal will then drive the Fiber transmitter.

Receive Process

The receive path includes a receiver with adaptive equalization and DC restoration, MLT-3-to-NRZI conversion, data and clock recovery at 125-MHz, NRZI-toNRZ conversion, Serial-to-Parallel conversion, descrambling, and 5B to 4B decoding. The receiver circuit starts with a DC bias for the differential RX± inputs, follows with a low-pass filter to filter out high-frequency noise from the transmission channel media. An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful in the power-saving mode. (See the description in Power

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