AMD Advanced Micro Devices AM79C873KCW Datasheet

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PRELIMINARY

Am79C873

NetPHY™ -1
10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support

DISTINCTIVE CHARACTERISTICS

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100BASE-FX direct interface to industry
standard electrical/optical transceivers

■

10/100BASE-TX physical-layer, single-chip
transceiver

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Compliant with the IEEE 802.3u 100BASE-TX
standard

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Compliant with the ANSI X3T12 TP-PMD 1995
standard

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Compliant with the IEEE 802.3u Auto­Negotiation protocol for automatic link type
selection

■

Supports the MII with serial management
interface

■

Supports Full Duplex operation for 10 Mbps and
100 Mbps

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High performance 100 Mbps clock generator
and data recovery circuitry

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Adaptive equalization circuitry for 100 Mbps
receiver

Controlled output edge rates in 100 Mbps
Supports a 10BASE-T interface without the

need for an external filter
Provides Loopback mode for system

diagnostics
Includes flexible LED configuration capability
Digital clock recovery circuit using advanced

digital algorithm to reduce jitter
Low-power, high-performance CMOS process
Available in a 100-pin PQFP package

GENERAL DESCRIPTION

The NetPHY-1 device is a physical-layer, single-chip,
low-power transceiver for 100BASE-TX, 100BASE-FX,
and 10BASE-T operations. On the media side, it pro­vides a direct interface to Fiber Media for 100BASE-FX
Fast Ethernet, Unshielded Twisted Pair Category 5
Cable (UTP5) for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. Through
the IEEE 802.3u Media Independent Interface (MII),
the NetPHY-1 device connects to the Medium Access
Control (MAC) layer, ensuring a high interoperability
among products from different vendors.

The NetPHY-1 device uses a low-power, high-perfor­mance CMOS process. It contains the entire physical

layer functions of 100BASE-FX and 100BASE-TX as
defined by the IEEE 802.3u standard, including the
Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), 100BASE-TX Twisted Pair Physical
Medium Dependent (TP-PMD) sublayer, and a
10BASE-T Encoder/Decoder (ENDEC). The NetPHY-1
device provides strong support for the Auto-Negotiation
function utilizing automatic media speed and protocol
selection. The NetPHY-1 device incorporates an inter­nal wave-shaping filter to control rise/fall time, eliminat­ing the need for external filtering on the 10/100
Mbps signals.

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 22164 Rev: AAmendment/+2
Issue Date: February 1999

BLOCK DIAGRAM

PRELIMINARY

MII

Signals

MII

Interface/

Control

4B/5B

Encoder

4B/5B

Decoder

Scrambler

Alignment

Register

Code­group

25M OSCI

TX CGM

Parallel

to Serial

Descrambler

Collision
Detection

NRZ

NRZI

25M CLK

Digital

Logic

Carrier

to

Serial to

Parallel

Sense

NRZI to

MLT-3

125M CLK

LED1-4

LED

Driver

NRZI to

NRZ

Auto-

Negotiation

MLT-3

Driver

Rise/Fall

Time

CTL

RX

CRM

10BASE-T

Module

PECL
Driver

MLT-3 to

NRZI

Receiver

RX
TX

PECL

Adaptive

EQ

FXTD±

100TXD±

RXI±

FXRD±
FXSD+

RXI±
10TXD±

22164A-1

2 Am79C873

CONNECTION DIAGRAM

AV

cc
FXSD­FXSD+

FXRD-

FXRD+

AGND

AV
AV

RXI-

RXI+
AGND
AGND

10TXO-

10TXO+

AV

AV
AGND
AGND

FXTD-

FXTD+

AV

AV
AGND
AGND

100TXO-

100TXO+

AV

AV

OSCI/X1

1
2

3
4
5
6
7

cc

8

cc

9
10
11
12
13
14
15

cc

16

cc

17
18

19
20
21

cc

22

cc

23
24
25
26
27

cc

28

cc

29
30

X2

AGND

100

31

AGND

99

32

PRELIMINARY

OPMODE1

OPMODE2

OPMODE3

RPTR/NODE

BPALIGN

BP4B5B

BPSCR

10BTSER

91

92

93

94

95

96

97

98

Am79C873/KC

NetPHY-1

39

38

37

36

35

34

33

OPMODE0

PHYAD3

PHYAD4

88

89

90

43

424041

44

DV

87

cc

DGND

86

45

PHYAD2

PHYAD1

84

85

47

46

TESTMODE

PHYAD0

82

83

49

48

RESET

81

80
79

78
77

76
75
74

73
72

71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

RX_EN
RX_ER/RXD4
RX_DV
COL
CRS
RX_CLK
DV

cc
DGND
RXD0

RXD1
RXD2
RXD3
DV

cc
DGND
MDIO

MDC
TX_CLK
TX_EN
DV

cc
DGND

TXD0
TXD1
TXD2
TXD3
TX_ER/TXD4
TXLED
RXLED
LINKLED
DGND
COLLED

AGND

cc

AV

OSC/XTL

AGND

BGRET

BGREF

DGND

DGND

DGND

cc

DV

UTP

TRIDRV

SPEED10

RX_LOCK

NC

DGND

CLK25M

LINKSTS

cc

DV

FDXLED

Am79C873 3

22164A-2

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in se ver al packages and operating ranges . The order number (V alid Combination) is f ormed
by a combination of the elements below.

Am79C873

Am79C873

KC\W

Valid Combinations

KC\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and formed in a tray

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

P ACKA GE TYPE

K = Plastic Quad Flat Pack (PQR100)

SPEED OPTION

Not Applicable

DEVICE NUMBER/DESCRIPTION

Am79C873
NetPHY-1™ 10/100 Mbps Ethernet Physical Layer
Single-Chip Transceiver with 100BASE-FX Support

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

4 Am79C873

PRELIMINARY

RELATED AMD PRODUCTS

Part No. Description

Controllers

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™)

Integrated Controllers

Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller
Am79C940 Media Access Controller for Ethernet (MACE™)
Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus
Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses
Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus
Am79C971 PCnet-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
Am79C973/

Am79C975
Am79C978 PCnet-Home Single-chip 1/10 Mbps PCI Home networking Controller

Physical Layer Devices (Single-Port)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)
Am79C98 Twisted Pair Ethernet Transceiver (TPEX)
Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Physical Layer Devices (Multi-Port)

Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)
Am79C988A Quad Integrated Ethernet Transceiver (QuIET™)
Am79C989 Quad Ethernet Switching Transceiver (QuEST™)

Integrated Repeater/Hub Devices

Am79C981 Integrated Multiport Repeater Plus (IMR+)
Am79C982 Basic Integrated Multiport Repeater (bIMR)
Am79C983 Integrated Multiport Repeater 2 (IMR2™)
Am79C984A Enhanced Integrated Multiport Repeater (eIMR™)

PCnet-Fast III Single-chip 10/100 Mbps PCI Ethernet Controller With Integrated PHY

Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™)
Am79C987 Hardware Implemented Management Information Base (HIMIB™)

Am79C873 5

PRELIMINARY

CONTENTS

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device Configuration/Control/Status Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PHY Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MII Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

100BASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

100BASE Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4B5B Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NRZ-to-NRZI Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PECL Driver For 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MLT-3 Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MLT-3 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE-TX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

100BASE-FX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PECL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MLT-3-to-NRZI Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

NRZI-to-NRZ Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Serial-to-Parallel Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Code Group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4B5B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10BASE-T Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MII Serial Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Key to Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Basic Mode Control Register (BMCR) - Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Basic Mode Status Register (BMSR) - Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PHY ID Identifier Register 1 (PHYIDR1) - Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PHY Identifier Register 2 (PHYIDR2) - Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Auto-Negotiation Advertisement Register(ANAR) - Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 . . . . . . . . . . . . . . . . . . . . 25

Auto-Negotiation Expansion Register (ANER) - Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AMD Specified Configuration Register (DSCR) - Register 16. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AMD Specified Configuration and Status Register (DSCSR) - Register 17. . . . . . . . . . . . . . . . . 29

10BASE-T Configuration/Status (10BTCSRSCR) - Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Am79C873

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

MII 100BASE-TX Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MII 100BASE-TX Transmit Timing Parameters (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . 34

MII 100BASE-TX Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MII-100BASE-TX Receive Timing Parameter (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . 35

Auto-Negotiation and Fast Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Auto-Negotiation and Fast Link Pulse Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII 10BASE-T Nibble Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII-10BASE-T Nibble Transmit Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MII 10BASE-T Receive Nibble Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MII-10BASE-T Receive Nibble Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T SQE (Heartbeat) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

MDIO Timing when OUTPUT by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MDIO Timing when OUTPUT by NetPHY-1 Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MII Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

MAGNETICS SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CRYSTAL SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

NETPHY-1 MII EXAMPLE SCHEMATIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Am79C873 7

PRELIMINARY

PIN DESCRIPTIONS
MII Interface
TX_ER/TXD4

Transmit Error Input

In 100 Mbps mode, if this signal is asserted high and
TX_EN is active, the HALT symbol is substituted for the
actual data nibble. In 10 Mbps mode, this input
is ignored.

In bypass modes (BP4B5B or BPALIGN), TX_ER be­comes the TXD4 pin, the fifth TXD data bit.

TXD[3:0]

Transmit Data Input

These are the transmit data input pins for nibble
data from the MII in 100 Mbps or 10 Mbps nibble
mode (25 MHz
Mbps nibble mode).

In 10 Mbps serial mode, the TXD0 pin is used as the
serial data input pin. TXD[3:1] are ignored.

for 100 Mbps mode, 2.5 MHz for 10

TX_EN

Transmit Enable Input

Active high input indicates the presence of valid nib­ble data on TXD[3:0] for both 100 Mbps or 10 Mbps
nibble mode.

RXD[3:0]

Receive Data Output/Z

Nibble wide receive data (synchronous to RX_CLK - 25
MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T
nibble mode). Data is dr iven on the falling edge of
RX_CLK.

In 10 Mbps serial mode, the RXD0 pin is used as the
data output pin. RXD[3:1] are ignored.

1

RX_CLK

Receive Clock Output/Z

Provides the recovered receive clock for different
modes of operation:

- 25 MHz nibble clock in 100 Mbps mode

- 2.5 MHz nibble clock in 10 Mbps nibble mode

- 10 MHz receive clock in 10 Mbps serial mode

1

CRS

Carrier Sense Output/Z

This pin is asserted high to indicate the presence of
carrier due to receive or transmit activities in 10BASE­T or 100BASE-TX Half Duplex modes.

In Repeater, when Full Duplex or Loopback mode is a
logic 1, it indicates the presence of carrier due only to
receive activity.

1

In 10 Mbps serial mode, active high indicates the pres­ence of valid 10 Mbps data on TXD0.

TX_CLK

Transmit Clock Output/Z

This pin provides the transmit clock output from the
NetPHY-1 deviceas follows:

- 25 MHz nibble transmit clock derived from trans­mit Phase Locked Loop (TX PLL) in 100BASE-TX
mode

- 2.5 MHz transmit clock in 10BASE-T nibble mode

- 10 MHz transmit clock in 10BASE-T serial mode

1

MDC

Management Data Clock Input

This pin is the synchronous clock to the MDIO manage­ment data input/output serial interface which is asyn­chronous to transmit and receive clocks . The maxim um
clock rate is 2.5 MHz.

MDIO

Management Data I/O Input/Output

This pin is the bidirectional management instruction/
data signal that may be driven by the station manage­ment entity or the PHY. This pin requires a 1.5 K Ω pull­up resistor.

COL

Collision Detect Output/Z

This pin is asserted high to indicate detection of colli­sion conditions in 10 Mbps and 100 Mbps Half Duplex­modes. In 10BASE-T Half Duplex mode with Heartbeat
set active (bit 13, register 18h), it is also asserted for a
duration of approximately 1ms at the end of transmis­sion to indicate heartbeat. In Full Duplex mode, this
signal is always logic 0. There is no heartbeat function
in Full Duplex mode.

1

RX_DV

Receive Data Valid Output/Z

This pin is asserted high to indicate that valid data is
present on RXD[3:0].

1

RX_ER/RXD4

Receive Error Output/Z

This pin is asserted high to indicate that an invalid sym­bol has been detected inside a received packet in 100
Mbps mode.

In a bypass mode (BP4B5B or BPALIGN modes),
RX_ER becomes RXD4, the fifth RXD data bit of the
5B symbols.

1

1. Goes to high impedance.

8 Am79C873

PRELIMINARY

RX_EN

Receive Enable Input

This pin is active high enabled for receive signals
RXD[3:0], RX_CLK, RX_D V and RX_ER. A low on this
input tri-states these output pins. For normal operation
in a NODE application, this pin should be pulled high.

Media Interface
RXI±

100/10 Mbps-TX/T Twisted Pair Differential Input
Pair Input

These pins are the differential receive input for
10BASE-T and 100BASE-TX. They are capable of re­ceiving 100BASE-TX MLT-3 or 10BASE-T Manchester
encoded data.

FXRD±

100BASE-FX PECL Differential Input Pair Input

These pins are the differential receive input for
100BASE-FX. They are capable of receiving
100BASE-FX.

FXSD±

100BASE-FX PECL Signal Detect Input

These input signals from the FX-PMD transceiver indi­cate detection of a receive signal from the Fiber Media.

function will change to indicate the Polarity status for 10
Mbps operation. If polarity is inv erted, the POLLED will
go ON.

COLLED

Collision LED Output

This pin indicates the presence of collision activity for
10 Mbps and 100 Mbps operation. This LED has no
meaning for 10 Mbps or 100 Mbps Full Duplex opera­tion (Active low).

LINKLED

Link LED Output

This pin indicates Good Link status for 10 Mbps and
100 Mbps operation (Active low). It functions as the
TRAFFIC LED when bit 5 of register 16 is set to 1. In
TRAFFIC LED mode, it is always ON when the link is
OK. The TRAFFIC LED flashes when transmitting or
receiving.

RXLED

Receive LED Output Drain

This pin indicates the presence of receive activity for 10
Mbps and 100 Mbps operation (Active low). The Net­PHY-1 device incorporates a “monostable” function on
the RXLED output. This ensures that even minimal re­ceive activity will generate an adequate LED ON time.

(TRAFFIC LED)

10TXO±

10BASE-T Differential Output Pair Output

This output pair provides controlled rise and fall times
designed to filter the transmitters output.

100TXO±

100BASE-TX Twisted Pair Differential Output Pair

Output

This output pair drives MLT-3 encoded data to the
100 M twisted pair cable and provides controlled rise
and fall times designed to filter the transmitters output,
reducing any associated EMI.

FXTD±

100BASE-FX PECL Differential Output PairOutput

These pins are the differential transmit output for
100BASE-FX. They are capable of transmitting
100BASE-FX

LED Interface

These outputs can directly drive LEDs or provide status
information to a network management device.

FDXLED

Polarity/Full Duplex LED Output

This pin indicates Full Duplex mode status for 100
Mbps and 10 Mbps operation (Active low). If bit 4 of
Register 16 (FDXLED_MODE) is set, the FDXLED pin

(POLLED)

TXLED

Transmit LED Output Drain

This pin indicates the presence of transmit activity for 10
Mbps and 100 Mbps operation (Active low). The Net­PHY-1 device incorporates a “monostable” function on
the TXLED output. This ensures that even minimal
transmit activity will generate an adequate LED ON time.

Device Configuration/Control/Status
Interface

UTP

UTP Cable Indication Output

This pin is the UTP Cable Indication. When UTP=1, it
indicates that the UTP cable is being used.

SPEED10

Speed 10 Mbps Output

When set high, this bit indicates a 10 Mbps operation,
when set low 100 Mbps operation. This pin can drive
a low current LED to indicate that 100 Mbps operation
is selected.

RX_LOCK

Lock for Clock/Data Recovery PLL Output

When this pin is high, it indicates that the receiver re­covery PLL logic has locked to the input data stream.

Am79C873 9

PRELIMINARY

LNKSTS

Link Status Register Bit Output

This pin reflects the status of bit 2 register 1.

OPMODE0-OPMODE3

OPMODE0-OPMODE3 Input

These pins are used to control the forced or advertised
operating mode of the NetPHY-1 device (see table be­low). The v alue is latched into the NetPHY-1 device reg­isters at power-up/rese..

OP-

MODE3

0000

0001

0010

0011

0100

OP-

MODE2

OP-

MODE1

OP-

MODE0 Function

Auto-Negotiation
enable with all
capabilities with
Flow Control

Auto-Negotiation
enable without all
capabilities without
Flow Control

Auto-Negotiation
100TX FDX with
Flow Control only

Auto-Negotiation
100TX FDX/HDX
without Flow
Control

Auto-Negotiation
10TP FDX with
Flow Control only

TPR/NODE

R

Repeater/Node Mode Input

When set high, this bit selects REPEA TER mode; when
set low, it selects NODE. In REPEATER mode or
NODE mode with Full Duplex configured, the Carrier
Sense (CRS) output from the NetPHY-1 device will be
asserted only during receive activity . In NODE mode or
a mode not configured for Full Duplex operation, CRS
will be asserted during receive or transmit activity. At
power-up/reset, the value on this pin is latched into
Register 16, bit 11.

BPALIGN

Bypass Alignment Input

This pin allows 100 Mbps transmit and receive data
streams to bypass all of the transmit and receive oper­ations when set high. At power-up/reset, the value on
this pin is latched into bit Register 16, bit 13.

BP4B5B

Bypass 4B5B Encoder/Decoder Input

This pin allows 100 Mbps transmit and receive data
streams to bypass the 4B to 5B encoder and 5B to 4B
decoder circuits when set high. At power-up/reset, the

value on this pin is latched into Register 16, bit 15.

BPSCR

Bypass Scrambler/Descrambler Input

This pin allows 100 Mbps transmit and receive data
streams to bypass the scrambler and descrambler cir­cuits when set high. At power-up/reset, the value on
this pin is latched into Register 16, bit 14.

Auto-Negotiation

0101

0110

0111

1000

1001

1010

1011

1111

10TX FDX/HDX
without Flow
Control

Manual select
100TX FDX

Manual select
100TX HDX

Manual select
10TX FDX

Manual select
10TX HDX

Manual select
100FX FDX

Manual select
100FX HDX

Auto-Negotiation
10/100TX. HDX
only

10BTSER

Serial/Nibble Select Input

10 Mbps Serial Operation:
When set high, this input selects a serial data transfer

mode. Manchester encoded transmit and receive data
is exchanged serially with a 10 MHz clock rate on the
least significant bits of the nibble-wide MII data buses,
pin TXD[0] and RXD[0] respectively. This mode is in­tended for use with the NetPHY-1 device connected to
a device (MAC or Repeater) that has a 10 Mbps serial
interface. Serial operation is not supported in 100 Mbps
mode. For 100 Mbps, this input is ignored.

10 and 100 Mbps Nibble Operation:
When set low, this input selects the MII compliant nib-

ble data transfer mode . Transmit and receive data is e x­changed in nibbles on the TXD[3:0] and RXD[3:0] pins
respectively.

At power-up/reset, the value on this pin is latched into
Register 18, bit 10.

10 Am79C873

PRELIMINARY

■

Clock Interface
OSCI/X1

Crystal or Oscillator Input Input

This pin should be connected to a 25 MHz (±50 ppm)
crystal if OSC/XTL=0 or a 25 MHz (±50 ppm) external
TTL oscillator input, if OSC/XTLB=1.

X2

Crystal Oscillator Output Output

An external 25 MHz (±50 ppm) crystal should be con­nected to this pin if OSC/XTL=0, or left unconnected if
OSC/XTL=1.

OSC/XTL

Crystal or Oscillator Selector Pin Output

OSC/XTL=0: An external 25 MHz (±50ppm) crystal
should be connected to X1 and X2 pins.

OSC/XTL=1 : An external 25 MHz (±50ppm) oscilla­tor should be connected to X1 and X2 should be left
unconnected.

CLK25M

25 MHz Clock Output Output/Z

This clock is derived directly from the crystal circuit.

PHY Address Interface

The PHYAD[4:0] pins provide up to 32 unique PHY
addresses. An address selection of all zeros (00000)
will result in a PHY isolation condition. See the isolate
bit description in the BMCR, address 00.

PHYAD0

PHY Address 0 Input

This pin provides PHY address bit 0 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 8 during power up/reset.

PHYAD4

PHY Address 4 Input

This pin provides PHY address bit 4 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 4 during power up/reset.

Miscellaneous
NC

No Connect

These pins are to be left unconnected (floating).

BGREF

Bandgap V oltage Reference Input

Connect a 6.01K Ω, 1% resistor between this pin and
the BGRET pin to provide an accurate current refer­ence for the NetPHY-1 device.

BGRET

Bandgap Voltage Reference Return Input

This is the return pin for 6.01K Ω resistor connection.

TRIDRV

Tri-State Digital Output Input

When set high, all digital output pins are set to a high
impedance state, and I/O pins, go to input mode.

RESET

Reset Input

This pin is the active low input that initializes the NetPHY­1 device. It should remain low for 30 ms after VCC has
stabilized at 5 Vdc (nominal) before it transitions high.

TESTMODE

Test Mode Control Pin Input

TESTMODE=0: Normal operating mode.
TESTMODE=1: Enable test mode.

PHYAD1

PHY Address 1 Input

This pin provides PHY address bit 1 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 7 during power up/reset.

PHYAD2

PHY Address 2 Input

This pin provides PHY address bit 2 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 6 during power up/reset.

PHYAD3

PHY Address 3 Input

This pin provides PHY address bit 3 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 5 during power up/reset.

Am79C873 11

Power and Ground Pins

The power (VCC) and ground (GND) pins of the Net­PHY-1 device are grouped in pairs of two categories ­Digital Circuitry Power/Ground Pairs and Analog Cir­cuitry Power/Ground Pair.

DGND

Digital Logic Ground Power

These pins are the digital supply pairs.

DVCC

Digital Logic Power Supply Power

These pins are the digital supply pairs.

AGND

Analog Circuit Ground Power

These pins are the analog circuit supply pairs.

AVCC

Analog Circuit Power Supply Power

These pins are the analog circuit supply pairs.

PRELIMINARY

FUNCTIONAL DESCRIPTION

The NetPHY-1 Fast Ethernet single-chip transceiver,
provides the functionality as specified in the IEEE

802.3u standard, integrates complete 100BASE-FX,
100BASE-TX modules and a complete 10BASE-T
module. The NetPHY-1 device provides a Media Inde­pendent Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).

MII Interface

Carrier

Sense

The NetPHY-1 device performs all Physical Coding
Sublayer (PCS), Physical Media Access (PMA),
Twisted Pair Physical Medium Dependent (TP-PMD)
sublayer, 10BASE-T Encoder/Decoder, and Twisted
Pair Media Access Unit (TPMAU) functions. Figure 1
shows the major functional blocks implemented in the
NetPHY-1 device.

100Base

Transmitter

100Base
Receiver

10Base-T

Tranceiver

Collision

Detection

Auto

Negotiation

MII Serial

Management

Interface

Figure 1. Functional Block Diagram

MII Interface

The purpose of the MII interface is to provide a simple,
easy to implement connection between the MAC Rec­onciliation layer and the PHY. The MII is designed to
make the differences between various media transpar­ent to the MAC sublayer.

The MII consists of a nibble wide receive data bus, a
nibble wide transmit data bus , and control signals to f a­cilitate data transfers between the PHY and the Recon­ciliation layer.

■ TXD (transmit data) is a nibble (4 bits) of data that
are driven by the reconciliation sublayer synchro­nously with respect to TX_CLK. For each TX_CLK
period which TX_EN is asserted, TXD (3:0) are ac­cepted for transmission by the PHY.

■ TX_CLK (transmit clock) output to the MAC recon­ciliation sublay er is a continuous clock that pro vides
the timing reference for the transfer of the TX_EN,
TXD, and TX_ER signals.

22164A-3

■ TX_EN (transmit enable) input from the MAC recon­ciliation sublay er to indicate nibbles are being pre­sented on the MII for transmission on the physical
medium. TX_ER (transmit coding error) transitions
synchronously with respect to TX_CLK. If TX_ER is
asserted for one or more clock periods, and TX_EN
is asserted, the PHY will emit one or more symbols
that are not part of the valid data delimiter set some­where in the frame being transmitted.

■ RXD (receive data) is a nibble (4 bits) of data that
are sampled by the reconciliation sublayer syn­chronously with respect to RX_CLK. For each
RX_CLK period which RX_DV is asserted, RXD
(3:0) are transferred from the PHY to the MAC
reconciliation sublayer.

■ RX_CLK (receive clock) output to the MA C reconcil­iation sublayer is a continuous clock that provides
the timing reference for the transfer of the RX_DV,
RXD, and RX_ER signals.

12 Am79C873

PRELIMINARY

■ RX_D V (receive data valid) input from the PHY to in­dicate the PHY is presenting recovered and de­coded nibbles to the MAC reconciliation sub lay er . To
interpret a receive frame correctly by the reconcilia­tion sublayer, RX_DV must encompass the frame
starting no later than the Star t-of-Frame delimiter
and excluding any End-Stream delimiter.

■ RX_ER (receive error) transitions synchronously
with respect to RX_CLK. RX_ER will be asserted

TXD

CRS

TXD

IDLE

SSD

J/K

Preamble SFD Data

Preamble

SFD

for 1 or more clock periods to indicate to
the reconciliation sublayer that an error was
detected somewhere in the frame being transmit­ted from the PHY to the reconciliation sublayer.

■ CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10BASE-T and 100BASE-TX transmission.

100Base-TX

Data

ESD

T/R

EFD

IDLE

CRS

Figure 2. Carrier Sense during 10BASE-T and 100BASE-TX Transmission

100BASE Operation

The 100BASE transmitter receives 4-bit nibble data
clocked in at 25 MHz at the MII and outputs a scram­bled 5-bit encoded MLT-3 signal to the media at 100
Mbps. The on-chip clock circuit converts the 25 MHz
clock into a 125 MHz clock for internal use.

The IEEE 802.3u specification defines the Media Inde­pendent Interface. The interface specification defines a
dedicated receive data bus and a dedicated transmit
data bus.

10Base-T

22164A-4

These two busses include various controls and signal
indications that facilitate data transfers between the
NetPHY-1 device and the Reconciliation layer.

100BASE T ransmit

The 100BASE transmitter consists of the functional
blocks shown in Figure 3. The 100BASE transmit sec­tion converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125 million symbols per sec­ond serial data stream.

Am79C873 13

PRELIMINARY

MII

Signals

MII

Interface/

Control

4B/5B

Encoder

Scrambler

25M OSCI

TX CGM

Parallel
to Serial

NRZ

to

NRZI

NRZI to

MLT-3

LED1-4#

LED

Driver

MLT-3

Driver

Rise/Fall

Time

CTL

10BASE-T

Module

PECL

Driver

RX
TX

FXTD±

100TXD±

RXI±
10TXD±

Register

Collision

Detection

Figure 3. 100BASE Transmitter Functional Block Diagram

The block diagram in Figure 3 provides an overview of
the functional blocks contained in the transmit section.
The transmitter section contains the following func­tional blocks:

■ 4B5B Encoder

■ Scrambler

■ Parallel-to-Serial Converter

■ NRZ-to-NRZI Converter

■ PECL Driver (For FX Operation)

■ NRZI to MLT-3 (For TX Operation)

■ MLT-3 Driver (For TX Operation)

4B5B Encoder

The 4B5B encoder converts 4-bit (4B) nibble data gen­erated by the MAC Reconciliation Layer into a 5-bit
(5B) code group for transmission (see Table 1). This
conversion is required f or control and pack et data to be

Carrier

Sense

Auto-

Negotiation

22164A-5

combined in code groups. The 4B5B encoder substi­tutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit.

The 4B5B encoder continues to replace subsequent
4B preamble and data nibbles with corresponding 5B
code-groups. At the end of the transmit packet, upon
the deassertion of the Transmit Enable signal from the
MAC Reconciliation lay er , the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating end of
frame. After the T/R code-group pair , the 4B5B encoder
continuously injects IDLEs into the transmit data
stream until Transmit Enable is asserted and the next
transmit packet is detected.

The NetPHY-1 device includes a Bypass 4B5B conver­sion option within the 100BASE-TX transmitter for sup­port of applications like 100 Mbps repeaters which do
not require 4B5B conversion.

14 Am79C873