AMD AM7969-175JC, AM7969-175DC, AM7969-125V-BXA, AM7969-125VB3A, AM7969-125JC Datasheet

TAXIchip

TM

Integrated Circuits

Transparent Asynchronous

Transmitter/Receiver Interface

Am7968/Am7969-125
Am7968/Am7969-175

Data Sheet

and

Technical Manual

1994

 1994 Advanced Micro Devices, Inc.

Advanced Micro Devices reserves the right to make changes in its products

without notice in order to improve design or performance characteristics.

This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD



assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.

The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.

Trademarks

AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc.
TAXIchip and TAXI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Table of Contents

iii

TABLE OF CONTENTS

Am7968/Am7969 TAXIchip Integrated Circuits

Am7968/Am7969 Data Sheet 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Am7968/Am7969 Technical Manual 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1 Introduction 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 The Am7968 TAXI

TM

Transmitter 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 The Am7969 TAXI Receiver 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2 Using the TAXIchip Set 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Data and Command 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Operational Modes: Local, Cascade and Test 53. . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3 Data Encoding, Violation and Syncs 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Data Encoding 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Violation Logic 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 TAXI PLL Characteristics 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4 Clock Generation and Distribution 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 TAXI Transmitter Clock Connections 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Local Mode Transmitters 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 TAXI Receiver Clock Connections 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Cascade Mode Receivers (Am7969-125 only) 61. . . . . . . . . . . . . . . . . .

Chapter 5 Interfacing with the Serial Media 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Very Short Link, DC Coupled 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Terminated, DC Coupled 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Terminated, AC Coupled 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Baseline Wander and the AC Coupling Capacitor 64. . . . . . . . . . . . . . . . . . . . .

5.5 Interfacing to Fiber Optic Transmitters/Receivers 66. . . . . . . . . . . . . . . . . . . . .

5.5.1 DC-Coupled TAXl-Fiber Optic Transceiver Interface 66. . . . . . . . . . . . .

5.5.2 AC-Coupled TAXl-Fiber Optic Transceiver Interface 68. . . . . . . . . . . . .

5.6 Interfacing to Coaxial Cable 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Interfacing to Twisted-Pair Cable 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 6 Board Layout Considerations 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Printed Circuit Board Layout 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Rules for Layout 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Layout using Fiber Optic Data Links 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD

Table of Contents

iv

Chapter 7 Cascade Mode Operation 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Transmit Cascaded Data with a Single TAXI Transmitter 76. . . . . . . . . . . . . . .

7.2 Receivers In Cascade Mode: Connections (Am7969-125 only) 79. . . . . . . . . . .

7.3 Auto-Repeat Configuration 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Receiver Connections in Auto-Repeat Configuration 81. . . . . . . . . . . . .

7.3.2 Timing Limitations of the Auto-Repeat Configuration 84. . . . . . . . . . . . .

7.4 Unbalanced Configuration (Am7968/Am7969-125 only) 85. . . . . . . . . . . . . . . .

Chapter 8 Test Mode 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Transmitter Connections 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Receiver Connections 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Timing Relationships in Test Mode 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Optical Components Manufacturers 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B Error Detection Efficiency 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix C TAXI TIPs 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Publication# 07370 Rev. F Amendment/0
Issue Date: April 1994

Advanced

Micro

Devices

Am7968/Am7969

TAXIchipTM Integrated Circuits
(Transparent Asynchronous Xmitter-Receiver Interface)

FINAL

DISTINCTIVE CHARACTERISTICS

■ Parallel TTL bus interface

— Eight Data and four Command Pins
— or nine Data and three Command Pins
— or ten Data and two Command Pins

■ Transparent synchronous serial link

— +5 V ECL Serial I/O

— AC or DC coupled
— NRZI 4B/5B, 5B/6B encoding/decoding

■ Drive coaxial cable or twisted pair directly

■ Easy interface with fiber optic data links

■ 32–140 Mbps (4–17.5 Mbyte/s) data

throughput

■ Asynchronous input using STRB/ACK

■ Automatic MUX/DEMUX of Data and Command

■ Complete on-chip PLL, Crystal Oscillator

■ Single +5 V supply operation

■ 28-pin PLCC or DIP or LCC

GENERAL DESCRIPTION

The Am7968 TAXIchip Transmitter and Am7969
TAXIchip Receiver Chipset is a general-purpose inter­face for very high-speed (4–17.5 Mbyte/s, 40–175
Mbaud serially) point-to-point communications over co­axial or fiber-optic media. The TAXIchip set emulates a
pseudo-parallel register. They load data into one side
and output it on the other, except in this case, the “other”
side is separated by a long serial link.

The speed of a TAXIchip system is adjustable over a
range of frequencies, with parallel bus transfer rates of
4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
high end. The flexible bus interface scheme of the
TAXIchip set accepts bytes that are either 8, 9, or
10 bits wide. Byte transfers can be Data or Command
signaling.

BLOCK DIAGRAM
Am7968

Note:

N can be 8, 9, or 10 bits; total of N + M = 12.

07370F-1

Strobe (STRB)

Acknowledge (ACK

Clock (CLK)

Data Mode Select (DMS)

Test Serial In

(TSERIN)

Test/Local Select (TLS)

Strobe &

Acknowledge

Oscillator

and

Clock Gen.

Serial Interface

Shifter

Data Encoder

Encoder Latch

Input Latch

Media

Interface

(SEROUT+) Serial Out +
(SEROUT–) Serial Out –

Data Command

NM

X1

X2

AMD

2 Am7968/Am7969

BLOCK DIAGRAM (continued)
Am7969

Note:

N can be 8, 9, or 10 bits Total of N + M = 12

Output Latch

Data Decoder

Decoder Latch

Shifter

(X1)

(X2)

Oscillator

and

Clock Gen.

Media

Interface

PLL Clock
Generator

Byte Sync

Logic

NM

Data Command

(VLTN)
Violation

(DMS) Data Mode Select

(CNB) Catch Next Byte
(IGM) I-Got-Mine

(CLK) Clock

(DSTRB) Data Strobe

(CSTRB) Command Strobe

Serial In+ (SERIN+)
Serial In– (SERIN–)

07370F-2

CONNECTION DIAGRAMS
Top View

Am7968

1

234

28 27

26

255
24

23
22

21
20
19

1817

1615

6
7
8
9
10

11

12 13 14

SEROUT-

SEROUT+

STRB

ACK

DI5

DI4

DI3

CI0

CI1

DI9/CI2

DI8/CI3

DI7

DI6

CLK

V

CC2

(ECL)

V

CC1

(TTL)

V

CC3

(TTL)

RESET

DMS

TLS

TSERIN

DI2
DI1
DI0
GND1 (TTL)

X1

X2

GND2 (CML)

16
15

28
27

26
25

24
23

22
21

20
19
18

17
13
14

1
2
3
4

5
6

7
8

9
10
11
12

DIPs LCC/PLCC

Note:

Pin 1 is marked for orientation.

07370F-3

CI1

DI9/CI2

ACK

STRB
SEROUT+
SEROUT–

V

CC2

(ECL)

V

CC1

(TTL)

V

CC3

(CML)

RESET

DMS

TLS

TSERIN

CI0

DI7
DI8/CI3

DI5
DI4

DI3
DI2

DI1
DI0

GND1

(TTL)
GND2 (CML)
X1
X2

CLK
DI6

07370F-4

AMD

3Am7968/Am7969

CONNECTION DIAGRAMS (continued)
Top View

Am7969

1

234

28 27

26

255
24

23
22

21
20
19

1817

1615

6
7
8
9
10

11

12 13 14

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DSTRB

CSTRB

VLTN

CO0

CO1

DO9/CO2

IGM

RESET

V

CC1

(TTL)

SERIN+

SERIN-

DMS

DO7
CNB
X2
X1

CLK

GND2 (CML)

V

CC2

(CML)

DO8/CO3

GND1 (TTL)

LCC/PLCC

Note:

Pin 1 is marked for orientation.

07370F-5

CSTRB

VLTN

DO3
DO2

DO1
DO0

IGM

RESET

V

CC1

(TTL)

V

CC2

(CML)

SERIN+
SERIN–

DMS

DSTRB

CO1
CO0

DO4
DO5

DO6
DO7

CNB
X2

X1
GND2 (CML)
GND1

(TTL)
CLK
DO8/CO3
DO9/C02

16
15

28
27
26
25

24
23

22
21

20
19
18

17
13
14

1
2
3
4

5
6

7
8

9
10
11
12

DIPs

07370F-6

LOGIC SYMBOLS

Am7969

DOn/CO

m

VLTN

DSTRB

CSTRB

IGM

CLK

CNB DMS RESET

X1

X2

12

VCC = Power Supply (3)
GND = Ground (2)

2

12 2

Am7968

ACK

CLK

TLS DMS RESET

X1

X2

SERIN+SEROUT+

STRB

DI

n

/CI

m

VCC = Power Supply (2)
GND = Ground (2)

07370F-7 07370F-8

TSERIN

AMD

4 Am7968/Am7969

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is
formed by a combination of:

AM7968

DC

TEMPERATURE RANGE

C = Commerical (0°C to +70°C)

PACKAGE TYPE

D = 28-Pin Ceramic DIP (CD 028)
J = 28-Pin Plastic Leaded Chip

Carrier (PL 028)

SPEED OPTION

-125 = Max Serial Encoded
Transmission Rate is 125 MHz

-175 = Max Serial Encoded
Transmission Rate is 175 MHz

DEVICE NUMBER/DESCRIPTION

Am7968 TAXIchip Transmitter
Am7969 TAXIchip Receiver

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

Valid Combinations

AM7969

AM7968-125
AM7969-125
AM7968-175
AM7969-175

DC, JC

–125

AMD

5Am7968/Am7969

MILITARY ORDERING INFORMATION
CPL Products

Pkg Temps (TC) VCC CPL Part Number SMD Part Number APL Part Number

LCC –30°C to 125°C 4.5 V to 5.5 V AM7968-125/LKC
LCC –55°C to 125°C 4.75 V to 5.5 V 5962-9052701M3A AM7968-125V/B3A

DIP –30°C to 125°C 4.5 V to 5.5 V AM7968-125/DKC
DIP –55°C to 125°C 4.75 V to 5.5 V 5962-9052701MXA AM7968-125V/BXA

LCC –30°C to 125°C 4.5 V to 5.5 V AM7969-125/LKC
LCC –55°C to 125°C 4.75 V to 5.5 V 5962-9052801M3A AM7969-125V/B3A

DIP –30°C to 125°C 4.5 V to 5.5 V AM7969-125/DKC
DIP –55°C to 125°C 4.75 V to 5.5 V 5962-9052801MXA AM7969-125V/BXA

AMD products for Aerospace and Defense applications are available in several packages and operating ranges. CPL (Controlled
Products List) products are compliant with MIL-STD-883C requirements with exceptions for V

CC

or operating temperature. The

order number (Valid Combination) is formed by a combination of:

TEMPERATURE RANGE

K = –30°C to 125°C
M = –55°C to 125°C

PACKAGE TYPE

D = 28-Pin Ceramic DIP (CD 028)
L = 28-Pin Ceramic Leadless Chip

Carrier (CL 028)

DEVICE NUMBER/DESCRIPTION

Am7968 – TAXIchip Transmitter (Local Mode only)
Am7969 – TAXIchip Receiver (Local Mode only)

AM7968
AM7969

/L

K

Valid Combinations

Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.

C = Controlled Product List

C

Group A Tests

Group A tests consist of Subgroups

1, 2, 3, 7, 8, 9, 10, 11.

-125

SPEED OPTION

-125 = Max Serial Encoded Transmission
Rate is 125 MHz

Valid Combinations

AMD

6 Am7968/Am7969

PIN DESCRIPTION
Am7968 TAXIchip Transmitter
ACK

Input-Strobe Acknowledge (TTL Output)

ACK High signifies that the Am7968 is ready to accept
new Data and Command. The timing of ACK’s response
to STRB depends on the condition of the Input Latch (in
given CLK cycle).

If the Input Latch is empty, data is immediately stored
and ACK

closely follows STRB. If the Input Latch con­tains previously stored data when STRB is asserted,
ACK is delayed until the next falling edge of CLK. Note
that for ACK to rise STRB must maintain HIGH for both
of the above conditions.

CI0 – CI1

Parallel Command In (TTL Inputs)

These two inputs accept parallel command information
from the host system. If one or more command bits are
logic “1”, the command bit pattern is latched, encoded,
and transmitted in place of any pattern on the
Data inputs.

CLK

Clock (TTL I/O)

CLK is an I/O pin that supplies the byte-rate clock refer­ence to drive all internal logic. When TLS is connected to
ground (Local mode), CLK is enabled as a free-running
(byte-rate) clock output which runs at the Crystal Oscil­lator frequency; this output can be used to drive the X1
input of TAXIchip Receivers or other system logic. In
Test mode CLK becomes an input. In Test Mode 1 CLK
is a Byte rate input and in Test Mode 2 it is a Bit
rate input.

DI0 – DI7

Parallel Data In (TTL Inputs)

These eight inputs accept parallel data from the host
system, to be latched, encoded and transmitted.

DI8/CI3

Parallel Data (8) In or Command (3) In (TTL Input)

DI

8/CI3 input is either Data or Command, depending

upon the state of DMS

.

DI9/CI2

Parallel Data (9) In or Command (2) In (TTL Input)

DI

9/CI2

input is either Data or Command, depending

upon the state of DMS

.

DMS

Data Mode Select (Input)

Data Mode Select input determines the Data pattern
width. When it is wired to GND, the Am7968 Transmitter
will assume Data to be eight bits wide, with four bits of

Command. When it is wired to V

CC, the Am7968

Transmitter will assume Data to be nine bits wide, with
three bits of Command. If DMS is left floating (or termi­nated to 1/2 V

CC), the Am7968 will assume Data to be

ten bits wide, with two bits of Command.

GND1, GND2

Ground Pins

GND1

is a TTL I/O Ground and GND2 is an internal

Logic and Analog Ground.

RESET

PLL RESET (Input)

This pin is normally left open, but can be momentarily
grounded to force the internal PLL to reactivate lock.
This allows for correction in the unlikely occurrence of
PLL lockup on application of power.

RESET has an internal pull-up resistor which causes it
to float high when left unconnected (50 K ohm nominal).

If this board is driven by a board Reset signal, an open
drain (or open collector) style output should be used to
insure the High level signal is at VCC.

SEROUT+, SEROUT–

Differential Serial Data Out (Differential Open Emit­ter ECL Outputs)

These differential ECL outputs generate data at ECL
voltage levels referenced to +5.0 V. When connected to
appropriated pull down resistors, they are capable of
driving 50-Ω terminated lines, either directly or through
isolating capacitors.

STRB

Input Strobe Signal (TTL Input)

A rising edge on the STRB

input causes the Data (DI0 –

DI9)

or the Command (CI0 – CI3) inputs to be latched
into the Am7968 Transmitter. The STRB signal is nor­mally taken LOW after ACK

has risen.

TLS

Test/Local Select (Input)

TLS input determines the mode of operation. When TLS
is wired to GND, the Am7968 Transmitter assumes a
Local mode connection to the media. It will output NRZI
encoded data, and will enable its CLK output driver. The
TLS pin should always be grounded during normal
operation.

When TLS is wired to VCC (Test Mode 1),the serial data
is NRZ, CLK becomes an input, and ACK timing is modi­fied. This mode is only used for Automatic Test Equip­ment (ATE) testing at full speed.

When this input is left unconnected, it floats to an inter­mediate level which puts the Am7968 Transmitter into
its Test Mode 2. In Test Mode 2, the internal clock

AMD

7Am7968/Am7969

multiplier is switched out, and the internal logic is
clocked directly from the CLK pin. Test Mode 2 is in­cluded to ease Automatic Test Equipment (A.T.E.) test­ing by making the internal logic of the Transmitter
synchronous to the external clock instead of the
internal PLL.

TSERIN

Test Serial Input (Pseudo ECL Input)

This pin is left unconnected in Local Mode operation.
TSERIN can be used to input serial data patterns into
the Shifter in Test Mode 1 operation.

V

CC1

, V

CC2

, V

CC3

Power Supply

V

CC1

, V

CC2

, and V

CC3

are +5.0 volt nominal power sup-

ply pins. V

CC1

powers TTL I/O, V

CC2

powers ECL and

V

CC3

powers internal Logic and Analog circuitry.

X1, X2

Crystal Oscillator Inputs (Inputs)

The two crystal input pins connect to an internal parallel
mode oscillator which operates at the fundamental fre­quency of the external crystal. The byte rate matches
the crystal frequency. During normal operation, the byte
rate is set by the crystal frequency.

Alternatively, X1 can be driven by an external TTL fre­quency source. In multiple TAXI systems this external
source could be another Am7968’s CLK output.

AMD

8 Am7968/Am7969

Am7969 TAXIchip Receiver
CLK

Clock (TTL Output)

This is a free-running clock output which runs at the byte
rate, and is synchronous with the serial input. It falls at
the time that the Decoder Latch is loaded from the
Shifter, and rises at mid-byte. The

CLK

output of the Re­ceiver is not suitable as a frequency source for another
TAXI Transmitter or Receiver. It is intended to be used
by the host system as a clock synchronous with the re­ceived data.

CNB

Catch Next Byte Input (TTL Input)

If this input is connected to the

CLK

output, the Receiver
will be in the Local mode, and each received byte will be
captured, decoded and latched to the outputs.

If the

CNB

input is HIGH, it allows the Am7969 Receiver
to capture the first byte after a sync. The Am7969 Re­ceiver will wait for another sync before latching the data
out, and capturing another. If

CNB

is toggled LOW, it will

react as if it had decoded a sync byte.
In Cascade mode,

CNB

input is typically connected to

an upstream Am7969’s

IGM

output. The first Am7969

Receiver in line will have its

CNB

input connected to

V

CC

.

For Am7969-175 applications, an inverter is required
between CLK and CNB for speeds above 140 MHz. See
Figure 3 and Timing Specifications T47A, T47B, T48,
and T49.

CO0 – CO1

Parallel Command Out (TTL Output)

These two outputs reflect the most recent Command
data received by the Am7969 Receiver.

CSTRB

Command Data Strobe (TTL Output)

The rising edge of this output signals the presence of
new Command data on the CO0 – CO3 lines. Command
bits are valid just before the rising edge of

CSTRB

.

DMS

Data Mode Select (Input)

DMS

selects the Data pattern width. When it is wired to
GND, the Am7969 Receiver will assume Data to be
eight bits wide, with four bits of Command. When it is
wired to V

CC

the Am7969 Receiver will assume Data to

be nine bits wide, with three bits of Command. If

DMS

is

left floating (or terminated to 1/2 V

CC

), the Am7969 Re­ceiver will assume Data to be ten bits wide, with two bits
of Command.

DO0 – DO7

Parallel Data Out (TTL Outputs)

These eight outputs reflect the most recent Data re­ceived by the Am7969 Receiver.

DO8/CO3

Parallel Data (8) Out or Command (3) Out
(TTL Output)

DO8/CO3 output will be either a Data or Command bit,
depending upon the state of

DMS

.

DO9/CO2

Parallel Data (9) Out or Command (2) Out
(TTL Output)

DO9/CO2

output will be either a Data or Command bit,

depending upon the state of

DMS

.

DSTRB

Output Data Strobe (TTL Output)

The rising edge of this output signals the presence of
new Data on the DO0 – DO9

lines. Data is valid just be-

fore the rising edge of

DSTRB.

GND1, GND2

Ground

GND1

is a TTL I/O Ground,

GND2

is an internal Logic

and Analog Ground.

IGM

I-Got-Mine (TTL Output)

This pin signals cascaded Am7969 Receivers that their
upstream neighbor has captured its assigned data byte.

IGM

falls at the mid-byte when the first half of a sync
byte is detected in the Shifter. It rises at mid-byte when it
detects a non-sync pattern. During Local mode opera­tion the

IGM

signal is undefined.

RESET

PLL RESET (Input)

This pin is normally left open, but can be momentarily
grounded to force the internal PLL to reactivate lock.
This allows for correction in the unlikely occurance of
PLL Lockup on application of power.

RESET has an internal pull-up resistor (50 K nominal)
which causes it to float high when left unconnected.

If this board is driven by a board Reset signal, an open
drain (or open collector) style output should be used to
insure the High level signal is at VCC.

SERIN+, SERIN–

Differential Serial Data In (ECL Inputs)

Data is shifted serially into the Shifter. The

SERIN+

and

SERIN–

differential ECL inputs accept ECL voltage

AMD

9Am7968/Am7969

swings, which are referenced to +5.0 V. When

SERIN–

is grounded, the Am7969 is put into Test Mode;

SERIN+

becomes a single-ended ECL input, the PLL clock gen­erator is bypassed, and

X1

determines the bit rate

(rather than the byte rate). Both pins have internal pull
down resistors which cause unterminated inputs to
stay low.

V

CC1

, V

CC2

Power Supply

V

CC1

and

V

CC2

are +5.0 volt nominal power supply pins.

V

CC1

powers TTL I/O, and

V

CC2

powers internal Logic

and Analog circuitry.

VLTN

Violation (TTL Output)

The rising edge of this output indicates that a transmis­sion error has been detected. It changes state at the

same time

DOi

or

COi

change and will be followed by

either

DSTRB

or

CSTRB

. This pin goes LOW when the

next valid byte is decoded.

X1, X2

Crystal Oscillator Inputs (Inputs)

These two crystal input pins connect to an internal paral­lel/mode oscillator which oscillates at the fundamental
frequency external crystal. During normal operation, the
byte rate is set by the crystal frequency. Alternatively,

X1

can be driven by an external frequency source. In
multiple TAXI systems, this external source could be a
TAXI Transmitter’s

CLK

output or an external TTL fre-

quency source.

AMD

10 Am7968/Am7969

FUNCTIONAL DESCRIPTION
System Configuration

The TAXIchip system provides a means of connecting
parallel data systems over a serial link (Figure 2). In
LOCAL Mode (normal operation mode) each TX/RX
pair is connected over a serial link which can be a Fiber
Optic or Copper Media (Figure 3).

The Am7968 Transmitter accepts inputs from a sending
host system using a simple

STRB/ACK

handshake.
Parallel bits are saved by the Am7968’s input latch on
the rising edge of a

STRB

input. The input latch can be

updated on every

CLK

cycle; if it still contains previously

stored data when a second

STRB

pulse arrives, Data is

stored in the input latch, and the second

ACK

response

is delayed until the next

CLK

cycle.

The inputs to an Am7968 Transmitter can be either Data
or Command and may originate from two different parts
of the host system. A byte cycle may contain Data or
Command, but not both. Data represents the normal
data channel message traffic between host systems.
Commands can come from a communication control
section of the host system. Commands occur at a rela­tively infrequent rate but have priority over Data. Exam­ples include communication specific commands such
as REQUEST-TO-SEND or CLEAR-TO-SEND; or
application specific commands such as MESSAGE­ADDRESS-FOLLOWS, MESSAGE-TYPE-FOLLOWS,
INITIALIZE YOUR SYSTEM, ERROR, RETRANSMIT,
HALT, etc.

The Am7968 Transmitter switches between Data and
Command by examining Command input patterns. All
0s on Command input pins cause information on the
Am7968’s Data input pins to be latched into the device
on the rising edge of

STRB

. All other Command patterns
cause a Command symbol to be sent in response to an
input strobe. The pattern on the Data inputs is ignored
when a Command symbol is sent. In either case, if there
is no

STRB

before the next byte boundary, a Sync sym­bol will be transmitted. The sync pattern maintains link
synchronization and provides an adequate signal transi­tion density to keep the Receiver Phase-Locked-Loop
(PLL) circuits in lock. It was chosen for its unique pattern
which never occurs in any Data or Command mes­sages. This feature allows Sync to be used to establish
byte boundaries.

The Sync pattern utilized by TAXIchip set keeps the
automatic gain control (AGC) fiber-optic transceiver cir­cuits in their normal range because the pattern has zero
DC offset.

The Am7969 Receiver detects the difference between
Data and Command patterns and routes each to the
proper Output Latch. When a new Data pattern enters
the output latch,

DSTRB

is pulsed and Command

information remains unchanged. If a Command pattern
is sent to the output latch or if Sync is received,

CSTRB

is pulsed and Data outputs remain in their previous
state. Reception of a Sync pattern clears the Command
outputs to all 0’s, since Sync is a legal command.

Noise-induced bit errors can distort transmitted bit pat­terns. The Am7969 Receiver logic detects most noise­induced transmission errors. Invalid bit patterns are
recognized and indicated by the assertion of the viola­tion (

VLTN

) output pin. This signal rises to a logic “1”
state at the same time that Data or Command outputs
change and remains HIGH until a valid pattern is
detected by the Data Decoder. The error detection
method used in the Receiver cannot identify bit
errors which transform one valid Command or Data pat­tern to another. Fault-sensitive systems should use ad­ditional error checking mechanisms to guarantee
message integrity.

Am7968 Transmitter

The Transmitter accepts messages from its parallel in­put pins (Command or Data). Once latched into an
Am7968, a parallel message is encoded, serialized, and
shifted out to the serial link. The idle time between trans­mitted bytes (evident by lack of STRB) is filled with
Sync bytes.

Am7969 Receiver

Receivers accept differential signals on the

SERIN+/

SERIN–

input pins. This information, previously
encoded by an Am7968 Transmitter, is loaded into
a decoder.

When serial patterns are received, they are decoded
and routed to the appropriate outputs. If the received
message is a Command, it is stored in the output latch,
appears at the Command output pins, and

CSTRB

is
pulsed; Data output pins continue holding the last Data
byte and

DSTRB

stays inactive. If a Data message fol­lows the reception of a Command, Command output
pins continue holding the previous Command byte and

CSTRB

stays inactive. The command outputs will retain
their states until another Command signal is received
(Sync is considered to be a valid command which, when
decoded, sets Command outputs to “0” and issues a re­sulting

CSTRB

).

Byte Width

The TAXIchip set has twelve parallel interface pins
which are designated to carry either Command or Data
bits. The Data Mode Select (

DMS

) pin on each chip can
be set to select one of three modes of operation: eight
Data and four Command bits, nine Data and three Com­mand, or ten Data and two Command. This allows the
system designer to select the byte-width which best
suits system needs.

AMD

11Am7968/Am7969

Am7968 Encoder/Am7969 Decoder

To guarantee that the Am7969’s PLL can stay locked
onto an incoming bit stream, the data encoding scheme
must provide an adequate number of transitions in each
data pattern. This implies a limit on the maximum time
allowed between transitions. The TAXIchip set encod­ing scheme is based on the ANSI X3T9.5 (FDDI) com­mittee’s 4-bit/5-bit (4B/5B) code.

An ANSI X3T9.5 system used an 8-bit parallel data pat­tern. This pattern is divided into two 4-bit nibbles which
are each encoded into a 5-bit symbol. Of the thirty-two
patterns possible with these five bits, sixteen are chosen
to represent the sixteen input Data patterns. Some of
the others are used as Command symbols. Those re­maining represent invalid patterns that fail either the
run-length test or DC balance tests.

Transmitters in 8-bit mode use two 4B/5B encoders to
encode eight Data bits into a 10-bit pattern. In 9-bit
mode, Transmitters use one 5B/6B encoder and one
4B/5B encoder to code nine Data bits into an 11-bit pat­tern. In 10-bit mode, two 5B/6B encoders are used to
change ten bits of Data into a 12-bit pattern (see Tables
1 and 2 for encoding patterns).

The Am7968 Transmitter further encodes all symbols
using NRZI (Non Return to Zero, Invert on Ones). NRZI
represents a “1” by a transition and a “0” by the lack of
transition. In this system a “1” can be a HIGH-to-LOW or
LOW-to-HIGH transition. This combination of 4B/5B
and NRZI encoding ensures at least two transitions per
symbol and permits a maximum of three consecutive
non-transition bit times. The Am7969 then uses the
same method to decode incoming symbols so that the
whole encoding/decoding process is transparent to
the user.

Most Serially transmitted data patterns with this code
will have the same average amount of HIGH and LOW
times. This near DC balance minimizes pattern-sensi­tive decoding errors which are caused by jitter in AC­coupled systems.

Operational Modes

In normal operational mode, a single Transmitter/
Receiver pair is used to transfer 8, 9, or 10 bits of parallel
Data over a private serial link. (On the Am7968, the

TLS

pin is tied to ground and

TSERIN

is left unconnected).

On the Am7969,

CNB

must be connected to the CLK
output. The Am7969 Receiver continuously deserial­izes the incoming bit stream, decodes the resulting pat­terns, and saves parallel data at its output latches (see
Figure 3).

Local mode provides a fast and efficient parallel
throughout because data can be transferred on every
clock cycle. On the other hand, it is not necessary for the
host to match the byte rate set by the Transmitter’s crys­tal oscillator; the Am7968 automatically sends a Sync

pattern during each clock cycle in which no new Data or
Command messages are being transmitted.

Cascade Mode (for –125 only)

For very wide parallel buses, TAXI Receiver’s (commer­cial temperature parts only) can be Cascaded. The
Am7969 Receivers all have their

SERIN+

and

SERIN–

pins connected to the media (or an optical data link).

IGM

of each Am7969 is connected to

CNB

of its down­stream neighbor or is left unconnected on the Receiver
farthest downstream.

CNB

of the first Receiver is tied
HIGH, making this device the only Receiver in the chain
that can act on the first non-Sync pattern in a message
(see below).

Each TAXIchip Receiver monitors the serial link and a
special acknowledgment scheme is used to direct sym­bols into each of the Am7969s. When a Catch-Next­Byte (

CNB

) input is HIGH, the Receiver will capture the
next non-Sync symbol from the serial link. At this point,
the device forces its I-Got-Mine (

IGM

) pin HIGH to tell
the downstream Receiver to capture the next symbol.
The Receiver then waits for the Sync symbol or for its

CNB

to be set LOW before transferring the message to

its output latch.

IGM

is forced LOW whenever a Sync

byte is detected or when

CNB

goes LOW. This

IGM

-

CNB

exchange continues down the chain until the last
Receiver captures its respective byte. The next byte to
appear on the serial link will be a Sync symbol which is
detected by all of the cascaded Am7969s. On the follow­ing Clock cycle their messages are transferred to the
output latch of each device and sent to the receiving
host.

IGM

pins on all Receivers are also set LOW when

the first half of the Sync symbol is detected.

Asynchronous Operation

Inputs to the Am7968 Transmitter Input Latch can be
asynchronous to its internal clock. Data

STRB

will latch
data into the Am7968 Transmitter and an internal clock
will transfer the data to the Encoder Latch at the first
byte boundary. Data can be entered at any rate less
than the maximum transfer rate without regard to actual
byte boundaries. As data rates approach the TAXI
BYTE RATE, care must be taken to insure that the 2
BYTE FIFO inside TAXI Transmitter is not over filled.

STRB/ACK

handshake will assure that every byte is
transferred correctly. At higher byte rates, where delays
and setup/hold times make the

STRB/ACK

handshake

impractical,

STRB

should be synchronized with

CLK

.

Synchronous Operation

The Transmitter may be strobed synchronous by tying
the strobe to the input clock. When doing this a provision
should be make to inhibit the strobe periodically to en­sure proper byte alignment. In the absence of a strobe,
Syncs will be transmitted on the serial link which will al­low the receiver to re-align the byte boundaries. In addi­tion it is essential that the delay between the falling edge

AMD

12 Am7968/Am7969

of the internal byte clock (CLK) and the rising edge of
strobe does not violate t

BB

specification shown in the

SWITCHING CHARACTERISTICS Section.
The internal byte clock controls the flow of data from the

input register through the shift register. The falling edge
of the internal byte clock delineates the end of one byte
from the start of the next. Due to various tolerances in
the PLL, the period of the internal byte clock may vary
slightly. This effect may cause a shift in the location of
the byte boundary with respect to the falling edge of the
clock. This variation may move the byte boundary and
therefore creates a window during which the part should
not be strobed. This window called the t

6

window, is
shown in the figure below. If the part is strobed during
the t

6

window data will not be lost however, a sync may
be added and the transmitter latency will be increased
by one byte time.

CLK

–9/8(t1/n) + 9 ns

20 ns

Strobe Stayout Area

(t6 window)

07370F-9

Nominal Byte

Boundary

Sync Acquisition

In case of errors which cause Am7969 Receivers to lose
byte/symbol sync, and on power-up, internal logic de­tects this loss-re-acquisition of sync and modifies the

CLK

output.

CLK

output is actually a buffered version of
the signal which controls Data transfers inside the
Am7969 Receiver on byte boundaries. Byte boundaries
move when the Am7969 Receiver loses, and re­acquires sync. To protect slave systems (which may use
this output as a clock synchronous with the incoming

data) from having clocks which are too narrow, the out­put logic will stretch an output pulse when the pulse
would have been less than a byte-time long. The data
being processed just prior to this re-acquisition of sync
will be lost. The Sync symbol, and all subsequent data
will be processed correctly.

TAXI User Test Modes

TLS

input can be used to force the Am7968 Transmitter

into either of the two Test modes. If

TLS

is open or termi-

nated to approximately V

CC

/2 (Test Mode 2), the internal
VCO is switched out and everything is clocked directly
from the

CLK

input. The serial output data rate will be at
the CLK bit rate and not at 10X, 11X, or 12X, as is the
case in normal operation. Test Mode 2 will allow testing
of the logic in the Latches, Encoder, and Shifter without
having to first stabilize the PLL clock multiplier. In Test
Mode 1 (

TLS

wired to VCC), the PLL is enabled and the
chip operates normally, except that the output is an NRZ
stream (CLK is an input & ACK function is slightly modi­fied). This will allow testing of all functions at full rate
without needing to perform match loop tests to accom­modate the data inversion characteristics of NRZI.

Differential

SERIN+/SERIN–

inputs can be used to
force the Am7969 Receiver into its Test mode. This will
allow testing of the logic in the Latches, Decoder, and
Shifter without having to first stabilize the the PLL. If

SERIN–

is tied to ground, the internal VCO is switched

out and

X

1

becomes the internal bit rate clock. The serial

data rate will be at the CLK bit rate, not at 10X, 11X, or
12X, as is the case in normal operation. In this mode,

SERIN+

becomes a single-ended serial data input with
nominal 100K ECL threshold voltages (Referenced to
+5 volts).

These Test Mode switches make the parts determinate,
synchronous systems, instead of statistical, asynchro­nous ones. An automatic test system will be able to
clock each part through the functional test patterns at
any rate or sequence that is convenient. After the logic
has been verified, the part can be put back into the nor­mal mode, and the PLL functions verified knowing that
the rest of the chip is functional.

AMD

13Am7968/Am7969

Oscillator

The Am7968 and Am7969 contain an inverting amplifier
intended to form the basis of a parallel mode oscillator.
The design of this oscillator considered several factors
related to its application.

The first consideration is the desired frequency accu­racy. This may be subdivided into several areas. An os­cillator is considered stable if it is insensitive to
variations in temperature and supply voltage, and if it is
unaffected by individual component changes and aging.
The design of the TAXIchip set is such that the degree to
which these goals are met is determined primarily by the
choice of external components. Various types of crystal
are available and the manufacturers’ literature should
be consulted to determine the appropriate type. For
good temperature stability, zero temperature coefficient
capacitors should be used (Type NPO).

The mechanism by which a crystal resonates is electro­mechanical. This resonance occurs at a fundamental

frequency (1st harmonic) and at all odd harmonics of
this frequency (even harmonic resonance is not me­chanically possible). Unless otherwise constrained,
crystal oscillators operate at their fundamental
frequencies.

A typical crystal specification for use in this circuit is:
Fundamental Frequency 3.3 MHz–17.5 MHz ± 0.1%

Resonance: Mode Parallel
Load Capacitor (Correlation) 30 pF
Operating Temperature Range 0°C to 70°C
Temperature Stability ±100 ppm
Drive Level (Correlation) 2 mW
Effective Series Resistance 25 Ω (max)
Holder Type Low profile
Aging for 10 years ±10 ppm
It is good practice to ground the case of the crystal to

eliminate stray pick-up and keep all connections as
short as possible.

RESET

Am7968 or, Am7969

X1 X2

CC

Power On RESET (Optional)

C* = 220 pF for 4.0–12.5 MHz crystal, 150 pF for a 12.5–17.5 MHz Crystal.
*C determined by crystal specifications and trace capacities. Values shown are typical.

07370F-10

Figure 1. Connections for 4.0 MHz–17.5 MHz

AMD

14 Am7968/Am7969

Table 1. TAXIchip Encoder Patterns

4-Bit 5-Bit 5-Bit 6-Bit

HEX Binary Encoded HEX Binary Encoded

Data Data Symbol Data Data* Symbol

0 0000 11110 00 00000 110110
1 0001 01001 01 00001 010001
2 0010 10100 02 00010 100100
3 0011 10101 03 00011 100101
4 0100 01010 04 00100 010010
5 0101 01011 05 00101 010011
6 0110 01110 06 00110 010110
7 0111 01111 07 00111 010111
8 1000 10010 08 01000 100010

9 1001 10011 09 01001 110001
A 1010 10110 0A 01010 110111
B 1011 10111 0B 01011 100111
C 1100 11010 0C 01100 110010
D 1101 11011 0D 01101 110011
E 1110 11100 0E 01110 110100
F 1111 11101 0F 01111 110101

10 10000 111110
11 10001 011001
12 10010 101001
13 10011 101101
14 10100 011010
15 10101 011011
16 10110 011110
17 10111 011111
18 11000 101010
19 11001 101011
1A 11010 101110

1B 11011 101111
1C 11100 111010
1D 11101 111011
1E 11110 111100
1F 11111 111101

* Note:

HEX data is parallel input data which is represented by the 4- or 5-bit binary data listed in the column to the immediate right
of HEX data. Binary bits are listed from left to right in the following order.

8-Bit Mode: D7, D6, D5, D4, (4-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
9-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D3, D2, D1, D0, (4-Bit Binary)
10-Bit Mode: D8, D7, D6, D5, D4, (5-Bit Binary), and D9,D3, D2, D1, D0, (5-Bit Binary)

Serial bits are shifted out with the most significant bit of the most significant nibble coming out first.

4B/5B Encoder Scheme 5B/6B Encoder Scheme

AMD

15Am7968/Am7969

Table 2. TAXIchip Command Symbols

Encoded

HEX Binary Symbol Mnemonic HEX Binary

8-Bit Mode

0 0000 XXXXX XXXXX Data No Change No Change

(Note 2) (Note 2)

No STRB No STRB 11000 10001 JK (8-bit Sync) 0 0000

(Note 1) (Note 1)

1 0001 11111 11111 I I 1 0001
2 0010 01101 01101 TT 2 0010
3 0011 01101 11001 TS 3 0011
4 0100 11111 00100 I H 4 0100
5 0101 01101 00111 TR 5 0101
6 0110 11001 00111 SR 6 0110
7 0111 11001 11001 SS 7 0111

8 (Note 3) 1000 00100 00100 HH 8 1000

9 1001 00100 11111 HI 9 1001

A (Note 3) 1010 00100 00000 HQ A 1010

B 1011 00111 00111 RR B 1011

C 1100 00111 11001 RS C 1100
D (Note 3) 1101 00000 00100 QH D 1101
E (Note 3) 1110 00000 11111 Q I E 1110
F (Note 3) 1111 00000 00000 QQ F 1111

9-Bit Mode

0 000 XXXXXX XXXXX Data No Change No Change

(Note 2) (Note 2)

No STRB No STRB 011000 10001 LK (9-bit Sync) 0 000

(Note 1) (Note 1)

1 001 111111 11111 I ’ I 1 001

2 010 011101 01101 T ’ T 2 010

3 011 011101 11001 T’S 3 011

4 100 111111 00100 I’ H 4 100

5 101 011101 00111 T’R 5 101

6 110 111001 00111 S’R 6 110

7 111 111001 11001 S’S 7 111

10-Bit Mode

0 00 XXXXXX XXXXXX Data No Change No Change

(Note 2) (Note 2)

No STRB No STRB 011000 100011 LM (10-bit Sync) 0 00

(Note 1) (Note 1)

1 01 111111 111111 I ’ I ’ 1 01

2 10 011101 011101 T ’ T ’ 2 10

3 11 011101 111001 T ’ S ’ 3 11

Notes:

1. Command pattern Sync cannot be explicitly sent by Am7968 Transmitter with any combination of inputs and STRB,
but is used to pad between user data.

2. A strobe with all Os on the Command input lines will cause Data to be sent. See Table 1.

3. While these Commands are legal data and will not disrupt normal operation if used occasionally, they
may cause data errors if grouped into recurrent fields. Normal PLL operation cannot be guaranteed if one or more
of these commands is continuously repeated.

Command Input Command Output

Am7969 Receiver

Am7968 Transmitter

AMD

16 Am7968/Am7969

Am7968 Transmitter Functional Block
Description

(Refer to page 1)

Crystal Oscillator/Clock Generator

The serial link speed is derived from a master frequency
source (byte rate). This source can either be the built-in
Crystal Oscillator, or a clock signal applied through the

X1

pin. This signal is buffered and sent to the

CLK

out-

put when Am7968 Transmitter is in Local mode.

CLK

(input is multiplied by ten (8-bit mode), eleven (9-bit
mode), or twelve (10-bit mode), using the internal PLL to
create the bit rate.

The working frequency can be varied between 3.3 MHz
and 17.5 MHz. The crystal frequency required to
achieve the maximum 175 Mbaud on the serial link, and
the resultant usable data transfer rate will be:

Crystal Am7968-125 Input and Am7969-125 Internal

Mode Frequency Maximum Parallel Throughput Divide Ratio

8-Bit 12.50 MHz 80 ns/pattern (100 Mbit/sec) 125/10
9-Bit 11.36 MHz 88 ns/pattern (102 Mbit/sec) 125/11

10-Bit 10.42 MHz 96 ns/pattern (104 Mbit/sec) 125/12

Crystal Am7968-175 Input and Am7969-175 Internal

Mode Frequency Maximum Parallel Throughput Divide Ratio

8-Bit 17.50 MHz 57.1 ns/pattern (140 Mbit/sec) 175/10
9-Bit 15.90 MHz 62.8 ns/pattern (143 Mbit/sec) 175/11

10-Bit 14.58 MHz 68.5 ns/pattern (145 Mbit/sec) 175/12

Input Latch

The Am7968’s Input Latch accommodates asynchro­nous strobing of Data and Command by being divided
into two stages.

If

STRB

is asserted when both stages are empty, Data
or Command bits are transferred directly to the second
stage of the Input Latch and

ACK

rises shortly after

STRB

. This pattern is now ready to move to the Encoder

Latch at the next falling edge of

CLK

.

An input pattern is strobed into the first stage of the Input
Latch only when the second stage is BUSY (contains
previously stored data). The Transmitter will be BUSY
when

STRB

is asserted a second time in a given

CLK

cycle. Contents of the first stage are not protected from
subsequent

STRBs

within the same

CLK

cycle. At the

falling edge of

CLK

, previously stored data is transferred
from the second stage to the Encoder Latch and the new
data is clocked into the second stage of the Input Latch.
If in Local mode,

ACK

will rise at this time.

Encoder Latch

Input to the Encoder Latch is clocked by an internal sig­nal which is synchronous with the shifted byte being
sent on the serial link. Whenever a new input pattern is
strobed into the Input Latch, the data is transferred to the
Encoder Latch at the next opportunity.

Data Encoder

Encodes twelve data inputs (8, 9, 10 Data bits or 4, 3, 2
Command inputs) into 10, 11, or 12 bits. The Command
data inputs control the transmitted symbol. If all Com­mand inputs are LOW, the symbol for the Data bits will
be sent. If Command inputs have any other pattern then
the symbol representing that Command will be
transmitted.

Shifter

The Shifter is parallel-loaded from the Encoder at the
first available byte boundary, and then shifted until the
next byte boundary. The Shifter is being serially loaded
at all times. As data is being shifted out of the Transmit­ter, the shifter fills from the LSB. If parallel data is avail­able at the end of the byte, it is parallel-loaded into the
Shifter and begins shifting out during the next clock cy­cle. Otherwise, the serially loaded data fills the next
byte. The serial data which loads into the Shifter is gen­erated by an internal state machine which generates a
repeating Sync pattern.

Media Interface

The Media Interface is differential ECL, referenced to
+5 V. It is capable of driving lines terminated with 50 Ω to
(V

CC

- 2.0) volts.

AMD

17Am7968/Am7969

Am7969 Receiver Functional Block
Description

(Refer to page 1)

Crystal Oscillator/Clock Generator

The data recovery PLL in the Am7969 must be supplied
with a reference frequency at the expected byte rate of
the data to be recovered. The source of this frequency
can either be the built-in Crystal Oscillator, or an exter­nal clock signal applied through the

X

1

pin. The refer­ence frequency source is then multiplied by ten (8-bit
mode), eleven (9-bit mode) or twelve (10-bit mode) us­ing an internal PLL.

Media Interface

SERIN+, SERIN– inputs are to be driven by differential
ECL voltages, referenced to +5 V. Serial data at these
inputs will serve as the reference for PLL tracking.

PLL Clock Generator

A PLL Clock recovery loop follows the incoming data
and allows the encoded clock and data stream to be de­coded into a separated clock and data pattern. It uses
the crystal oscillator and clock generator to predict the
expected frequency of data and will track jittered data
with a characteristically small offset frequency.

Shifter

The Shifter is serially loaded from the Media Interface,
using the bit clock generated by PLL.

Byte Sync Logic

The incoming data stream is a continuous stream of
data bits, without any significant signal which denotes
byte boundaries. This logic will continuously monitor the
data stream, and upon discovering the reserved code
used for Am7969 Receiver Sync, will initialize a
synchronous counter which counts bits, and indicates
byte boundaries.

The logic signal that times data transfers from the Shif­ter to the Decoder Latch is buffered and sent to the

CLK

output.

CLK

output from the Receiver is not suitable as a
frequency source for another TAXI Transmitter or Re­ceiver. It is intended to be used by the host system as a
clock synchronous with the received data. This output is
synchronous with the byte boundary and is synchronous
with the Receiver’s internal byte clock.

Byte Sync Logic is responsible for generating the inter­nal strobe signals for Parallel Output Latches. It also
generates the

IGM

(I-Got-Mine) signal in Test mode

when the first byte after a Sync symbol is transferred.
Parallel outputs are made on a byte boundary, after

CNB

falls, or when Sync is detected.

The I-Got-Mine (

IGM

) signal will fall when the first half of

a Sync is detected in the Shifter or when

CNB

goes
LOW. It will remain LOW until the first half of a non-Sync
byte is detected in the Shifter, whereupon it will rise (as­suming that the

CNB

input is HIGH). A continuous

stream of normal data or command bytes will cause

IGM

to go HIGH and remain HIGH. A continuous stream of
Sync’s will cause

IGM

to stay LOW.

IGM

will go HIGH
during the byte before data appears at the output. This
feature could be used to generate an early warning of in­coming data.

Decoder Latch

Data is loaded from the Shifter to this latch at each
symbol/byte boundary. It serves as the input to the
Data Decoder.

Data Decoder

Decodes ten, eleven, or twelve data inputs into twelve
outputs. In 8-bit mode, data is decoded into either an
8-bit Data pattern or a 4-bit Command pattern. In 9-bit
mode, data is decoded into either a 9-bit Data pattern or
a 3-bit Command pattern. In 10-bit mode, data is de­coded into either a 10-bit Data pattern or a 2-bit Com­mand pattern.

The decoder separates Data symbols from Command
symbols, and causes the appropriate strobe output to
be asserted.

Parallel Output Latch

Output Latch will be clocked by the byte clock, and will
reflect the most recent data on the link. Any Data pattern
will be latched to the Data outputs and will not affect the
status of the Command outputs. Likewise, any Com­mand pattern will be latched to the Command outputs
without affecting the state of the Data outputs.

Any data transfer, either Data or Command will be syn­chronous with an appropriate output strobe. However,
there will be

CSTRBs

when there is no active data on the

link, since Sync is a valid Command code.
Any pattern which does not decode to a valid Command

or Data pattern is flagged as a violation. The output of
the decoder during these violations is indeterminate and
will result in either a

CSTRB

or

DSTRB

output when the

indeterminate pattern is transferred to the output latch.

AMD

18 Am7968/Am7969

Note:

N can be 8, 9, or 10 bits of parallel data; total of N + M = 12.

07370F-11

M

N

Data

Signals

Data

Source

Message

Transfer

Control

Logic

Command

Source

Command

Signals

Command

Signals

Command

Destination

Data Path

Control

Logic

Data

Destination

N

M

Transmission

Media

ACK

STRB CSTRB

VLTN
DSTRB

Data

Signals

Am7968 Am7969

Figure 2. TAXIchip System Block Diagram

AMD

19Am7968/Am7969

Notes:

1. DMS = GND = 8 Bit Mode TLS = GND = Local Mode Pin 11 = Don’t Connect = Local Mode

2. DMS = V

CC

= 9 Bit Mode TLS = GND = Local Mode Pin 11 = Don’t Connect = Local Mode

3. Two 8-bit local mode systems in parallel will result in an effective data rate of 200 Mbps.

4. Use inverter for operation above 140 MHz only.
*Alternatively, the X1 inputs may be driven by external TTL frequency sources.

Figure 3. TAXIchip System in Local Mode

(Note 1)

SEROUT+
SEROUT–

STRB ACK

CLK

TAXI TX #1

TLS DMS

X1

X2

Message Transfer Control Logic

Data

Source

Command

Source

8

3.3 MHz to

17.5 MHz

8

3.3 MHz to

17.5 MHz

X1 X2 DMS CLOCK

SERIN+ SERIN–

CNB

DSTRB

IGM

VLTN

CSTRB

TAXI RX #1

4

DO0– DO7 CO0 – CO3

Data

Destination

Command

Destination

Data Path Control Logic

Message Transfer Control Logic

Command

Source

Data

Source

9 3

SEROUT+
SEROUT–

STRB ACK

CLK

TLS DMS

X1

X2

TAXI TX #2

To Other Stages

SERIN+ SERIN– X1

X2

DMS CLOCK

3.3 MHz to

17.5 MHz

IGM

VLTN

CNB

DSTRB

DO0 – DO8 CO0

– CO2

CSTRB

9

3

Data

Destination

Command

Destination

Data Path Control Logic

TAXI RX #2

4

*

(Note 4)

(Note 1)

(Note 2)

(Note 4)

*

*

07370F-12

DI0 – DI7 CI0 – CI3

DI0 – DI8 CI0 – CI2

AMD

20 Am7968/Am7969

SERIN– SERIN+ SERIN– SERIN+ SERIN– SERIN+

Crystal

OSC

RX1

Am7969

Primary RX

V

CC

CNB

CLK X2 X1

IGM

DMS

RX2

Am7969

IGM

DMS

RX3

Am7969

IGM

DMS

CNB CNB

X1 X1X2 X2

N/C

From Serial Media

07370F-13

Figure 4. Cascaded Receiver Clock Connections (Commercial –125 only)

AMD

21

Am7968/Am7969-125

Am7968/Am7969-125
ABSOLUTE MAXIMUM RATINGS

StorageTemperature –65°C to +150°C. . . . . . . . . . . .

Ambient Temperature

Under Bias –55°C to +125°C. . . . . . . . . . . . . . . . . . .

Supply Voltage to Ground

Potential Continuous –0.5 V to +7.0 V. . . . . . . . . . . .

DC Voltage Applied to
Outputs –0.5 V to V

CC

Max. . . . . . . . . . . . . . . . . . . . .

DC Input Voltage –0.5 V to +5.5 V. . . . . . . . . . . . . . .

DC Output Current ±100 mA. . . . . . . . . . . . . . . . . . .

DC Input Current –30 mA to +5.0 mA. . . . . . . . . . . . .

Stresses above those listed under Absolute Maximum Rat­ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi­mum ratings for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Temperature (T

A

)0°C to +70°C. . . . . . . . . . . . . . . . .

Supply Voltage (V

CC

) +4.5 V to +5.5 V. . . . . . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

AMD

22 Am7968/Am7969-125

DC CHARACTERISTICS over operating range unless otherwise specified
Am7968-125 TAXIchip Transmitter

Parameter

Symbol Parameter Description Test Conditions (Note 1) Min Max Unit

Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK

V

OH1

Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V
ACK V

IN

= 0 or 3 V

V

OH2

Output HIGH Voltage VCC = Min, IOH = –3 mA 2.4 V
CLK V

IN

= 0 or 3 V

V

OL

Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V
ACK, CLK V

IN

= 0 or 3 V

V

IH

Input HIGH Voltage VCC = Max (Note 9) 2.0 V

V

IL

Input LOW Voltage VCC = Max (Note 9) 0.8 V

V

I

Input Clamp Voltage VCC = Min IIN = –18 mA –1.5 V

I

IL

Input LOW Current VCC = Max, VIN = 0.4 V –400 µA

I

IH

Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA

I

I

Input Leakage Current VCC = Max, All Inputs 50 µA

V

IN

= 5.5 V Except CLK

CLK Input 150 µA

I

SC

Output Short Circuit (Note 4) –15 –85 mA
Current ACK, CLK

Serial Interface Signals: SEROUT+, SEROUT–

V

OH

Output HIGH Voltage VCC = Min ECL Load V

CC

V

CC

V

–1.025 –0.88

V

OL

Output LOW Voltage VCC = Min ECL Load V

CC

V

CC

V

–1.81 –1.62

Miscellaneous Signals: X1, V

CC1

, V

CC2

, V

CC3

V

IHX

Input HIGH Voltage X1 2.0 V

V

ILX

Input LOW Voltage X1 0.8 V

I

ILX

Input LOW Current X1 VIN = 0.45 V –900 µA

I

IHX

Input HIGH Current X1 VIN = 2.4 V +600 µA

I

CC

Supply Current SEROUT = ECL

Load, DMS = 0
V

CC1

= V

CC2

=

V

CC3

= Max

Pin V

CC1

(TTL) 20 mA

Pin V

CC2

(ECL) 45 mA

Pin V

CC3

(CML) 200 mA

*See notes following end of Switching Characteristics tables.

AMD

23

Am7968/Am7969-125

Am7969-125 TAXIchip Receiver

Parameter

Symbol Parameter Description Test Conditions (Note 1) Min Max Unit

Bus Interface Signals: DO0–DO7, DO8/CO3, DO9/CO2, CO0–CO1, DSTRB, CSTRB, IGM, CLK, CNB, VLTN

V

OH

Output HIGH Voltage VCC = Min, IOH = –1 mA 2.4 V

V

IN

= 0 or 3 V

V

OL

Output LOW Voltage VCC = Min, IOL = 8 mA 0.45 V

V

IN

= 0 or 3 V

V

IH

Input HIGH Voltage VCC = Max (Note 9) 2.0 V

V

IL

Input LOW Voltage VCC = Max (Note 9) 0.8 V

V

I

Input Clamp Voltage VCC = Min, IIN = –18 mA –1.5 V

I

IL

Input LOW Current VCC = Max, VIN = 0.4 V –400 µA

I

IH

Input HIGH Current VCC = Max, VIN = 2.7 V 50 µA

I

I

Input Leakage Current VCC = Max, VIN = 5.5 V 50 µA

I

SC

Output Short Circuit –15 –85 mA
Current (Note 4)

Serial Interface Signals: SERIN+, SERIN–

V

IHS

Input HIGH Voltage (Notes 9, 21) V

CC

V

CC

V

SERIN+ –1.165 –0.88

V

ILS

Input LOW Voltage (Notes 9, 21) V

CC

V

CC

V

SERIN+ –1.81 –1.475

V

THT

Test Mode Threshold VCC = Max 0.25 V
SERIN–

V

DIF

Differential Input Voltage 0.3 1.1 V

V

ICM

Input Common Mode (Note 6) 3.05 V

CC

V

Voltage –0.55

I

IL

Input LOW Current VCC = Max, VIN = VCC –1.81 V 0.5 µA

I

IH

Input HIGH Current VCC = Max, 220 µA

V

IN

= VCC –0.88 V

Miscellaneous Signals: X1, V

CC1

, V

CC2

V

IHX

Input HIGH Threshold X1 2.0 V

V

ILX

Input LOW Threshold X1 0.8 V

I

ILX

Input LOW Current X1 VIN = 0.45 V –900 µA

I

IHX

Input HIGH Current X1 VIN = 2.4 V +600 µA

I

CC

Supply Current V

CC1

= V

CC2

= Max Pin V

CC1

(TTL) 50 mA

DMS = 0 V Pin V

CC2

(CML) 300 mA

AMD

24 Am7968/Am7969-125

SWITCHING CHARACTERISTICS (Note 20)
Am7968-125 TAXIchip Transmitter (Notes 10, 13, 22)

Parameter

No. Symbol Parameter Description Test Conditions Min Max Units

Bus Interface Signals: DI0–DI7, DI8/CI3, DI9/CI2, CI0–CI1, STRB, ACK, CLK

1t

P

CLK Period 8n 25n ns

2t

PW

CLK Pulse Width HIGH 30 ns

3t

PW

CLK Pulse Width LOW 30 ns

4t

PW

STRB Pulse Width HIGH (Note 7) 15 ns

5t

PW

STRB Pulse Width LOW 15 ns

6t

BB

Internal Byte Boundary to CLK↓ 20 ns
(Note 11)

9t

S

Data–STRB Setup Time 5 ns

10 t

H

Data–STRB Hold Time 15 ns

11 t

H

ACK↑ to STRB↓ Hold (Note 8) TTL Output Load 0 ns

12 t

H

ACK↓ to STRB↑ Hold TTL Output Load 0 ns

13 t

PD

STRB↑ to ACK↑ (Note 18) TTL Output Load 40 ns

14 t

PD

STRB↓ to ACK↓ TTL Output Load 23 ns

15 t

PD

CLK↓ to ACK↑ (Note 18) TTL Output Load ns

Serial Interface Signals: SEROUT+, SEROUT– (Note 2)

22 t

SK

✝

SEROUT± Skew ECL Output Load –200 +200 ps

23 t

R

✝

SEROUT± Output Rise Time ECL Output Load .45 2 ns

24 t

F

✝

SEROUT± Output Fall Time ECL Output Load .45 2 ns

26 t

PW

✝

SEROUT ± Pulse Width LOW ECL Output Load ns

27 t

PW

✝

SEROUT ± Pulse Width HIGH ECL Output Load ns

Miscellaneous Signals: X1

(Note 15)

29 t

PW

X1 Pulse Width HIGH (Note 12) TTL Output Load on CLK 35 ns

30 t

PW

X1 Pulse Width LOW (Note 12) TTL Output Load on CLK 35 ns

32 t

PD

X1 ↑ to CLK↑ TTL Load 32 ns

33 t

PD

X1 ↓ to CLK↓ TTL Load 32 ns

3t1

n

+ 33

t1

n

– 5%

t1

n

+ 5%

t1

n

+ 5%

t1

n

– 5%

–9t1

8n

+9

AMD

25

Am7968/Am7969-125

Am7969-125 TAXIchip Receiver (Notes 13, 14, 22)

Parameter

No. Symbol Parameter Description Test Conditions Min Max Unit

Bus Interface Signals: DO0–DO7,DO8/CO3,DO9/CO2,CO0–CO1,DSTRB,CSTRB, IGM,CLK,CNB,VLTN

35 t

P

CLK Period (Note 24) 8n 25n ns

36 t

PD

Data Valid to STRB↑ Delay TTL Output Load ns

37 t

PD

CLK↓ to STRB↑ TTL Output Load ns

38 t

PD

CLK↑ to STRB↓ TTL Output Load ns

38a t

PD

STRB↑ to CLK↑ (Note 23) TTL Output Load ns

39 t

PD

CLK↓ to Data Valid Delay TTL Output Load ns

40 t

PW

STRB Pulse Width HIGH TTL Output Load ns

41 t

PW

CLK Pulse Width HIGH TTL Output Load ns

42 t

PW

CLK Pulse Width LOW TTL Output Load ns

43 t

PD

SERIN to CLK↓ Delay TTL Output Load ns

44 t

PD

CLK↑ to IGM↓ TTL Output Load ns

45 t

PD

CLK↑ to IGM↑ TTL Output Load ns

46 t

PD

CNB↓ to IGM↓ TTL Output Load 20 ns

47 t

S

CNB↑ to CLK↑ Setup Time ns
(Note 5)

47A t

S

CNB↓ to CLK↑ Setup Time ns
(Note 19)

48 t

H

CNB↓ to CLK↑ Hold ns

49 t

PW

CNB Pulse Width LOW ns

Serial Interface Signals: SERIN+, SERIN–

57 t

J

✝

SERIN± Peak to Peak Input Jitter 5 ns
Tolerance (Note 16)

Miscellaneous Signals: X1 (Note 15)

60 t

PW

X1 Pulse Width HIGH 35 ns

61 t

PW

X1 Pulse Width LOW 35 ns

2t

35

n

-

2t

35

n

2t

35

n

+15

t

35

n

–7

5t

35

2n

5t

35

n

–15

5t

35

n

–15

t

35

2n

+17

2t

35

n

+26

2t

35

n

+7

2t

35

n

+10

–32

t

35

n

–31

-

t

35

n

+

-

23

5t

35

n

2t

35

n

+5

2t

35

n

3t

35

n

–14

AMD

26 Am7968/Am7969-175

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