AMD Am55DL128C8G Service Manual

PRELIMINARY

Am55DL128C8G

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

T w o Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memories and 64 Mbit (4 M x 16-Bit) Fast Cycle RAM and 8 Mbit (512K x 16-Bit) Static RAM

DISTINCTIVE CHARACTERISTICS

MCP Features

■ Power supply voltage of 2.7 to 3.1 volt

■ High performance

— Access time as fast as 70 ns

■ Package

— 93-Ball FBGA

■ Op erating Temperature

— –40°C to +85°C

Flash Memory Features ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

— Zero latency between read and write operations

■ Flexible Bank architecture

— Read may occur in any of the three banks not being written

or erased.

— Four banks may be grouped by customer to achieve desi red

bank divisions.

■ Manufactured on 0.17 µm process technology

■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data

— Customer lockable: Sector is one-time pr ogrammable. Once

sector is locked, data cannot be changed.

■ Zero Power Operation

— Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

■ Boot sectors

— Top and bottom boot sectors in the same device

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply

flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function

■ Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode

■ Minimum 1 million erase cycles guaranteed per sector

■ 20 year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

■ Supports Common Flash Memory Interface (CFI)

■ Program/Erase Suspend/Erase Resume

— Suspends program/erase operations to allow

programming/erasing in same bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase cycle

completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state machine to

the read mode

■ WP#/ACC input pin

— Write protect (WP#) function protects sectors 0 , 1, 140, and

141, regardless of sector protect status

— Acceleration (ACC) function accelerates program timing

■ Sec tor protection

— Hardware method of locking a sector, either in-system or

using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

FCRAM Features

■ Pow er dissipation

— Operating: 25 mA maximum — Standby: 150 µA maximum — Deep power-down standby: 10 µA

■ CE1s# and CE2s Chip Select

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 2.7 to 3.1 volt

■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

SRAM Features

■ Pow er dissipation

— Operating: 30 mA maximum — Standby: 15µA maximum

■ CE1s# and CE2s Chip Select

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 1.5 to 3.1 volt

■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 26829 Rev: A Amendment/0 Issue Date: October 25, 2002

GENERAL DESCRIPTION

PRELIMINARY

Am29DL640G Features

The Am29DL640G is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 by tes of 8 bits each. Word mode data appears on DQ15 –DQ0; byte mo de dat a appears on D Q7–DQ0. The device is designed to be programmed in-system with the stand ard 3.0 volt V

supply, and can also be programmed in standard EPROM programmers.

The device is available with an access time of 70 or 85 ns and is offered in a 93-ball FBGA package. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control n ormal read and write operations, and avoid bus contention issues.

The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provi ded for the program and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the me mory space into four banks , t wo 8 Mb banks with small and large sectors, and two 24 M b banks of large s ectors only. Sector addresses are fixed, system software can be used to form user-defined bank groups.

During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and si multaneously re ad from the othe r bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

The Am29DL640 G can be organi zed as both a to p and bottom boot sector configuration.

Bank Megabits Sector Sizes

Bank 1 8 Mb Bank 2 24 Mb Forty-eight 64 Kbyte/32 Kword

Bank 3 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 4 8 Mb

The SecSi™ (Secured Silicon) Secto r is an extra 256 byte sec tor c apabl e of be ing pe rman ently lock ed by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, customer lockable parts can never be used to replace a factory locked part.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Factory locked parts pro vide several options. Th e SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Numb er), cust omer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as a one-time programmable area.

DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation o f the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands are written to the command

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically re turns to the read mode.

The sector erase archite cture allow s memo ry sectors to be erased and reprogrammed without affecting the data conten ts of oth er sec tors. Th e devi ce is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase operations in any com bination of the secto rs of memory. This can be achieved in-system or via programming equipment.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly r educed in both modes.

2 Am55DL128C8G October 25, 2002

PRELIMINARY

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memo r y Bl oc k Dia gram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . .10

FCRAM Power Down Program . . . . . . . . . . . . . . .12

Table 2. Basic Key Table ................................................................12

Table 3. Available Key Table ..........................................................12

Flash Device Bus Operations . . . . . . . . . . . . . . .13

Requirements for Reading Array Data ...................................13

Writing Commands/Command Sequences ............................ 13

Accelerated Program Operation .......................................... 13

Autoselect Functions ........................................................... 13

Simultaneous Read/Write Operations with Zero Latency ....... 13

Automatic Sleep Mode ...........................................................14

RESET#: Hardware Reset Pin ............................................... 14

Output Disable Mode ..............................................................14

Table 4. Am29DL640G Sector Architecture ....................................15

Table 5. Bank Address ....................................................................18

Table 6. SecSi Sector Addresses ...............................................18

Table 7. Am29DL640G Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................19

Write Protect (WP#) ................................................................ 19

Table 8. WP#/ACC Modes ..............................................................20

Temporary Sector Unprotect .................................................. 20

Figure 1. Temporary Sector Unprotect Operation........................... 20

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 22

Figure 3. SecSi Sector Protect Verify.............................................. 23

Hardware Data Protection ...................................................... 23

Low V

Write Pulse “Glitch” Protection ............................................23

Logical Inhibit ......................................................................23

Power-Up Write Inhibit ......................................................... 23

Common Flash Memory Interface (CFI) . . . . . . .23

Flash Command Definitions . . . . . . . . . . . . . . . . 27

Reading Array Data ................................................................ 27

Reset Command .....................................................................27

Autoselect Command Sequence ............................................27

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 27

Word Program Command Sequence ..................................... 28

Unlock Bypass Command Sequence .................................. 28

Figure 4. Program Operation .......................................................... 29

Chip Erase Command Sequence ...........................................29

Sector Erase Command Sequence ........................................ 29

Erase Suspend/Erase Resume Commands ........................... 30

Figure 5. Erase Operation............................................................... 30

Flash Write Operation Status . . . . . . . . . . . . . . . . 32

Figure 6. Data# Polling Algorithm ................................................... 32

DQ7: Data# Polling .................................................................32

DQ6: Toggle Bit I .................................................................... 33

Figure 7. Toggle Bit Algorithm......................................................... 33

DQ2: Toggle Bit II ................................................................... 34

Write Inhibit ...........................................................23

Reading Toggle Bits DQ6/DQ2 ............................................... 34

DQ5: Exceeded Timing Limits ................................................ 34

DQ3: Sector Erase Timer ....................................................... 34

Table 14. Write Operation Status ................................................... 35

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36

Figure 8. Maximum Negative Overshoot Waveform ...................... 36

Figure 9. Maximum Positive Overshoot Waveform........................ 36

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37

CMOS Compatible .................................................................. 37

Figure 10. I

Automatic Sleep Currents)............................................................. 40

Figure 11. Typical I

Current vs. Time (Showing Active and

CC1

vs. Frequency............................................ 40

CC1

MCP Test Conditions . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12. Test Setup.................................................................... 41

Figure 13. Input Waveforms and Measurement Levels ................. 41

MCP AC Characteristics . . . . . . . . . . . . . . . . . . . 42

CE#s Timing ........................................................................... 42

Figure 14. Timing Diagram for Alternating Between

SRAM to Flash or FCRAM............................................................. 42

Flash AC Characteristics . . . . . . . . . . . . . . . . . . 43

Flash Read-Only Operations ................................................. 43

Figure 15. Read Operation Timings ............................................... 43

Hardware Reset (RESET#) .................................................... 44

Figure 16. Reset Timings............................................................... 44

Erase and Program Operations ..............................................45

Figure 17. Program Operation Timings.......................................... 46

Figure 18. Accelerated Program Timing Diagram.......................... 46

Figure 19. Chip/Sector Erase Operation Timings .......................... 47

Figure 20. Back-to-back Read/Write Cycle Timings ...................... 48

Figure 21. Data# Polling Timings (During Embedded Algorithms) . 48

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 49

Figure 23. DQ2 vs. DQ6................................................................. 49

Temporary Sector Unprotect .................................................. 50

Figure 24. Temporary Sector Unprotect Timing Diagram .............. 50

Figure 25. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 51

Alternate CE#f Controlled Erase and Program Operations .... 52

Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 53

Read Cycle .............................................................................54

Figure 27. SRAM Read Cycle—Address Controlled...................... 54

Figure 28. SRAM Read Cycle........................................................ 55

Write Cycle ............................................................................. 56

Figure 29. SRAM Write Cycle—WE# Control................................ 56

Figure 30. SRAM Write Cycle—CE#1s Control ............................. 57

Figure 31. SRAM Write Cycle—UB#s and LB#s Control ............... 58

FCRAM AC CHaracteristics . . . . . . . . . . . . . . . . 59

Read Operation ......................................................................59

Write Operation ....................................................................... 60

Power Down and Power Down Program Parameters ............. 61

Other Timing Parameters ....................................................... 61

AC Test Conditions .................................................................62

Read Timing ...........................................................................62

Figure 32. OE# Control Access...................................................... 62

FCRAM AC Characteristics .................................................... 63

Figure 33. CE#1 Control Access.................................................... 63

Figure 34. Address after OE# Control Access ............................... 63

Figure 35. Address Access after CE#1 Control Access................. 64

Figure 36. CE#1 Control ................................................................ 64

October 25, 2002 Am55DL128C8G 3

PRELIMINARY

Figure 37. WE# Control Single Write Operation ............................. 65

Figure 38. WE# Control Continuous Write Operation ..................... 65

Figure 39. Read/Write Timing CE#1 Control,

Read Cycle First.............................................................................. 66

Figure 40. Read/Write Timing CE#1 Control,

Write Cycle First.............................................................................. 66

Figure 41. Read (OE# Control)/Write (WE# Control) Timing,

Read Cycle First.............................................................................. 67

Figure 42. Read (OE# Control)/Write (WE# Control) Timing,

Write Cycle First.............................................................................. 67

Figure 43. Power Down Program Timing........................................ 68

Figure 44. Power Down Program Timing........................................ 68

Figure 45. Power Down Entry and Exit Timing ............................... 68

Figure 46. Power Up Timing #1 ...................................................... 69

Figure 47. Power Up Timing #2 ...................................................... 69

Figure 48. Standby Entry Timing after Read or Write ..................... 69

FCRAM Data Retention . . . . . . . . . . . . . . . . . . . . 70

Low VDD Characteristics ........................................................ 70

Figure 49. Data Retention Timing.................................................. 70

Flash Erase And Programming Performance . . 71

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 71

BGA Package Pin Capacitance . . . . . . . . . . . . . . 71

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 72

Figure 50. CE#1s Controlled Data Retention Mode....................... 72

Figure 51. CE2s Controlled Data Retention Mode......................... 72

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 73

FNA093—93-Ball Fine-Pitch Grid Array 10 x 10 mm ............. 73

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 74

4 Am55DL128C8G October 25, 2002

PRELIMINARY

PRODUCT SELECTOR GUIDE

Part Number Am55DL128C8G

Speed Options

Standard Voltage Range: V

= 2.7–3.1 V

Flash Memory Pseudo SRAM

70 85 70 85

Max Access Time, ns 70 85 70 85 CE#f Access, ns 70 85 70 85 OE# Access, ns 30 40 40 40

MCP BLOCK DIAGRAM

RY/BY#1

DQ15 to DQ0

VCCf

A21 to A0

CE#f1

RESET #1

64 MBit

Flash Memory

VCCf

WP#/ACC

RESET#2

CE#f2

PE#

LB#s

UB#s

WE#

OE#

CE1#fc

CE2fc

CE1#s

CE2s

A21 to A0

A18 to A0

Flash Memory

VCCs/V

CCQ

Fast Cycle

64 MBit

RAM

8 MBit SRAM

VSS/V

RY/BY#2

DQ15 to DQ0

SSQ

DQ15 to DQ0

October 25, 2002 Am55DL128C8G 5

PRELIMINARY

FLASH MEMORY BLOCK DIAGRAM

OE# BYTE#

A21–A0

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ15–DQ0

A21–A0

Mux

RY/BY#

A21–A0A0–A21

STATE

CONTROL

& COMMAND REGISTER

Mux

Bank 1 Address

Bank 2 Address

Bank 3 Address

Bank 4 Address

Status

Control

Bank 1

X-Decoder

Bank 2

X-Decoder

Bank 3

X-Decoder

Bank 4

Y-gate

DQ15–DQ0

Mux

DQ15–DQ0

6 Am55DL128C8G October 25, 2002

CONNECTION DIAGRAM

PRELIMINARY

93-Ball FBGA

Top View

Flash 1 only

B2 B3 B7 B8

NC VSSRY/BY#2

C2 C9

NC NC

CE#f1

CE1#FC

NC NC

OE#

DQ0

DQ8

B4 B9

LB#s

UB#s

A18

A17

DQ1

DQ9

DQ10

DQ2

CE#f2

WP#/ACC

RESET#1

RY/BY#1

CE#1s NC

DQ3

DQ11

WE#

CE2FC

A20

CE2s

DQ4

NC NC

A19

A10

PE#FC

DQ6

DQ13

DQ12

DQ5

A11

A12

A13

A14

DQ15

DQ7

DQ14

A15

A21

A16

A10

B10

F10

Flash 2 only

FCRAM only

Flash 1 and 2 shared

Shared

FCRAM & SRAM Shared

2nd SRAM only

G10

L2 L3 L4 L5 L6 L7 L8 L9

NC RESET#2 V

VCCf

Special Package Handling Instructions

Special handling is required fo r Flash Memo ry products in m olde d pa ckage s (B GA). The package and/or

NC NC NC

data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

L10

M10

October 25, 2002 Am55DL128C8G 7

PRELIMINARY

PIN DESCRIPTION

A18–A0 = 19 Address Inputs (Common) A21–A19 = 2 Address Inputs (Flash + FCRAM) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash) CE#f2 = Chip Enable 2 (Flash) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY#1 = Ready/Busy Output 1 (Flash 1) RY/BY#2 = Ready/Busy Output 2 (Flash 2) UB#s = Upper Byte Control (FCRAM +

SRAM)

LB#s = Lower Byte Control (FCRAM +

SRAM)

RESET#1 = Hardware Reset Pin, Active Low

(Flash 1)

RESET#2 = Hardware Reset Pin, Active Low

(Flash 2)

WP#/ACC = Hardware Write Protect/

Acceleration Pin (Flash)

LOGIC SYMBOL

A18–A0

A21–A19 CE#f1 CE#f2 CE#1FC CE2FC

PE#FC

CE#1s CE2s OE#

WE# WP#/ACC

RESET#1 RESET#2 UB#s LB#s

16 or 8

DQ15–DQ0

RY/BY#

f = Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for speed options and voltage supply tolerances)

s = SRAM Power Supply

= Device Ground (Common) NC = Pin Not Connected Internally CE#1FC = Chip Enabled #1 (FCRAM) CE2FC = Chip Enable #2 (FCRAM) CE#1s = Chip Enable #1 (SRAM) CE2s = Chip Enable #2 (SRAM)

FC = FCRAM power supply

PE#FC = FCRAM power down enable

8 Am55DL128C8G October 25, 2002

PRELIMINARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am55DL128 C 8 G 70 L T

TAPE AND REEL

T=7 inches S = 13 inches

TEMPERATURE RANGE

L = Light Industrial (–30

SPEED OPTION

See “Product Selector Guide” on page 5

PROCESS TECHNOLOGY

G = 0.17 µm

SRAM Device Density

8 = 8 Mbits

FAST CYCLE RAM DEVICE DENSITY

C= 64 Mbits

°C to +85°C)

AMD DEVICE NUMBER/DESCRIPTION

Am55DL128C8G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) FastCycle RAM and 8 Mbit (512K x 16 bit) SRAM

Valid Combinations

Valid Comb inations list configurations planned to be supported in volume for this device . Consult the lo cal AMD sales office t o confirm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations

Order Number Package Marking

Am55DL128C8G70L T, S M550000000 Am55DL128C8G85L T, S M550000001

October 25, 2002 Am55DL128C8G 9

PRELIMINARY

MCP DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are in itiated through the internal command register. The command register itself does not occupy any addressabl e memory l ocation. The register is a latch used to store the commands, along with the ad dress and da ta information

needed to execute the command. The contents of the register serve as inputs to the intern al state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

10 Am55DL128C8G October 25, 2002

PRELIMINARY

Table 1. Device Bus Operations—Flash Word Mode, (Notes 1, 2, 3)

CE#f

Operation

Active

Notes

Read from Active Flash

Write to Active Flash

10 X L

10 X L Standby Deep Power-down

Standby Output

Disable Flash

Hardware Reset

Sector Protect

Sector Unprotect

Temporary Sector Unprotect

10 X L

7, 9,

7, 10,

7, 9,

7, 10,

10 X L

Read from SRAM H H L H H H H L H

Write to SRAM H H L H H H H X L

Read from FCRAM

Write to FCRAM

Power Down Program

CE#f

Inactive

CE#1s CE2s CE#1FC CE2FC PE#FC OE# WE# Addr. LB#s UB#s RESET#

(Note 3)

± 0.3 V

HHHLH

HHHHL

H H HXXXXX

NA NA X L X X X X X X

LHLHLHH

H H H X X X X X L L/H High-Z High-Z

HHHHL

H H HXXXXX

LHHLHA

XL LH

LHHHLA

XL LH

± 0.3 V

HHLXX

HH X X X HH X X X

SADD, A6 = L,

A1 = H,

A0 = L

SADD, A6 = H, A1 = H,

A0 = L

Key (12)

WP#/ACC

(Note 6)

XX H L/H

XX H 6

0.3 V V

0.3 V

DQ7–

DQ15–

DQ0

OUT

H High-Z High-Z

H L/H High-Z High-Z

L/H

LL HL High-Z

HX LH LL HL High-Z

LL HL High-Z

0.3 V

H High-Z High-Z

High-Z

OUT

High-Z

OUT

High-Z

OUT

High-Z

OUT

High-Z

OUT

DQ8

OUT

D D

OUT

IN IN

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, D

= Data In, D

= Data Out

OUT

Notes:

1. Other operations except for those indicated in this column are inhibited.

2. Do not apply CE#f1 or 2 = VIL, CE#1s = VIL and CE2s = VIH at the same time.

3. All operations assume FCRAM is in standby. To put in Power Down program PE must be Low. To put in Power Down CE2 must be Low.

4. Active flash is device being addressed.

5. Don’t care or open LB#s or UB#s.

6. If WP#/ACC = V = V

the boot sectors protection will be removed.

If WP#/ACC = V 40%.

, the boot sectors will be protected. If WP#/ACC

(9V), the program time will be reduced by

ACC

8. If WP#/ACC = V protected. If WP#/ACC = V protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V be unprotected.

9. Data will be retained in FCRAM.

10. Data will be lost in FCRAM.

11. CE# inputs on both flash devices may be held low for this operation.

12. See “Power Down Program Key Table” on p. 13

13. Valid for FCRAM only.

, the two outermost boot sectors remain

, the two outermost boot sector

all sectors will

HH,

7. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section.

October 25, 2002 Am55DL128C8G 11

PRELIMINARY

FCRAM POWER DOWN PROGRAM

Definition A0 A8 A21 A20

KEY Mode Select Area Select

Table 2. Basic Key Table

Mode

NAP L L X X X None

16M Partial

SLEEP H H X X X None

A0 A8 A18 A21 A20

Mode Select Area Select

H L L L L Bottom 16M only H L H H H Top 16M only

A18 A21 A20 AREA

L L

LLBOTTOM (2)

HXRESERVED

H L X RESERVED H H H TOP (3)

A0 A8 Mode

LLNAP (4)

LHRESERVED HL16M Partial H H SLEEP (4, 5)

Data Retention Area

Table 3. Available Key Tabl e

Notes:

1. The Power Down Program can be perfor med one t i me aft er co mpl i anc e of P ower-up timings and it should not be re-programm ed af ter re gul ar Read or Write. Unspecified addresses, A1 to A7, A9 to A17 and A19, can be either High or Low during the programming. The RESERVED key should not be used.

2. BOTTOM area is from the lowest address location.

3. TOP area is from the highest address location.

4. NAP and SLEEP do not retain the data and Area Select is ignored.

5. Default state. Power Down Program to this SLEEP mode can be omitted.

12 Am55DL128C8G October 25, 2002

PRELIMINARY

FLASH DEVICE BUS OPERATIONS Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE#f and OE# pins to V

. CE#f is the power

control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs durin g the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.

Refer to the Flash Read-Only Operations table for timing specifications and to Figure 15 for the timing diagram. I

in the DC Characteristics table represents

CC1

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V

For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Flash Device Bus Operations” for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquel y select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank.

, and OE# to VIH.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manu facturing throu ghput at the factory.

If the system asserts V

on this pin, the device auto-

matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protec ted sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle progra m command sequence as required by the Unlock Bypass mode. Removing

from the WP#/ACC p in returns th e device to nor-

mal operation. Note that V

must not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floa ting or unconnected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 19 for related information.

Autoselect Functions

If the system writes the autoselect command s equence, the device enters the autoselect mo de. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is c apable of r eading da ta from on e bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I

CC6

f and I

f in the table represent the cur-

CC7

rent specifications for read- while-program and read-while-erase, respectively.

Standby Mode

When the system is n ot reading or wri ting to the device, it can place the device in the standby mode. In this mode, current consum ption is greatly reduc ed, and the outputs are placed in the high impedance state, independent of the OE# input.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The Flash AC Characteristics section contains timing specification tables and timing diagrams for write operations.

The device enters the CMOS standby mode when the CE#f and R ESET # pins are bo th hel d at V

± 0.3 V.

(Note that this is a more restricted voltage range tha n

.) If CE#f and RESET# are h eld at VIH, but not

October 25, 2002 Am55DL128C8G 13

PRELIMINARY

within V

± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The device requires standard access time (t

) for read ac-

cess when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

f in the table represents the standby current spec-

CC3

ification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.

f in the table represents the automatic sleep mode

CC5

current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware me thod of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately term inates any operation in progress, tristates all output pins, and ignores all read/write command s for the duration o f the RESE T# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is

, the

ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby current (I held at V

but not within VSS±0.3 V, the standby cur-

±0.3 V, the device

f). If RESET# is

CC4

rent will be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is a sserted during a prog ram or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t Algorithms). The system can read data t RESET# pin returns to V

(not during Embedded

READY

after the

Refer to the MCP AC Character istics tables for RESET# parame ters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

14 Am55DL128C8G October 25, 2002

PRELIMINARY

Bank Sector

Bank 1

Table 4. Am29DL640G Sector Architecture

Sector Address

A21–A12

SA0 0000000000 8/4 00000h–00FFFh SA1 0000000001 8/4 01000h–01FFFh SA2 0000000010 8/4 02000h–02FFFh SA3 0000000011 8/4 03000h–03FFFh SA4 0000000100 8/4 04000h–04FFFh SA5 0000000101 8/4 05000h–05FFFh SA6 0000000110 8/4 06000h–06FFFh SA7 0000000111 8/4 07000h–07FFFh SA8 0000001xxx 64/32 08000h–0FFFFh

SA9 0000010xxx 64/32 10000h–17FFFh SA10 0000011xxx 64/32 18000h–1FFFFh SA11 0000100xxx 64/32 20000h–27FFFh SA12 0000101xxx 64/32 28000h–2FFFFh SA13 0000110xxx 64/32 30000h–37FFFh SA14 0000111xxx 64/32 38000h–3FFFFh SA15 0001000xxx 64/32 40000h–47FFFh SA16 0001001xxx 64/32 48000h–4FFFFh SA17 0001010xxx 64/32 50000h–57FFFh SA18 0001011xxx 64/32 58000h–5FFFFh SA19 0001100xxx 64/32 60000h–67FFFh SA20 0001101xxx 64/32 68000h–6FFFFh SA21 0001101xxx 64/32 70000h–77FFFh SA22 0001111xxx 64/32 78000h–7FFFFh

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

October 25, 2002 Am55DL128C8G 15

Bank Sector

SA23 0010000xxx 64/32 80000h–87FFFh SA24 0010001xxx 64/32 88000h–8FFFFh SA25 0010010xxx 64/32 90000h–97FFFh SA26 0010011xxx 64/32 98000h–9FFFFh SA27 0010100xxx 64/32 A0000h–A7FFFh SA28 0010101xxx 64/32 A8000h–AFFFFh SA29 0010110xxx 64/32 B0000h–B7FFFh SA30 0010111xxx 64/32 B8000h–BFFFFh SA31 0011000xxx 64/32 C0000h–C7FFFh SA32 0011001xxx 64/32 C8000h–CFFFFh SA33 0011010xxx 64/32 D0000h–D7FFFh SA34 0011011xxx 64/32 D8000h–DFFFFh SA35 0011000xxx 64/32 E0000h–E7FFFh SA36 0011101xxx 64/32 E8000h–EFFFFh SA37 0011110xxx 64/32 F0000h–F7FFFh SA38 0011111xxx 64/32 F8000h–FFFFFh SA39 0100000xxx 64/32 F9000h–107FFFh SA40 0100001xxx 64/32 108000h–10FFFFh SA41 0100010xxx 64/32 110000h–117FFFh SA42 0101011xxx 64/32 118000h–11FFFFh SA43 0100100xxx 64/32 120000h–127FFFh SA44 0100101xxx 64/32 128000h–12FFFFh SA45 0100110xxx 64/32 130000h–137FFFh

Bank 2

SA46 0100111xxx 64/32 138000h–13FFFFh SA47 0101000xxx 64/32 140000h–147FFFh SA48 0101001xxx 64/32 148000h–14FFFFh SA49 0101010xxx 64/32 150000h–157FFFh SA50 0101011xxx 64/32 158000h–15FFFFh SA51 0101100xxx 64/32 160000h–167FFFh SA52 0101101xxx 64/32 168000h–16FFFFh SA53 0101110xxx 64/32 170000h–177FFFh SA54 0101111xxx 64/32 178000h–17FFFFh SA55 0110000xxx 64/32 180000h–187FFFh SA56 0110001xxx 64/32 188000h–18FFFFh SA57 0110010xxx 64/32 190000h–197FFFh SA58 0110011xxx 64/32 198000h–19FFFFh SA59 0100100xxx 64/32 1A0000h–1A7FFFh SA60 0110101xxx 64/32 1A8000h–1AFFFFh SA61 0110110xxx 64/32 1B0000h–1B7FFFh SA62 0110111xxx 64/32 1B8000h–1BFFFFh SA63 0111000xxx 64/32 1C0000h–1C7FFFh SA64 0111001xxx 64/32 1C8000h–1CFFFFh SA65 0111010xxx 64/32 1D0000h–1D7FFFh SA66 0111011xxx 64/32 1D8000h–1DFFFFh SA67 0111100xxx 64/32 1E0000h–1E7FFFh SA68 0111101xxx 64/32 1E8000h–1EFFFFh SA69 0111110xxx 64/32 1F0000h–1F7FFFh SA70 0111111xxx 64/32 1F8000h–1FFFFFh

PRELIMINARY

Table 4. Am29DL640G Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

16 Am55DL128C8G October 25, 2002

Bank Sector

SA71 1000000xxx 64/32 200000h–207FFFh SA72 1000001xxx 64/32 208000h–20FFFFh SA73 1000010xxx 64/32 210000h–217FFFh SA74 1000011xxx 64/32 218000h–21FFFFh SA75 1000100xxx 64/32 220000h–227FFFh SA76 1000101xxx 64/32 228000h–22FFFFh SA77 1000110xxx 64/32 230000h–237FFFh SA78 1000111xxx 64/32 238000h–23FFFFh SA79 1001000xxx 64/32 240000h–247FFFh SA80 1001001xxx 64/32 248000h–24FFFFh SA81 1001010xxx 64/32 250000h–257FFFh SA82 1001011xxx 64/32 258000h–25FFFFh SA83 1001100xxx 64/32 260000h–267FFFh SA84 1001101xxx 64/32 268000h–26FFFFh SA85 1001110xxx 64/32 270000h–277FFFh SA86 1001111xxx 64/32 278000h–27FFFFh SA87 1010000xxx 64/32 280000h–28FFFFh SA88 1010001xxx 64/32 288000h–28FFFFh SA89 1010010xxx 64/32 290000h–297FFFh SA90 1010011xxx 64/32 298000h–29FFFFh SA91 1010100xxx 64/32 2A0000h–2A7FFFh SA92 1010101xxx 64/32 2A8000h–2AFFFFh SA93 1010110xxx 64/32 2B0000h–2B7FFFh

Bank 3

SA94 1010111xxx 64/32 2B8000h–2BFFFFh SA95 1011000xxx 64/32 2C0000h–2C7FFFh SA96 1011001xxx 64/32 2C8000h–2CFFFFh SA97 1011010xxx 64/32 2D0000h–2D7FFFh SA98 1011011xxx 64/32 2D8000h–2DFFFFh SA99 1011100xxx 64/32 2E0000h–2E7FFFh

SA100 1011101xxx 64/32 2E8000h–2EFFFFh SA101 1011110xxx 64/32 2F0000h–2FFFFFh SA102 1011111xxx 64/32 2F8000h–2FFFFFh SA103 1100000xxx 64/32 300000h–307FFFh SA104 1100001xxx 64/32 308000h–30FFFFh SA105 1100010xxx 64/32 310000h–317FFFh SA106 1100011xxx 64/32 318000h–31FFFFh SA107 1100100xxx 64/32 320000h–327FFFh SA108 1100101xxx 64/32 328000h–32FFFFh SA109 1100110xxx 64/32 330000h–337FFFh SA110 1100111xxx 64/32 338000h–33FFFFh SA111 1101000xxx 64/32 340000h–347FFFh SA112 1101001xxx 64/32 348000h–34FFFFh SA113 1101010xxx 64/32 350000h–357FFFh SA114 1101011xxx 64/32 358000h–35FFFFh SA115 1101100xxx 64/32 360000h–367FFFh SA116 1101101xxx 64/32 368000h–36FFFFh SA117 1101110xxx 64/32 370000h–377FFFh SA118 1101111xxx 64/32 378000h–37FFFFh

PRELIMINARY

Table 4. Am29DL640G Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

October 25, 2002 Am55DL128C8G 17

Bank Sector

SA119 1110000xxx 64/32 380000h–387FFFh SA120 1110001xxx 64/32 388000h–38FFFFh SA121 1110010xxx 64/32 390000h–397FFFh SA122 1110011xxx 64/32 398000h–39FFFFh SA123 1110100xxx 64/32 3A0000h–3A7FFFh SA124 1110101xxx 64/32 3A8000h–3AFFFFh SA125 1110110xxx 64/32 3B0000h–3B7FFFh SA126 1110111xxx 64/32 3B8000h–3BFFFFh SA127 1111000xxx 64/32 3C0000h–3C7FFFh SA128 1111001xxx 64/32 3C8000h–3CFFFFh SA129 1111010xxx 64/32 3D0000h–3D7FFFh

Bank 4

SA130 1111011xxx 64/32 3D8000h–3DFFFFh SA131 1111100xxx 64/32 3E0000h–3E7FFFh SA132 1111101xxx 64/32 3E8000h–3EFFFFh SA133 1111110xxx 64/32 3F0000h–3F7FFFh SA134 1111111000 8/4 3F8000h–3F8FFFh SA135 1111111001 8/4 3F9000h–3F9FFFh SA136 1111111010 8/4 3FA000h–3FAFFFh SA137 1111111011 8/4 3FB000h–3FBFFFh SA138 1111111100 8/4 3FC000h–3FCFFFh SA139 1111111101 8/4 3FD000h–3FDFFFh SA140 1111111110 8/4 3FE000h–3FEFFFh SA141 1111111111 8/4 3FF000h–3FFFFFh

PRELIMINARY

Table 4. Am29DL640G Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kbytes/Kwords)

(x16)

Address Range

Note:A21:A0 in word mode.

Bank A21–A19

1 000 2 001, 010, 011 3 100, 101, 110 4 111

Table 5. Bank Address

Table 6. SecSi Sector Addresses

Device Sector Size

Am29DL640G 256 bytes 00000h–0007Fh

(x16)

Address Range

18 Am55DL128C8G October 25, 2002

PRELIMINARY

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies to both sectors and s ector blocks. A sector block consists of two or more adjacent sectors that are protected or unpro tected at th e same time (see Table

7). The hardware sector protection feature disables both

program and erase operations in any sector. The hardware sector unprotection feature re-enabl es both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

Table 7. Am29DL640G Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector A21–A12

SA0 0000000000 8 Kbytes SA1 0000000001 8 Kbytes SA2 0000000010 8 Kbytes SA3 0000000011 8 Kbytes SA4 0000000100 8 Kbytes SA5 0000000101 8 Kbytes SA6 0000000110 8 Kbytes SA7 0000000111 8 Kbytes

SA8–SA10

SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes

SA27-SA30 00101XXXXX 256 (4x64) Kbytes

SA31-SA34 00110XXXXX 256 (4x64) Kbytes

SA35-SA38 00111XXXXX 256 (4x64) Kbytes

SA39-SA42 01000XXXXX 256 (4x64) Kbytes

SA43-SA46 01001XXXXX 256 (4x64) Kbytes

SA47-SA50 01010XXXXX 256 (4x64) Kbytes

SA51-SA54 01011XXXXX 256 (4x64) Kbytes SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes

0000001XXX, 0000010XXX, 0000011XXX,

Sector/

Sector Block Size

192 (3x64) Kbytes

Sector A21–A12

SA99–SA102 10111XXXXX 256 (4x64) Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes

SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes

SA131–SA133

SA134 1111111000 8 Kbytes SA135 1111111001 8 Kbytes SA136 1111111010 8 Kbytes SA137 1111111011 8 Kb ytes SA138 11111111 00 8 Kbytes SA139 11111111 01 8 Kbytes SA140 11111111 01 8 Kbytes SA141 1111111111 8 Kbytes

1111100XXX, 1111101XXX,

1111110XXX

Sector Protect/Sector Unprotect requires V

Sector/

Sector Block Size

192 (3x64) Kbytes

on the

RESET# pin only, and can be implemented either in-system or via programm ing equipment. Figure 2 shows the algorithms and Fi gure 25 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector un protect algo-

rithm unprotects all sectors in parallel . All previously protected sectors must be individually re-protected. To

change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector Unprotect”.

The device is shipped wi th all sectors unprotected. AMD offers the option of pro grammin g and protec ting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See the Sector/Sector Block Protection and Unprotection section for details.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting without using V one of two provided by the WP#/ACC pin.

If the system asserts V

on the WP#/ACC pin, the de-

vice disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”.

. This function is

October 25, 2002 Am55DL128C8G 19

PRELIMINARY

If the system asserts V

on the WP#/ACC pin, the de-

vice reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Table 8. WP#/ACC Modes

WP# Input

Voltage

Disables programming and erasing in SA0, SA1, SA140, and SA141

Enables programming and erasing in SA0, SA1, SA140, and SA141

Enables accelerated prog ram min g (ACC). See “Accelerated Program Operation” on page 13.

Device

Mode

Temporary Sector Unprotect

(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A secto r block consists of two or more adjacent sectors that are protected or unpro tected at th e same time (see Table

7). This feature al lows tempor ary unprotec tion of prev i-

ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased by selec ting the sector addresses. Once V SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 24 shows the timing diagrams , for this feature. If the WP#/ACC pin is at V 141 will remain protected during the Temporary sector Unprotect mode.

. During this mode, formerly protected

is removed from the RE-

, sectors 0, 1, 140, and

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Tem por ary Se ctor

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V sectors 0, 1, 140, and 141 will remain protected).

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

20 Am55DL128C8G October 25, 2002

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

October 25, 2002 Am55DL128C8G 21

PRELIMINARY

SecSi™ (Secured Silicon) Sector Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.

AMD offers the device with the SecSi Sector either factory locked or customer lockable. The factory-locked version is alw ays protected when shipped from the factory, and has the SecSi (S ecured Silicon ) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has th e SecSi (Se cured Sili con) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked.

The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of oper ation continues until th e system issues the Exit SecSi Sector command sequence, or until power is removed from the dev ice.

Note that the ACC function and unlock bypass modes are not availa ble when th e SecSi Se ctor is enab led.

On power-up, or following a hardware reset, the device reverts to sending comman ds to the first 256 bytes of Sector 0.

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode (or

000000h–00000Fh in byte mode). The secure ESN will be programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–000020h in byte mode). The device is available preprogrammed with one of the following:

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt to have their code pro grammed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the random ESN. The device s are then shippe d from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service.

Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector can be treated as an a dditional F lash mem ory spac e. The SecSi Sector can be read any number of times, but can be programme d and locked o nly once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector.

The SecSi Sector area ca n be protecte d using one of the following procedures:

■ Write the three-cycle Enter SecSi Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RE-

SET# may be at either V

in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector.

■ To v erify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array.

The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

or VID. This allows

22 Am55DL128C8G October 25, 2002

PRELIMINARY

START

RESET# =

or V

Wait 1 µs

Write 60h to any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data pro tection against inadvertent writes (refer to Table 13 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V and power-down transitions, or from system noise.

power-up

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE#f = VIH or WE# = VIH. To initiate a w rite cycle,

CE#f and WE# must be a logical zero while OE# is a logical one.

Power-Up Wri t e Inhibit

If WE# = CE#f = V

and OE# = VIH during powe r up,

the device does not accept commands on the rising edge of WE#. The internal s tate machine is automatically reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-comp atible for the spe cified flash dev ice families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9–12. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI qu ery mod e, and th e syste m can r ead CFI data at the addresses given in Tables 9–12. The system must write the reset command to return the device to reading array data.

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled,

For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.

and the device resets to the read mode. Subsequent writes are igno red unti l V

is greater than V

LKO

. The system must provide the proper signals to the control pins to prevent unintentional writes when V greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 n s (typical) on OE#, C E#f or WE# do not initiate a write cycle.

October 25, 2002 Am55DL128C8G 23

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