Am53C974A PCSCSI
Technical Manual
Revision 1.0
TM
II
A D V A N C E D M I C R O D E V I C E S
© 1994 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness
for a particular application. AMD
®
assumes no responsibility for the use of any circuitry other than the circuitry in an AMD product.
The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice.
AMD assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the
information included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.
Trademarks
AMD is a registered trademark of Advanced Micro Devices, Inc.
SCSI and GLITCH EATER are trademarks of Advanced Micro Devices, Inc.
PC
Microsoft is a registered trademark of Microsoft Corporation.
Windows NT Miniport is a trademark of Microsoft Corporation.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
TABLE OF CONTENTS
Chapter 1 General Information 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Hardware 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Fast SCSI Block 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1.1 Features 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1.1.1 Access FIFO Command 1-3. . . . . . . . . . . . . . . . . . .
1.2.1.1.2 Reduced Power Mode 1-3. . . . . . . . . . . . . . . . . . . .
1.2.1.1.3 Programmable GLITCH EATER Circuitry 1-3. . . . . .
1.2.1.1.4 Programmable Active Negation 1-4. . . . . . . . . . . . .
1.2.2 DMA Engine 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Software 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 AMD’s PC
Chapter 2 Signal Descriptions 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Logic Symbol 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Quick Reference Pin Descriptions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Signal Descriptions 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Address and Data Pins 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 PCI Interface Control Pins 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Arbitration Pins 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 System Pins 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 Error Reporting Pins 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.6 Interrupt Request Pins 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.7 SCSI Interface Signals 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.8 Power Management Signals 2-7. . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.9 Boot ROM Support Pins 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.10 Miscellaneous Signals 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.11 Power Supply Pins 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Connection Diagram Tables 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Listed by Pin Number 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Listed by Pin Name 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Pin Out Map 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 NAND Tree Testing 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Am53C974A Register Map 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCSI Software Solution 1-5. . . . . . . . . . . . . . . . . . . . . .
Chapter 3 Power Management Features 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 SCSI Activity Indicators 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Reduced Power Mode 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Power Down Pin (PWDN Pin) 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Software Disk Spin-Down 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
iii
AMD
Chapter 4 The PCI Bus Interface Unit 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Introduction 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Addressing 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Bus Acquisition 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Bus Cycle Definition 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Bus Cycle Diagrams 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Slave I/O Read 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Slave I/O Write 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 Master Memory Read 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4 Slave Memory Read 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.5 Master Memory Write 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.6 Slave Configuration Read 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7 Slave Configuration Write 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.8 Master Memory Read Line 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Transaction Termination 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 Target Initiated Termination 4-11. . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1.1 Disconnect With Data Transfer 4-11. . . . . . . . . . . . . . . .
4.6.1.2 Disconnect Without Data Transfer 4-12. . . . . . . . . . . . . .
4.6.1.3 Target Abort 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 Master Initiated Termination 4-14. . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2.1 Preemption 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2.2 Master Abort 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Configuration Registers 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Predefined Header Register Description 4-17. . . . . . . . . . . . . . . . .
4.7.1.1 Vendor ID Register 4-17. . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.2 Device ID Register 4-17. . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.3 Command Register 4-17. . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.4 Status Register 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.5 Revision ID Register 4-20. . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.6 Programming Interface Register 4-20. . . . . . . . . . . . . . .
4.7.1.7 Sub-Class Register 4-20. . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.8 Base Class Register 4-20. . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.9 Latency Timer Register 4-20. . . . . . . . . . . . . . . . . . . . . .
4.7.1.10 Header Type Register 4-21. . . . . . . . . . . . . . . . . . . . . . .
4.7.1.11 Base Address Register 4-21. . . . . . . . . . . . . . . . . . . . . .
4.7.1.12 Expansion ROM Base Address Register 4-22. . . . . . . . .
4.7.1.13 Interrupt Line Register 4-23. . . . . . . . . . . . . . . . . . . . . . .
4.7.1.14 Interrupt Pin Register 4-23. . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.15 Min_Gnt Register 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1.16 Max_Lat Register 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Device Dependent Register Description 4-24. . . . . . . . . . . . . . . . .
4.7.3 AMD’s Scratch Register Usage 4-24. . . . . . . . . . . . . . . . . . . . . . . .
4.7.3.1 Target Device Configuration Register Definition 4-24. . .
4.7.3.2 Host Configuration Register Definition 4-26. . . . . . . . . . .
iv
Table of Contents
AMD
Chapter 5 The FAST SCSI Block 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Functional Overview 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Part-Unique ID 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 SCSI FIFO Threshold 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Data Transmission 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 REQ/ACK Control 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5 Parity 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5.1 Parity from the SCSI Bus 5-3. . . . . . . . . . . . . . . . . . . . .
5.1.6 Reset Levels 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6.1 Hard Resets: (H) 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6.2 Soft Reset: (S) 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6.3 Disconnected Reset: (D) 5-5. . . . . . . . . . . . . . . . . . . . .
5.2 Register Description 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Register Bit Map: Read 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Register Bit Map: Write 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 Register Descriptions 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.1 Current Transfer Count Register 5-9. . . . . . . . . . . . . . .
5.2.3.2 Start Transfer Count Register 5-10. . . . . . . . . . . . . . . . .
5.2.3.3 SCSI FIFO Register 5-10. . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.4 SCSI Command Register 5-11. . . . . . . . . . . . . . . . . . . .
5.2.3.5 SCSI Status Register 5-12. . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.6 SCSI Destination ID Register 5-14. . . . . . . . . . . . . . . . .
5.2.3.7 Interrupt Status Register 5-14. . . . . . . . . . . . . . . . . . . . .
5.2.3.8 SCSI Timeout Register 5-15. . . . . . . . . . . . . . . . . . . . . .
5.2.3.9 Internal State Register 5-16. . . . . . . . . . . . . . . . . . . . . . .
5.2.3.10 Synchronous Transfer Period Register 5-20. . . . . . . . . .
5.2.3.11 Current FIFO/Internal State Register 5-22. . . . . . . . . . . .
5.2.3.12 Synchronous Offset Register 5-23. . . . . . . . . . . . . . . . . .
5.2.3.13 Control Register One 5-24. . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.14 Clock Factor Register 5-25. . . . . . . . . . . . . . . . . . . . . . .
5.2.3.15 Reserved 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.16 Control Register Two 5-26. . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.17 Control Register Three 5-27. . . . . . . . . . . . . . . . . . . . . .
5.2.3.18 Control Register Four 5-28. . . . . . . . . . . . . . . . . . . . . . .
5.2.3.19 Reserved 5-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3.20 Part-Unique ID Register 5-29. . . . . . . . . . . . . . . . . . . . . .
5.3 Device Commands 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Command Stacking 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Invalid Commands 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Command Window 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Initiator Commands 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4.1 Information Transfer Command 5-33. . . . . . . . . . . . . . . .
5.3.4.2 Initiator Command Complete Steps 5-34. . . . . . . . . . . . .
5.3.4.3 Message Accepted Command 5-34. . . . . . . . . . . . . . . . .
5.3.4.4 Transfer Pad Bytes Command 5-34. . . . . . . . . . . . . . . . .
5.3.4.5 Set ATN Command 5-35. . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4.6 Reset ATN Command 5-35. . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Target Commands 5-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5.1 Send Message Command 5-36. . . . . . . . . . . . . . . . . . . .
5.3.5.2 Send Status Command 5-36. . . . . . . . . . . . . . . . . . . . . .
5.3.5.3 Send Data Command 5-36. . . . . . . . . . . . . . . . . . . . . . .
5.3.5.4 Disconnect Steps Command 5-36. . . . . . . . . . . . . . . . . .
5.3.5.5 Terminate Steps Command 5-36. . . . . . . . . . . . . . . . . . .
5.3.5.6 Target Command Complete Steps Command 5-37. . . . .
5.3.5.7 Disconnect Command 5-37. . . . . . . . . . . . . . . . . . . . . .
5.3.5.8 Receive Message Steps Command 5-37. . . . . . . . . . . . .
5.3.5.9 Receive Commands Command 5-37. . . . . . . . . . . . . . . .
Table of Contents
v
AMD
5.3.5.10 Receive Data Command 5-37. . . . . . . . . . . . . . . . . . . . .
5.3.5.11 Receive Command Steps Command 5-38. . . . . . . . . . . .
5.3.5.12 DMA Stop Command 5-38. . . . . . . . . . . . . . . . . . . . . . . .
5.3.5.13 Access FIFO Command 5-39. . . . . . . . . . . . . . . . . . . . .
5.3.6 Idle State Commands 5-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6.1 Reselect Steps Command 5-39. . . . . . . . . . . . . . . . . . .
5.3.6.2 Select without ATN Steps Command 5-40. . . . . . . . . . . .
5.3.6.3 Select with ATN Steps Command 5-40. . . . . . . . . . . . .
5.3.6.4 Select with ATN and Stop Steps Command 5-40. . . . . .
5.3.6.5 Enable Selection/Reselection Command 5-40. . . . . . . .
5.3.6.6 Disable Selection/Reselection Command 5-40. . . . . . . .
5.3.6.7 Select with ATN3 Steps Command 5-41. . . . . . . . . . . . .
5.3.6.8 Reselect with ATN3 Steps Command 5-41. . . . . . . . . . .
5.3.7 General Commands 5-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7.1 No Operation Command 5-42. . . . . . . . . . . . . . . . . . . . .
5.3.7.2 Clear FIFO Command 5-42. . . . . . . . . . . . . . . . . . . . . .
5.3.7.3 Reset Device Command 5-42. . . . . . . . . . . . . . . . . . . . .
5.3.7.4 Reset SCSI Bus Command 5-42. . . . . . . . . . . . . . . . . .
Chapter 6 DMA Engine 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Introduction 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Data Path Unit 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 DMA FIFO 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 DMA Blast Command 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Funneling Logic 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 SCSI DMA Programming Sequence 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 MDL Based DMA Programming 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 DMA Registers 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 Command Register 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2 Starting Transfer Count 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.3 Starting Physical Address 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.4 Working Byte Counter 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.5 Working Address Counter 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.6 Status Register 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.7 Starting Memory Descriptor List Address (SMDLA) 6-10. . . . . . . .
6.7.8 Working MDL Address Counter (WMAC) 6-10. . . . . . . . . . . . . . . .
6.7.9 SCSI Bus and Control (SBAC) 6-11. . . . . . . . . . . . . . . . . . . . . . . .
6.8 DMA Scatter-Gather Mechanism 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.1 Memory Descriptor List (MDL) 6-14. . . . . . . . . . . . . . . . . . . . . . . .
6.8.2 DMA Scatter – Gather Operation (4k aligned elements) 6-14. . . . .
6.8.3 DMA Scatter – Gather Operation
(Non-4k aligned elements MDL not set) 6-17. . . . . . . . . . . . . . . . .
6.9 Interrupts 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Chapter 7 Expansion ROM Support 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Introduction 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 ROM Base Address Register 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Sample Implementation 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 ROM Access Cycle 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Expansion ROM Mapping 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
AMD
Chapter 8 SCAM Tutorial 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Introduction 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Requirements 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 SCAM Terminology 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 Normal SCSI and SCAM Selections 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1 Normal SCSI Selection 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.2 Level 1 SCAM Selection 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 SCAM Protocol 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5.1 SCAM Master Device Operation 8-5. . . . . . . . . . . . . . . . . . . . . . .
8.5.2 SCAM Slave Device Operation 8-6. . . . . . . . . . . . . . . . . . . . . . . .
8.6 SCAM Examples 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7 ID Assignment 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7.1 Protocol Initialization 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7.2 Function Codes 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7.3 Identification String 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7.4 Assigning IDs 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7.5 Default ID and ID Assignment 8-15. . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 9 Design Considerations for Motherboards and Adapter Cards 9-1. . . . . . . . .
9.1 Introduction 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Signal Routing and SCSI Placement 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1 The Motherboard 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1.1 Layout #1 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.1.2 Layout #2 9-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2 The Adapter Card 9-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Noise Considerations 9-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.1 Electromagnetic Interference (EMI) 9-6. . . . . . . . . . . . . . . . . . . . .
9.3.2 Decoupling Methods 9-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Termination Considerations 9-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1 Termination 9-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.1 Scheme #1 9-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.2 Scheme #2 9-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.3 Scheme #3 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Other Considerations 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 10 AMD’s PC
SCSI Software 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 Introduction 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 PC
SCSI Software Architecture 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Operating System Support 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.1 DOS 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Netware 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.3 OS/2 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.4 Windows 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.5 Windows NT 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.6 SCO UNIX 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.7 SCSI ROM BIOS 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4 Peripheral Support 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A Am53C974A Literature/Tool Support A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents
vii
AMD
viii
Table of Contents
SCSI TECHNOLOGY OVERVIEW
INTRODUCTION
This chapter is included in the technical specification for the PCI family of AMD SCSI
solutions because of the nature of these devices. Each SCSI chip is effectively a
complete solution for integrating SCSI on a PCI adapter card or onto the motherboard of
a PCI based system. All of the logic required for a SCSI port is included in the PCI SCSI
device. Because AMD also furnishes the software solution for PC operating systems,
users are (for the first time) looking at SCSI as a standard I/O solution, but may have
little experience in the basics of the standard. This introduction will provide a basic
understanding of the relevant information so that users can quickly integrate and use the
SCSI interface.
Before the SCSI standard was defined, in the 1979 time frame, the typical introduction
of new peripheral technology required 18 to 24 months. The tasks consisted of:
1. Designing a disk controller board
2. Designing a host adapter board
3. Changing system software to accommodate new device characteristics
4. Testing the new configuration
Disk drive manufacturers were faced with a delay that severely impacted business.
If disk development required 18 months, and integration took another 18 months, the
total time to revenue was three years. Clearly, this technology bottleneck caused
problems for the disk industry. Consequently, vendors began to define logical interfaces
that could survive beyond each model, and allow integrators to preserve the majority of
their development investment. SCSI was one of these definitions that survived. Originally defined by Shugart Associates, SASI (Shugart Associates Systems Interface) was
offered as a public document by Shugart in hopes that other system vendors would use
it and establish it as a defacto standard. Within a short time, an ANSI standards group
was formed, the name was changed to Small Computer Systems Interface, and the
standardization efforts began.
With support from peripheral vendors, the document defined a logical interface to a wide
variety of peripherals. This interface would allow system vendors to attach peripherals
easily and quickly to new systems, in order to meet a fast moving market window. The
standard defined a physical level (mechanical and electrical) as well as a logical level
(commands and messages). The actual command passing protocol and the set of
peripheral command sets were defined by the standard. Using logical addressing
mechanisms, rather than physical addressing (sector 347 vs. cylinder 13, head 2,
sector 3), the standard allowed the physical details of the peripheral to be hidden from
the system software. Therefore, after the standard was defined, a typical integration
cycle was reduced to three months, and consisted of:
1. Replacing the current SCSI disk with a new model
2. Testing the new configuration for compliance
Am53C974A PCSCSI II Technical Manual
ix
AMD
The process was complicated because new peripherals offered features that were
enabled through the system software, and because vendors did not offer devices that
were compatible with other vendors. But in general, the process was much simpler and
faster than before.
Since 1979, the SCSI standard passed through several key stages as it matured into
today’s standard. These stages are:
SASI (1979 – 1982) — This was a DTC/Shugart collaboration that was a controller
board shipped with Shugart drives. Although limited in function, it highlighted the
advantages of a high level logical interface for disk drives.
SCSI-1 (1982 – 1986) — A group of companies (Shugart, Adaptec, NCR, & OMTI)
banded together and approached ANSI for permission to develop a SCSI standard.
The effort generated industry wide interest and was quickly written because of the
participants’ common interest (i.e. everyone desired quick time to market for their
products). The ANSI specification (X3.131–1986) won final approval in May of 1986.
CCS (1985 – 1986) — Upon finalization of the SCSI-1 specification, the participants
barely had time to congratulate each other before the weakness of the document
began to emerge. The number of options allowed vendors were to develop disks that
worked fine, but which were not compatible with each other. Thus system vendors
could not easily integrate disk drives from all vendors into their system. So, disk
vendors met to define an extended subset of SCSI that would (if followed closely)
permit vendors to produce compatible disk products. This document (Common Command Set) became a defacto standard and allowed further standardization of the
SCSI market.
SCSI-2 (1986 – 199X) — As soon as the CCS specification was written, the complete
SCSI community realized the benefit of these extensions and restarted the SCSI
effort to bring the benefits of CCS into the complete SCSI standard document. The
original goal was to quickly fold CCS into the disk section and expand other command sets to include CCS features. Unfortunately, the door of improvement, once
open, allowed a flood of improvements to come in. Updates were cut off by 1990 and
the specification has been finalized as of August 1990.
SCSI-3 (1990 – 199X) — The stated goal of the first two SCSI specifications was
downward compatibility, but with SCSI-3, backward compatibility was sacrificed. The
goal was to define a protocol that accommodated the new serial interfaces and
solved some of the problems of the parallel interface. The result is a family of documents being written for SCSI-3.
Basic SCSI
The standard SCSI parallel bus allows connection for 8 or 16 devices (computers or
peripherals). Each has a unique identifier that allows selection and communication
between any two devices on the SCSI bus. An Initiator is an entity on the bus that issues
a command to a Target. Note that any device on the bus, peripheral or computer
system, can initiate a command sequence. The Initiator arbitrates for and wins the SCSI
bus, selects the desired Target, and sends a command to that Target. At this point, the
Target controls the bus and directs the remainder of the command sequence. The
Initiator can always regain control by use of the attention line that signals the Target that
something is coming. But in general, the Target remains in control.
There are nine control signals on the SCSI bus that allow the complete handshake to
happen. Target or Initiator controls the Bus depending on the phase of the command
sequence. There are 8, 16, or 32 data lines with each 8 bit set having a parity line.
The data width can be negotiated for, with 8 being the default, and 16 or 32 being
x
Am53C974A PCSCSI II Technical Manual
AMD
options. Sixteen-bit SCSI devices are available but are not in widespread use, while
32-bit devices are not yet available. There is considerable inertia resisting going beyond
8-bit cables because of the physical sizes involved. There is a Fast SCSI option that
allows SCSI to transfer data at 10 mega transfers per second, thus allowing 10 MB/sec
on 8-bit cables. This configuration is the clear winner in today’s market, because it
allows faster transfers with no change in the physical environment. Single ended SCSI
is by far the most popular implementation and the specification allows 6 meter cables in
this environment. Fast SCSI is not defined for single-ended cables, however, vendors
are providing silicon that will allow data to be transferred at the higher speeds.
The SCSI protocol defines the phases required to complete a SCSI I/O. The Message
phase allows short transfers of protocol related information to be sent across the bus to
establish and control the logical connection between an Initiator and a Target. The
Command phase allows the Initiator to tell the Target what action must be performed.
Read, write, rewind, etc. are all SCSI commands. User data is transferred during the
Data phase, allowing the data to be sent into or out from the Initiator. This data can be
written to the media, or it can be control information that is used to communicate
operating modes or sensed information to(from) the peripheral. Status information (one
byte only) is sent to the Initiator from the Target at the end of the complete SCSI
command sequence. If an error occurred, the Initiator must request the details of the
problem with a subsequent SCSI command.
The basic SCSI command sequence follows:
Bus is free and any device is allowed to arbitrate for ownership
An Initiator arbitrates for the bus and selects a Target device
The Target, after sensing selection, goes to Message Out phase and receives a one
byte ID message from the Initiator that establishes which physical device the Initiator
wants to communicate with
After switching to Command phase, the Target receives the SCSI command.
Changing to the appropriate Data phase (in/out) the Target handshakes the data
across the bus
A single status byte is sent to the Initiator
A command complete message is sent to the Initiator to signal completion of the
SCSI I/O
The Target then physically disconnects from the SCSI bus, and it is free for the next
device to use
Any time after the ID message is sent, the Target controls the sequence and directs the
Initiator’s next step. The Target is allowed to disconnect, temporarily get off the bus and
reselect later. In this manner, data can be multiplexed from various peripherals to the
host computer, in support of overlapped physical actions at the peripheral and multithreaded I/O in the operating system.
SCSI-1 provided the basic protocol functionality that supported the original goals of
device connectability, allowing 8 bit buses and a limited protocol flexibility. As noted
above, the plug and play aspects of the specification were not quickly realized because
of the large set of options. The CCS specification defined the extended subset of the
SCSI-1 document that allowed multiple disk vendors to work in one system environment
without compatibility issues in the host software. The main SCSI-2 features were:
Compatibility –– There must be an evolutionary growth, and mixed environments
were permitted. Requirements in SCSI-2 were popular options in SCSI-1.
Am53C974A PCSCSI II Technical Manual
xi
AMD
High Performance –– The original 5 MB/sec limit was pushed to 40 MB/sec using a
combination of 32-bit buses and 10 Mega transfers per second. The maximum cable
limits were still set at 6 (single ended) and 25 (differential) meters. Eight devices were
allowed on the bus, but a working paper described how sixteen devices could be
attached.
Hardware Requirements –– Parity on the bus is required for data integrity, and dis-
connect/reconnect is required for multiplexing the SCSI bus. SCSI-1 had no requirement for messages (all were optional) because of compatibility with SASI, but SCSI-2
required certain messages to make SCSI more usable in a complex systems
environment.
Logical interface improvements –– A group of features were defined to generally
improve SCSI. Features included were queueing of 256 commands at the peripheral,
more detailed definition for all control data used to change device characteristics
(or report information about the device), cache support for direct access devices, and
tape partition support.
New Command Sets –– New device command sets were for scanners, optical
memory devices, medium changers, and communication devices.
These changes dramatically increased the size of the SCSI-2 specification, and moved
the definition into a more high performance system environment.
SCSI-3 has given SCSI a totally new set of capabilities. The basic desire was to
increase the functionality to cover all the physical interfaces and allow the architecture to
be extended to the future requirements with few restrictions for compatibility. The
standard was divided into multiple documents to ease the pain of an editor. There are
four transport layers:
Standard parallel interface for 8- and 16-bit cables
Fiber channel for 100 MB/sec, full duplex transfers
Serial Storage Architecture in support of high performance (20 MB/sec) disks
P1394 allows 400 Mb/sec isochronous transfers
Five protocols:
Interlocked
Fiber channel
SSA
Serial bus
Generic packetized
Five command sets:
Primary
Block
Stream
Graphics
Medium Changer
xii
The target release date for these set of documents is 1994, but if the past is any
indication, SCSI-3 will require many years of work before being ready for official release.
The delay will not stop products from emerging however, because products with the new
interfaces and features are already appearing in the marketplace.
Am53C974A PCSCSI II Technical Manual
AMD
Before SCSI could penetrate the PC market, a critical piece of technology was required:
I/O software drivers to support the SCSI capabilities in the PC operating system
environments. As the first vendors introduced host adapter boards that connected SCSI
devices to the PC, the user quickly learned the importance of software. Consider the
following scenario:
User buys a SCSI disk with host adapter
A tape drive is required to back up the disk
User buys a tape drive
The tape can be connected, but there is no software to drive the device
User buys a host adapter to drive the tape
The tape works now, but there is no software to move data to/from the disk
Point solutions became available, but general solutions were not available until 1991.
Although the hardware was available and certain systems vendors were able to make
SCSI work, there was no guarantee that a user could find an off-the-shelf solution for the
DOS/Windows environment. Host adapter companies quickly began to offer limited
software capabilities that allowed several devices to be used in the PC.
Several defacto interfaces were available and in the interest of standardization, a
Common Access Method (CAM) committee was formed to standardize access to the
SCSI interface for each PC operating system environment. Unfortunately, once software
was running, users were reluctant to change. Therefore, the CAM specification,
although technically sound, has never been widely accepted as a standard. The
Advanced SCSI Programming Interface (ASPI) instead became a defacto standard
interface for I/O application software such as CD-ROM and tape backup utilities.
Consequently, ASPI seems to be entrenched as the interface of choice for DOS/
Windows.
However, more sophisticated operating systems already have a logical I/O interface
defined and do not share the same limitations as DOS. As the new operating systems
become more widely used in PCs and DOS I/O gradually becomes buried in an
emulation mode, the critical driver issues for the PC will disappear. Until then (as Yogi
Berra says, “Tomorrow isn’t here yet”), highly integrated SCSI chips must be supplied
with SCSI I/O drivers for the operating systems that execute on a PC. The drivers must
be architected carefully so as to require minimal change when the SCSI device
changes. Known as a two layer software interface, a good architecture will isolate
changes in the operating system from changes in the SCSI interface. Software technology like this allows SCSI to be commonly available in the PC environment.
Another key element in the I/O performance saga is the availability of bus mastering in
the PC environment. Rather inexpensive 32 bit bus mastering SCSI chips with FIFO’s in
the chip have taken high performance I/O to new levels. The combination of bus
mastering on the chip, extremely high performance system processors and increasing
levels of silicon integration have combined recently to result in high performance low
cost solutions in a single chip.
Performance that was once only available as a host adapter board (with a separate
processor, SCSI chip, RAM, and system interface) is now achieved using a single chip.
System processors offer a level of MIPS on the motherboard that can easily support I/O
silicon on the motherboard, thus simplifying the SCSI port dramatically. This new level of
cost effective silicon, combined with a complete software solution will no doubt enable
SCSI in a new environment and drive the industry to another level of capability.
Am53C974A PCSCSI II Technical Manual
xiii
AMD
xiv
Am53C974A PCSCSI II Technical Manual
GENERAL INFORMATION
1
1.1 INTRODUCTION
The Am53C974A from Advanced Micro Devices was developed in response to the PC
industry’s need for a hardware solution which harnessed the speed and flexibility of high
bandwidth local and I/O buses. Combining the performance of the PCI local bus with the
intelligence of the SCSI I/O bus, Advanced Micro Devices offers this Bus Mastering
SCSI Controller for PCI systems. The Am53C974A is one member of a family of AMD’s
plug compatible PCI products which share a common software solution. These products
are compliant with PCI specification rev 2.0; the Am53C974A also complies with ANSI
standards X3.131–1986 (SCSI-1) and X3.131–199X (SCSI-2).
The Am53C974A offers a glueless interface to the PCI Bus, making it an ideal choice for
motherboard as well as adapter card designs. The on-chip state machine which controls
SCSI sequences in hardware is coupled with a bus-mastering DMA engine to eliminate
the need for an additional RISC processor. The result is a PCI-SCSI controller with a
superior price/performance advantage. Furthermore, AMD’s value-added proposition for
the Am53C974A offering is a complete, licensable solution to minimize your time to
market.
Distinctive Features:
PCI Bus Interface Unit
PCI specification rev 2.0 compliant interface
32-bit address/data bus master DMA Host interface
Glueless interface to 33 MHz 32-bit PCI Bus
96-byte DMA FIFO for low bus latency
SCSI Controller Features
Single chip PCI to SCSI interface
Boot ROM support
Level 1 SCAM support
SCSI-2 compliant, 8-bit Fast SCSI interface
Supports single-ended SCSI bus
48 mA SCSI drivers
Performance
10 MByte/s synchronous and 7 MByte/s asynchronous transfer rates on the SCSI bus
132 MByte/s burst DMA transfer rate
Supports Scatter-Gather data transfers
Power Management
Sleep mode capability for Fast SCSI block –– Power down for SCSI receivers
General Information
1-1
AMD
SCSI activity monitoring pin and status bit
Fully static design for low frequency operation
SCSI clock disconnect capability
SCSI Bus Reliability
AMD’s patented Programmable GLITCH EATER Circuitry on REQ and ACK inputs
Programmable Active Negation on REQ, ACK and data lines
Other Features
132-pin PQFP
Uses state of the art advanced CMOS technology
The Am53C974A hardware solution is complemented by an extensive software package
for all major operating systems. The software solution incorporates AMD’s portable
SCSI software which is based in part on the Microsoft
1.2 HARDWARE
The Am53C974A is a high performance PCI local bus-SCSI controller. It is comprised of
the PCI Bus Interface Unit (BIU), a Fast SCSI block, and a bus master DMA engine. The
PCI BIU consists of configuration space and a PCI master/slave interface as defined in
rev 2.0 of the PCI specification. Figure 1-1 shows the basic interface block diagram of
the Am53C974A.
Windows NT Miniport model.
Figure 1-1 PCI-DMA-SCSI Interface Block Diagram
Fast SCSI Block
Data
CNTL
DMA
Engine
Data
CNTL
DREQ
DACK
PCI^REQ
PCI^GNT
PCI Bus Interface Unit
ADDR
CNTL
19113A-1
1-2
General Information
1.2.1 Fast SCSI Block
The Am53C974A’s Fast SCSI block supports SCSI transfer rates of up to 10 MBytes/s
synchronously, and up to 7 MByte/s asynchronously. The Am53C974A combines this
functionality with features such as programmable Active Negation, and a 24-bit transfer
counter. AMD’s proprietary features such as power-down mode for SCSI receivers and
programmable GLITCH EATER Circuitry are also included for improved product
performance.
The Am53C974A has an 8-bit SCSI data interface and can operate as either an Initiator
or a Target to support all SCSI applications. The SCSI block is designed to minimize
host intervention by implementing common SCSI sequences in hardware. Selection,
Reselection, Information Transfer and Disconnection commands are directly supported.
For example, functions such as Target Selection/Initiator Reselection, Command,
Message, and data transfers between the SCSI bus and the SCSI FIFO are internal
processes that the Am53C974A handles without microprocessor intervention. An
on-chip state machine reduces protocol overhead by performing the required sequences
in response to a single command from the host.
Additionally, a 16-byte SCSI FIFO further assists in minimizing host involvement. The
FIFO provides a temporary storage for all command, data, status and message bytes as
they are transferred between the 32-bit host data bus and the 8-bit SCSI data bus.
Parity checking on data received from the SCSI bus is optional. Parity is generated in
the SCSI block as data is loaded into the SCSI FIFO. Data transfers between the SCSI
bus and the SCSI FIFO are internal processes that the Am53C974A also handles
without microprocessor intervention.
AMD
1.2.1.1 Features
Key features in the Am53C974A Fast SCSI block are highlighted below:
1.2.1.1.1 Access FIFO Command
The Target command set for the Am53C974A includes the Access FIFO command. This
command allows the host or DMA controller to remove remaining FIFO data following
the host’s issuance of a Target abort DMA command, or following an abort due to parity
error. This command facilitates data recovery and thereby minimizes the need to
re-transmit data. For more details, refer to the Target Command Set.
1.2.1.1.2 Reduced Power Mode
AMD’s exclusive power-down feature can be enabled to help reduce power consumption. The receivers on the SCSI bus may be turned off to eliminate current flow due to
termination power (~3 V) near the trip point of the input buffers. Additionally, the clock to
the SCSI core can be disconnected for further power reduction.
1.2.1.1.3 Programmable GLITCH EATER Circuitry
The patented GLITCH EATER Circuitry in the Am53C974A PCSCSI II Controller can be
programmed to filter glitches with widths up to 35 ns. It is designed to dramatically
increase system reliability by detecting and removing glitches that may cause system
failure. The GLITCH EATER Circuitry is implemented on the REQ and ACK inputs since
these lines are most susceptible to electrical anomalies such as reflections and voltage
spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data
transfers, addition of random data, and double clocking. AMD’s GLITCH EATER
Circuitry therefore maintains system performance and improves reliability. The following
diagram illustrates this circuit’s operation.
General Information
1-3
AMD
Figure 1-2 GLITCH EATER Circuitry Operation
>15 ns <15 ns
SCSI Environment
Valid Signal Glitches
Device without the
GLITCH EATER Circuit
AMD’s Device with the
GLITCH EATER Circuit
By default, this feature is enabled and will filter glitches with widths up to 12 ns. When
this feature is implemented, the setup and hold times for the following parameters are
modified. However, they are still compliant with the SCSI-2 specification and have no
effect on the Am53C974A’s ability to meet Fast SCSI timings.
Data to REQ or ACK Setup Time:
Fast SCSI ANSI Requirement: 25 ns
Normal SCSI ANSI Requirement: 55 ns
Data to REQ Setup Time
(Async Initiator Receive Mode): 0 ns 12 ns
Data to ACK Setup Time
(Async Target Receive Mode): 0 ns 12 ns
Data to REQ or ACK Setup Time
(Sync Initiator/Target Receive Mode): 5 ns 12 ns
ACK or
REQ Input
ACK or
REQ Input
Valid Signal Passes
Glitches pass through as valid signals
Glitches Filtered
19113A-2
0 ns 12 ns
Window Window
1.2.1.1.4 Programmable Active Negation
AMD offers programmable active negation, a feature which, when implemented, will
actively drive the REQ, ACK and SCSI Data lines to a high state. This feature is
especially helpful for reducing SCSI Bus noise and improving data reliability. By actively
driving these signals to their high state, Active Negation eliminates unwanted signal
transitions and associated data double-clocking.
This feature is controlled by bits 3:2 in the SCSI Control Register Four ((B)+34h), and
may be implemented on REQ and ACK, or on REQ, ACK, and data lines during all SCSI
Bus phases except Arbitration and Selection. For more information on programming
options, refer to Control Register Four ((B)+34h) bit level descriptions.
1-4
General Information
1.2.2 DMA Engine
The Am53C974A bridges the PCI and SCSI buses by providing a buffer for these buses.
A 96-byte DMA FIFO (24 Double Words) internally interfaces with the 16-byte SCSI
FIFO to provide temporary storage for command, data, status, and message bytes as
they are transferred between the two buses.
The DMA engine is also capable of handling block type transfers (4 KB pages) during
scatter-gather operations. Odd/even boundary conditions are handled through hardware
to minimize software overhead.
1.3 SOFTWARE
To minimize your time to market, AMD offers a complete software solution for the
Am53C974A. This combination represents a powerful PCI systems solution which
enhances the flexibility of your system.
1.3.1 AMD’s PCSCSI II Software Solution
AMD’s PCSCSI II Software maximizes reusability and portability of SCSI protocol chip and
device driver source code across multiple operating system platforms. The software
architecture was based in part on the Microsoft Windows NT SCSI Miniport Driver
model.
AMD’s SCSI Software architecture supports the following features:
AMD
Device level overlapped/multithreaded operation
Tagged-queuing
Automatic request sense
Scatter-gather operations
Synchronous Transfers (including Fast SCSI)
General Information
1-5
AMD
1-6
General Information
SIGNAL DESCRIPTIONS
2
2.1 LOGIC SYMBOL
Figure 2-1 Am53C974A Logic Symbol
PCI Interface
AD [31:0]
C/BE [3:0]
PAR
FRAME
TRDY
IRDY
STOP
DEVSEL
IDSEL
PCI^REQ
PCI^GNT
CLK
PCI^RST
INTA
LOCK
PERR
SERR
PC
SCSI
(Am53C974A)
SD [7:0]
SDP
MSG
C/D
I/O
ATN
BSY
SEL
SCSI^RST
REQ
ACK
BA [7:0]
BD [7:0]
OE
LCK
BOOT
SCSI
Bus
Boot ROM
Support
VDD VSS
Signal Descriptions
SCSI CLK1
RES_DNC
PWDN
BUSY
Miscellaneous
Power
Management
Signals
19113A-3
2-1
AMD
2.2 QUICK REFERENCE PIN DESCRIPTIONS
Pin Name Pin Type Description
PCI
AD [31:00] IN/OUT Address/Data Bus
C/BE [3:0] IN/OUT Command/Byte Enable signals
PAR IN/OUT Parity Signal
FRAME IN/OUT Cycle Frame
TRDY IN/OUT Target Ready
IRDY IN/OUT Initiator Ready
STOP IN/OUT Stop
LOCK IN/OUT Lock
IDSEL IN Initialization Device Select
DEVSEL IN/OUT Device Select
PCI^REQ OUT PCI Request
PCI^GNT IN PCI Grant
CLK IN PCI Clock
PCI^RST IN PCI Reset
PERR IN/OUT Parity Error
SERR OUT System Error
INTA OUT Interrupt
SCSI Interface
SD [7:0] IN/OUT SCSI Data
SDP IN/OUT SCSI Data Parity
MSG IN/OUT Message
C/D IN/OUT Command/Data
I/O IN/OUT Input/Output
ATN IN/OUT Attention
BSY IN/OUT Busy
SEL IN/OUT Select
SCSI^RST IN/OUT SCSI Bus Reset
REQ IN/OUT Request
ACK IN/OUT Acknowledge
Boot ROM Interface
BOOT IN Boot ROM Enable
BA [7:0] OUT Boot ROM Address
BD [7:0] IN Boot ROM Data
OE OUT ROM Output Enable
LCK OUT High Address Byte Latch Clock
Miscellaneous
SCSI CLK1 IN SCSI Core Clock
RES_DNC IN Reserved, DO NOT CONNECT
Power Management
PWDN IN Power Down Indicator
BUSY OUT SCSI Bus Activity Pin
Power Supply
VDD +5 V
VSS GND
VDDB +5 V (Buffer)
VSSB GND (Buffer)
VDD3B +5 V (PCI)
VSS3B GND (5 V PCI)
2-2
Signal Descriptions
2.3 SIGNAL DESCRIPTIONS
2.3.1 Address and Data Pins
AD (31:00)
Address/Data
Address and Data are multiplexed on the same PCI pins. During the first clock of a
transaction the AD (31:00) contains the physical address (32 bits). During
subsequent clocks AD (31:00) may contain data. Little-endian byte ordering is used.
AD (07:00) is defined as least significant byte and AD (31:24) is defined as the most
significant byte.
When PCI^RST is active, AD(31:00) are inputs for NAND tree testing.
C/BE (3:0)
Bus Command/Byte Enable
Command and Byte Enables are multiplexed on the same PCI pins. During the
address phase of the transaction, C/BE(3:0) define the bus command. During the
data phase C/BE(3:0) are used as Byte Enables. The Byte Enables define which byte
lanes carry meaningful data. C/BE(0) applies to the least significant byte (byte 0) and
C/BE(3) applies to the most significant byte (byte 3).
When PCI^RST is active, C/BE (3:0) are inputs for NAND tree testing.
(Input/Output, Active High)
(Input/Output, Active Low)
AMD
PAR
Parity
(Input/Output, Active High)
Parity is even across AD(31:00) and C/BE (3:0). Parity is generated and driven
during Master Address Cycle, Memory Write, I/O Read, and Configuration Read
cycles. Parity is checked during Slave Address Cycle, Memory Read, I/O Write, and
Configuration Write cycles.
When PCI^RST is active, PAR is an input for NAND tree testing.
2.3.2 PCI Interface Control Pins
FRAME
Cycle Frame
This signal is driven by the Am53C974A when it is the bus master to indicate the
beginning and duration of the access. FRAME is asserted to indicate that bus
transaction is beginning. FRAME is asserted while data transfers continue. FRAME is
driven high when the transaction is in the final data phase.
When PCI^RST is active, FRAME is an input for NAND tree testing.
TRDY
Target Ready
When the Am53C974A is selected as a slave, it will drive(low) this signal to indicate
its ability to complete the current data phase of the transaction. As a master, this
signal is an input to the Am53C974A from the selected (slave) device.
(Input/Output, Active Low)
(Input/Output, Active Low)
TRDY is used in conjunction with IRDY to indicate completion of the data phase.
The data phase is complete (on any clock) when both TRDY and IRDY are sampled
asserted. During a read transaction, TRDY is asserted when valid data is present on
AD (31:00), while during a write transaction, TRDY asserted indicates the target is
prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are
asserted together.
When PCI^RST is active, TRDY is an input for NAND tree testing.
Signal Descriptions
2-3
AMD
IRDY
Initiator Ready
(Input/Output, Active Low)
When the Am53C974A is the initiator (master), it will drive (low) this signal to indicate
its ability to complete the current data phase of the transaction. As a slave, this signal
is an input to the Am53C974A from the initiating (master) device.
IRDY is used in conjunction with TRDY to indicate completion of the data phase. The
data phase is complete (on any clock) when both IRDY and TRDY are sampled
asserted. During a read transaction, IRDY asserted indicates the master is prepared
to accept data, while during a write transaction, IRDY is asserted to indicate that valid
data is present on AD (31:00). Wait cycles are inserted until both IRDY and TRDY
are asserted together.
When PCI^RST is active, IRDY is an input for NAND tree testing.
STOP
Stop
(Input/Output, Active Low)
In the slave role the Am53C974A drives the STOP signal to indicate to the bus
master to stop the current transaction. In the bus master role the Am53C974A
receives the STOP signal and stops the current transaction.
When PCI^RST is active, STOP is an input for NAND tree testing.
LOCK
Lock
(Input/Output, Active Low)
In the master role the Am53C974A drives the LOCK signal to indicate to the slave
device that multiple transactions may be necessary to complete an operation. When
LOCK is asserted, non-exclusive transactions may proceed. Control of LOCK is
obtained under its own protocol in conjunction with PCI^GNT. In the slave role the
Am53C974A receives the LOCK signal from the master.
When PCI^RST is active, LOCK is an input for NAND tree testing.
Note: In the current implementation, the Am53C974A as a master will never generate a
LOCK
. However in slave role, the chip will respond to a
LOCK
asserted by a master.
IDSEL
Initialization Device Select
(Input, Active High)
This signal is used as a chip select for the Am53C974A in lieu of the 24 address lines
during configuration read and write transaction.
When PCI^RST is active, IDSEL is an input for NAND tree testing.
DEVSEL
Device Select
(Input/Output, Active Low)
This signal when actively driven by the Am53C974A as a slave device signals to the
master device that it has decoded its address as the target of the current access. As
an input it indicates whether any device on the bus has been selected.
When PCI^RST is active, DEVSEL is an input for NAND tree testing.
2-4
Signal Descriptions
2.3.3 Arbitration Pins
PCI^REQ
PCI Request
(Output, Active Low, Tristate)
This signal indicates to the arbiter that the Am53C974A desires use of the bus. This
is a point to point signal. Every master has its own equivalent of PCI^REQ, which will
be tristated after a power-up or a chip reset.
When PCI^RST is active, PCI^REQ is an input for NAND tree testing.
PCI^GNT
PCI Grant
(Input, Active Low)
This signal indicates that the access to the bus has been granted to the Am53C974A.
This is a point to point signal. Every master has its own equivalent of PCI^GNT.
When PCI^RST is active, PCI^GNT is an input for NAND tree testing.
2.3.4 System Pins
CLK
Clock
(Input)
This signal provides timing for all the transactions on the PCI bus and all PCI devices
on the bus including the Am53C974A. All signals are sampled on the rising edge of
CLK and all parameters are defined with respect to this edge. The Am53C974A
operates up to 33 MHz.
AMD
When PCI^RST is active, CLK is an input for NAND tree testing.
PCI^RST
PCI Reset
(Input, Active Low)
This signal forces the Am53C974A sequencer to a known state. All Three-State
bi-directional signals are forced to a high impedance state and all Sustained Open
Drain signals are allowed to float high. The Am53C974A will tristate PCI^REQ, and
completely reset the Am53C974A. PCI^RST may be asynchronous to the CLK when
asserted or driven low. It is recommended that the deassertion be synchronous to
guarantee a clean and bounce free edge.
When PCI^RST is active, NAND tree testing is enabled. All PCI interface pins are
input mode. The result of the NAND tree testing can be observed on the BUSY
output (pin 62).
2.3.5 Error Reporting Pins
PERR
Parity Error
(Input/Output, Active Low)
This signal may be pulsed by the Am53C974A when it detects a parity error during
any data phase when its AD (31:00) and C/BE (3:0) lines are inputs. The
Am53C974A monitors the PERR input during a bus master write cycle. It will assert
the Data Parity Reported bit in the Status Register of the PCI Configuration Space
when a parity error is reported by the target device.
When PCI^RST is active, PERR is an input for NAND tree testing.
Signal Descriptions
2-5
AMD
SERR
System Error
(Output, Active Low, Open Drain)
This signal may be pulsed by the Am53C974A for reporting address parity errors
when AD(31:00) are inputs.
When PCI^RST is active, SERR is an input for NAND tree testing.
2.3.6 Interrupt Request Pins
INTA
Interrupt Request
(Output, Active Low, Open Drain)
This signal combines the interrupt request from both the DMA engine and the SCSI
block. The interrupt source can be determined by reading the DMA Status register
((B)+70). Interrupts caused by the DMA engine may be cleared in two ways. When
the Write Erase feature is not set in the SBAC register ((B)+54), the INTA signal will
be cleared when the Status Register ((B)+54) is read. When the Write Erase feature
is set, the INTA signal will only be cleared when a ‘1’ is written to the bit associated
with the interrupting condition. For those interrupts generated by the SCSI block, the
SCSI interrupt register must be serviced in order to clear the interrupt.
When PCI^RST is active, INTA is an input for NAND tree testing.
2.3.7 SCSI Interface Signals
SD (7:0)
SCSI Data
(Input/Output, Active Low, Schmitt Trigger, Open Drain/Active Negation)
These pins are defined as bi-directional SCSI data bus.
SDP
SCSI Data Parity
(Input/Output, Active Low, Schmitt Trigger, Open Drain/Active Negation)
This pin is defined as bi-directional SCSI data parity.
MSG
Message
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
MSG is a bi-directional signal which is asserted during a MESSAGE phase. It is a
schmitt triggered input in the Initiator role and an output with a 48 mA driver in the
Target role.
C/D
Command/Data
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
C/D is a bi-directional signal which is used to indicate whether CONTROL or DATA
information is on the SCSI data bus. It is a schmitt trigger input in the Initiator role
and an output with a 48 mA driver in the Target role.
I/O
Input/Output
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
I/O is a bi-directional signal which controls the direction of data movement on the
SCSI data bus with respect to the initiator. It is a schmitt triggered input in the Initiator
role and an output with a 48 mA driver in the Target role.
2-6
Signal Descriptions
AMD
ATN
Attention
ATN is a bi-directional signal which is used to indicate the ATTENTION condition. It is
a schmitt triggered input in the Target role and an output with a 48 mA driver in the
Initiator role.
BSY
Busy
BSY is a bi-directional signal which is asserted when the Am53C974A is arbitrating
for the SCSI bus or when it is connected as a Target. As an input it has a schmitt
trigger and as an output it has a 48 mA driver.
SEL
Select
SEL is a bi-directional signal which is asserted when the Am53C974A is attempting
to select or reselect another SCSI device. As an input it has a schmitt trigger and as
an output it has a 48 mA driver.
SCSI RST
Reset
SCSI RST is a bi-directional SCSI bus reset signal. As a schmitt triggered input to the
Am53C974A, this signal when asserted will reset portions of the SCSI logic (see Soft
Reset). As a 48 mA output driver, this signal when asserted will cause all other
devices on the SCSI bus to be reset. The Reset SCSI command will also cause the
SCSI RST pin to be driven active for 25–40 ms, depending on the SCSI clock
frequency and conversion factor.
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
REQ
Request
ACK
Acknowledge
2.3.8 Power Management Signals
PWDN
Power Down Indicator
This signal, when asserted, sets the PWDN status bit in the DMA status register and
sends an interrupt to the host.
When PCI^RST is active, PWDN is an input for NAND tree testing.
BUSY
SCSI Devices Busy
(Input/Output, Active Low, Schmitt Trigger, Open Drain)
REQ is a bi-directional SCSI bus signal which indicates a request for a REQ/ACK
data transfer. It is a schmitt triggered input in the Initiator role and an output with a
48 mA driver in the Target role.
(Input /Output, Active Low, Schmitt Trigger/Open Drain)
ACK is a bi-directional SCSI bus signal which is used to indicate an acknowledgment
for a REQ/ACK data transfer handshake. It is a schmitt triggered input in the Target
role and a output with a 48 mA driver in the Initiator role.
(Input, Active High)
(Output, Active Low)
This signal is the logical equivalent of the SCSI bus BSY ORed with SEL signals. It is
duplicated so that external logic can be connected to monitor SCSI bus activity.
Signal Descriptions
2-7
AMD
When PCI^RST is active, the results of the NAND tree testing can be observed on
BUSY. When PCI^RST is driven low, BUSY will function as described above.
2.3.9 Boot ROM Support Pins
BOOT
Boot ROM Present
(Input)
The state of this pin determines whether or not the Boot ROM interface on the
Am53C974A is enabled. When this pin is connected to VCC, the interface is enabled
to support the Boot ROM feature. When this pin is connected to ground, all input
buffers on BD (7:0) are disabled, and BA (7:0), OE, and LCK pins are tri-stated.
Since this pin was VSS on the Am53C974, the Boot ROM interface on the
Am53C974A is automatically disabled in existing Am53C974 designs.
BD (7:0)
Boot ROM Data
(Input)
When the Am53C974A is configured for Boot ROM support (Pin 100 tied to VCC),
BD (7:0) carries data from the ROM to the Am53C974A. When not configured to
support a Boot ROM (Pin 100 tied to ground), the input buffers on these pins are
disabled.
BA (7:0)
ROM Address
(Output)
When the Am53C974A is configured for Boot ROM support (Pin 100 tied to VCC),
BA (7:0) carries the Boot ROM address from the Am53C974A. When Boot ROM support
is disabled (Pin 100 tied to ground), these pins are tri-stated.
OE
ROM Output Enable
(Output)
When the Am53C974A is configured for Boot ROM support (Pin 100 tied to VCC), this pin
is used as the output enable for the ROM. When Boot ROM support is disabled (Pin 100
Tied to ground), this pin is tri-stated.
LCK
Latch Clock
(Output)
When the Am53C974A is configured for Boot ROM support (Pin 100 tied to VCC), this pin
is used as a clock to latch the high byte of the ROM address. When Boot ROM support
is disabled (Pin 100 tied to ground), this pin is tri-stated.
2.3.10 Miscellaneous Signals
SCSI CLK1
SCSI Clock
(Input)
The SCSI clock signal is used to generate all internal device timings. The maximum
frequency of this input is 40 MHz, while the minimum is 10 MHz to maintain SCSI bus
timing requirements. To achieve Fast SCSI timings, a 40 MHz clock must be supplied
to this input.
2-8
RES_DNC
Reserved _Do Not Connect
(Input)
This pin (#116) is reserved for factory testing. To ensure proper chip operation, it
must not be connected.
Signal Descriptions
2.3.11 Power Supply Pins
VDD
+5 V
Power
(Input)
These inputs provide power necessary to operate the Am53C974A. All VDD pins must
be connected to a +5 V source.
VDDB
+5 V
Power
(Input)
These inputs are for SCSI Buffers. These pins can be connected to the VDD pins.
VDD3B
+5 V
Power
(Input)
These inputs provide power for the PCI Interface block. These pins must be
connected to a +5 V source.
VSS/VSSB/VSS3B
Ground
(Input)
These inputs provide the necessary grounds to operate the Am53C974A. The VSSB
and VSS3B can be connected to VSS provided there is a decoupling capacitor between
VSSB and VDDB and VSS3B and VDD3B.
AMD
Signal Descriptions
2-9
AMD
2.4 CONNECTION DIAGRAM TABLES
2.4.1 Listed by Pin Number
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1 VDD3B 34 PAR 67 VSSB 100 BOOT
2 AD27 35 C/BE1 68 SD0 101 BD0
3 AD26 36 AD15 69 SD1 102 NC
4 VSS3B 37 VSS3B 70 SD2 103 VDD
5 AD25 38 AD14 71 SD3 104 OE
6 AD24 39 AD13 72 VSSB 105 LCK
7 C/BE3 40 AD12 73 SD4 106 BA0
8 VDD 41 AD11 74 SD5 107 NC
9 IDSEL 42 AD10 75 SD6 108 VDD
10 NC 43 VSS3B 76 VDDB 109 VDD
11 VSS 44 AD9 77 SD7 110 NC
12 AD23 45 AD8 78 SDP 111 BA1
13 AD22 46 VDD3B 79 VSS 112 BA2
14 VSS3B 47 C/BE0 80 SEL 113 VSS
15 AD21 48 AD7 81 REQ 114 BA3
16 AD20 49 AD6 82 VSSB 115 BA4
17 VDD3B 50 VSS3B 83 ACK 116 RES_DNC
18 AD19 51 AD5 84 VDD 117 INTA
19 AD18 52 AD4 85 MSG 118 BA5
20 VSS3B 53 AD3 86 C/D 119 VSS
21 AD17 54 AD2 87 I/O 120 PCI^RST
22 AD16 55 VSS3B 88 VSS 121 CLK
23 C/BE2 56 AD1 89 BD7 122 VDD
24 FRAME 57 AD0 90 BD6 123 BA6
25 IRDY 58 PWDN 91 VDD 124 PCI^GNT
26 TRDY 59 VDD 92 NC 125 VSS
27 DEVSEL 60 SCSICLK1 93 BD5 126 BA7
28 STOP 61 VSS 94 BD4 127 PCI^REQ
29 LOCK 62 BUSY 95 BD3 128 AD31
30 VSS 63 VSS 96 VDD 129 AD30
31 PERR 64 BSY 97 BD2 130 VSS3B
32 SERR 65 ATN 98 VSS 131 AD29
33 VDD3B 66 SCSI^RST 99 BD1 132 AD28
NC = No Connect
RES_DNC = Reserved_DO NOT CONNECT.
2-10
Signal Descriptions
2.4.2 Listed by Pin Name
AMD
Pin Name Pin No.
ACK 83
AD0 57
AD1 56
AD2 54
AD3 53
AD4 52
AD5 51
AD6 49
AD7 48
AD8 45
AD9 44
AD10 42
AD11 41
AD12 40
AD13 39
AD14 38
AD15 36
AD16 22
AD17 21
AD18 19
AD19 18
AD20 16
AD21 15
AD22 13
AD23 12
AD24 6
AD25 5
AD26 3
AD27 2
AD28 132
AD29 131
AD30 129
AD31 128
Pin Name Pin No.
ATN 65
BA0 106
BA1 111
BA2 112
BA3 114
BA4 115
BA5 118
BA6 123
BA7 126
BD0 101
BD1 99
BD2 97
BD3 95
BD4 94
BD5 93
BD6 90
BD7 89
BOOT 100
BSY 64
BUSY 62
C/BE0 47
C/BE1 35
C/BE2 23
C/BE3 7
C/D 86
CLK 121
DEVSEL 27
FRAME 24
I/O 87
IDSEL 9
INTA 117
IRDY 25
LCK 105
NC = No Connect
RES_DNC = Reserved_DO NOT CONNECT.
Pin Name Pin No.
LOCK 29
MSG 85
NC 10
NC 92
NC 102
NC 107
NC 110
OE 104
PAR 34
PCI^GNT 124
PCI^REQ 127
PCI^RST 120
PERR 31
PWDN 58
REQ 81
RES_DNC 116
SCSI^RST 66
SCSICLK1 60
SD0 68
SD1 69
SD2 70
SD3 71
SD4 73
SD5 74
SD6 75
SD7 77
SDP 78
SEL 80
SERR 32
STOP 28
TRDY 26
VDD 8
VDD 59
Pin Name Pin No.
VDD 84
VDD 91
VDD 96
VDD 103
VDD 108
VDD 109
VDD 122
VDD3B 1
VDD3B 17
VDD3B 33
VDD3B 46
VDDB 76
VSS 11
VSS 30
VSS 61
VSS 63
VSS 79
VSS 88
VSS 98
VSS 113
VSS 119
VSS 125
VSS3B 4
VSS3B 14
VSS3B 20
VSS3B 37
VSS3B 43
VSS3B 50
VSS3B 55
VSS3B 130
VSSB 67
VSSB 72
VSSB 82
Signal Descriptions
2-11
AMD
2.5 PIN OUT MAP
AD28
AD29
VSS3B
AD30
AD31
PCI^REQ
BA7
131
130
VDD3B
C/BE2
FRAME
IRDY
132
1
2AD27
3AD26
4VSS3B
5AD25
6AD24
7C/BE3
8VDD
9IDSEL
10NC
11VSS
12AD23
13AD22
14VSS3B
15AD21
16AD20
17VDD3B
18AD19
19AD18
20VSS3B
21AD17
22AD16
23
24
25
26TRDY
27DEVSEL
28STOP
29LOCK
30VSS
31PERR
32SERR
33VDD3B
34
35
36
129
37
128
38
127
126
40
VSS
PCI^GNT
125
124
41
BA6
123
43
VDD
CLK
PCI^RST
VSS
122
121
120
119
(Am53C974A)
44
45
46
47
BA5
118
PC
48
INTA
RES_DNC
117
116
SCSI
49
50
BA4
115
II
51
BA3
114
52
VSS
113
BA2
112
54
BA1
111NC110
55
56
VDD
109
57
VDD
108NC107
59
58
BA0
106
60
LCK
105OE104
61
62
VDD
103NC102
63
64
BD0
101
65
BOOT
100
BD199
VSS98
BD297
VDD96
BD395
BD494
BD593
NC92
VDD91
BD690
BD789
VSS88
I/O87
C/D86
MSG85
VDD84
ACK83
VSSB82
REQ81
SEL80
VSS79
SDP78
SD777
VDDB76
SD675
SD574
SD473
VSSB72
SD371
SD270
SD169
SD068
VSSB67
66
2-12
PAR
C/BE1
VSS3B
AD15
AD1439AD13
AD12
VSS3B
AD1142AD10
AD9
AD8
VDD3B
AD7
C/BE0
AD6
VSS3B
AD5
Signal Descriptions
AD453AD3
AD2
VSS3B
AD1
AD0
VDD
PWDN
VSS
BUSY
SCSICLK1
VSS
ATN
BSY
SCSI^RST
19113A-4
2.6 NAND TREE TESTING
The Am53C974A PCSCSI II controller provides a NAND tree test mode to allow connectivity checking to the device on a printed circuit board. The NAND tree is built on all PCI
bus signals.
The NAND tree test is enabled by asserting PCI^RST. All PCI signals will become inputs
when PCI^RST is asserted. The result of the NAND tree test can be observed on the
BUSY pin.
Figure 2-2 NAND Tree
VDD
PCI^RST
(pin 120)
INTA
(pin 117)
AMD
CLK
(pin 121)
PWDN
(pin 58)
PC
SCSI II
BUSY
B
A
MUX
S
O
BUSY
(pin 62)
19113A-5
Signal Descriptions
2-13
AMD
Pin 120 (PCI^RST) is the first input to the NAND tree. Pin 117 (INTA) is the second input
to the NAND tree, followed by pin 121 (CLK). All other PCI bus signals follow, counterclockwise, with pin 58 (PWDN) being the last. Pins labeled NC and power supply pins
are not part of the NAND tree. The table below shows the complete list of pins connected to the NAND tree.
NAND NAND NAND
Tree Tree Tree
Input # Pin # Name Input # Pin # Name Input # Pin # Name
1 120 PCI^RST 19 16 AD20 37 39 AD13
2 117 INTA 20 18 AD19 38 40 AD12
3 121 CLK 21 19 AD18 39 41 AD11
4 124 PCI^GNT 22 21 AD17 40 42 AD10
5 127 PCI^REQ 23 22 AD16 41 44 AD9
6 128 AD31 24 23 C/BE2 42 45 AD8
7 129 AD30 25 24 FRAME 43 47 C/BE0
8 131 AD29 26 25 IRDY 44 48 AD7
9 132 AD28 27 26 TRDY 45 49 AD6
10 2 AD27 28 27 DEVSEL 46 51 AD5
11 3 AD26 29 28 STOP 47 52 AD4
12 5 AD25 30 29 LOCK 48 53 AD3
13 6 AD24 31 31 PERR 49 54 AD2
14 7 C/BE3 32 32 SERR 50 56 AD1
15 9 IDSEL 33 34 PAR 51 57 AD0
16 12 AD23 34 35 C/BE1 52 58 PWDN
17 13 AD22 35 36 AD15
18 15 AD21 36 38 AD14
PCI^RST must be asserted (logic low) to start a NAND tree test sequence. Initially, all
NAND tree inputs except PCI^RST should be driven high. This will result in a low output
at the BUSY pin. If the NAND tree inputs are driven low in the same order as they are
connected to build the NAND tree, BUSY will toggle every time an additional input is
driven low. BUSY will change to a ONE, when INTA is driven low and all other NAND
tree inputs stay high. BUSY will toggle back to low, when CLK is additionally driven low.
The square wave will continue until all NAND tree inputs are driven low. BUSY will be
high when all NAND tree inputs are driven low.
When testing is complete, deassert PCI^RST to exit this test mode.
Note: Some of the pins connected to the NAND tree are outputs in normal mode of
operation. They must not be driven from an external source until the PC
SCSI controller is
configured for NAND tree testing.
2-14
Signal Descriptions
Figure 2-3 NAND Tree Waveform
PCIRST
INTA
CLK
PCIGNT
PCIREQ
AD[31:0]
C/BE[3:0]
IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
LOCK
PERR
SERR
PAR
PWDN
BUSY
FFFFFFFF
F
AMD
0000FFFF
7
3 1
0
19113A-6
Signal Descriptions
2-15
AMD
2.7 Am53C974A REGISTER MAP
Configuration Register Map
31 16 15 0
Device ID Vendor ID 00h
Status Command 04h
Base Class Sub Class Prog. If. Revision ID 08h
BIST* Header Type* Latency Timer Cache Line Size* 0Ch
Base Address 10h
Reserved* 14h – 38h
Expansion ROM Base Address 30h
Reserved* 34h – 38h
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch
Reserved for Reserved for Reserved for Reserved for 40h –
SCSI Software SCSI Software SCSI Software SCSI Software 4Ch**
* Not Implemented on Am53C974A. Writes to these locations will have no effect; reads from these locations will return ‘00h’.
** Reserved for SCSI software.
SCSI Register Map
Register
Acronym Address (Hex.) Register Description Type
CTCREG (B)+00 Current Transfer Count Register Low R
STCREG (B)+00 Start Transfer Count Register Low W
CTCREG (B)+04 Current Transfer Count Register Middle R
STCREG (B)+04 Start Transfer Count Register Middle W
FFREG (B)+08 SCSI FIFO Register R/W
CMDREG (B)+0C SCSI Command Register R/W
STATREG (B)+10 SCSI Status Register R
SDIDREG (B)+10 SCSI Destination ID Register W
INSTREG (B)+14 Interrupt Status Register R
STIMREG (B)+14 SCSI Timeout Register W
ISREG (B)+18 Internal State Register R
STPREG (B)+18 Synchronous Transfer Period Register W
CFIREG (B)+1C Current FIFO/Internal State Register R
SOFREG1 (B)+1C Synchronous Offset Register W
CNTLREG1 (B)+20 Control Register One R/W
CLKFREG (B)+24 Clock Factor Register W
RES (B)+28 Reserved W
CNTLREG2 (B)+2C Control Register Two R/W
CNTLREG3 (B)+30 Control Register Three R/W
CNTLREG4 (B)+34 Control Register Four R/W
CTCREG (B)+38 Current Transfer Count Register High/Part-Unique ID Code R
STCREG (B)+38 Start Current Transfer Count Register High W
RES (B)+3C Reserved W
2-16
Signal Descriptions
AMD
DMA Register Map
Register
Acronym Address (Hex.) Register Description Type
CMD (B)+40 Command R/W
STC (B)+44 Starting Transfer Count R/W
SPA (B)+48 Starting Physical Address R/W
WBC (B)+4C Working Byte Counter R
WAC (B)+50 Working Address Counter R
STATUS (B)+54 Status Register R
SMDLA (B)+58 Starting Memory Descriptor List (MDL) Address R/W
WMAC (B)+5C Working MDL Counter R
SBAC (B)+70 SCSI Bus and Control *
*Certain bits are Read/Write, certain bits are Read Only. Refer to the SBAC (SCSI Bus and Control) register for more detail.
Signal Descriptions
2-17
AMD
2-18
Signal Descriptions
POWER MANAGEMENT FEATURES
3
3.1 INTRODUCTION
As a leader in low-voltage technology, AMD has incorporated power-saving features into
the Am53C974A. Through hardware and software or just software alone, the
Am53C974A can be powered down to reduce consumption during chip inactivity. This
significantly reduces overall power usage, as the system and associated peripherals can
benefit from these features.
3.2 SCSI ACTIVITY INDICATORS
The SCSI Bus activity can be monitored through hardware or software. Through the
hardware, the SCSI Bus activity is reflected by the BUSY output pin. This pin, when
active, indicates that the SCSI Bus is in use and therefore the Am53C974A should not
be powered down. Similarly, the SCSI activity can also be monitored through software
by polling the SBSY bit (bit 20) in the SBAC register ((B)+70). Both these indicators are
the logical equivalent to the SCSI bus signal BSY ORed with SEL. However, they are
not physically connected to the BSY signal on the SCSI bus. To correctly identify the
Bus Free State on the SCSI bus, either the BUSY pin or the SBSY bit must be inactive
for at least 250 ms (Selection Timeout period). Once this condition is valid, the SCSI
software can safely commence the power down sequence. Note that if the BUSY pin is
used to detect SCSI bus free condition, then external logic on the host must drive the
PWDN pin to notify the SCSI software to commence the power down sequence.
3.2.1 Reduced Power Mode
When the SCSI Bus is free and there are no pending commands, the Am53C974A may
be powered down by turning off the input buffers on the SCSI Bus lines. This is done by
setting bit 5 in Control Register Four (B)+34h. Additionally, for further power reduction,
the internal registers may be programmed to a predetermined state, and the clock to the
SCSI core disconnected via the PWD bit (bit 21) in the SBAC register ((B)+70). However
before disconnecting the clock from the SCSI core, the state of the SCSI bus should first
be saved. This can be done through use of the Scratch registers in the PCI configuration
space starting at address 40h.
3.3 POWER DOWN PIN (PWDN Pin)
When the PWDN pin is driven active, it sets the PWDN bit in the Status Register (Bit 0,
DMA Status Register (B)+54h), signaling the Am53C974A that the host would like to
power down the SCSI interface. An interrupt is generated when this bit is set.
3.3.1 Software Disk Spin-Down
Incorporated into the SCSI ROM BIOS and certain device driver’s of AMD’s software
solution is a module which physically spins down SCSI fixed disks when the host system
elects to enact power management on the SCSI system. The software module is
activated upon the ROM BIOS and/or other device driver’s receipt of an interrupt caused
by the PWDN pin being driven active. Upon receipt of this interrupt, the current software
process is suspended and software control is given to the power management module.
Power Management Features
3-1
AMD
When the power management module is activated, it checks the status of all SCSI fixed
disks on the system under its control. The SCSI fixed disks that are idle are issued a
command to spin down their media. All fixed disks that are active at the time will be
scheduled for spin down upon completion of their pending commands. Once the BIOS
and/or drivers have detected the completion of each fixed disk’s final pending commands, they are issued the command to spin down as well.
To spin down the disk drives, the power management module issues a SCSI command
(1B– Start/Stop unit). When the command is received by the drive, it spins down and
waits in an idle state. For multiple drives on the SCSI bus, the power management
driver spins down each drive individually. The drives remain in the idle state until the
BIOS and/or driver receives a command for the particular fixed disk. Once this occurs,
the drive is issued the command to spin up. When the drive has completely spun up and
is ready, the pending command is issued to the drive. Only the particular fixed disk
issued the command is instructed to spin up. All other drives will remain in the spun
down state until a command is issued to them.
Note: This sequence does not turn off the SCSI input buffers as described in the previous section.
3-2
Power Management Features
THE PCI BUS INTERFACE UNIT
4
4.1 INTRODUCTION
The Am53C974A handles all PCI bus accesses through its PCI Bus Interface Unit (BIU).
The PCI BIU interprets and generates all PCI bus signals in accordance with the PCI
specification Rev 2.0. In addition to interfacing the Am53C974A with the PCI bus, the
PCI BIU also contains a 256 byte PCI configuration register which is accessible via
Configuration Read/Write cycles from the PCI bus. This chapter covers the PCI block of
the Am53C974A PCISCSI II controller. The Am53C974A’s I/O address map, PCI bus
cycles and modes supported are described in detailed as well as the function and
contents of its PCI configuration registers. For more information on the PCI bus protocol,
refer to the
4.2 ADDRESSING
PCI defines three physical address spaces: Memory, I/O, and Configuration. The
memory and I/O address space are customary while configuration has been defined to
support PCI hardware. Am53C974A accesses to the memory space requires a Memory
Read/Write command to the desired memory location while host CPU accesses to the
I/O space requires an I/O Read/Write command to the location specified by the Base
Address Register of the device’s configuration space. That is, the value written to the
Base Address Register of the Configuration space defines the base I/O location of the
Am53C974A. Configuration accesses to the Am53C974A are done by issuing a
Configuration Read/Write command with the Am53C974A IDSEL line asserted.
PCI Local Bus Specification
.
4.3 BUS ACQUISITION
The first step in any Am53C974A bus master transfer is to acquire ownership of the bus.
This task is handled by synchronous logic within the PCI BIU. Bus ownership is
requested with the PCI^REQ signal and ownership is granted by the arbiter through the
PCI^GNT signal. Figure 4-1 shows the Am53C974A’s bus acquisition timing. In this
figure, although bus ownership is granted on clock 3 with the assertion of PCI^GNT, the
Am53C974A will not assert FRAME (indicating the start of bus cycle) until clock 5. Note,
however, that although the Am53C974A will begin driving AD[31:0] and C/BE[3:0] prior
to clock 4, these lines will not be valid until FRAME is asserted. ADSTEP (bit 7) in the
PCI command register is set to ONE to indicate that the Am53C974A uses address
stepping. However, address stepping is only used for the first address phase of a bus
master period.
The PCI Bus Interface Unit
4-1
AMD
Figure 4-1 Bus Acquisition Timing
CLK
FRAME
1 2 3 4 5 6
AD
C/BE
PCI^REQ
PCI^GNT
4.4 BUS CYCLE DEFINITION
The Am53C974A supports only the relevant PCI bus cycles (eight of the sixteen cycles).
These cycles are defined by the C/BE [3:0] command lines during the address phase of
each PCI bus cycle. Table 4-1 shows these bus cycles and the mode supported by the
Am53C974A. Note that Bus cycles with an asterisk (*) are ignored by the Am53C974A,
while those with double asterisks (**) are aliased to the Slave Memory read cycle.
Table 4-1 PCI Bus Cycles Supported by the Am53C974A
C/BE[3:0] Bus Cycle Type Mode Supported
0000 Interrupt ACK *
0001 Special Cycle *
0010 I/O Read Slave
0011 I/O Write Slave
0100 Reserved *
0101 Reserved *
0110 Memory Read Master, Slave
0111 Memory Write Master, Slave***
1000 Reserved *
1001 Reserved *
1010 Config. Read Slave
1011 Config. Write Slave
1100 Mem Read Multiple **Slave
1101 Dual Address Cycle *
1110 Mem Read Line Master, **Slave
1111 Mem Write & Invalidate *
* These cycles are ignored by the Am53C974A.
** Both the Slave Memory Read Line and Slave Memory Read Multiple Cycles are aliased to the Slave
Memory Read cycle.
*** Slave Memory Write commands to the Am53C974A will complete normally but the data is ignored by the
device.
ADDR
CMD
19113A-7
4-2
The PCI Bus Interface Unit
4.5 BUS CYCLE DIAGRAMS
The following are samples of the Am53C974A’s bus cycles in Table 4-1. Each cycle
shows an example timing diagram along with a brief description of the cycle. Note that
the cycles shown are only typical PCI bus cycles; each cycle can be distinct because of
various factors such as Bus Latency, IRDY and TRDY timing, etc.
4.5.1 Slave I/O Read
The Slave I/O Read command is used by the processor to read internal registers in the
Am53C974A. It is a single cycle, non_burst 8-bit, 16-bit, or 32-bit transfer which is
initiated by the host CPU. The Am53C974A will not produce slave I/O Read commands
while a bus master. Slave I/O Read cycles are fixed length cycles, i.e. the Am53C974A
will return TRDY on the 10th bus cycle of the transfer. Figure 4-2 shows the timing for a
Slave I/O Read bus cycle.
Figure 4-2 Slave I/O Read Timing
CLK
1 2 3
FRAME
4 5 6 7 8 9 10 11 12
AMD
C/BE
PAR
SERR
PERR
IRDY
TRDY
DEVSEL
AD
ADDR DATA
0010 BE
PAR
SERR
PAR
PERR
19113A-8
The PCI Bus Interface Unit
4-3
AMD
4.5.2 Slave I/O Write
The Slave I/O Write command is used by the processor to write the internal registers in
the Am53C974A. It is a single cycle, non-burst 8-bit, 16-bit, or 32-bit transfer which is
initiated by the host CPU. The Am53C974A will not produce Slave I/O Write commands
while a bus master. Slave I/O Write cycles are fixed length cycles, i.e. the Am53C974A
will return TRDY on the 10th bus cycle of the transfer. Figure 4-3 shows the timing for a
Slave I/O Write bus cycle.
Figure 4-3 Slave I/O Write Timing
CLK
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
1 2 3 4 5 6 7 8 9 10 11 12
ADDR DATA
0011 BE
PAR PAR
SERR
PERR
4-4
DEVSEL
19113A-9
The PCI Bus Interface Unit
4.5.3 Master Memory Read
The Master Memory Read command is used by the Am53C974A when it will be reading
2 or less 32-bit locations of memory. If the device needs to read more than 2 Doublewords (Dwords) of memory, the Master Memory Read Line command is used. Figure 4-4 shows an example timing diagram for a Master Memory Read command. In this
figure, the device issues a request for the bus, is granted access, and then reads a
32-bit Dword from system memory before releasing the bus. The data phase in this
diagram takes two clock cycles, this being determined by the timing of TRDY.
Note that during a Master Memory Read, the Am53C974A will always activate all byte
enables, even though some byte lanes may not contain “valid” data. In such instances,
the Am53C974A will internally discard unnecessary bytes.
Figure 4-4 Master Memory Read Timing
AMD
CLK
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
1 2 3 4 5 6 7 8
ADDR
0110
DATA
BE
PAR
SERR
9 10
PAR
PERR
DEVSEL
PCI^REQ
PCI^GNT
The PCI Bus Interface Unit
19113A-10
4-5
AMD
4.5.4 Slave Memory Read
The Slave Memory Read Command is used by the processor to read data from the
Am53C974A’s expansion ROM. This is a single cycle, non-burst 8-bit,16-bit, or 32-bit
transfer which is initiated by the host CPU. The Am53C974A will always respond to this
cycle by returning valid data on all byte lanes. Thus, it is the responsibility of the host to
discard any unneccessary bytes via the C/BE[3:0] lines. The Am53C974A will not
produce Slave Memory Read commands while a bus master. Slave Memory Read
cycles are fixed length cycles, i.e. the Am53C974A will return TRDY on the 54th bus
cycle of the transfer. Figure 4-5 shows the timing for a Slave Memory Read bus cycle.
Note that the Slave Memory Read Multiple and the Slave Memory Read Line commands
are aliased to the Slave Memory Read command.
Figure 4-5 Slave Memory Read Timing
CLK
1 2 3 4 5 53 54
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
STOP
DEVSEL
ADDR
0110
PAR
DATA
BE
PAR
SERR
PERR
19113A-11
4-6
The PCI Bus Interface Unit
4.5.5 Master Memory Write
The Master Memory Write command is used by the Am53C974A when it will be writing
to memory. Figure 4-6 shows an example timing diagram for a Master Memory Write
command. In this figure, the device issues a request for the bus, is granted access, and
then writes a 32-bit Dword into system memory before releasing the bus. Note that in
this example, the data phase transfer takes 2 clock cycles. The timing of this transfer, in
this case, was controlled by TRDY.
Figure 4-6 Master Memory Write Timing
AMD
CLK
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
1 2 3 4 5 6 7 8
ADDR DATA
0111
PAR
BE
PAR
SERR
9 10
PERR
DEVSEL
PCI^REQ
PCI^GNT
The PCI Bus Interface Unit
19113A-12
4-7
AMD
4.5.6 Slave Configuration Read
The Slave Configuration Read command is used by the host CPU to read the PCI
configuration space in the Am53C974A. This provides the host CPU with information
concerning the device and its capabilities. This is a single cycle, non-burst 8-bit, 16-bit,
or 32-bit transfer. Slave Configuration Read cycles are fixed length cycles, i.e. the
Am53C974A will return TRDY on the 5th bus cycle of the transfer. Figure 4-7 shows the
Configuration Read cycle timing.
Figure 4-7 Slave Configuration Read Timing
CLK
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
1
2 3 4 5 6 7 8
ADDR DATA
1010
PAR
BE
PAR
SERR
PERR
4-8
IDSEL
DEVSEL
19113A-13
The PCI Bus Interface Unit
4.5.7 Slave Configuration Write
The Slave Configuration Write command is used by the host CPU to write the configuration space in the Am53C974A. This allows the host CPU to control basic activity of the
device, such as enable/disable, change I/O location, etc. This is a single cycle, nonburst 8-bit, 16-bit, or 32-bit transfer. Slave Configuration Write cycles are fixed length
cycles, i.e. the Am53C974A will return TRDY on the 5th bus cycle of the transfer. Figure
4-8 shows the Configuration Write cycle timing.
Figure 4-8 Slave Configuration Write Timing
AMD
CLK
FRAME
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
1
2 3 4 5 6 7 8
ADDR
1011
DATA
BE
PARPAR
SERR
PERR
IDSEL
DEVSEL
The PCI Bus Interface Unit
19113A-14
4-9
AMD
4.5.8 Master Memory Read Line
The Master Memory Read Line command is used by the Am53C974A when it will be
reading more than two 32-bit locations of memory. If the device needs to read less
than 2 Dwords of memory the Master Memory Read command is used. Figure 4-9
shows an example timing diagram for a Master Memory Read Line command. In this
figure, the device issues a request for the bus, is granted access, and then reads four
32-bit Dwords from system memory before releasing the bus. Note that all data phases
in this example take 2 clock cycles, this being determined by the timing of TRDY.
Figure 4-9 Master Memory Read Line Timing
CLK
1 2 3 4 5 6 7 8 9 10 11 12
FRAME
13 14
AD
C/BE
PAR
SERR
PERR
IRDY
TRDY
DEVSEL
PCI^REQ
ADDR
1110
PAR
BE
SERR
DATA
DATA
PAR
PERR PERR
DATA DATA
PAR
PERR
PAR
PERR
PAR
PCI^GNT
4-10
19113A-15
The PCI Bus Interface Unit
4.6 TRANSACTION TERMINATION
Termination of a PCI transaction may be initiated by either the master or the target.
During termination, the master remains in control to bring all PCI transactions to an
orderly and systematic conclusion regardless of what caused the termination. All
transactions are concluded when FRAME and IRDY are both deasserted, indicating an
IDLE cycle.
4.6.1 Target Initiated Termination
When the Am53C974A is a bus master, the cycles it produces on the PCI bus may be
terminated by the target in one of three different ways: Disconnect with data transfer,
disconnect without data transfer, and target abort.
4.6.1.1 Disconnect With Data Transfer
Figure 4-10 shows a disconnection in which one last data transfer occurs after the target
asserted STOP. STOP is asserted on clock 4 to start the termination sequence. Data is
still transferred during this cycle, since both IRDY and TRDY are asserted. The
Am53C974A terminates the current transfer with the deassertion of FRAME on clock 5
and then one clock cycle later with the deassertion IRDY. It finally releases the bus on
clock 6. The Am53C974A will re-request the bus after 2 clock cycles, if it wants to
transfer more data. The starting address of the new transfer will be the address of the
next untransferred data.
AMD
Figure 4-10 Disconnect With Data Transfer
CLK
FRAME
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
1 2 3 4 5 6 7 8
ADDR
DATA DATA
i
00000111
PAR PAR PAR
109
ADDR +8
11
i
0111
PCI^REQ
PCI^GNT
DEVSEL
is sampled by the Am53C974A
The PCI Bus Interface Unit
19113A-16
4-11
AMD
4.6.1.2 Disconnect Without Data Transfer
Figure 4-11 shows a target disconnect sequence during which no data is transferred.
STOP is asserted on clock 4 without TRDY being asserted at the same time. The
Am53C974A terminates the current transfer with the deassertion of FRAME on clock 5
and one clock cycle later with the deassertion of IRDY. It finally releases the bus on
clock 6. The Am53C974A will re-request the bus after 2 clock cycles to retry the last
transfer. The starting address of the new transfer will be the same address as the last
untransferred data.
Figure 4-11 Disconnect Without Data Transfer
CLK
1 2 3 4 5 6 7 8
FRAME
109
11
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
PCI^REQ
ADDRi ADDRi
DATA
00000111
PAR PAR
0111
PCI^GNT
4-12
DEVSEL
is sampled by the Am53C974A
19113A-17
The PCI Bus Interface Unit
4.6.1.3 Target Abort
Figure 4-12 shows a target abort sequence. The target asserts DEVSEL for one clock. It
then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort
sequence to indicate that it cannot service the data transfer and that it does not want the
transaction to be retried. Additionally, the Am53C974A cannot make any assumption
about the success of the previous data transfers in the current transaction. The
Am53C974A terminates the current transfer with the deassertion of FRAME on clock 5
and one clock cycle later with the deassertion of IRDY. It finally releases the bus on
clock 6.
Since data integrity is not guaranteed, the Am53C974A cannot recover from a target
abort event. Any on-going SCSI activity will be stopped immediately and an interrupt will
be generated. The ABORT and ERROR bits will be set in the DMA Status register. The
PCI configuration registers will not be cleared. RTABORT (bit 12) in the PCI Configuration Space Status register will be set to indicate that the Am53C974A has received a
target abort.
Figure 4-12 Target Abort
CLK
AMD
1 2 3 4 5 6
FRAME
C/BE
PAR
IRDY
TRDY
DEVSEL
STOP
PCI^REQ
AD
ADDR
DATA
00000111
PAR PAR
PCI^GNT
DEVSEL
is sampled by the Am53C974A
The PCI Bus Interface Unit
19113A-18
4-13
AMD
4.6.2 Master Initiated Termination
There are two scenarios besides normal completion of a transaction where the
Am53C974A will terminate the cycles it produces on the PCI bus. These are Preemption
and Master Abort.
4.6.2.1 Preemption
The central arbiter can take PCI^GNT to the Am53C974A away if the current bus
operation takes too long. This may happen during DMA bursts. When PCI^GNT is
removed and the value in the Latency Timer register has counted to zero, the
Am53C974A will finish the current transfer and then immediately release the bus. The
Latency Timer in PCI configuration space of the Am53C974A is programmable. The
Am53C974A will keep PCI^REQ asserted to regain bus ownership as soon as possible.
Figure 4-13 Preemption
CLK
1 2 3 4 5 6 7 8
FRAME
9
C/BE
PAR
IRDY
TRDY
DEVSEL
PCI^REQ
PCI^GNT
AD
DEVSEL
ADDR DATA DATA DATA
00000111
PAR PAR PAR
is sampled by the Am53C974A
4-14
19113A-19
The PCI Bus Interface Unit
4.6.2.2 Master Abort
The Am53C974A will terminate its cycle with a Master Abort sequence if DEVSEL is not
asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error
by the Am53C974A. Any on-going SCSI activity will be stopped immediately and an
interrupt will be generated. The ABORT and ERROR bits will be set in the DMA Status
Register. The PCI configuration registers will not be cleared. RMABORT (bit 13) in the
PCI Configuration Space Status register will be set to indicate that the Am53C974A has
terminated its transaction with a master abort.
Figure 4-14 Master Abort
CLK
FRAME
1 2 3 4 5 6 7 8
AMD
109
AD
C/BE
PAR
IRDY
TRDY
DEVSEL
PCI^REQ
PCI^GNT
DEVSEL
ADDR DATA
00000111
PAR PAR
is sampled by the Am53C974A
19113A-20
The PCI Bus Interface Unit
4-15
AMD
4.7 CONFIGURATION REGISTERS
PCI Configuration Registers are used to determine which devices are in the system as
well as to configure those devices. Configuration registers can be accessed any time
but only by PCI configuration read/write cycles. This space is divided into two regions:
A predefined header region and a device dependent region. The predefined header
region contains 64 bytes organized as 4 Dwords while the device dependent region may
contain up to 192 bytes also organized as 4 Dwords. The Am53C974A supports the full
64 byte predefined header and only 16 bytes of the device dependent region. Table 4-2
shows the configuration register map for both these regions. In Table 4-2, the first 64
bytes (00h – 3Fh) are the predefined header and the last 16 reserved bytes (40h – 4Fh)
belong to the device dependent space.
Table 4-2 Configuration Register Map
31 16 15 0 Address
Offset
Device ID Vendor ID 00h
Status Command 04h
Base Class Sub Class Prog. If. Revision ID 08h
Reserved* Header Type Latency Timer Reserved* 0Ch
Base Address 10h
Reserved* 14h
Reserved* 18h
Reserved* 1Ch
Reserved* 20h
Reserved* 24h
Reserved* 28h
Reserved* 2Ch
Expansion ROM Base Address 30h
Reserved* 34h
Reserved* 38h
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch
Reserved for Reserved for Reserved for Reserved for 40h**
SCSI Software SCSI Software SCSI Software SCSI Software
Reserved for Reserved for Reserved for Reserved for
SCSI Software SCSI Software SCSI Software SCSI Software 44h**
Reserved for Reserved for Reserved for Reserved for
SCSI Software SCSI Software SCSI Software SCSI Software 48h**
Reserved for Reserved for Reserved for Reserved for
SCSI Software SCSI Software SCSI Software SCSI Software 4Ch**
* Not Implemented on Am53C974A. Writes to these locations will have no effect; reads from these locations will return ‘00h’.
** Reserved for SCSI software.
All PCI compliant devices, including the Am53C974A, must support the
Device ID, Command and Status register
in the header portion. Implementation of the
Vendor ID,
other registers in this header is optional depending on device functionality. In Table 4-2,
an asterisk (*) means the location is NOT implemented on the Am53C974A while a
double asterisk (**) specifies that the location is reserved for use by the SCSI software.
Write operations to unimplemented registers in the configuration space are treated as
no-ops. That is, the access will be completed normally on the bus and the data discarded. Read accesses to unimplemented registers are completed normally and a data
value of ‘00h’ is returned.
4-16
The PCI Bus Interface Unit
4.7.1 Predefined Header Register Description
The following only describes the functions of the registers that are supported by the
Am53C974A. Refer to the
PCI registers.
4.7.1.1 Vendor ID Register
Address 00h READ ONLY
This register identifies the manufacturer of this device as Advanced Micro Devices, Inc.
(AMD) The Vendor ID is ‘1022h.’
4.7.1.2 Device ID Register
Address 02h READ ONLY
This register uniquely identifies this device within AMD’s product line. The Am53C974A
Device ID is ‘2020h.’
4.7.1.3 Command Register
Address 04h READ/WRITE
The Command Register is used to control the gross functionality of the device. It
controls a device’s ability to generate and respond to PCI bus cycles. To logically
disconnect the Am53C974A from all PCI bus cycles except Configuration cycles, a
value of zero should be written to this register. The Command Register is cleared by a
PCI reset.
PCI Local Bus Specification
AMD
for more detailed information on
15 14 13 12 11 10 9 8
Reserved Reserved Reserved Reserved Reserved Reserved FBTBEN SERREN
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
ADSTEP PERREN VGASNOOP MWIEN SCYCEN BMEN MEMEN IOEN
1 0 0 0 0 0 0 0
Bit 15:10 – Reserved
These 6 bits are reserved by the PCI Specification. Write operations to these locations
have no affect on the device. Read operations from these locations will return 0’s.
Bit 9 – FBTBEN – Fast Back-to-Back Enable
This bit is hardwired to a value of ‘0’ since Am53C974A back-to-back transactions are
only allowed to the same agent.
The PCI Bus Interface Unit
4-17
AMD
Bit 8 –
SERREN
–
SERR
Enable
This read/write bit is an enable bit for the SERR driver. When this bit is set to ‘1’, the
SERR driver is enabled. When this bit is reset to ‘0’, the SERR driver is disabled. This
bit and bit 6 (Parity Error Response) must be set to ‘1’ to report address parity errors.
This bit’s state is zero after a device reset.
Bit 7 – ADSTEP – Wait Cycle Control
This bit is hardwired to a value of ‘1’ since the Am53C974A always does address
stepping. The Am53C974A uses address stepping for the first address phase of each
bus master period. FRAME will be asserted on the second clock following the assertion
of PCI^GNT, indicating a valid address on the AD bus.
Bit 6 – PERREN – Parity Error Response Enable
This read/write bit controls the Am53C974A’s response to parity errors. When PERREN
is ‘0’ and the Am53C974A detects a parity error, it only sets the Detected Parity Error bit
in the PCI Configuration Space Status Register. When PERREN is ‘1’, the Am53C974A
asserts PERR on the detection of a data parity error. It also sets the DATAPERR bit (bit
8 in the PCI Configuration Space Status Register) when the data parity error occurred
during a master cycle. PERREN also enables reporting address parity errors through
the SERR pin and the SERR bit in the PCI Configuration Space Status Register. This bit
must be reset to ‘0’ after PCI^RST. Parity is still generated by the device even if this bit is
disabled (0).
Bit 5 – VGASNOOP – VGA Palette Snoop
This bit is hardwired to a value of ‘0’ since the Am53C974A is not a graphics device.
Bit 4 – MWIEN – Memory Write & Invalidate Enable
This bit is hardwired to a value of ‘0’ since the Am53C974A does not generate memory
write & invalidate commands. Instead, the memory write command must be used.
Bit 3 – SCYCEN – Special Cycles Enable
The Am53C974A will ignore all Special Cycle operations since this bit is hardwired to a
value of ‘0’.
Bit 2 – BMEN – Bus Master Enable
This read/write bit controls the Am53C974A’s ability to act as a master on the PCI bus.
When this bit is ‘0’, the device is disabled from generating PCI accesses. When this bit
is 1, the device is allowed to behave as a bus master.
Bit 1 – MEMEN – Memory Space Enable
This bit is programmable to allow support for expansion ROM accesses. This bit must
be set to ‘1’ before the Expansion ROM can be accessed. When this bit is ‘0’, access to
the boot ROM is disabled.
Bit 0 – IOEN – I/O Space Enable
This read/write bit controls the Am53C974A’s response to I/O space accesses. When
this bit is ‘0’, the device will not respond to I/O space accesses. When this bit is ‘1’, the
device is allowed to respond to I/O space accesses. The host must set IOEN before the
first I/O access to the device. The Base Address register at address (10H) must be
programmed with a valid I/O address before setting IOEN.
4-18
The PCI Bus Interface Unit
4.7.1.4 Status Register
Address 06h READ/WRITE
The Status register is used to record status information for PCI bus related activities.
Reads from this register function normally, however writes function differently. On a
write of ‘1’, bits will be reset (from 1 to 0), not set. For example, to reset bit 15 and not
affect any other bits, a value of 1000_0000_0000_0000 should be written to the Status
register.
15 14 13 12 11 10 9 8
PERR SERR RMABORT RTABORT STABORT DEVSEL1 DEVSEL0 DATAPERR
X X X X X 0 1 X
7 6 5 4 3 2 1 0
FBBOK Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Bit 15 – PERR – Detected Parity Error
This bit is used by the Am53C974A to report parity errors. This bit is set to ‘1’ whenever
the device detects a parity error. This bit is cleared by writing a ‘1’ to this location. The
value of this bit is undefined after a device reset. The Am53C974A samples the
AD(31:00), C/BE(3:0) and the PAR lines for a parity error at the following times:
AMD
In slave mode, during the address phase of any PCI bus command.
In slave mode, during the data phase of all I/O and Configuration Write commands
that select the Am53C974A.
In master mode, during the data phase of all Memory Read and Memory Read line
commands.
During the data phase of the memory write command, the Am53C974A sets the PERR
bit if the target reports a data parity error by asserting the PERR signal. PERR is not
affected by the state of the Parity Error Response Enable bit (bit 6 in the PCI Configuration Space Command register).
Bit 14 – SERR – Signaled System Error
This bit is set to ‘1’ when the SERR pin is asserted. This bit is cleared by writing a ‘1’ to
this location.
Bit 13 – RMABORT – Received Master Abort
As a bus master, the Am53C974A will set this bit to ‘1’ whenever its transaction is
terminated with a Master-abort. This bit is cleared by writing a ‘1’ to this location.
Bit 12 – RTABORT – Received Target Abort
As a bus master, the Am53C974A will set this bit to ‘1’ whenever its transaction is
terminated with a target-abort. This bit is cleared by writing a ‘1’ to this location.
Bit 11 – STABORT – Signaled Target Abort
As a target device, this bit is set to ‘1’ by the Am53C974A whenever it terminates a
transaction with a target-abort. This bit is cleared by writing a ‘1’ to this location.
The PCI Bus Interface Unit
4-19
AMD
Bit 10:9 – DEVSEL1:0 – DEVSEL Timing
These bits encode the timing of the DEVSEL signal. These bits are hardwired to a value
of ‘0’ and ‘1’ (for bits 10 and 9 respectively) since the Am53C974A uses medium
assertion timing for the DEVSEL signal. That is, DEVSEL is asserted two clocks after
FRAME is asserted. These bits are read-only and indicate the time that the Am53C974A
asserts DEVSEL for any bus command.
Bit 8 – DATAPERR – Data Parity Detected
DATAPERR is set when the Am53C974A detects a data parity error during master
mode and the Parity Error Response enable bit (bit 6 in the PCI Configuration Space
Command register) is set.
During the data phase of all Memory Read and Memory Read Line commands, the
Am53C974A checks for parity errors by sampling the AD(31:00), C/BE(3:0) and the PAR
lines. During the data phase of all Memory Write commands, the Am53C974A checks
the PERR input to detect whether the target has reported a parity error.
DATAPERR is set by the Am53C974A and is cleared by writing a ‘1’ to this location.
Writing a ‘0’ has no effect.
Bit 7 – FBBOK – Fast Back-to-Back Capable
This bit is hardwired to a value of ‘0’ since the Am53C974A is not capable of accepting
fast back-to-back transactions when the transactions are not to the same agent.
Bit 6–0 – Reserved
These 7 bits are reserved by the PCI Specification. Write operations to these locations
have no affect on the device. Read operations from these locations will return 0’s.
4.7.1.5 Revision ID Register
Address 08h READ ONLY
This register specifies the device specific revision number. On the Am53C974A, the
value of this register is ‘10h’.
4.7.1.6 Programming Interface Register
Address 09h READ ONLY
This register identifies the programming interface of this device. The value in this
register is ‘00h’.
4.7.1.7 Sub-Class Register
Address 0Ah READ ONLY
This register identifies this device as a SCSI Controller as defined by the PCI specification. The value in this register is ‘00h’.
4.7.1.8 Base Class Register
Address 0Bh READ ONLY
This register identifies this device as a Mass Storage controller as defined by the PCI
specification. The value in this register is ‘01h’.
4.7.1.9 Latency Timer Register
Address 0Dh READ/WRITE
This register specifies the maximum time the Am53C974A can continue with bus master
transfers after the system arbiter has removed PCI^GNT. The time is measured in CLK
4-20
The PCI Bus Interface Unit
cycles. The working copy of the timer will start counting down when the Am53C974A
asserts FRAME for the first time during a bus mastership period. The counter will freeze
at ZERO. When the counter is ZERO and PCI^GNT is deasserted by the system arbiter,
the Am53C974A will finish the current data phase and then immediately release the bus.
The value for the Am53C974A Latency Timer Register is programmable.
4.7.1.10 Header TYPE Register
Address 0Eh READ ONLY
7 6 5 4 3 2 1 0
FUNCT LAYOUT6 LAYOUT5 LAYOUT4 LAYOUT3 LAYOUT2 LAYOUT1 LAYOUT0
0 0 0 0 0 0 0 0
This is an 8-bit register that describes the format of the PCI Configuration Space
locations 10h to 3Ch and that identifies a device to be single or multi-function. This
register is located at address 0Eh in the PCI Configuration Space and is Read only.
The value contained in this register is 00h.
4.7.1.11 Base Address Register
Address 10h READ/WRITE
This read/write register defines the Base Address for the Am53C974A. Bit 0 is hardwired to a value of ‘1’ to indicate that the base address is mapped into the I/O space
while bit 1 is ‘reserved’ and will always return a ‘0’ when read. That is, a value of ‘01’ for
bits 1 and 0 respectively will be returned on reads.
AMD
31 30 29 28 27 26 25 24
IOBASE26 IOBASE25 IOBASE24 IOBASE23 IOBASE22 IOBASE21 IOBASE20 IOBASE19
X X X X X X X X
23 22 21 20 19 18 17 16
IOBASE18 IOBASE17 IOBASE16 IOBASE15 IOBASE14 IOBASE13 IOBASE12 IOBASE11
X X X X X X X X
15 14 13 12 11 10 9 8
IOBASE10 IOBASE9 IOBASE8 IOBASE7 IOBASE6 IOBASE5 IOBASE4 IOBASE3
X X X X X X X X
7 6 5 4 3 2 1 0
IOBASE2 IOBASE1 IOBASE0 IOSIZE2 IOSIZE1 IOSIZE0 Reserved IOSPACE
X 0 0 0 0 0 0 1
The PCI Bus Interface Unit
4-21
AMD
Bit 31:5 – IOBASE 26:0 – I/O Base Address
These bits are written by the host to specify the location of the Am53C974A in all of I/O
space. IOBASE 26:0 must be written with a valid address before the Am53C974A slave
I/O mode is turned on with the setting of the IOEN bit (bit 0 in the PCI Configuration
Space Command register).
When the Am53C974A is enabled for I/O mode (IOEN is set), it monitors the PCI bus for
a valid I/O command. If the value on AD(31:05) during the address phase of the cycles
matches the value of IOBASE, the Am53C974A will drive DEVSEL indicating it will
respond to the access.
IOBASE 26:2 is read and written by the host. IOBASE 1:0 is hardwired to ‘0’.
Bit 4:2 – IOSIZE 2:0 – I/O Size Requirements
IOSIZE 2:0 together with IOBASE 1:0 and bits 1 and 0 indicate the size of the I/O space the
Am53C974A requires. When the host writes a value of FFFF_FFFF to the Base Address register,
it will read back a value of ‘0’ in bits 6–1. This indicates an Am53C974A I/O space requirement of
128 bytes.
Bit 1 – Reserved
This bit is reserved. Writes to this location have no effect. Reads from this location will
return a ‘0’.
Bit 0 – IOSPACE – I/O Space Indicator
This bit indicates that the Base Address Register describes an I/O Base address. Writes
to this location have no effect. Read from this location will return a ‘1’.
4.7.1.12 Expansion ROM Base Address Register
Address 30h READ/WRITE
This is a 32-bit read/write register which is used to hold the expansion ROM Base
Address. It is used to specify the size and alignment of the expansion ROM for the
Am53C974A. It supports expansion ROMs of up to 64K.
31 30 29 28 27 26 25 24
ROM31 ROM30 ROM29 ROM28 ROM27 ROM26 ROM25 ROM24
X X X X X X X X
23 22 21 20 19 18 17 16
ROM23 ROM22 ROM21 ROM20 ROM19 ROM18 ROM17 ROM16
X X X X X X X X
15 14 13 12 11 10 9 8
ROM15 ROM14 ROM13 ROM12 ROM11 ROM10 ROM9 ROM8
0 0 0 0 0 0 0 0
4-22
7 6 5 4 3 2 1 0
ROM7 ROM6 ROM5 ROM4 ROM3 ROM2 ROM1 ROM0
0 0 0 0 0 0 0 0
The PCI Bus Interface Unit
Bit 31:16 – ROM31:16 – ROM Base Address
These bits are programmable for storing the expansion ROM base address. The values
in these bits are unknown after power-on or reset.
Bit 15:11 – ROM15:11 – ROM Alignment
These bits are hardwired to ‘0’, specifying a 64K alignment ROM support.
Bit 10:1 – ROM10:1 – Reserved
These bits are reserved as defined by the PCI specification, rev 2.0. These bits will
return a value of 0 when read.
Bit 0 – ROM0 – ROM Address DecodeEnable
This bit is used to enable/disable the ROM address space decoding. When this bit is ‘0’,
the expansion ROM address space is disabled. When this bit is ‘1’, address decoding is
enabled using the value programmed into bits 31:16 of this register. This bit will default
to ‘0’ after power-on or reset.
4.7.1.13 Interrupt Line Register
Address 3Ch READ/WRITE
The interrupt line register is used to communicate the routing of the interrupt. This
read/write register is written by the POST (Power-On Self Test) software as it initializes
the PCI devices in the system. The value in this register tells which input of the system
interrupt controller(s) the Am53C974A’s interrupt pin is connected to. Device drivers and
operating systems can use this information to determine priority and vector information.
Values in the register are system architecture specific. For example, in x86 based PCs,
the values in this register correspond to IRQ numbers (0–15) of the standard dual 8259
configuration. Values between 15 and 255 are reserved. Value 255 is defined as
“unknown” or “no connection” to the interrupt controller.
AMD
4.7.1.14 Interrupt Pin Register
Address 3Dh READ ONLY
This register indicates which interrupt pin the device is using. This register is hard wired
with a value of ‘1’ because the Am53C974A only uses INTA.
4.7.1.15 Min_Gnt Register
Address 3Eh READ ONLY
The Min_Gnt register is an 8-bit read only register. It is hardwired to a value of ‘04h’.
This value equals a burst period of 1 µs calculated at a 33 MHz clock rate. The register
value specifies the time in units of 1/4 microseconds. The host should use the value of
this register to determine the setting of the Am53C974A’s Latency Timer Register.
4.7.1.16 Max_Lat Register
Address 3Fh READ ONLY
The Max_Lat register is an 8-bit read only register. It is hardwired to a value of ‘28h’.
This value equals a PCI bus latency of 10 µs calculated at a 33 MHz clock rate. The
register value specifies the time in units of 1/4 microseconds. The host should use
the value of this register to determine the setting of the Am53C974A’s Latency
Timer Register.
The PCI Bus Interface Unit
4-23
AMD
4.7.2 Device Dependent Register Description
The Am53C974A implements 16 bytes (4 Dwords located at locations 40h, 44h, 48h,
and 4Ch) of the 192 byte device dependent registers. These 16 bytes are scratch data
registers provided for use by SCSI device drivers. Developers of SCSI device drivers for
the Am53C974A can use these register for their own needs provided that AMD’s SCSI
drivers are not used. If AMD SCSI drivers are used, these registers must not be
modified. Note that since these are scratch registers, they may be used to contain any
data. For example, AMD’s SCSI drivers for the Am53C974A uses these registers to hold
specific information concerning the state of the SCSI bus and each Target device
connected. Examples of information contained in these registers as used by AMD’s
drivers are current SCSI bus status for each device, synchronous parameters, protected/real mode driver initialization flags, etc. The next section describes how AMD’s
SCSI device drivers take advantage of these registers.
4.7.3 AMD’s Scratch Register Usage
The registers located at locations 40h, 44h, 48h, and 4Ch (Table 4-1) are four 32-bit
registers (16 bytes total) which are used by AMD’s SCSI device drivers to hold information about the state of the SCSI bus and the target devices connected. Table 4-3
illustrates how AMD’s SCSI software defines and uses these registers. In Table 4-3,
seven of the eight registers are used for target devices and one is used for the host.
That is, there is one Target Configuration register for each SCSI Target and one Host
Configuration register for the host.
Table 4-3 Scratch Register Definition for AMD’s PCSCSI Software
SCSI Configuration PCI Configuration
Register Byte Bits 15:0
0 41h, 40h SCSI Configuration Register 0
1 43h, 42h SCSI Configuration Register 1
2 45h, 44h SCSI Configuration Register 2
3 47h, 46h SCSI Configuration Register 3
4 49h, 48h SCSI Configuration Register 4
5 4Bh, 4Ah SCSI Configuration Register 5
6 4Dh, 4Ch SCSI Configuration Register 6
7 4Fh, 4Eh SCSI Configuration Register 7
The following define the SCSI configuration registers for target devices and Host
adapters for the Am53C974A SCSI software drivers.
4.7.3.1 Target Device Configuration Register Definition READ/WRITE
The Target Device Configuration Register layout is shown below. Bit placements follow
“Little Endian” ordering.
15 14 13 12 11 10 9 8
4-24
Reserved Reserved FSCSI SPD4 SPD3 SPD2 SPD1 SPD0
0 0 0 X X X X X
The PCI Bus Interface Unit
AMD
7 6 5 4 3 2 1 0
SOFF3 SOFF2 SOFF1 SOFF0 STATUS2 STATUS1 STATUS0 PRES
X X X X X X X X
Bits 15:14 – Reserved
These 2 bits are reserved by AMD’s SCSI software driver.
Bit 13 – FSCSI – Fast SCSI Drive Present
This bit identifies the Target as a Fast SCSI drive. A value of ‘1’ indicates that a Fast
drive is present, while a ‘0’ indicates either that a drive is not present, or that the drive is
not capable of sustaining fast synchronous SCSI transfers rates of 10 Mbytes/s. This bit
will default to a value of ‘0’.
Note: This register is defined by AMD’s PCSCSI Software and does not represent a
change in the chip’s functionality.
Bits 12:8 – SPD4:0 – Synchronous Period
These bits define the synchronous period negotiated for the SCSI target device.
Bits 7–4 – SOFF3:0 – Synchronous Offset
These bits define the synchronous offset negotiated for the SCSI target device in
number of bytes. A value of ‘0’ indicates Asynchronous transfers. Valid values are from
1 to 15 (bytes).
Bits 3:1 – STATUS2:0 – SCSI Bus Status
These bits define the current state of the SCSI Target Device relating to the SCSI Bus.
Valid values for the SCSI Bus Status are as follows:
Bits 3:1 SCSI Bus Status
000 Data Out Phase
001 Data In Phase
010 Command Phase
011 Status Phase
100 Idle
101 Active and Disconnected
110 Message Out Phase
111 Message In Phase
Bit 0 – PRES – Present
This bit is used to indicate that the target device is present and active. If this bit is set to
‘1’, then the target device is present on the SCSI bus and all other bits are considered
valid. If this bit is reset to ‘0’, then the target device is assumed to be not present on the
SCSI bus and all other bits must be reset to ‘0’. The exception to this case is if the
Target Present bit is reset to ‘0’ and the SCSI Bus Status bits are set to ‘1xx’ (where ‘x’
is a don’t care). In this case, the configuration register definition indicates the host
adapter target ID.
The PCI Bus Interface Unit
4-25
AMD
4.7.3.2 Host Configuration Register Definition READ/WRITE
The Host Adapter Device Configuration Register layout is shown below. Bit placements
follow “Little Endian” ordering.
15 14 13 12 11 10 9 8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
SBNV SBN2 SBN1 SBN0 HOST PROTECT RM TP
0 0 0 0 1 X X 0
Bits 15:9 – Reserved
These 7 bits are reserved by AMD’s SCSI software driver.
Bit 8 – RESET – SCSI Bus Reset Has Taken Place
If this bit is set to ‘1’, it indicates that a SCSI Bus Reset has occurred. This is useful for
Protected Mode/Real Mode driver SCSI controller sharing. If device configuration
parameters, such as Mode Select information or Synchronous Negotiation, have been
issued to the SCSI devices, these parameters may no longer be valid upon the SCSI
bus reset. When this bit is set, it indicates to the non-controlling driver that a Bus Reset
has occurred and that appropriate action should be taken.
Bit 7 – SBNV – Starting BIOS Number Valid
When set to ‘1’, this bit indicates that the Starting BIOS Number (SBN2:0, Bits 6–4) is
valid. When reset to ‘0’, the Starting BIOS Number is invalid.
Bit 6:4 – SBN2:0 – Starting BIOS Number
These bits are valid if the Starting BIOS Number Valid bit (bit 7) is set to ‘1’. This value
ranges from 0 to 7 and indicates the starting BIOS unit number of the SCSI BIOS. For
example, if the value is ‘1’, this indicates that the SCSI BIOS starts controlling fixed
disks at BIOS unit ‘81h’. If the value is ‘3’, SCSI BIOS fixed disks start at BIOS unit ‘83h’
and so on.
Bit 3 – HOST – Host
This bit is set to ‘1’ to indicate that the device associated with this register is a host
device.
Bit 2 – PROTECT – Protected Mode Driver Initialized
This bit is set to ‘1’ when a Protected Mode device driver initializes the SCSI controller.
A Real Mode driver that regains control due to a mode change (i.e. Windows to DOS or
Netware 3.X to DOS, etc.) will reset this bit to ‘0’ to indicate that once the Protected
Mode driver regains control of the SCSI controller, it must re-initialize itself in order to
continue proper operation. Upon re-initialization of the SCSI controller by the Protected
Mode driver, this bit will once again be set to ‘1’.
4-26
Bit 1 – RM – Real Mode Driver Initialized
This bit is set to ‘1’ when a Real Mode device driver initializes the SCSI controller. A
Protected Mode driver that loads and initializes will reset this bit to ‘0’ to indicate that if
and when the Real Mode driver regains control of the SCSI controller, it must re-initialize
The PCI Bus Interface Unit
AMD
itself in order to operate. Upon re-initialization of the SCSI controller by the Real Mode
driver, this bit will once again be set to ‘1’.
Bit 0 – TP – Target Present Bit
This bit is set to ‘0’ and is used in conjunction with Bit 3, which is set to ‘1’, to indicate
that this configuration register defines the Host configuration.
The PCI Bus Interface Unit
4-27
AMD
4-28
The PCI Bus Interface Unit
THE FAST SCSI BLOCK
5
5.1 FUNCTIONAL OVERVIEW
The functionality of the SCSI block is described in the following section. Topics to be
covered are:
Part-unique ID
SCSI FIFO Threshold
Data Transmission
REQ/ACK Control
Parity
Reset Levels
5.1.1 Part-Unique ID
The Am53C974A contains a part-unique ID code which is stored in the MSB of the
Current Transfer Count Register. The code reflects the chip’s revision level and family
code. This 8-bit code may be read when the following conditions are true.
After power up or a chip reset has occurred
Before the Current Transfer Counter ((B)+38h) is loaded
The part-unique ID code in Register ((B)+38h) will read as follows:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 1 0 0 1 0
5.1.2 SCSI FIFO Threshold
The threshold value for the SCSI FIFO is two bytes (one word). When this threshold is
reached, the SCSI block will indicate to the DMA engine that it is capable of receiving
or sending data bytes.
5.1.3 Data Transmission
Data transmission rates will vary from system to system, depending on the number of
devices configured on the SCSI bus, as well as the transfer rates that each individual
device is capable of sustaining.
Transfer rates for the Am53C974A are controlled by the FASTSCSI and FASTCLK bits
in Control Register Three, as well as by the Extended Timing Feature in Control
Register One. The chart below shows the effects of different bit configurations on
minimum asynchronous and synchronous cycle times.
The Fast SCSI Block
5-1
AMD
Ext. Timing Min Min Min
FASTCLK FASTSCSI Mode Cycles per Cycles per Cycles per
Cntl Reg 3 Cntl Reg 3 Cntl Reg 1 Data Setup Data Setup Period
Bit3 Bit4 Bit 7 Asynch Xfer Synch Xfer Synch Xfer
0 X 0 2 2 5
0 X 1 3 3 6
1 0 0 3 3 8
1 0 1 5 3 8
1 1 0 3 2 4
1 1 1 5 2 4
To achieve 10 MB/sec transmission rates, the following requirements must be true:
A 40 MHz clock (50% duty cycle) must be supplied to SCSICLK1.
The target must be able to sustain Fast SCSI timings
Bits 3 and 4 in Control Register Three must be set to ‘1’
The lower three bits of Register ((B)+24h), the Clock Conversion Factor Register
must be programmed to ‘000’
The lower 5 bits of the Synchronous Transfer Period Register ((B)+18h) must be set
to a value of ‘04h.’
Control Register Three contains two bits which modify the SCSI state machine to
produce both FAST and Normal SCSI timings. Synchronous data transmission rates
are dependent on the input clock frequency selected, as well as the transfer period.
The registers listed above should be programmed consistently.
Bits 4:0 in the Synchronous Transfer Period Register ((B)+18h) specify the timing
between the leading edges of consecutive REQ and ACK pulses during synchronous
transfers. For programming information, refer to the register level descriptions.
5.1.4 REQ/ACK Control
The assertion and deassertion time for the REQ and ACK signals may be controlled via
the Synchronous Offset Register ((B)+1Ch). Bits 7:6 control REQ/ACK deassertion
delay, while bits 5:4 control REQ/ACK assertion delay. The deassertion for REQ/ACK
may be moved ahead 0.5 clock cycles, or it may be delayed for up to 1.5 clock cycles.
Deassertion delay options depend on the status of the FASTCLK bit in Control Register
Three. Assertion delay for REQ/ACK can vary from 0 to 1.5 clock cycles.
For programming information, refer to the register level descriptions. The following
drawings illustrate the REQ/ACK assertion/deassertion feature:
5-2
The Fast SCSI Block
FASTCLK Enabled
CLK
REQ/ACK
AMD
FASTCLK Disabled
Synch Offset Reg
Note: Care must be taken in programming this feature, as it is possible to violate
SCSI-2 timing specifications.
5.1.5 Parity
Parity on the SCSI bus is such that the total number of logical ones on the data bus
including the parity bit must be odd. Parity checking features are implemented via two
bits in the Status Register and Control Register One. Parity checking can be implemented on data flowing in from the SCSI bus. Parity is always generated internally by
the Am53C974A for data moving onto the SCSI bus.
Synch Offset Reg
Binary Value:
CLK
REQ/ACK
Binary Value:
0 1 2 3 0 1 2 3
19113A-21
0 1 2 3 01 23
19113A-22
Feature Bit Name Bit # Register
Parity from SCSI Parity Error Reporting 4 Control Reg One ((B)+20h)
Parity Status Parity Error 5 Status Register ((B)+10h)
5.1.5.1 Parity From the SCSI Bus
The Parity Error Reporting Bit (Bit 4, Control Register One) applies parity checking on
all incoming bytes from the SCSI bus. This feature is cleared to ‘0’ by a hardware reset.
When this feature is enabled, the Am53C974A will check parity on all data received
from the SCSI bus. Any detected error will be flagged by setting bit 5 in the SCSI
Status Register, and ATN will be asserted on the SCSI bus. However, no interrupt
will be generated.
When this feature is disabled (bit 4 set to ‘0’), no parity check is done on incoming bytes;
rather, the Am53C974A generates parity internally for each byte. Note that the parity on
the PCI bus is generated internally and is distinct from the parity received from the
SCSI bus.
The Fast SCSI Block
5-3
AMD
5.1.6 Reset Levels
The Am53C974A has two reset pins and two reset commands that affect the SCSI
block. The PCI^RST pin resets the whole chip including the SCSI controller and the
PCI interface.
The Reset Device command causes almost the same effect on the SCSI controller that
the PCI^RST pin does. However, the Reset Device command has no effect on the PCI
interface. Also, after the Reset Device command has been issued, the user must issue a
NOP command before another command can be executed.
The Action of the PCI^RST signal or the Reset Device command is called Hard Reset.
The SCSI^RST pin is a bidirectional signal on the SCSI bus that resets a portion of the
SCSI logic when it is asserted by a device on the SCSI bus. Similarly, the Am53C974A
can assert the SCSI^RST signal to cause all of the other devices on the SCSI bus to
reset.
The Reset SCSI command causes the same effect on the SCSI controller that the
SCSI^RST pin does, except that this command also causes the SCSI^RST pin to be
asserted so that all other (external) devices on the SCSI bus are also reset. Once a
SCSI Reset command has been executed, the SCSI^RST signal will remain asserted
until a Hard Reset has occurred.
The action of the SCSI^RST signal and the Reset SCSI command is called Soft Reset.
In addition there is a third type of reset, called Disconnected Reset, that is caused by
certain sequences on the SCSI bus. These three types of reset are described in the
following sections.
5.1.6.1 Hard Resets: (H)
This reset occurs at power up, when the PCI^RST pin is asserted through external
hardware, or when the Reset Device command is issued by writing 02h to the SCSI
command register at ((B)+0Ch). Hard reset causes all chip functions to halt and resets
all internal state machines. It leaves the SCSI block in the disconnected state. It leaves
all SCSI registers in their default states.
In addition, if the Hard Reset is caused by the assertion of the PCI^RST pin, the
following actions occur.
The Command register in the PCI configuration space is cleared to zero.
(No other register in the configuration space is affected.)
The DMA CCB registers are set to their default values.
5.1.6.2 Soft Reset: (S)
This reset occurs either when the SCSI^RST pin on the SCSI bus is asserted or when
the Reset SCSI Bus command is issued (by writing 03h to the SCSI command register
at ((B)+0Ch). Soft reset causes the following actions to occur:
All SCSI bus signals except SCSI^RST are released.
5-4
The chip is returned to the Disconnected state.
An interrupt is generated if bit 6 in Control Register One is enabled.
The Fast SCSI Block
5.1.6.3 Disconnected Reset: (D)
This reset is caused by various commands or situations which cause the Am53C974A to
disconnect from the SCSI bus. Disconnected reset occurs when any of the following
conditions occur:
Target Disconnect, Disconnect Steps, and Terminate Steps
The Am53C974A is the Initiator and the SCSI bus moves to a Bus Free state.
The Selection or Reselection command terminates due to selection timeout.
Disconnected reset causes the following actions to occur:
All SCSI signals except SCSI^RST are deasserted.
The SCSI Command Register is initialized to empty.
The IS1 and IS0 bits in the Internal State Register, ((B)+18h), are cleared to 0.
Resets bit 6:4 in the Command Register.
The table below describes chip operations and features which are affected by the
various reset levels.
Chip Operation/Feature Reset Level
Deassert all SCSI signals except SCSIRST*
*SCSIRST cleared by Hard Reset only HSD
Reset bits 6:4 in the Command Register HSD
Command register FIFO initialized to empty HSD
Reset Internal State Bits in Registers (B)+18h and (B)+1Ch HS
Clear Internal State Register bits:
Enable select (IS2 = ‘0’) HS
Target (IS 0 = ‘0’) HSD
Initiator (IS 1:0 = ‘00’) HSD
Reset command sequence module HS
Reset DMA Interface HS
Reset bus-initiated selection/reselection module HS
Clear SCSI Status Register (B)+10h H
Clear Interrupt Status Register (B)+14h H
Release INT pin H
Deassert SCSIRST signal H
Synchronous Offset Register = ‘0’ H
Synchronous Transfer Period Register = ‘5’ H
Initialize SCSI FIFO to empty condition H
Clear all Control Registers H
Set Clock Conversion Factor = ‘2’ H
AMD
H = Hard Reset
S = Soft Reset
D = Disconnected Reset
The Fast SCSI Block
5-5
AMD
5.2 REGISTER DESCRIPTION
The Am53C974A SCSI registers are mapped to a double word address space as shown
in the table below. However, the actual register data occupies only the least significant
byte of the address. The register addresses are represented by the PCI Configuration
Base Address (B) and its corresponding offset value. The Base Address for the
Am53C974A is stored at register address (10h) in the PCI Configuration space.
Register
Acronym Address (Hex.) Register Description Type
CTCREG (B)+00 Current Transfer Count Register Low Read
STCREG (B)+00 Start Transfer Count Register Low Write
CTCREG (B)+04 Current Transfer Count Register Middle Read
STCREG (B)+04 Start Transfer Count Register Middle Write
FFREG (B)+08 SCSI FIFO Register Read/Write
CMDREG (B)+0C SCSI Command Register Read/Write
STATREG (B)+10 SCSI Status Register Read
SDIDREG (B)+10 SCSI Destination ID Register Write
INSTREG (B)+14 Interrupt Status Register Read
STIMREG (B)+14 SCSI Timeout Register Write
ISREG (B)+18 Internal State Register Read
STPREG (B)+18 Synchronous Transfer Period Register Write
CFIREG (B)+1C Current FIFO/Internal State Register Read
SOFREG1 (B)+1C Synchronous Offset Register Write
CNTLREG1 (B)+20 Control Register One Read/Write
CLKFREG (B)+24 Clock Factor Register Write
RES (B)+28 Reserved Write
CNTLREG2 (B)+2C Control Register Two Read/Write
CNTLREG3 (B)+30 Control Register Three Read/Write
CNTLREG4 (B)+34 Control Register Four Read/Write
CTCREG (B)+38 Current Transfer Count Register High/Part-Unique ID Code Read
STCREG (B)+38 Start Current Transfer Count Register High Write
RES (B)+3C Reserved Write
5-6
The Fast SCSI Block
AMD
5.2.1 Register Bit Map: Read
Register
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Xfer Cntr
XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
(B)+00h (07) (06) (05) (04) (03) (02) (01) (00)
Xfer Cntr
(B)+04h (15) (14) (13) (12) (11) (10) (09) (08)
Xfer Cntr
(B)+38h (23) (22) (21) (20) (19) (18) (17) (16)
FIFO
(B)+08h (07) (06) (05) (04) (03) (02) (01) (00)
Command
(B)+0Ch (06) (05) (04) (03) (02) (01) (00)
Status
(B)+10h OP ERROR MSG C/D I/O
XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
FIF0 FIFO FIFO FIFO FIFO FIFO FIFO FIFO
DMA CMD CMD CMD CMD CMD CMD CMD
INT ILLEGAL PARITY CTZ GCV PHASE PHASE PHASE
Interrupt SCSI INVALID DISC SVC SUCCESS RESEL SEL SEL
(B)+14h RST CMD REQ OP W/ATN
Internal State RES RES RES RES SYNCH INTERNAL INTERNAL INTERNAL
(B)+18h OFFSET FLAG STATE STATE STATE
Current FIFO/ INTERNAL INTERNAL INTERNAL CURRENT CURRENT CURRENT CURRENT CURRENT
Int State STATE STATE STATE FIFO FIFO FIFO FIFO FIFO
(B)+1Ch
Control 1 XTEND DISABLE RES PAR ERROR RES ID ID ID
(B)+20h TIMING INT REPORT (02) (01) (00)
Clk Factor RES RES RES RES RES CLK CLK CLK
(B)+24h FACTOR FACTOR FACTOR
Reserved RES RES RES RES RES RES RES RES
(B)+28h
Control 2 RES ENABLE RES RES SCSI-2 RES RES RES
(B)+2Ch FEATURES FEATURES
Control 3 ADD’L QTAG GROUP2 FAST FAST RES RES RES
(B)+30h ID CHK EN CMD SCSI CLOCK
Control 4 GLITCH GLITCH POWER RES RES ACTIVE RES RES
(B)+34h EATER EATER DOWN NEG
Reserved RES RES RES RES RES RES RES RES
(B)+3Ch
The Fast SCSI Block
5-7
AMD
5.2.2 Register Bit Map: Write
Register
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Xfer Cntr
(B)+00h (07) (06) (05) (04) (03) (02) (01) (00)
XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
Xfer Cntr XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
(B)+04h (15) (14) (13) (12) (11) (10) (09) (08)
Xfer Cntr XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT XFER CNT
(B)+38h (23) (22) (21) (20) (19) (18) (17) (16)
FIFO FIF0 FIFO FIFO FIFO FIFO FIFO FIFO FIFO
(B)+08h (07) (06) (05) (04) (03) (02) (01) (00)
Command DMA CMD CMD CMD CMD CMD CMD CMD
(B)+0Ch (06) (05) (04) (03) (02) (01) (00)
Destination ID RES RES RES RES RES DEST DEST DEST
(B)+10h ID ID ID
Time Out TIME TIME TIME TIME TIME TIME TIME TIME
(B)+14h (07) (06) (05) (04) (03) (02) (01) (00)
Synch Xfer Pd RES RES RES SYNCH SYNCH SYNCH SYNCH SYNCH
(B)+18h PERIOD PERIOD PERIOD PERIOD PERIOD
Synch Offset REQ/ACK REQ/ACK REQ/ACK REQ/ACK SYNCH SYNCH SYNCH SYNCH
(B)+1Ch DEASSERT DEASSERT ASSERT ASSERT OFFSET OFFSET OFFSET OFFSET
Control 1 XTEND DISABLE RES PAR ERROR RES ID ID ID
(B)+20h TIMING INT REPORT (02) (01) (00)
Clk Factor RES RES RES RES RES CLK CLK CLK
(B)+24h FACTOR FACTOR FACTOR
Reserved RES RES RES RES RES RES RES RES
(B)+28h
Control 2 RES ENABLE RES RES RES RES RES RES
(B)+2Ch FEATURES
Control 3 ADD’L RES RES FAST FAST RES RES RES
(B)+30h ID CHK SCSI CLOCK
Control 4 GLITCH GLITCH POWER RES ACTIVE ACTIVE RES RES
(B)+34h EATER EATER DOWN NEG NEG
Reserved RES RES RES RES RES RES RES RES
(B)+3Ch
5-8
The Fast SCSI Block
5.2.3 Register Descriptions
The values shown below each bit reflect register reset values. The register shall default
to these values following a power-up or chip reset. Bit level descriptions are valid for the
LSB at each address location. Remaining bytes at each address location are ‘reserved.’
5.2.3.1 Current Transfer Count Register (CTCREG)
Address [(B)+00h, (B)+04h, (B)+38h] READ ONLY
Address (B)+38h
7 6 5 4 3 2 1 0
CRVL23 CRVL22 CRVL21 CRVL20 CRLV19 CRVL18 CRVL17 CRVL16
X X X X X X X X
Address (B)+04h
7 6 5 4 3 2 1 0
CRVL15 CRVL14 CRVL13 CRVL12 CRLV11 CRVL10 CRVL9 CRVL8
X X X X X X X X
Address (B)+00h
7 6 5 4 3 2 1 0
AMD
CRVL7 CRVL6 CRVL5 CRVL4 CRLV3 CRVL2 CRVL1 CRVL0
X X X X X X X X
Bit 23:0 – CRVL 23:0 – Current Value
This is a three-byte register which decrements to keep track of the number of bytes
transferred during a DMA transfer. Reading these registers returns the current value of
the counter. The counter will decrement by one for every byte and by two for every word
transferred. The transaction is complete when the count reaches zero, and bit 4 of the
SCSI Status Register ((B)+10h) is set. Should the sequence terminate early, the sum of
the values in the Current FIFO ((B)+1Ch) and the Current Transfer Count Register
reflect the number of bytes remaining.
The least significant byte is located at address ((B)+00h), the middle byte is located at
address ((B)+04h), and the most significant byte is located at address ((B)+38h).
Register ((B)+38h) extends the total width of the register from 16 to 24 bits, and is only
enabled when the Enable Features bit (bit 6) of Control Register Two is set to a value
of ‘1’.
These registers are automatically loaded with the values in the Start Transfer Count
Register every time a DMA command is issued. However, following a chip or power on
reset, up until the time register ((B)+38h) is loaded, the Am53C974A’s part-unique ID
can be obtained by reading register ((B)+38h).
The value in the Current Transfer Count Register will be decremented as follows:
Asynch Data In: active edge of ACK
Synch Data In: active edge of DACK
Data Out: active edge of DACK
The Fast SCSI Block
5-9
AMD
5.2.3.2 Start Transfer Count Register (STCREG)
Address [(B)+00h, (B)+04h, (B)+38h] WRITE
Address (B)+38h
7 6 5 4 3 2 1 0
STVL23 STVL22 STVL21 STVL20 STVL19 STVL18 STVL17 STVL16
X X X X X X X X
Address (B)+04h
7 6 5 4 3 2 1 0
STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8
X X X X X X X X
Address (B)+00h
7 6 5 4 3 2 1 0
STVL7 STVL6 STVL5 STVL4 STVL3 STVL2 STVL1 STVL0
X X X X X X X X
Bit 23:0 – STVL 23:0 – Start Value
This is a three-byte register which contains the number of bytes to be transferred during
a DMA operation. The value in the Start Transfer Count Register must be programmed
prior to command execution. The value programmed in this register should be the same
as the value programmed in the DMA Starting Transfer Counter ((B)+44h).
The least significant byte is located at address ((B)+00h), the middle byte is located at
address ((B)+04h), and the most significant byte is located at address ((B)+38h).
Register ((B)+38h) extends the total width of the register from 16 to 24 bits, and is only
enabled when the Enable Features bit (bit 6) of Control Register Two is set to a value of
‘1’. This sets the maximum transfer count to 16 MBytes. When a value of ‘0’ is written to
these registers, the transfer count will be set to the maximum.
These registers retain their value until overwritten, and are therefore unaffected by a
hardware or software reset. This reduces programming redundancy since it is no longer
necessary to reprogram the count for subsequent DMA transfers of the same size.
5.2.3.3 SCSI FIFO Register (FFREG)
Address (B)+08h READ/WRITE
7 6 5 4 3 2 1 0
FF7 FF6 FF5 FF4 FF3 FF2 FF1 FF0
0 0 0 0 0 0 0 0
Bit 7:0 – FF 7:0 – FIFO
The FIFO on the Am53C974A is 16 bytes deep and is used to transfer SCSI data to and
from the Am53C974A. The FIFO may be accessed via a read or write to this register.
This is the only register that can be accessed with REQ or ACK. This register is reset to
zero by hardware or software reset or if the Clear FIFO command is issued.
5-10
The Fast SCSI Block
5.2.3.4 SCSI Command Register (CMDREG)
Address (B)+0Ch READ/WRITE
7 6 5 4 3 2 1 0
DMA CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
X X X X X X X X
Commands to the Am53C974A are issued by writing to this register which is two bytes
deep. Commands may be queued, and will be read from the bottom of the queue. At
the completion of the bottom command, the top command, if present, will drop to the
bottom of the register to begin execution. All commands are executed within six clock
cycles of dropping to the bottom of the SCSI Command Register, with the exception of
the Reset SCSI Bus, Reset Device, and DMA Stop commands. These commands are
not queued and are executed within four clock cycles of being loaded into the top this
register.
Interrupts are generated upon completion of some commands. Should back-to-back
commands generate interrupts, and the first interrupt has not been serviced, the
interrupt from the second (top) command will be stacked behind the first. The SCSI
Status Register ((B)+10h), Interrupt Register ((B)+14h), and Internal State Register
((B)+18h) will be updated to reflect the second interrupt after the microprocessor
services the first interrupt.
Reading this register will return the command currently being executed (or the last
command executed if there are no pending commands). When this register is cleared,
existing commands will be terminated and any queued commands will be ignored.
However, clearing this register does not reset the bits to ‘00h’.
AMD
Under the following conditions, the SCSI Command Register will be cleared and
maintained in a reset state (00h) until the host services the Interrupt Status Register
((B)+18h).
Illegal Command
SCSI Bus reset or disconnect
Completion of
Bus-initiated Selection or Reselection
Select command
Reselect command (if ATN is asserted)
Target disconnect or Terminate command
Selection or reselection timeout
Bad parity received in Target mode
ATN asserted in Target mode
Receiving a message while in Target mode and ATN is deasserted before completion
Not in Message In phase for the second byte of the Initiator Command
Complete Steps
Unexpected phase change during an Information Transfer or Transfer Pad Bytes
command
Bit 7 – DMA – Direct Memory Access
When set, this bit notifies the device that the command is a DMA instruction, when reset
it is a non-DMA instruction.
The Fast SCSI Block
5-11
AMD
For DMA instructions the Current Transfer Count Register (CTCREG) will be loaded
with the contents of the Start Transfer Count Register (STCREG). The data is then
transferred and the CTCREG is decremented for each byte until it reaches zero. Data
is transferred between system memory and the SCSI bus via the bus-mastering
DMA engine.
Non-DMA instructions do not modify the Transfer Count Registers ((B)+00h, (B)+04h,
and (B)+38h), since the number of bytes transferred is a function of the operation rather
than the transfer count. These type of instructions move data between the SCSI FIFO
and the SCSI bus, and requires host processor intervention to handle data transmission
between the SCSI FIFO and memory.
Bits 6:0 – CMD 6:0 – Command 6:0
These command bits decode the commands that the device needs to perform. There
are a total of 31 commands grouped into four categories. The groups are Initiator
Commands, Target Commands, Selection/Reselection Commands and General
Purpose Commands. See Section 5.3 for descriptions of these commands.
5.2.3.5 SCSI Status Register (STATREG)
Address (B)+10h READ ONLY
7 6 5 4 3 2 1 0
INT IOE PE CTZ GCV MSG C/D I/O
0 0 0 0 X X X X
This read-only register contains flags which indicate the status of the chip and the
current phase of the SCSI bus. These bits are read in conjunction with the Interrupt
Status Register ((B)+14h) to determine the reason for the interrupt. This register should
always be read prior to servicing the Interrupt Status Register (INSTREG) since bits 7:3
will be reset to ‘0’ once the Interrupt Status Register is read. If command stacking is
used, the phase bits may be latched by setting the ENF bit (Control Register Two, bit 6).
With this feature enabled, the SCSI bus phase of the last complete command (preceding the interrupt) will be latched by bits 2:0.
Bits 7:3 are reset to ‘0’ during a hardware reset.
Bit 7 – INT – Interrupt
The INT bit is set when the SCSI block detects an interrupt condition. This bit will
be cleared by a hardware or software reset. Reading the Interrupt Status Register
((B)+14h) will deassert the interrupt output and also clear this bit.
Note: SCSI interrupt conditions will also be flagged in the DMA Status Register
((B)+54h, Bit 4).
Bit 6 – IOE – Illegal Operation Error
The IOE bit is set when an illegal operation is attempted. This condition will not cause
an interrupt, and will therefore be detected by reading the Status Register ((B)+10h)
while servicing another interrupt. The following conditions will cause the IOE bit to
be set:
5-12
DMA and SCSI transfer directions are opposite.
FIFO overflows or data is overwritten.
In Initiator mode and unexpected phase change detected during synchronous data
transfer.
The Fast SCSI Block
AMD
Command Register overwritten.
This bit is cleared by reading the Interrupt Status Register ((B)+14h) or by a hard or soft
reset.
Bit 5 – PE – Parity Error
The PE bit is set if any of the parity checking options are enabled and the device detects
a parity error on bytes sent or received on the SCSI Bus. Parity options are controlled by
bit 4 in Control Register One ((B)+20h), and by bit 2 in Control Register Two ((B)+2Ch).
Detection of a parity error condition will not cause an interrupt but will be reported with
other interrupt causing conditions.
This bit will be cleared by reading the Interrupt Status Register ((B)+14h) or by a hard or
soft reset.
Bit 4 – CTZ – Count To Zero
The CTZ bit is set when the Current Transfer Count Register ((B)+00h, (B)+04h,
(B)+38h) has decremented to zero. This bit is reset when the Current Transfer Count
Register is re-loaded. Reading the Interrupt Status Register ((B)+14h) will not affect this
bit. This bit will however be cleared by a hard or soft reset.
Note: A non-DMA NOP will not reset the CTZ bit since it does not load the Current
Transfer Count Register. However, a DMA NOP will reset this bit since it loads the Current Transfer Count Register.
Bit 3 – GCV – Group Code Valid
The GCV bit is set if the group code field in the Command Descriptor Block (CDB) is one
that is defined by the ANSI Committee in their document X3.131 – 1986. If the SCSI-2
Features Enable (S2FE) bit in the Control Register 2 ((B)+2Ch) is set, Group 2 commands will be treated as 10-byte commands and the GCV bit will be set. If S2FE is reset
then Group 2 commands will be treated as reserved commands. Group 3 and 4
commands will always be considered reserved commands. The device will treat all
reserved commands as 6-byte commands. Group 6 commands will always be treated as
vendor unique 6-byte commands and Group 7 commands will always be treated as
vendor unique 10-byte commands.
The GCV bit is cleared by reading the Interrupt Status Register (INSTREG at (B)+14h)
or by a hard or soft reset.
Bit 2 – MSG – Message
Bit 1 – C/D – Command/Data
Bit 0 – I/O – Input/Output
The MSG, C/D and I/O bits together are referred to as the SCSI Phase bits. They
indicate the phase of the SCSI bus. These bits may be latched or unlatched depending
on whether or not the ENF bit in Control Register Two is set. In the latched mode the
SCSI phase bits are latched at the end of a command and the latch is opened when the
Interrupt Status Register ((B)+14h) is read. In the unlatched mode, they indicate the
real-time phase of the SCSI bus.
The Fast SCSI Block
5-13
AMD
Bit 2 Bit 1 Bit 0
MSG C/D I/O SCSI Phase
1 1 1 Message In
1 1 0 Message Out
1 0 1 Reserved
1 0 0 Reserved
0 1 1 Status
0 1 0 Command
0 0 1 Data In
0 0 0 Data Out
5.2.3.6 SCSI Destination ID Register (SDIDREG)
Address (B)+10h WRITE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved DID2 DID1 DID0
0 0 0 0 0 X X X
Bit 7:3 – Reserved
Bit 2:0 – DID 2:0 – Destination ID
The DID 2:0 bits are the encoded SCSI ID of the device on the SCSI bus which needs to
be selected or reselected. At power-up the state of these bits is undefined. The DID 2:0
bits are not affected by reset.
DID2 DID1 DID0 SCSI ID
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 0
5.2.3.7 Interrupt Status Register (INSTREG)
Address (B)+14h READ ONLY
7 6 5 4 3 2 1 0
SRST ICMD DIS SR SO RESEL SELA SEL
0 0 0 0 0 0 X X
The Interrupt Status Register (INSTREG) indicates the reason for the interrupt. This
register is used with the SCSI Status Register ((B)+10h) and Internal State Register
((B)+18h) to determine the reason for the interrupt. Reading the Interrupt Status
Register will clear all three registers. Therefore the SCSI Status Register ((B)+10h) and
Internal State Register ((B)+18h) should be examined prior to reading this register.
5-14
This register should only be read when an interrupt is pending. All bits will be cleared to
‘0’ by a hardware reset.
The Fast SCSI Block
AMD
Bit 7 – SRST – SCSI Reset
The SRST bit will be set if a SCSI Reset is detected and SCSI reset reporting is enabled
via the DISR (bit 6) of Control Register One ((B)+20h).
Bit 6 – ICMD – Invalid Command
The ICMD bit will be set if the device detects an illegal command code. This bit is also
set if a command code is detected from a mode that is different from the mode the
device is currently in. Once set, an invalid command interrupt will be generated.
Bit 5 – DIS – Disconnected
The DIS bit can be set in the Target or the Initiator mode when the device disconnects
from the SCSI bus. In the Target mode this bit will be set if a Terminate or a Command
Complete steps causes the device to disconnect from the SCSI bus. In the Initiator
mode this bit will be set if the Target disconnects; while in Idle mode, this bit will be set if
a Selection or Reselection timeout occurs.
Bit 4 – SR – Service Request
The SR bit can be set in the Target or the Initiator mode when another device on the
SCSI bus has a service request. In the Target mode, this bit will be set when the Initiator
asserts the ATN signal. In the Initiator mode, this bit is set when a Command Steps
Successfully Completed Command is issued.
Bit 3 – SO – Successful Operation
The SO bit can be set in the Target or the Initiator mode when an operation has
successfully completed. In the Target mode this bit will be set when any Target or Idle
state command is completed. In the Initiator mode this bit is set after a Target has been
successfully selected, after a command has successfully completed and after an
information transfer command when the Target requests a Message In phase.
Bit 2 – RESEL – Reselected
The RESEL bit is set at the end of the Reselection phase indicating that the device has
been reselected as an Initiator.
Bit 1 – SELA – Selected with Attention
The SELA bit is set at the end of the selection phase indicating that the device has been
selected as a Target by the Initiator and that the ATN signal was active during Selection.
Bit 0 – SEL – Selected
The SEL bit is set at the end of the selection phase indicating that the device has been
selected as a Target by the Initiator and that the ATN signal was inactive during
Selection.
5.2.3.8 SCSI Timeout Register (STIMREG)
Address (B)+14h WRITE
7 6 5 4 3 2 1 0
STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 STIM1 STIM0
X X X X X X X X
This register determines how long the Initiator will wait for a response to a Selection
before timing out. It should be set to yield 250 ms to comply with ANSI standards for
The Fast SCSI Block
5-15
AMD
SCSI. The maximum time out period may be calculated using the following formulas.
A hardware reset will clear this register.
Bit 7:0 – STIM 7:0 – SCSI Timer
The value loaded in STIM 7:0 can be calculated as shown below:
STIM 7:0 = [(SCSI Time Out) (Clock Frequency) / (8192 (Clock Factor))]
Example:
SCSI Time Out (in seconds): 250 ms.
(Recommended by the ANSI Standard) = 250 x 10
Clock Frequency: 40 MHz. (assume) = 40 x 10
Clock Factor: 8 (See Clock Factor Register)
STIM 7:0 = (250 x 10–3) X (40 x 106) / (8192 (8)) = 152.59 decimal
The decimal value of 152.59 must be rounded up to 153 (the next integer value), and
its hexadecimal value of ‘99h’ should be written to this register.
5.2.3.9 Internal State Register (ISREG)
Address (B)+18h READ ONLY
7 6 5 4 3 2 1 0
6
Hz.
–3
s.
Reserved Reserved Reserved Reserved SOF IS2 IS1 IS0
X X X X 0 0 0 0
The lower four bits of this register track the progress of a sequence-type command. It is
updated after each successful completion of an intermediate operation. If an error
occurs, the host can read this register to determine the point where the command failed
and take the necessary procedure for recovery. Reading the Interrupt Status Register
((B)+14h) while an interrupt is pending will clear this register. A hard or soft reset will
also clear this register.
Bit 7:4 – Reserved
Bit 3 – SOF – Synchronous Offset Flag
The SOF is reset when the Synchronous Offset Register ((B)+1Ch) has reached its
maximum value of 15.
Note: The SOF bit is active LOW.
Bit 2:0 – IS 2:0 – Internal State
The IS 2:0 bits along with the Interrupt Status Register ((B)+14h) indicate the completion
status of certain device commands. Certain commands cause the contents of the 3-bit
Internal State register to be changed at several steps in the execution process. The
value left in this register when the command terminates along with the contents of the
Interrupt Status register indicate how far the execution had proceeded prior to the
command termination. The following status decode tables show how to interpret the
Internal State register after these commands have terminated.
5-16
The Fast SCSI Block
Status Decode:
Initiator Select without ATN Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 20 Arbitration steps completed. Selection time-out
occurred, then disconnected
4 18 Selection without ATN steps fully executed
3 18 Sequence halted during command transfer due
to premature phase change (Target)
2 18 Arbitration and selection completed; sequence
halted because Target failed to assert command
phase
Initiator Select with ATN Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 20 Arbitration steps completed; Selection time–out
occurred then disconnected
4 18 Selection with ATN steps fully executed
3 18 Sequence halted during command transfer due
to premature phase change; some CDB bytes
may not have been sent; check FIFO flags
2 18 Message out completed; sent one message byte
with ATN true, then released ATN; sequence
halted because Target failed to assert command
phase after message byte was sent
0 18 Arbitration and selection completed; sequence
halted because Target did not assert message
out phase; ATN still driven by the Am53C974A
Initiator Select with ATN3 Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 20 Arbitration steps completed; Selection time-out
occurred then disconnected
4 18 Selection with ATN3 steps fully executed
3 18 Sequence halted during command transfer due
to premature phase change; some CDB bytes
may not have been sent; check FIFO flags
2 18 One, two, or three message bytes sent;
sequence halted because Target failed to assert
command phase after third message byte or
prematurely released message out phase; ATN
released only if third message byte was sent
0 18 Arbitration and selection completed; sequence
halted because Target did not assert message
out phase; ATN still driven by the Am53C974A
AMD
The Fast SCSI Block
5-17
AMD
Status Decode (continued):
Initiator Select with ATN and Stop Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 20 Arbitration steps completed; Selection time-out
occurred then disconnected
0 18 Arbitration and selection completed; sequence
halted because Target did not assert message
out phase; ATN still driven by the Am53C974A
1 18 Message out completed; one message byte
sent; ATN on
Target Selected without ATN Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
2 11 Selected; received entire CDB; check group
code valid bit; Initiator asserted ATN in
command phase
1 11 Sequence halted in command phase due to
parity error; some CDB bytes may not have been
received; check FIFO flags; Initiator asserted
ATN in command phase
2 01 Selected; received entire CDB; check group
code valid bit
1 01 Sequence halted in command phase because of
parity error; some CDB bytes may not have been
received; check FIFO flags
0 01 Selected; loaded bus ID into FIFO; null-byte
message loaded into FIFO
Target Select with ATN Steps, SCSI-2 Bit NOT SET
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
2 12 Selection complete; received one message byte
and entire CDB; Initiator asserted ATN during
command phase
1 12 Halted in command phase; parity error and
ATN true
0 12 Selected with ATN; stored bus ID and one
message byte; sequence halted because
ATN remained true after first message byte
2 02 Selection completed; received one message
byte and the entire CDB
1 02 Sequence halted in command phase because of
parity error; some CDB bytes not received;
check group code valid bit and FIFO flags
0 02 Selected with ATN; stored bus ID and one
message byte; sequence halted because of
parity error or invalid ID message
5-18
The Fast SCSI Block
Status Decode (continued):
Target Select with ATN Steps, SCSI-2 Bit SET
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
6 12 Selection completed; received three message
bytes and entire CDB. ATN is true
5 12 Halted in command phase; parity error and
ATN true
4 12 ATN remained true after third message byte
2 12 Selection completed; Initiator deasserts ATN
after receipt of one message byte; entire
CDB received. ATN asserted during
command phase
1 12 Sequence halted during command phase;
Initiator deasserts ATN after receipt of one
message byte; parity error and ATN true
0 12 Selected with ATN; stored bus ID and one
message byte; sequence halted because of
parity error or invalid ID message; ATN is true
6 02 Selection completed; received three message
bytes and the entire CDB
5 02 Received three message bytes then halted in
command phase because of parity error; some
CDB bytes not received; check group code valid
bit and FIFO flags
4 02 Parity error during second or third message byte
2 02 Selection completed; Initiator deasserts ATN
after receipt of one message byte; entire CDB
received
1 02 Sequence halted during command phase
because of parity error; Initiator deasserts ATN
after receipt of one message byte; some bytes of
CDB not received; check FIFO flags and group
code valid bit
0 02 Selected with ATN; stored bus ID and one
message byte; sequence halted because of
parity error or invalid ID message
Target Receive Command Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
2 18 Received entire CDB; Initiator asserted ATN
1 18 Sequence halted during command transfer due
to parity error; ATN asserted by Initiator
2 08 Received entire CDB
1 08 Sequence halted during command transfer due
to parity error; check FIFO flags
AMD
The Fast SCSI Block
5-19
AMD
Status Decode (continued):
Target Disconnect Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
2 28 Disconnect steps fully executed; disconnected;
bus is free
1 18 Two message bytes sent; sequence halted
because Initiator asserted ATN
0 18 One message byte sent; sequence halted
because Initiator asserted ATN
Target Terminate Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
2 28 Terminate steps fully executed; disconnected;
bus is free
1 18 Status and message bytes sent; sequence
halted because Initiator asserted ATN
0 18 Status byte sent; sequence halted because
Initiator asserted ATN
Target Command Complete Steps
Internal State Interrupt Status
Register ((B)+18h) Register ((B)+14h) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 18 Status byte sent; sequence halted because
Initiator set ATN
2 08 Command complete steps fully executed
5.2.3.10 Synchronous Transfer Period Register (STPREG)
Address (B)+18h WRITE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved STP4 STP3 STP2 STP1 STP0
X X X 0 0 1 0 1
The Synchronous Transfer Period Register (STPREG) contains a 5-bit value indicating
the number of clock cycles each byte will take to be transferred over the SCSI bus in
synchronous mode. The STPREG defaults to 5 clocks/byte after a hard or soft reset.
Bits 7:5 – Reserved
Bits 4:0 – STP 4:0 – Synchronous Transfer Period
The STP 4:0 bits are programmed to specify the synchronous transfer period or the
number of clock cycles for each byte transferred in the synchronous mode. The
minimum value for STP 4:0 is 4 clocks/byte.
5-20
The Fast SCSI Block
AMD
The following tables list Synchronous Transfer Period options for both Fast and Normal
SCSI modes. Table entries follow the binary code, and may be extrapolated if necessary. The synchronous transfer requirements as defined by the ANSI specification are
listed for each instance.
Setup Hold Assert/Negate
Normal synchronous 55 ns 100 ns 90 ns
Fast Synchronous 25 ns 35 ns 30 ns
FASTSCSI enabled
FASTCLK enabled, 40 MHz clock frequency:
Data hold: 2 cycles Assert: 2 cycles
STP4-0 Clocks per Data Setup Negate Transfer Rate
(hex) cycle (cycles) (cycles) (MBytes/sec)
4 4 2 2 10.0
5 5 3 3 8.0
6 6 4 4 6.6
7 7 5 5 5.7
8 8 6 6 5.0
9 9 7 7 4.4
A 10 8 8 4.0
B 11 9 9 3.6
C 12 10 10 3.3
D 13 11 11 3.0
FASTSCSI disabled
FASTCLK enabled, 40 MHz clock frequency:
Data hold: 5 cycles Assert: 4 cycles
STP4-0 Clocks per Data Setup Negate Transfer Rate
(hex) cycle (cycles) (cycles) (MBytes/sec)
7 8 3 4 5.0
8 9 4 5 4.4
9 10 5 6 4.0
A 11 6 7 3.6
B 12 7 8 3.3
C 13 8 9 3.0
D 14 9 10 2.8
E 15 10 11 2.6
F 16 11 12 2.5
10 17 12 13 2.3
11 18 13 14 2.2
12 19 14 15 2.1
13 20 15 16 2.0
The Fast SCSI Block
5-21
AMD
FASTSCSI disabled
FASTCLK disabled, 25 MHz clock frequency:
Data hold: 3 cycles Assert: 2.5 cycles
STP4-0 Clocks per Data Setup Negate Transfer Rate
(hex) cycle (cycles) (cycles) (MBytes/sec)
5 5 2 2.5 5.0
6 6 3 3.5 4.2
7 7 4 4.5 3.6
8 8 5 5.5 3.1
9 9 6 6.5 2.8
A 10 7 7.5 2.5
B 11 8 8.5 2.3
C 12 9 9.5 2.1
D 13 10 10.5 1.9
5.2.3.11 Current FIFO/Internal State Register (CFISREG)
Address (B)+1Ch READ ONLY
7 6 5 4 3 2 1 0
IS2 IS1 IS0 CF4 CF3 CF2 CF1 CF0
0 0 0 0 0 0 0 0
This register has two fields, the Current FIFO field and the Internal State field.
Bits 7:5 – IS 2:0 – Internal State
The Internal State Register (ISREG) tracks the progress of a sequence-type command.
These bits IS 2:0 are duplicated from the IS 2:0 field in the Internal State Register
((B)+18h).
Bits 4:0 – CF 4:0 – Current FIFO
The CF 4:0 bits are the binary coded value of the number of bytes in the SCSI FIFO.
These bits should not be read when the device is transferring data since this count may
not be stable. The maximum value read from this register is 10h or 16 decimal due to
the size of the SCSI FIFO.
When the Am53C974A is the Initiator and the phase changes to Synchronous Data In
from either Message Out or Command Phase, CF4:0 will latch the number of message
or command bytes that were not transmitted to the SCSI Bus. This value will be held
until the next command begins. All bytes in the SCSI FIFO will be flushed, and only
incoming data bytes will be retained.
5-22
The Fast SCSI Block
AMD
5.2.3.12 Synchronous Offset Register (SOFREG)
Address (B)+1Ch WRITE
7 6 5 4 3 2 1 0
RAD1 RAD0 RAA1 RAA0 SO3 SO2 SO1 SO0
0 0 0 0 0 0 0 0
The Synchronous Offset Register (SOFREG) controls REQ/ACK deassertion/assertion
delay and stores a 4-bit count of the number of bytes that can be sent to (or received
from) the SCSI bus during synchronous transfers without a REQ (or ACK). Bytes
exceeding the threshold will be sent one byte at a time (asynchronously). That is, each
byte will require an REQ/ACK handshake. To set up an asynchronous transfer, the
SOFREG is set to zero. The SOFREG is set to zero after a hard or soft reset.
Bits 7:6 – RAD 1:0 –
REQ/ACK
Deassertion
These bits may be programmed to control the deassertion delay of the REQ and ACK
signals during synchronous transfers. Deassertion delay is expressed in input clock
cycles, and depends on the implementation of FASTCLK.
(See Control Register Three, bit 3)
Deassertion Delay
SOFREG FASTCLK REQ/ACK
Bits 7:6 Ctrl 3, bit 3 Input Clock Cycles
00 0 Default – 0 cycles
01 0 1/2 cycle early
10 0 1 cycle delay
11 0 1/2 cycle delay
00 1 Default – 0 cycles
01 1 1/2 cycle delay
10 1 1 cycle delay
11 1 1 1/2 cycles delay
Bits 5:4 – RAA 1:0 –
REQ/ACK
Assertion
These bits may be programmed to control the assertion delay of the REQ and ACK
signals during synchronous transfers. Unlike deassertion delay, assertion delay is
independent of the FASTCLK setting.
Assertion Delay
SOFREG REQ/ACK
Bits 5:4 Input Clock Cycles
00 Default – 0 cycles
01 1/2 cycle delay
10 1 cycle delay
11 1 1/2 cycles delay
Note: Exercise caution when programming bits 7:4 in the Synchronous Offset Register
as it is possible to violate the SCSI-2 timing specifications.
Bits 3:0 – SO 3:0 – Synchronous Offset 3:0
The SO 3:0 bits are the binary coded value of the number of bytes that can be sent to
(or received from) the SCSI bus without an ACK (or REQ) signal. A zero value designates Asynchronous transfers, while a non-zero value designates the byte offset for
synchronous transfers. The Am53C974A supports a maximum synchronous offset of
15 bytes.
The Fast SCSI Block
5-23
AMD
5.2.3.13 Control Register One (CNTLREG1)
Address (B)+20h READ/WRITE
7 6 5 4 3 2 1 0
ETM DISR Reserved PERE Reserved SID2 SID1 SID0
0 0 0 0 0 X X X
The Control Register One (CNTLREG1) programs the operating parameters for the
Am53C974A.
Bit 7 – ETM – Extended Timing Mode
Enabling this feature will increase the minimum setup time for data being transmitted on
the SCSI bus. This bit should only be set if the external cabling conditions produce SCSI
timing violations. FASTCLK operation is unaffected by this feature.
Bit 6 – DISR – Disable Interrupt on SCSI Reset
The DISR bit masks the reporting of the SCSI reset. When the DISR bit is set and a
SCSI reset is asserted, the device will disconnect from the SCSI bus and remain idle
without interrupting the host processor. When the DISR bit is reset and a SCSI reset is
asserted the device will respond by interrupting the host processor. The DISR bit is
reset to zero by a hard or soft reset.
Bit 5 – Reserved
This bit is reserved and must always be programmed to ‘0’.
Bit 4 – PERE – Parity Error Reporting Enable
The PERE bit enables the checking and reporting of parity errors on incoming SCSI
bytes during the information transfer phase. When the PERE bit set and bad parity is
detected, the PE bit in the SCSI Status Register will be set but an interrupt will not be
generated. In the Initiator mode the ATN signal will also be asserted on the SCSI bus.
When the PERE bit is reset and bad parity occurs, the error is not detected and no
action is taken.
Bit 3 – Reserved
This bit is reserved and must always be programmed to ‘0’.
Bit 2:0 – SID 2:0 – SCSI ID 2:0
The Chip ID 2:0 bits specify the binary coded value of the device ID on the SCSI bus.
The device will arbitrate with this ID and will respond to Reselection with this ID. At
power-up the state of these bits are undefined. These bits are not affected by hard
or soft reset.
5-24
The Fast SCSI Block
5.2.3.14 Clock Factor Register (CLKFREG)
Address (B)+24h WRITE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved CLKF2 CLKF1 CLKF0
0 0 0 0 0 0 1 0
The Clock Factor Register (CLKFREG) must be set to indicate the input frequency
range of the device. This value is crucial for controlling various timings to meet the SCSI
specification. The value of bits CLKF 2:0 can be calculated by rounding off the quotient
of (Input Clock Frequency in MHz)/(5 MHz). The device has a frequency range of 10 to
40 MHz.
Bits 7:3 – Reserved
These bits are reserved and must always be programmed to ‘0’.
Bits 2:0 – CLKF 2:0 – Clock Factor 2:0
The CLKF 2:0 bits specify the binary coded value of the clock factor. The CLKF 2:0 bits
will default to a value of 2 by a hard or soft reset. These bits encode the decimal value
to be used in calculating the SCSI Timeout Register value.
CLKF2 CLKF1 CLKF0 Input Clk Freq (MHz)
0 1 0 10
0 1 1 10.01 to 15
1 0 0 15.01 to 20
1 0 1 20.01 to 25
1 1 0 25.01 to 30
1 1 1 30.01 to 35
0 0 0 35.01 to 40
AMD
Note: CLKF2:0 must be set to ’000’ (binary) and a 40 MHz clock must be used to gen-
erate the CLK signal in order to achieve 10 MB/sec synchronous transfer rates. For this
case, a value of 8 should be used to calculate the SCSI Timeout Register value. See the
SCSI Timeout Register.
5.2.3.15 RESERVED
Address (B)+28h WRITE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Bits 7:0 – Reserved
These bits are reserved and must always be programmed to ‘00h’.
The Fast SCSI Block
5-25
AMD
5.2.3.16 Control Register Two (CNTLREG2)
Address (B)+2Ch READ/WRITE
7 6 5 4 3 2 1 0
Reserved ENF Reserved Reserved SCSI-2 Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Control Register Two (CNTLREG2) programs various operating parameters for the
Am53C974A.
Bit 7 – Reserved
This bit is reserved and must always be programmed to ‘0’.
Bit 6 – ENF – Enable Features
When set to a value of ‘1’, this bit activates the following product enhancements:
1) The Current Transfer Count Register High ((B)+38h) will be enabled, extending the
transfer counter from 16 to 24 bits to allow for larger transfers.
2) Following a chip or power on reset, up until the point where the Current Transfer
Count Register High ((B)+38h) is loaded with a value, reading this register will return
the Am53C974A’s part-unique ID.
3) The SCSI phase will be latched at the completion of each command by bits 2:0 in the
SCSI Status Register ((B)+10h). When this bit is ‘0’, the SCSI Status Register will reflect real-time SCSI phases.
A software or hardware reset will clear this bit to its default value of ‘0’; a SCSI reset will
leave this bit unaffected.
Bit 5:4 – Reserved (Read Only)
This bit is reserved and will always return a value of ‘0’ when read.
Bit 3 – S2FE – SCSI–2 Features Enable
The S2FE bit allows the device to recognize two SCSI-2 features: the extended
message feature and the Group 2 command recognition. (These features can also be
controlled independently by bits 6:5 in CNTLREG3).
Extended Message Feature: When the S2FE bit is set and the device is selected with
attention, the device will monitor the ATN signal at the end of the first message byte. If
the ATN signal is active, the device will request two more message bytes before
switching to the command phase. If the ATN signal is inactive the device will switch to
the Command phase. When the S2FE bit is reset as a Target the device will request a
single message byte.
Group 2 Command Recognition: When the S2FE bit is set, Group 2 commands are
recognized as 10-byte commands. When the S2FE bit is reset, the device will interpret
Group 2 commands as reserved commands. Thus the Am53C974A will only request
6-byte commands when the S2FE bit is reset.
Bit 2:0 – Reserved
These bits are reserved and must always be programmed to ‘0’.
5-26
The Fast SCSI Block
5.2.3.17 Control Register Three (CNTLREG3)
Address (B)+30h READ/WRITE
7 6 5 4 3 2 1 0
ADIDCHK QTAG G2CB FASTSCSI FASTCLK Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Bit 7 – ADIDCHK – Additional ID Check
This bit enables additional check on ID message during bus-initiated Select with ATN.
The Am53C974A will check bits 7, and bits 5:3 in the first byte of the ID message during
Selection. An interrupt will be generated if bit 7 is ‘0’, or if bits 5, 4, or 3 are ‘1’.
Bit 6 – QTAG – QTAG Control
This bit controls the Queue Tag feature in the Am53C974A. When enabled, the
Am53C974A is capable of receiving 3-byte messages during bus-initiated Select/
Reselect with ATN. The 3-byte message consists of one byte Identify Message and two
bytes of Queue Tag message. The Am53C974A will check the second byte for values of
20h, 21h, and 22h. If this condition is not satisfied, the sequence halts and the
Am53C974A generates an interrupt.
When the QTAG feature is not enabled, the Am53C974A halts the Selected with ATN
sequence following the receipt of one ID message byte if ATN is still true.
AMD
Bit 3, Control Register Two also enables this feature.
Bit 5 – G2CB – Group 2 Command Block
When this bit is set, the Am53C974A is capable of recognizing 10-byte Group 2
Commands as valid CDBs (Command Descriptor Blocks). (This feature is also controlled by bit 3 of CNTLREG2). When this feature is enabled, the Target receives 10
bytes of Group 2 commands, and sets the group code valid bit (bit 3) in the Status
Register (STATREG). When this feature is disabled, the Target receives only 6 bytes of
command code, and does not set bit 3 in the Status Register ((B)+10h).
This bit may be programmed in conjunction with bit 6 (described above) to send 1 or 3
byte messages with 6 or 10 byte CDBs. The following table illustrates the transmission
options:
CNTLREG3 CNTLREG3 CNTLREG2
Bit 6 Bit 5 Bit 3 Enabled Features
QTAG G2CB S2FE
X X 1 10-byte CDB,
3-byte message
1 0 0 3-byte message
0 1 0 10-byte CDB
1 1 0 10-byte CDB,
3-byte message
0 0 0 Features disabled
X is don’t care
The Fast SCSI Block
5-27
AMD
Bit 4 – FASTSCSI – Fast SCSI
Bit 3 – FASTCLK – Fast SCSI Clocking
These bits configure the Am53C974A’s state machine to support both Fast SCSI timings
and SCSI-1 timings. These bits affect the SCSI transfer rate, and must be considered in
conjunction with the Am53C974A’s clock frequency and mode of operation.
CNTLREG3
FASTSCSI FASTCLK Clock
Bit 4 Bit 3 Frequency Mode of Operation
1 1 25 MHz – 40 MHz 10 MBytes/sec, Fast SCSI
0 1 25 MHz – 40 MHz 5 MBytes/sec, SCSI-1
–– 0 <=25 MHz 5 MBytes/sec, SCSI-1
–– = don’t care
Bit 2 – Reserved
This bit is reserved and must always be programmed to ‘0’.
Bit 1 – Reserved (Read Only)
This bit is reserved and will always return a value of ‘0’ when read.
Bit 0 – Reserved
This bit is reserved and must always be programmed to ‘0’.
5.2.3.18 Control Register Four (CNTLREG4)
Address (B)+34h READ/WRITE
7 6 5 4 3 2 1 0
GE1 GE0 PWD Reserved RES (R) RADE Reserved Reserved
0 0 0 0 0 0 0 0
This register is used to control several features implemented in the SCSI block.
At power up, this register will contain a ‘0’ value on all bits except bit 4.
Bit 7:6 – GE1:0 – GLITCH EATER
The GLITCH EATER Circuitry has been implemented on REQ and ACK lines and are
controlled by bits 7and 6. The valid signal window may be adjusted by setting the bits
according to the combinations listed below.
CNTLREG4
Bit 7 Bit 6 Valid Signal
GE1 GE0 Window
0 0 12 ns
1 0 25 ns
0 1 35 ns
1 1 0 ns
RAE (W)
5-28
Note: Changes in the valid signal window will affect data setup and hold times for Fast
SCSI timings.
The Fast SCSI Block
AMD
Bit 5 – PWD – Reduced Power Feature
Setting this bit to ‘1’ enables AMD’s reduced power feature. This feature turns off the
input buffers on all the SCSI bus signal lines to reduce power consumption. For further
power savings, the clock input may be removed using bit 21 in the SBAC register
((B)+ 70h).
Bit 4 – Reserved
This bit is reserved for internal use.
Bit 3 (Read Only) – RES – Reserved
This bit is reserved for internal use.
Bit 3 (Write Only) – RAE – Active Negation Control
Bit 2 – RADE – Active Negation Control
Bits 2 and 3 control the Active Negation Drivers which may be enabled on REQ, ACK, or
DATA lines. The following table shows the programming options for this feature:
CNTLREG4
Bit 3 Bit 2
RAE RADE Function Selected
0 0 Active Negation Disabled
1 0 Active Negation on REQ and ACK only
— 1 Active Negation on REQ, ACK and DATA
— = don’t care
Bit 1:0 – Reserved
This bit is reserved for internal use.
5.2.3.19 RESERVED
Address (B)+3Ch WRITE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Bit 7:0 – Reserved
These bits are reserved and must always be programmed to ‘00h’.
5.2.3.20 Part-Unique ID Register (CTCREG)
Address (B)+38h READ ONLY
This register extends the transfer counter from 16 to 24 bits and is only enabled when
the ENF bit is set (bit 6, Control Register Two). The descriptions accompanying the Start
Transfer Count Registers and the Current Transfer Count Registers should be referenced for more information regarding the transfer counter.
This register is also used to store the part-unique ID code for the Am53C974A. This
information may be accessed when all of the following are true:
A power up or chip reset has taken place
A value has not been loaded into this register
The ID value in this register is 12h.
The Fast SCSI Block
5-29
AMD
5.3 DEVICE COMMANDS
The device commands can be broadly divided into two categories, DMA commands and
non-DMA commands. DMA commands are those which cause data movement between
the host memory and the SCSI bus while non-DMA commands are those that cause
data movement between the SCSI FIFO and the SCSI bus. The Most Significant Bit of
the command byte differentiate the DMA from the non-DMA commands.
When a DMA command is issued, the contents of the Start Transfer Count Register will
be loaded into the Current Transfer Count Register. Data transmission will continue until
the Current Transfer Count Register decrements to zero.
Before a DMA device command is issued, the software must initialize the DMA Starting
Transfer Count and Starting Physical Address registers. Then it must issue a DMA Start
command. Once this is done, it can issue the device command.
Non-DMA commands do not modify the Current Transfer Count Register and are
unaffected by the value in the Current Transfer Count Register. For non-DMA commands, the number of bytes transmitted depends solely on the operation in progress.
Some of the non-DMA commands are output commands that transfer data from the
SCSI FIFO to the SCSI bus. Before these commands are executed, the SCSI FIFO must
be loaded with the bytes to be sent. Other non-DMA commands are input commands
that transfer data from the SCSI bus to the SCSI FIFO. After these commands are
executed, the data received can be accessed by reading one byte at a time from the
SCSI FIFO.
5-30
The Fast SCSI Block
AMD
Code
(Hex.)
Command
NonDMA
Mode
DMA
Mode
Initiator Commands
Information Transfer 10 90
Initiator Command Complete Steps 11 91
Message Accepted 12 –
Transfer Pad Bytes 18 98
Set ATN* 1A –
Reset ATN* 1B –
Target Commands
Send Message 20 A0
Send Status 21 A1
Send Data 22 A2
Disconnect Steps 23 A3
Terminate Steps 24 A4
Target Command Complete Steps 25 A5
Disconnect 27 –
Receive Message Steps 28 A8
Receive Commands 29 A9
Receive Data 2A AA
Receive Command Steps 2B AB
DMA Stop 04 –
Access FIFO – 85
Idle State Commands
Reselect Steps 40 C0
Select without ATN Steps 41 C1
Select with ATN Steps 42 C2
Select with ATN and Stop Steps 43 C3
Enable Selection/Reselection* 44 C4
Disable Selection/Reselection 45 –
Select with ATN3 Steps 46 C6
Reselect with ATN3 Steps 47 C7
General Commands
No Operation* 00 80
Clear FIFO* 01 81
Reset Device* 02 82
Reset SCSI Bus** 03 83
* These commands do not generate interrupt.
** An interrupt is generated when SCSI bus reset interrupt reporting is not disabled (see Control Register1/DISR bit 6).
The Fast SCSI Block
5-31
AMD
5.3.1 Command Stacking
The microprocessor may stack commands in the Command Register ((B)+0Ch) since it
functions as a two-byte deep FIFO. Non-DMA commands may not be stacked, and
commands which transfer data in opposing directions should not be stacked together.
If DMA commands are queued together, the Start Transfer Count must be written before
the associated command is loaded into the Command Register. Since multiple interrupts
can occur when commands are stacked, it is recommended that the ENF bit in Control
Register Two (Bit 6) be set in order to latch the SCSI phase bits in the SCSI Status
Register ((B)+10h) at the completion of a command. This allows the host to determine
the phase of the interrupting command without having to consider phase changes that
occurred after the stacked command began execution.
Note: Command stacking and queuing should only be used during SCSI Data In or Data
Out transfers.
5.3.2 Invalid Commands
When an illegal command is written to the Am53C974A, the Invalid Command Bit (Bit 6,
Register (B)+14h) will be set to ‘1’, and an interrupt will be generated to the host. When
this happens, the interrupt must be serviced before another command may be written to
the Command Register.
An Invalid command is defined as a command written to the Am53C974A that is either
not supported, not allowed in the specified mode, or a command that has an unsupported command mode.
The following conditions will also cause an Invalid Command interrupt to occur:
An Initiator Information Transfer, Transfer Pad, or Command Complete is issued
when ACK is still asserted.
A Selection or Reselection command is issued with the DMA bit enabled, if the
Selection/Reselection command was previously issued with the DMA enabled.
5.3.3 Command Window
The window at the point where the Disable Selection/Reselection command (45H/C5H)
has been loaded into the Command Register ((B)+0Ch), and before bus-initiated
Selection or Reselection begins, has been eliminated. This prevents a false Successful
Operation Interrupt from being generated when the Selection/Reselection sequence
continues to completion after the Disable command has been loaded.
5.3.4 Initiator Commands
Initiator commands are executed by the device when it is in the Initiator mode. If the
device is not in the Initiator mode and an Initiator command is received the device will
ignore the command, generate an Invalid Command interrupt and clear the Command
Register.
Should the Target disconnect from the SCSI bus by deasserting the BSY signal line
while the Am53C974A (Initiator) is waiting for the Target to assert REQ, a Disconnected
Interrupt will be issued 1.5 to 3.5 clock cycles following BSY going false.
5-32
Upon receipt of the last byte during Message In phase, ACK will remain asserted to
prevent the Target from issuing any additional bytes, while the Initiator decides to
accept/reject the message. If non-DMA commands are used, the last byte signals the
SCSI FIFO is empty. If DMA commands are used, the Current Transfer Count signals
the last byte.
The Fast SCSI Block
Loading...