AMD Am29LV800D Service Manual

Am29LV800D

Data Sheet

For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Publication Number Am29LV800D_00 Revision A Amendment 4 Issue Date January 21, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

PRELIMINARY

Am29LV800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

For new designs, S29AL008D supersedes Am29LV800D and is the factory-recommended migration path. Please refer to the S29AL008D Data Sheet for specifications and ordering information.

Distinctive Characteristics

■ Single power supply operation

— 2.7 to 3.6 volt read and write operations

for battery-powered applications

■ Manufactured on 0.23 µm process

technology

— Compatible with 0.32 µm Am29LV800

device

■ High performance

— Access times as fast as 70 ns

■ Ultra low power consumption (typical

values at 5

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current

— 15 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector to prevent

any program or erase operations within that

sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command

sequences

MHz)

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm

automatically writes and verifies data at specified addresses

■ Minimum 1 million write cycle guarantee

per sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package option

— 48-ball FBGA — 48-pin TSOP

—44-pin SO

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to

reading array data

This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the right to change or discontinue work on this proposed produc t without notice.

Publication Am29LV800D_00 Rev. A Amend. 4 Issue Date: January 21, 2005

General Description

PRELIMINARY

The Am29LV800D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

This device is manufactured using AMD’s 0.23 µm process technology, and offers all the fea tures and benefits of the Am29LV800B, which was manufactured using 0.32 µm process technology.

The standard device offers access times of 70, 90, and 120 ns, allowing high speed micropro cessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power supply for both read and write func tions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase opera tions. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before exe

cuting the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equip ment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the auto- matic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

detector that automatically inhibits

2Am29LV800DAm29LV800D_00_A4_E January 21, 2005

PRELIMINARY

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Package .............. 7

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Standard Products ......................................................................8

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .10

Table 1. Am29LV800D Device Bus Operations .10

Word/Byte Configuration ...................................................... 10

Requirements for Reading Array Data ............................... 10

Writing Commands/Command Sequences .........................11

Program and Erase Operation Status ...................................11

Standby Mode ..............................................................................11

Automatic Sleep Mode ..............................................................11

RESET#: Hardware Reset Pin .................................................11

Output Disable Mode ...............................................................12

Table 2. Am29LV800DT Top Boot Block

Sector Addresses ........................................12

Table 3. Am29LV800DB Bottom Boot Block

Sector Addresses ........................................13

Autoselect Mode ........................................................................13

Table 4. Am29LV800D Autoselect Codes

(High Voltage Method) ................................14

Sector Protection/Unprotection .......................................... 14

Temporary Sector Unprotect ............................................... 14

Figure 1. Temporary Sector Unprotect

Operation .................................................. 15

Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms ........................ 16

Hardware Data Protection .....................................................17

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ...................................................................17

Reset Command .........................................................................17

Autoselect Command Sequence .......................................... 18

Word/Byte Program Command Sequence .......................18

Figure 1. Program Operation ........................ 19

Chip Erase Command Sequence .......................................... 19

Sector Erase Command Sequence ...................................... 19

Erase Suspend/Erase Resume Commands ....................... 20

Figure 1. Erase Operation ............................ 21

Table 5. Am29LV800D Command Definitions ..21

Write Operation Status . . . . . . . . . . . . . . . . . . . . 22

DQ7: Data# Polling ..................................................................22

Figure 1. Data# Polling Algorithm ................. 23

RY/BY#: Ready/Busy# .............................................................23

DQ6: Toggle Bit I ......................................................................24

DQ2: Toggle Bit II .....................................................................24

Reading Toggle Bits DQ6/DQ2 ............................................24

DQ5: Exceeded Timing Limits ..............................................25

DQ3: Sector Erase Timer .......................................................25

Figure 1. Toggle Bit Algorithm ...................... 25

Table 6. Write Operation Status ....................26

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 27

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .28

CMOS Compatible .................................................................. 28

Figure 1. I

and Automatic Sleep Currents) .................... 29

Figure 1. Typical I

Current vs. Time (Showing Active

CC1

vs. Frequency ............. 29

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 1. Test Setup................................... 30

Table 7. Test Specifications ........................................30

Key to Switching Waveforms. . . . . . . . . . . . . . . . 30

Figure 1. Input Waveforms and

Measurement Levels................................... 30

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31

Read Operations ........................................................................31

Figure 1. Read Operations Timings ............... 31

Hardware Reset (RESET#) ....................................................32

Figure 1. RESET# Timings........................... 32

Word/Byte Configuration (BYTE#) ..................................33

Figure 1. BYTE# Timings for Read

Operations ................................................ 34

Figure 1. BYTE# Timings for Write

Operations ................................................ 34

Erase/Program Operations ....................................................35

Figure 1. Program Operation Timings............ 36

Figure 1. Chip/Sector Erase Operation

Timings .................................................... 37

Figure 1. Data# Polling Timings (During

Embedded Algorithms) ............................... 38

Figure 1. Toggle Bit Timings (During

Embedded Algorithms) ............................... 38

Figure 1. DQ2 vs. DQ6 ............................... 39

Temporary Sector Unprotect ...............................................39

Figure 1. Temporary Sector Unprotect

Timing Diagram ......................................... 39

Figure 1. Sector Protect/Unprotect

Timing Diagram ......................................... 40

Alternate CE# Controlled

Erase/Program Operations .................................................... 41

Figure 1. Alternate CE# Controlled Write

Operation Timings...................................... 42

Erase and Programming Performance . . . . . . . . .43

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 43

TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 43

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . . .44

TS 048—48-Pin Standard TSOP ........................................ 44

TSR048—48-Pin Reverse TSOP .........................................45

FBB 048—48-Ball Fine-Pitch Ball Grid Array

(FBGA) 6 x 9 mm ................................................................... 46

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 47

VBK 048 - 48 Ball Fine-Pitch Ball Grid Array

(FBGA) 6.15 x 8.15 mm .............................................................47

SO 044—44-Pin Small Outline Package ..........................48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .49

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 3

PRELIMINARY

Product Selector Guide

Family Part Number Am29LV800D

Speed Options Full Voltage Range: VCC = 2.7–3.6 V -70 -90 -120

Max access time, ns (t

Max CE# access time, ns (tCE) 70 90 120

Max OE# access time, ns (tOE) 30 35 50

Note: See “AC Characteristics” for full specifications.

) 70 90 120

ACC

Block Diagram

DQ0–DQ15 (A-1)

Input/Output

Buffers

Data

STB

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

Sector Switches

Erase Voltage

Generator

PGM Voltage

Generator

Chip Enable

Output Enable

A0–

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

4Am29LV800DAm29LV800D_00_A4_E January 21, 2005

Connection Diagrams

PRELIMINARY

A15 A14 A13 A12 A11 A10

A8 NC NC

WE#

RESET#

NC NC

RY/BY#

A18 A17

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard TSOP

Reverse TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1

Am29LV800D_

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 5

Connection Diagrams

PRELIMINARY

RY/BY#

A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

CE#

V OE# DQ0 DQ8 DQ1 DQ9 DQ2

DQ10

DQ3

DQ11

1 2 3 4 5 6 7 8 9

10 11 12 13

14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

FBGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

BYTE#A16A15A14A12A13

DQ15/A-1 V

A5 B5 C5 D5 E5 F5 G5 H5

DQ13 DQ6DQ14DQ7A11A10A8A9

A4 B4 C4 D4 E4 F4 G4 H4

DQ4DQ12DQ5NCNCRESET#WE#

A3 B3 C3 D3 E3 F3 G3 H3

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

A2 B2 C2 D2 E2 F2 G2 H2

DQ9 DQ1DQ8DQ0A5A6A17A7

A1 B1 C1 D1 E1 F1 G1 H1

CE#A0A1A2A4A3

OE# V

6Am29LV800DAm29LV800D_00_A4_E January 21, 2005

PRELIMINARY

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Pin Configuration

A0–A18 = 19 addresses

DQ0–DQ14= 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word

mode),

A-1 (LSB address input, byte

mode)

BYTE# = Selects 8-bit or 16-bit mode

CE# = Chip enable

VCC = 3.0 volt-only single power supply

(see Product Selector Guide for

speed

options and voltage supply

tolerances)

= Device ground

NC = Pin not connected internally

Logic Symbol

A0–A18

DQ0–DQ15

CE#

OE#

WE#

RESET

BYTE# RY/BY#

16 or 8

(A-1)

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 7

PRELIMINARY

Ordering Information

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29LV800D T -70 E C

TEMPERATURE RANGE

C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-Free Package I = Industrial (–40°C to +85°C) F = Industrial (–40°C to +85°C) with Pb-Free Package

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout

(TS 048)

F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout

(TSR048) S = 44-Pin Small Outline Package (SO 044) WB = 48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

WC = 48-Ball Fine Pitch Ball Grid Array (FBGA)

= 0.80 mm pitch, 6.15 x 8.15 mm package (VBK 048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800D 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages

AM29LV800DT-70, AM29LV800DB-70

AM29LV800DT-90, AM29LV800DB-90

AM29LV800DT-120,

EC, EI, ED, EF, FC, FD, FF, FI,

SC, SD, SF, SI

EC, EI, ED,EF,FD, FF,FC,

FI,SD, SFSC, SI

AM29LV800DB-120

8Am29LV800DAm29LV800D_00_A4_E January 21, 2005

PRELIMINARY

Valid Combinations for FBGA Packages

Order Number Package Marking

WBC

WBI

WBD

AM29LV800DT-70,

AM29LV800DB-70

AM29LV800DT-90,

AM29LV800DB-90

AM29LV800DT-120,

AM29LV800DB-120

WBF

WCC

WCI

WCD

WCF

WCC

WCI

WCD

WCF

WBC

WBI

WBD

WBF

WBC

WBI

WBD

WBF

L800DT70V, L800DB70V

L800DT90V, L800DB90V

L800DT12V, L800DB12V

C, I,

D,F

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 9

PRELIMINARY

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents

Table 1. Am29LV800D Device Bus Operations

OE#WE#RESET#Addresses

Operation CE#

Read L L H H A

Write L H L H A

Standby

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

VCC ±

0.3 V

X X

VCC ±

0.3 V

of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Ta b le 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

DQ8–DQ15

BYTE

= V

DQ8–DQ14 = High-

OUT

X X

Z, DQ15 = A-1

BYTE#

= V

High-Z

OUT

(Note 1)

Sector Address,

A6 = L, A1 = H,

Sector Address, A6 = H, A1 = H,

DQ0–

DQ7

X High-Z High-Z High-Z

A0 = L

OUT

= Data Out

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

. The

BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 1 for the timing diagram. I

in the DC Characteristics table repre-

CC1

sents the active current specification for reading array data.

10 Am29LV800D Am29LV800D_00_A4_E January 21, 2005

PRELIMINARY

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autose lect Mod e” and “Autosele ct Command Sequence” sections for more information.

in the DC Characteristics table represents

CC2

the active current specification for the write mode. The

“AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in

the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3 V. (Note that this is a more restricted

voltage range than VIH.) If CE# and RESET# are held at VIH, but not within V

± 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device requires stan

dard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

+ 30 ns. The automatic

ACC

sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in the DC Characteristics table

CC4

represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately termi- nates any operation in progress, tristates all output pins, and ignores all read/write com mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (I

). If RESET# is held at VIL but not

CC4

within VSS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 11

PRELIMINARY

If RES E T # is a sserte d duri n g a p r o g ram or e rase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

READY

(during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not exe cuting (RY/BY# pin is “1”), the reset operation is completed within a time of t

READY

(not during

Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 1 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the

device is disabled. The output pins are placed in the high impedance state.

Table 2. Am29LV800DT Top Boot Block Sector Addresses

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh

SA1 0 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA2 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA3 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA4 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA5 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA6 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA7 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

SA8 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh

SA9 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh

SA10 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh

SA11 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA12 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh

SA13 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh

SA14 1 1 1 0 X X X 64/32 E0000h–EFFFFh 70000h–77FFFh

SA15 1 1 1 1 0 X X 32/16 F0000h–F7FFFh 78000h–7BFFFh

SA16 1 1 1 1 1 0 0 8/4 F8000h–F9FFFh 7C000h–7CFFFh

SA17 1 1 1 1 1 0 1 8/4 FA000h–FBFFFh 7D000h–7DFFFh

SA18 1 1 1 1 1 1 X 16/8 FC000h–FFFFFh 7E000h–7FFFFh

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

Address Range

12 Am29LV800D Am29LV800D_00_A4_E January 21, 2005

PRELIMINARY

Table 3. Am29LV800DB Bottom Boot Block Sector Addresses

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh

SA1 0 0 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh

SA2 0 0 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh

SA3 0 0 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh

SA4 0 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA5 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA6 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA7 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA8 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA9 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA10 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

SA11 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh

SA12 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh

SA13 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh

SA14 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA15 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh

SA16 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh

SA17 1 1 1 0 X X X 64/32 E0000h–EFFFFh 70000h–77FFFh

SA18 1 1 1 1 X X X 64/32 F0000h–FFFFFh 78000h–7FFFFh

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range

(x16)

Address Range

Note for Tab l e s 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section.

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed insystem through the command register.

When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Ta bl e 4. In addition, when

verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Tab le 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tab le 5 . This method does not require VID. See “Command Definitions” for details on using the autoselect mode.

January 21, 2005 Am29LV800D_00_A4_E Am29LV800D 13

Table 4. Am29LV800D Autoselect Codes (High Voltage Method)

Description Mode CE# OE#

PRELIMINARY

A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H X X V

Device ID: Am29LV800B (Top Boot Block)

Device ID: Am29LV800B (Bottom Boot Block)

Sector Protection Verification

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Word L L H

X X V

Byte L L H X DAh

Word L L H

X X V

Byte L L H X 5Bh

L L H SA X V

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s Express Flash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Sector Protection/unprotection can be implemented via two methods.

The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure

X L X L L X 01h

X L X L H

X L X H L

standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 voltonly AMD flash devices. Publication number 20536 contains further details; contact an AMD representative to request a copy.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is acti vated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algo-

1 shows the timing diagram. This method uses

22h DAh

22h 5Bh

01h

(protected)

00h

(unprotecte

14 Am29LV800D Am29LV800D_00_A4_E January 21, 2005

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