AMD Am29LV640D, Am29LV64ID Service Manual
Am29LV640D/Am29LV641D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the docu ment is ma rked with the name o f the comp any that o riginally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 22366 Revision B Amendment +8 Issue Date September 20, 2002
Am29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileIO Control
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 3.0 to 3.6 volt read, erase, and program operations
■ VersatileIO contro l
— Device generates output voltages and tolerates data
input voltages on the DQ input/ouputs as determined
by the voltage on V
■ High performance
— Access times as fast as 90 ns
■ Manufactured on 0.23 µm process technology
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■ SecSi (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Elec tron ic Ser ial Num be r
— May be programmed and locked at the factory or by
the customer
— Accessible through a comma nd seque nce
■ Ultra low power consumption (typical values at 3.0 V ,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
■ Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■ Sector Protection
— A hardware method to lock a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Embedded Algorithms
— Embedded Erase algorith m aut oma tic ally
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
IO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
■ Minimum 1 million erase cycle guarantee per sector
■ Package options
— 48-pin TSOP (Am29LV641DH/DL only)
— 56-pin SSOP (Am29LV640DH/DL only)
— 63-ball Fine-Pitch BGA (Am29LV640DU only)
— 64-ball Fortified BGA (Am29LV640DU only)
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sect27
— or that is not being erased, then resumes the erase
operation
■ Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■ Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA
package only)
— Provides a hardware method of detecting program or
erase cycle completion
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array
data
■ WP# pin (Am29LV641DH/DL in TSOP,
Am29LV640DH/DL in SSOP only)
— At V
— At V
— An internal pull up to V
■ ACC pin
— Accelerates programming time for higher throughput
■ Program and Erase Performance (V
the ACC input pin)
— Word program time: 11 µs typical
— Sector erase time: 0.9 s typical for each 32 Kword
, protects the first or last 32 Kword sector,
IL
regardless of sector protect/unprotect status
, allows removal of sector protection
IH
during system production
sector
is provided
CC
not applied to
HH
Publication# 22366 Rev: B Amendment/+8
Issue Date: September 20, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0
Volt (3.0 V to 3.6 V) single power supply flash memory
devices organized as 4 ,194,304 wo rds. Data appe ars
on DQ0-DQ15. The device is designed to be programmed in-system with the stand ard system 3.0 volt
supply. A 12.0 volt VPP is not required for program
V
CC
or erase operations. The device can also be programmed in standard EPROM programmers.
Access times of 90 and 120 ns are available for applications where V
ns are available for applications where V
device is offered in 48- pin TSOP, 56-pin SSOP, 63-ball
Fine-Pitch BGA and 64-ball Fortified BGA packages.
To eliminate bus contention each device has separate
chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regula ted voltages ar e
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-pow er-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
≥ VCC. Access times of 100 and 120
IO
< VCC. The
IO
gle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase archite cture allow s memo ry sectors to be erased and reprogrammed without affecting
the data conten ts of oth er sec tors. Th e devi ce is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspen d/Erase R esume fe ature ena bles
the user to put erase on hold for any period of time to
read data from, or prog ram data to, an y sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# p in terminates any opera tion
in progress and re sets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash mem ory device.
The device offers a standby mode as a power-saving
feature. Once the system p laces the device into th e
standby mode power consumption is greatly reduced.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not alread y programmed) before executin g the erase op eration. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The VersatileIO™ (V
) control allows the host system
IO
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/O s to the same voltag e
level that is asserted on V
. VIO is available in two
IO
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
The SecSi (Secured Silicon) Sector provid es an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The Write Protect (WP#) feature prot ects the f irst o r
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
, the device enters the
HH
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increas e factory th roughput d uring sys tem production, but may also be used in the field if desired.
AMD’s Flash techn ology combines y ears of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
2 Am29LV640D/Am29LV641D September 20, 2002
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA/fBGA Packages .........8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Device Bus Operations .............. .............. .........................11
VersatileIO (VIO) Control .......... .. ........................ .. ... ............11
Requirements for Reading Array Data ...................... .. ...........11
Writing Commands/Command Sequences ..................... .......12
Accelerated Program Operation ......................................................12
Autoselect Function s ......................... .............. ........................... .....12
Standby Mode ................................... .....................................12
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................13
Table 2. Sector Address Table ............... ........................... ..............13
Autoselect Mode ........ ....................... .................... ..................17
Table 3. Autoselect Codes, (High Voltage Method) ..................... ..17
Sector Group Protection and Unprotection ...................... .......18
Table 4. Sector Group Protection/Unprotection Address Table .....18
Write Protect (WP#) ................................................................19
Temporary Sector Group Unprotect .......................................19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
SecSi (Secured Silicon) Sector Flash Memory Region ..........21
Table 5. SecSi Sector Contents ......................................................21
Hardware Data Protection ......................................................21
Low VCC Write Inhibit .....................................................................21
Write Pulse “Glitch” Protection ................................................. .......22
Logical Inhibit ............................................... ................ ......... ..........2 2
Power-Up Write Inhibit ............................................... .....................22
Common Flash Memory Interface (CFI). . . . . . . 22
Table 6. CFI Query Identification String .......................................... 22
System Interface String...................... .............. ........................... .... 23
Table 8. Device Geometry Definit ion.............................................. 23
Table 9. Primary Vendor-Specific Extended Query........................ 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24
Reading Array Data ................................................................24
Reset Command ......................................... ............................25
Autoselect Command Sequence ............................................25
Enter SecSi Sector/Exit SecSi Sector CommandSequence ..25
Word Program Command Sequence .....................................25
Unlock Bypass Command Sequence ..............................................26
Figure 3. Program Operation........... .............. ............. .................... 26
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................27
Erase Suspend/Erase Resume Commands ...........................27
Figure 4. Erase Operation............................................................... 28
Command Definitions .............................................................29
Command Definitions...................................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . .30
DQ7: Data# P o ll in g .......... .. ........................ ........................ .....30
Figure 5. Data# Polling Algorithm................................................... 30
RY/BY#: Ready/Busy# ............................................................31
DQ6: Toggle Bit I ....................................................................31
Figure 6. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ...................................................................32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timing Limits ................................................32
DQ3: Sector Era s e Time r ..... ........................ .. ........................32
Table 11. Write Operation Sta tus ........................ .............. .............33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform ..................... 34
Figure 8. Maximum Positive Overshoot Waveform....................... 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. I
Activeand Automatic Sleep Currents)............... .............. .............. 36
Figure 10. Typical I
Current vs. Time (Showing
CC1
vs. Frequency.................. .......................... 36
CC1
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup................... .............. .............. ..................... 37
Table 12. Test Specifications ................................... ......................37
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ...........................................................38
Figure 13. Read Operation Timings............................................... 38
Hardware Reset (RESET#) .............................................. ......39
Figure 14. Reset Timings............................................................... 39
Erase and Program Operations ........... .. .................................40
Figure 15. Program Operation Timings.......................................... 41
Figure 16. Accelerated Program Timing Diagram.......................... 41
Figure 17. Chip/Sector Erase Operation Timings.......................... 42
Figure 18. Data# Polling Timings
(During Embedded Algorithms)...................................................... 43
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)...................................................... 44
Figure 20. DQ2 vs. DQ6......................... ............................ ............ 44
Temporary Sector Unprotect .................................................. 45
Figure 21. Temporary Sector Group Unprotect Timing Diagram... 45
Figure 22. Sector Group Protect and Unprotect Timing Diagram.. 46
Alternate CE# Controlled Erase and Program Operations .....47
Figure 23. Alternate CE# Controlled Write
(Erase/Program)Operation Timings.................. ........................... . 48
Erase And Programming Performance . . . . . . . 49
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 49
TSOP Pin Capacitance. . . . . . . . . . . . . . . . . . . . . 49
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50
SSO056—56-Pin Shrink Small Outline Package (SSOP) ......50
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 12 x 11 mm package ................................................. 51
LAA064—64-Ball Fortified Ball Grid Array
(FBGA) 13 x 11 mm package ................................................. 52
TS 048—48-Pin Standard TSOP ............................................53
TSR048—48-Pin Reverse TSOP ............................ ... ............54
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
September 20, 2002 Am29LV640D/Am29LV641D 3
PRODUCT SELECTOR GUIDE
Part Number Am29LV640D/Am29LV641D
= 3.0–3.6 V, VIO = 3.0–5.0 V 90R 120R
V
Speed Option
CC
V
= 3.0–3.6 V, VIO = 1.8–2.9 V 101R 121R
CC
Max Access Time (ns) 90 100 120
CE# Access Time (ns) 90 100 120
OE# Access Time (ns) 35 35 50
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0
–DQ15
Input/Output
Buffers
V
CC
V
SS
RESET#
RY/BY# (Note 1)
Sector Switches
Erase Voltage
Generator
V
IO
WE#
WP#
State
Control
(Note 2)
ACC
Command
Register
PGM Voltage
Generator
CE#
OE#
VCC Detector
Timer
A0–A21
Notes:
1. RY/BY# is only available in the FBGA package.
2. WP# is only available in the TSOP and SSOP packages.
Chip Enable
Output Enable
STB
Logic
Address Latch
Y-Decoder
X-Decoder
STB
Data
Latch
Y-Gating
Cell Matrix
4 Am29LV640D/Am29LV641D September 20, 2002
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
(Am29LV641DH/DL only)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
V
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
IO
2
3
4
5
6
7
8
9
10
48-Pin Reverse TSOP
(Am29LV641DH/DL only)
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
September 20, 2002 Am29LV640D/Am29LV641D 5
CONNECTION DIAGRAMS
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
NC
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
56-Pin SSOP
(Am29LV640DH/DL
only)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET#
WE#
A20
A21
A8
A9
A10
A11
A12
A13
A14
A15
NC
NC
NC
NC
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
6 Am29LV640D/Am29LV641D September 20, 2002
CONNECTION DIAGRAM
63-Ball Fine-Pitch BGA (FBGA)
Top View, Balls Facing Down
(Am29LV640DU only)
A8 B8
C7 D7A7 B7
NC NC
C6 D6 E6 F6 G6 H6 J6 K6
C5 D5 E5 F5 G5 H5 J5 K5
C4 D4 E4 F4 G4 H4 J4 K4
C3 D3 E3 F3 G3 H3 J3 K3
A2
A1 B1
NC* NC* NC* NC*
C2 D2 E2 F2 G2 H2 J2 K2
* Balls are shorted together via the substrate but not connected to the die.
E7 F7 G7 H7 J7 K7 L7
A16A15A14A12A13
DQ15
IO
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE#
V
SSV
V
SSCE#A0A1A2A4A3
L8
NC* NC*NC NC
NC* NC*
L2
NC* NC*NC*
L1
M8
M7
M2
M1
September 20, 2002 Am29LV640D/Am29LV641D 7
CONNECTION DIAGRAMS
64-Ball Fortified BGA (FBGA)
Top View , Balls Facing Down
(Am29LV640DU only)
A8
RFU
A7
A13
A6
A9
A5
WE#
A4
RY/BY#
A3
A7
A2
A3
A1
RFU
B8 C8 D8 E8 F8 G8 H8
RFURFU
B7 C7 D7 E7 F7 G7 H7
B6 C6 D6 E6 F6 G6 H6
B5 C5 D5 E5 F5 G5 H5
B4 C4 D4 E4 F4 G4 H4
B3 C3 D3 E3 F3 G3 H3
B2 C2 D2 E2 F2 G2 H2
B1 C1 D1 E1 F1 G1 H1
V
IO
SS
DQ15NCA16A15A14A12
DQ13DQ14DQ7A11A10A8
DQ12DQ5A19A21RESET#
RFURFURFURFU
IO
CC
OE#CE#A0A1A2A4
RFURFURFUV
V
SS
DQ6
DQ4V
DQ3DQ11DQ10DQ2A20A18ACC
DQ1DQ9DQ8DQ0A5A6A17
V
SS
RFURFUV
Special Handling Instructions for FBGA/fBGA Packages
Special handling is required for Flash Memory products
in BGA packages.
Flash memory devices in BGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
8 Am29LV640D/Am29LV641D September 20, 2002
PIN DESCRIPTION
A0–A21 = 22 Addresses inputs
DQ0–DQ15 = 16 Data inputs/outputs
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP# = Hardware Write Protect input (N/A on
FBGA)
ACC = Acceleration Input
RESET# = H ardware Reset Pin input
RY/BY# = Ready/Busy output (FBGA only)
= 3.0 volt-only single power supply
V
CC
= Output Buffer power
V
IO
V
SS
NC = Pin Not Connected Internally
(see Product Selector Guide for
speed options and voltage
supply tolerances)
= Device Ground
LOGIC SYMBOL
22
A0–A21
CE#
OE#
WE#
WP#
ACC
RESET#
V
IO
Note: WP# is not available on the FBGA package. RY/BY#
is not available on the TSOP and SSOP packages.
DQ0–DQ15
RY/BY#
16
September 20, 2002 Am29LV640D/Am29LV641D 9
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29LV640D
Am29LV641D H 90R E I N
OPTIONAL PROCESSING
Blank= Standard Processing
N = 32-byte ESN devices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I = Industrial (–40
E = Extended (–55
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
Z = 56-Pin Shrink Sm all Outline Package (SSO056)
PC = 64-Ball Fortified Ball Grid Array (
1.0 mm pitch, 13 x 11 mm package (LAA064)
WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE063)
°C to +85°C)
°C to +125°C)
FBGA),
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0)
H = Uniform sector device, highest address sector protecte d
L = Uniform sector device, lowest address sector protected
U = Uniform sector device (WP# not available)
DEVICE NUMBER/DESCRIPTION
Am29LV640DU/DH/DL, Am29LV641DH/DL
64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO Control
3.0 Volt-only Read, Program, and Erase
Valid Combinations for
TSOP and SSOP Packages Speed/VIO Range
AM29LV640DH90R,
AM29LV640DL90R
AM29LV640DH101R,
AM29LV640DL101R
AM29LV641DH90R,
AM29LV641DL90R
AM29LV641DH101R,
AM29LV641DL101R
AM29LV640DH120R,
AM29LV640DL120R
AM29LV640DH121R,
AM29LV640DL121R
AM29LV641DH120R,
AM29LV641DL120R
AM29LV641DH121R,
AM29LV641DL121R
ZI
EI, FI
ZI, ZE
EI, FI, EE, FE
90ns,
V
= 3.0 V – 5.0 V
IO
100 ns,
V
= 1.8 V – 2.9 V
IO
90 ns
V
= 3.0 V – 5.0 V
IO
100 ns
V
= 1.8 V – 2.9 V
IO
120 ns,
V
= 3.0 V – 5.0 V
IO
120 ns,
V
= 1.8 V – 2.9 V
IO
120 ns,
V
= 3.0 V – 5.0 V
IO
120 ns
V
= 1.8 V – 2.9 V
IO
Note: LV640/641DH & DL have WP#, but no RY/BY#. U
designator in base part number replac ed by H or L.
Valid Combinations for BGA Packages
Package
Order Number
AM29LV640DU90R
AM29LV640DU101R
AM29LV640DU120R
AM29LV640DU121R
PCI L640DU90N
WHI L640DU90R
PCI L640DU01N
WHI
PCI,
PCE
WHI,
WHE
PCI,
PCE
WHI,
WHE
Marking
L640DU01R
L640DU12N
L640DU12R
L640DU21N
L640DU21R
Speed/
V
IO
90 ns, V
3.0 V – 5.0 V
I
100 ns, V
1.8 V – 2.9 V
120 ns, V
3.0 V – 5.0 V
I,
E
120 ns, V
1.8 V – 2.9 V
Range
IO
IO
IO
IO
=
=
=
=
Note: LV640DU has RY/BY#, but no WP#.
Valid Combinations
Valid Combinati ons list configurations plann ed to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
10 Am29LV640D/Am29LV641D September 20, 2002
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are in itiated through
the internal command register. The command register
itself does not occupy any addressabl e memory l ocation. The register is a latch used to store the commands, along with the ad dress and da ta information
needed to execute the command. The contents of the
Table 1. Device Bus Operations
register serve as inputs to the intern al state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control l evels they requir e, and the resultin g
output. The following subsections de scribe each of
these operations in further detail.
Operation CE# OE# WE# RESET# WP# ACC
Read L L H H
Write (Program/Erase) L H L H
Accelerated Program L H L H
±
V
Standby
Output Disable L H H H
Reset X X X L
Sector Group Protect (Note 2) L H L V
Sector Group Unprotect
(Note 2)
Temporary Sector Group
Unprotect
CC
0.3 V
XX
LHL V
XXX V
VCC ±
0.3 V
(Note 3) X
(Note 3) V
ID
ID
ID
XX
HH
XH
XX
XX
HX
HX
HX
Addresses
(Note 2)
A
IN
A
IN
A
IN
X High-Z
X High-Z
X High-Z
SA, A6 = L,
A1 = H, A0 = L
SA, A6 = H,
A1 = H, A0 = L
A
IN
DQ0–
DQ15
D
OUT
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
Legend: L = Logic Low = VIL, H = Logic Hig h = VIH, VID = 8.5–12.5 V, VHH = 1 1. 5–12.5 V, X = Don’t Care, SA = Sector Address,
= Address In, DIN = Data In, D
A
IN
= Data Out
OUT
Notes:
1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may al so be i mplemente d via programmi ng equipmen t. See the “Sector Group
Protection and Unprotection” sectio n.
3. If WP# = V
, the first or last sector remains protect ed. I f WP# = VIH, the first or last sector wi ll be protec ted or unprot ected as
IL
determined by the method described in “Sector Group Protection and Unprotection ”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be f actory protec ted depend ing on versi on order ed.)
4. D
IN
or D
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
OUT
VersatileIO (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/O s to the same voltag e
level that is asserted on V
configurations (1.8–2.9 V and 3.0–5.0 V) for operation
in various system environments.
For example, a V
of 4.5–5.0 volts allows for I/O at
I/O
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
. VIO is available in two
IO
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at V
.
IH
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs durin g the power transition. No com-
. CE# is the power
IL
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
September 20, 2002 Am29LV640D/Am29LV641D 11
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Read-Only Operations
table for timing specifications and to F igure 13 for the
timing diagram. I
in the DC Characteristics table
CC1
represents the activ e current specific ation for r eading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mo de, only two write cycles are required to program a word or byte, instead of four. The
“Word Program Command Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies.
I
CC2
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production.
, and OE# to VIH.
IL
in the DC Characteristics table represents the ac-
lect Command Sequence sections for more inform ation.
Standby Mode
When the system is n ot reading or wri ting to the device, it can place the device in the standby mode. In
this mode, current consum ption is greatly reduc ed,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
± 0.3 V.
CC
(Note that this is a more restricted voltage range tha n
.) If CE# and RESET# are held at VIH, but not within
V
IH
± 0.3 V, the device will be in the s tandby mode,
V
CC
but the standby current will be greater. The device requires standard ac cess time (t
) for read access
CE
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
in the DC Characteristics table represents the
I
CC3
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
in the DC Characteristics table represents the
I
CC4
automatic sleep mode current specification.
ACC
+
If the system as serts V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected se ctors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle pro gram comm and sequence
as required by the Unlock Bypass mode. Removing
from the ACC pin returns the device to normal op-
V
HH
eration. Note that the ACC pin must not be at V
operations other than accelerated program ming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect comman d sequence, the device enters the autoselect mo de. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
on this pin, the device auto-
HH
HH
for
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware meth od of resetting the device to reading array data. When the RESET# pin is dri ven low for at least a perio d of t
device immediately term inates any operation in
progress, tristates all output pins, and ignores all
read/write command s for the dur ation of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
but not within VSS±0.3 V, the standby current will
at V
IL
±0.3 V, the device
SS
). If RESET# is held
CC4
be greater.
RP
, the
this mode. Refer to the Autoselect M ode and Auto se-
12 Am29LV640D/Am29LV641D September 20, 2002
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is a sser ted duri ng a pr ogram or eras e op-
pleted within a time of t
Algorithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
ecuting (RY/BY# pin is “1”), the reset operation is com-
Table 2. Sector Address Table
Sector A21 A20 A19 A18 A17 A16 A15
SA0 0000000 000000–007FFF
SA1 0000001 008000–00FFFF
SA2 0000010 010000–017FFF
SA3 0000011 018000–01FFFF
SA4 0000100 020000–027FFF
(not during Embedded
READY
.
IH
16-bit Address Range
(in hexadecimal)
after the
RH
SA5 0000101 028000–02FFFF
SA6 0000110 030000–037FFF
SA7 0000111 038000–03FFFF
SA8 0001000 040000–047FFF
SA9 0001001 048000–04FFFF
SA10 0001010 050000–057FFF
SA11 0001011 058000–05FFFF
SA12 0001100 060000–067FFF
SA13 0001101 068000–06FFFF
SA14 0001110 070000–077FFF
SA15 0001111 078000–07FFFF
SA16 0010000 080000–087FFF
SA17 0010001 088000–08FFFF
SA18 0010010 090000–097FFF
SA19 0010011 098000–09FFFF
SA20 0010100 0A0000–0A7FFF
SA21 0010101 0A8000–0AFFFF
SA22 0010110 0B0000–0B7FFF
SA23 0010111 0B8000–0BFFFF
SA24 0011000 0C0000–0C7FFF
SA25 0011001 0C8000–0CFFFF
September 20, 2002 Am29LV640D/Am29LV641D 13
Table 2. Sector Address Table (Continued)
16-bit Address Range
Sector A21 A20 A19 A18 A17 A16 A15
SA26 0011010 0D0000–0D7FFF
SA27 0011011 0D8000–0DFFFF
SA28 0011100 0E0000–0E7FFF
SA29 0011101 0E8000–0EFFFF
SA30 0011110 0F0000–0F7FFF
SA31 0011111 0F8000–0FFFFF
SA32 0100000 100000–107FFF
SA33 0100001 108000–10FFFF
SA34 0100010 110000–117FFF
SA35 0100011 118000–11FFFF
SA36 0100100 120000–127FFF
SA37 0100101 128000–12FFFF
SA38 0100110 130000–137FFF
(in hexadecimal)
SA39 0100111 138000–13FFFF
SA40 0101000 140000–147FFF
SA41 0101001 148000–14FFFF
SA42 0101010 150000–157FFF
SA43 0101011 158000–15FFFF
SA44 0101100 160000–167FFF
SA45 0101101 168000–16FFFF
SA46 0101110 170000–177FFF
SA47 0101111 178000–17FFFF
SA48 0110000 180000–187FFF
SA49 0110001 188000–18FFFF
SA50 0110010 190000–197FFF
SA51 0110011 198000–19FFFF
SA52 0110100 1A0000–1A7FFF
SA53 0110101 1A8000–1AFFFF
SA54 0110110 1B0000–1B7FFF
SA55 0110111 1B8000–1BFFFF
SA56 0111000 1C0000–1C7FFF
SA57 0111001 1C8000–1CFFFF
SA58 0111010 1D0000–1D7FFF
SA59 0111011 1D8000–1DFFFF
SA60 0111100 1E0000–1E7FFF
14 Am29LV640D/Am29LV641D September 20, 2002
Table 2. Sector Address Table (Continued)
16-bit Address Range
Sector A21 A20 A19 A18 A17 A16 A15
SA61 0111101 1E8000–1EFFFF
SA62 0111110 1F0000–1F7FFF
SA63 0111111 1F8000–1FFFFF
SA64 1000000 200000–207FFF
SA65 1000001 208000–20FFFF
SA66 1000010 210000–217FFF
SA67 1000011 218000–21FFFF
SA68 1000100 220000–227FFF
SA69 1000101 228000–22FFFF
SA70 1000110 230000–237FFF
SA71 1000111 238000–23FFFF
SA72 1001000 240000–247FFF
SA73 1001001 248000–24FFFF
(in hexadecimal)
SA74 1001010 250000–257FFF
SA75 1001011 258000–25FFFF
SA76 1001100 260000–267FFF
SA77 1001101 268000–26FFFF
SA78 1001110 270000–277FFF
SA79 1001111 278000–27FFFF
SA80 1010000 280000–287FFF
SA81 1010001 288000–28FFFF
SA82 1010010 290000–297FFF
SA83 1010011 298000–29FFFF
SA84 1010100 2A0000–2A7FFF
SA85 1010101 2A8000–2AFFFF
SA86 1010110 2B0000–2B7FFF
SA87 1010111 2B8000–2BFFFF
SA88 1011000 2C0000–2C7FFF
SA89 1011001 2C8000–2CFFFF
SA90 1011010 2D0000–2D7FFF
SA91 1011011 2D8000–2DFFFF
SA92 1011100 2E0000–2E7FFF
SA93 1011101 2E8000–2EFFFF
SA94 1011110 2F0000–2F7FFF
SA95 1011111 2F8000–2FFFFF
September 20, 2002 Am29LV640D/Am29LV641D 15
Table 2. Sector Address Table (Continued)
16-bit Address Range
Sector A21 A20 A19 A18 A17 A16 A15
SA96 1100000 300000–307FFF
SA97 1100001 308000–30FFFF
SA98 1100010 310000–317FFF
SA99 1100011 318000–31FFFF
SA100 1100100 320000–327FFF
SA101 1100101 328000–32FFFF
SA102 1100110 330000–337FFF
SA103 1100111 338000–33FFFF
SA104 1101000 340000–347FFF
SA105 1101001 348000–34FFFF
SA106 1101010 350000–357FFF
SA107 1101011 358000–35FFFF
SA108 1101100 360000–367FFF
(in hexadecimal)
SA109 1101101 368000–36FFFF
SA110 1101110 370000–377FFF
SA111 1101111 378000–37FFFF
SA112 1110000 380000–387FFF
SA113 1110001 388000–38FFFF
SA114 1110010 390000–397FFF
SA115 1110011 398000–39FFFF
SA116 1110100 3A0000–3A7FFF
SA117 1110101 3A8000–3AFFFF
SA118 1110110 3B0000–3B7FFF
SA119 1110111 3B8000–3BFFFF
SA120 1111000 3C0000–3C7FFF
SA121 1111001 3C8000–3CFFFF
SA122 1111010 3D0000–3D7FFF
SA123 1111011 3D8000–3DFFFF
SA124 1111100 3E0000–3E7FFF
SA125 1111101 3E8000–3EFFFF
SA126 1111110 3F0000–3F7FFF
SA127 1111111 3F8000–3FFFFF
Note: All sectors are 32 Kwords in size.
16 Am29LV640D/Am29LV641D September 20, 2002
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is prim arily intend ed for progr amming equi pment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register .
When using programming equipment, the autoselect
mode requires V
Address pins A6, A1, and A0 must be as shown in
Description CE# OE# WE#
Manufacturer ID: AMD L L H X X V
Device ID: LV640DU/H/L,
LV641DH/L
Sector Protection
Verification
SecSi Sector Indicator Bit
(DQ7), WP# protects
highest address sector
(LV640DH/641DH), or
no WP# (LV640DU)
SecSi Sector Indicator Bit
(DQ7), WP# protects
lowest address sector
(LV640DL/641DL)
(8.5 V to 12.5 V) on address pin A9.
ID
Tabl e 3. Autoselect Codes, (High Voltage Method)
A21
to
A15
LLH X XV
LLHSAXV
LLH X XV
LLH X XV
A14
to
A10 A9
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3
shows the rema ining a ddress b its that ar e don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 10. This method
does not require V
. Refer to the Autoselect Com-
ID
mand Sequence section for more information.
A8
to
A7 A6
XLXLL 0001h
ID
XLXLH 22D7h
ID
XLXHL
ID
XLXHH
ID
XLXHH
ID
A5
to
A2 A1 A0 DQ15 to DQ0
XX01h (protected),
XX00h (unprotected)
XX98h (factory locked),
XX18h (not factory locked)
XX88h (factory locked),
XX08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
September 20, 2002 Am29LV640D/Am29LV641D 17
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