AMD Advanced Micro Devices AM29LV400BT-90SIB, AM29LV400BT-90SI, AM29LV400BT-90SEB, AM29LV400BT-90SE, AM29LV400BT-80FIB Datasheet
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PRELIMINARY
Publication# 21606 Rev: C Amendment/0
Issue Date: April 1998
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Simultaneous Read/Write operations
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Zero latency between read and write operations
— Read-while-erase
— Read-while-program
■ Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■ Manufactured on 0.35 µm process technology
■ High performance
— Access times as fast as 70 ns
■ Low current consumption (typical values
at 5 MHz)
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 17 mA active program-while-erase-suspended
current
— 200 nA in standby mode
— 200 nA in automatic sleep mode
— Standard t
CE
chip enable access time applies to
transition from automatic sleep mode to active
mode
■ Flexible sector architecture
— Two 16 Kword, two 8 Kword, four 4 Kword, and
six 32 Kword sectors in word mode
— Two 32 Kb yt e, two 16 Kbyte, four 8 Kbyte, and
six 64 Kbyte sectors in byte mode
— Any combination of sectors can be erased
— Supports full chip erase
■ Unlock Bypass Program Command
— Reduces overall progr amming time when
issuing multiple program command sequences
■ Sector protection
— Hardware method of locking a sector to prevent
any program or erase operation within that
sector
— Sectors can be locked in-system or via
programming equipment
— T emporary Sector Unprotect f eature allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
— Embedded Program algorithm automatically
programs and verifies data at specified address
■ Minimum 1 million program/erase cyc les
guaranteed per sector
■ Package options
— 44-pin SO
— 48-pin TSOP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Superior inadvertent write protection
■ Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— No need to suspend if sector is in the other bank
■ Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
2 Am29DL400B
PRELIMINARY
GENERAL DESCRIPTION
The Am29DL 400B is an 4 Mb it, 3.0 volt-only flas h
memory device, organized as 262,144 words or
524,288 bytes. The device is offered in 44-pin SO and
48-pin TSOP packages. The word-wide (x16) data ap-
pears on DQ0–DQ15; the byte-wide (x8) data appears
on DQ0–DQ7 . This device requir es only a single 3. 0
volt V
CC
supply to perform read , program, and erase
operations. A standard EPROM programmer can also
be used to program and erase the device.
The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high-speed microprocessors to
operate without wait states. Standard control pins—
chip enable (CE#), write enable (WE#), and out put enable (OE#)—control read and write operations, and
avoid bu s contention issues.
The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space
into two banks. Bank 1 contains boot/parameter sectors, and Bank 2 consists of larger, code sectors of uniform size. The device can improve overall system
performance by allowing a host system to program or
erase in one bank, then immediately and simultaneously read from the other bank, with zer o la tenc y. This
releases the system from waiting for the completion of
program or erase operations.
Am29DL400B Features
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard micr oprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase
operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequenc e. This initiates the Embedded Erase
algorithm—an in ternal algorithm that auto matically
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device automatically returns to
reading array data.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.
The hardware RESET# pin term inates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enab ling the system microprocessor to read the boot-up firmware from
the Flash memory.
The device off ers two power-sa ving f eatures. When addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash memory manufacturin g experience to produce th e highest
levels of quality, reliability, and cost effectiveness. The
device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are
programmed one byte or word at a time using hot electron injection.
Am29DL400B 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29DL400B
Speed Options (Full Voltage Range: V
CC
= 2.7 – 3.6 V) -70 -80 -90 -120
Max Access Time (ns) 70 80 90 120
CE# Access (ns) 70 80 90 120
OE# Access (ns) 30 30 35 50
V
CC
V
SS
Upper Bank Address
A0–A17
RESET#
WE#
CE#
BYTE#
DQ0–DQ15
STATE
CONTROL
&
COMMAND
REGISTER
RY/BY#
Upper Bank
X-Decoder
Y-Decoder
Latches and Control Logic
OE# BYTE#
DQ0–DQ15
Lower Bank
Y-Decoder
X-Decoder
Latches and
Control Logic
Lower Bank Address
Status
Control
A0–A17
A0–A17
A0–A17A0–A17
DQ0–DQ15 DQ0–DQ15
OE# BYTE#
21606C-1
4 Am29DL400B
PRELIMINARY
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
Reverse TSOP
Standard TSOP
21606C-2
Am29DL400B 5
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
21606C-3
6 Am29DL400B
PRELIMINARY
PIN DESCRIPTION
A0-A17 = 18 Addresses
DQ0-DQ14= 15 Data Inputs/Outputs
DQ15/A-1 = DQ15 (Data Input/Output, word mode),
A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output En able
WE# = Write Enable
BYTE# = Selects 8-bit or 16-bit mode
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
V
CC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
V
SS
= Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
21606C-4
18
16 or 8
DQ0–DQ15
(A-1)
A0–A17
CE#
OE#
WE#
RESET#
BYTE# R Y/BY#
Am29DL400B 7
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confir m availability of specifi c valid combinations to
check on newly released combinations.
DEVICE NUMBER/DES CR IPT IO N
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Am29DL400B -70 E C
T
OPTIONAL PROCESSING
Blank = Standa rd Pro ces sin g
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
Valid Combinations
Am29DL400BT-70
Am29DL400BB-70
EC, EI, FC, FI,
SC, SI
Am29DL400BT-80
Am29DL400BB-80
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
Am29DL400BT-90
Am29DL400BB-90
Am29DL400BT-120
Am29DL400BB-120
8 Am29DL400B
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29DL400B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D
OUT
= Data Out
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
IH
), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0-15 are active and controlled by CE#
and OE# .
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control and gates arra y data to the output pins . WE# should
remain at V
IH
. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array
data upon device po wer-u p , or after a hardw are res et.
This ensure s that no sp urious alteration of the memory content occurs dur ing the power transition. No
command is nece ssary in this mode to ob tain array
data. Standard microprocessor read cycles that assert valid addresses on the de vice addr ess inputs produce valid d ata on th e de vice data outputs . Each ban k
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I
CC1
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
Operation CE# OE# WE# RESET#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H A
IN
D
IN
D
IN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
D
IN
XX
Sector Unprotect (Note 2) L H L V
ID
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
XX
Temporary Sector Unprotect X X X V
ID
A
IN
D
IN
D
IN
High-Z
Am29DL400B 9
PRELIMINARY
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
For program operations, the BYT E# pin determin es
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the Unlock
Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Byte/Word
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
If the system writes the autoselect co mmand sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the write mode. The AC
Characteristics section contains timing specification tables and timing diagrams for write operations.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of readin g data from one bank of
memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or pro gram to another location
within the same bank (except the sector being erased).
Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency.
I
CC6
and I
CC7
in the DC Characteristics table represent
the current specificatio ns for read-while-program and
read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is gr eatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# ar e held at VIH, but not within
V
CC
± 0.3 V, the device will be in the standby mode , b ut
the standby current will be grea ter. The device requires
standard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enables
this mode when addresses remain stable f or t
ACC
+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC4
in the DC
Characteristics table represents the automatic sleep
mode current specification.
10 Am29DL400B
PRELIMINARY
RESET#: Hardware Reset Pin
The RESET# pin provides a har dware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse .
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the de vi ce is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embe dded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
Am29DL400B 11
PRELIMINARY
Table 2.
Am29DL400BT Top Boot Sector Architecture
Note: The address range is A17:A-1 if in byte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).
Bank Sector
Sector Address
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
(x16)
Address Range
Bank
Address
A15 A14 A13 A12A17 A16
Bank 2
SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
Bank 1
SA6 1 1 0 0 0 X 16/8 60000h–63FFFh 30000h–31FFFh
SA7 1 1 0
01X
32/16 64000h–6BFFFh 32000h–35FFFh
10X
SA8 1 1 0 1 1 0 8/4 6C000h–6DFFFh 36000h–36FFFh
SA9 1 1 0 1 1 1 8/4 6E000h–6FFFFh 37000h–37FFFh
SA10 1 1 1 0 0 0 8/4 70000h–71FFFh 38000h–38FFFh
SA11 1 1 1 0 0 1 8/4 72000h–73FFFh 39000h–39FFFh
SA12 1 1 1
01X
32/16 74000h–7BFFFh 3A000h–3DFFFh
10X
SA13 1 1 1 1 1 X 16/8 7C000h–7FFFFh 3E000h–3FFFFh
12 Am29DL400B
PRELIMINARY
Tab le 3. Am29DL400BB Bottom Boot Sector Architecture
Note: The address range is A17:A-1 if in byte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In a ddition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
ID
. Refer to the Autoselect Command
Sequence section for more information.
Bank Sector
Sector Address
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Bank
Address
A15 A14 A13 A12A17 A16
Bank 2
SA13 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh
SA12 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA11 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA10 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA9 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA8 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
Bank 1
SA7 0 0 1 1 1 X 16/8 1C000h–1FFFFh 0E000h–0FFFFh
SA6 0 0 1
10X
32/16 14000h–1BFFFh 0A000h–0DFFFh
01X
SA5 0 0 1 0 0 1 8/4 12000h–13FFFh 09000h–09FFFh
SA4 0 0 1 0 0 0 8/4 10000h–11FFFh 08000h–08FFFh
SA3 0 0 0 1 1 1 8/4 0E000h–0FFFFh 07000h–07FFFh
SA2 0 0 0 1 1 0 8/4 0C000h–0DFFFh 06000h–06FFFh
SA1 0 0 0
10X
32/16 04000h–0BFFFh 02000h–05FFFh
01X
SA0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh
Am29DL400B 13
PRELIMINARY
Table 4. Am29DL400B Autoselect Codes (High Voltage Method)
Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors. Sector protection/unprotecti on can be implemented via two methods.
The primary method requires V
ID
on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This
method uses standard m icroprocessor bus cycle timing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unpro tect write
cycle.
The alternate method intended on ly for programming
equipment requires V
ID
on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 v olt-only AMD flash de vices. Publication number 22145 contains further details; contact
an AMD representative to request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See the Autoselect Mode section for
details.
Temporary Sector Unprotect
This feature allows temporary unpr otection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to V
ID
(11.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once V
ID
is
removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the
algorithm, and Figur e 23 shows the timing diagrams,
for this feature.
Figure 1. Temporary Sector Unprotect Operation
Description Mode CE# OE# WE#
A17
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H BA X V
ID
XLXLL X 01h
Device ID:
Am29DL400B
(Top Boot Block)
Word L L H
BA X V
ID
XLXLH
22h 0C
Byte L L H X 0C
Device ID:
Am29DL400B
(Bottom Boot Block)
Word L L H
BA X V
ID
XLXLH
22h 0F
Byte L L H X 0F
Sector Protection Verification L L H SA X V
ID
XLXHL
X
01h
(protected)
X
00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
21606C-5
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