AMD Advanced Micro Devices Am29LV400T90RWACB, Am29LV400T90RWAC, Am29LV400T90RSIB, Am29LV400T90RSI, Am29LV400T90RSCB Datasheet
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PRELIMINARY
Publication# 20514 Rev: C Amendment/+2
Issue Date: July 1998
Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3. 6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3. 6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■ High performance
— Full voltage range: access times as fast as 100
ns
— Regulated voltage range: access times as fast
as 90 ns
■ Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— 20 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Typical 1,000,000 write cycles per sector
(100,000 cycles minimu m guaranteed)
■ Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the de vi ce to reading
array data
Am29LV400 2
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV400 is a 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. The wor d-wide data (x16)
appears on DQ 15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system using only a single 3.0 volt V
CC
supply. No VPP is required for write or erase operations. The device can also be programmed in standard
EPROM programmers.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wai t states . To eliminate bus contention the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already progr ammed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all b its wit hin
a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
3 Am29LV400
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV400
Speed Options
Regulated Voltage Range: VCC =3.0–3.6 V -90R
Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150
Max access time, ns (t
ACC
) 90 100 120 150
Max CE# access time, ns (tCE) 90 100 120 150
Max OE# access time, ns (tOE) 40 40 40 55
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A17
20514C-1
Am29LV400 4
PRELIMINARY
CONNECTION DIAGRAMS
A1
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
20514C-2
Reverse TSOP
Standard TSOP
5 Am29LV400
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
20514C-3
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 V
SS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5NCNCRESET#WE#
DQ11 DQ3DQ10DQ2NCNCNCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# V
SS
CE#A0A1A2A4A3
FBGA
Bump Side (Bottom) View
Am29LV400 6
PRELIMINARY
Special Handling Instructions for Fine
PItch Ball Grid Array (FBGA)
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the package bod y is exposed to
temperatures above 150°C for prolonged periods of
time.
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
V
CC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply toleranc es)
V
SS
= Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20514C-4
18
16 or 8
DQ0–DQ15
(A-1)
A0–A17
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
7 Am29LV400
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
CE90RAm29LV400 T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WA = 48-ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 8 mm package
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
Valid Combinations
Am29LV400T90R,
Am29LV400B90R
EC, EI, FC,
FI, SC, SI, WAC
Am29LV400T100,
Am29LV400B100
EC, EI, EE,
FC, FI, FE,
SC, SI, SE,
WAC, WAI, WAE
Am29LV400T120,
Am29LV400B120
Am29LV400T150,
Am29LV400B150
Am29LV400 8
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory loc ation.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV400 Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D
OUT
= Data Out
Note: Addresses are A17:A0 in word mode (BYTE# = V
IH
), A17:A-1 in byte mode (BYTE# = VIL).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are activ e and c ontrolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at V
IH
. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address input s produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to Figure 12 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To wr ite a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
For program operations, the BYTE # pin determines
whether the device accepts program data in bytes o r
words. Refer to “Word/Byte Configuration” for more information.
An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 i ndicate the
address space that each sector occupies. A “sector address” consists of the address b its requ ired to uni quely
select a sector. The “Command D efinitions” section
Operation CE# OE# WE# RESET#
Addresses
(See Note)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H A
IN
D
IN
D
IN
Standby
V
CC
±
0.3 V
XX
VCC ±
0.3 V
X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
T emporary Sector Unprotect X X X V
ID
A
IN
D
IN
D
IN
High-Z
9 Am29LV400
PRELIMINARY
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# ar e held a t VIH, but not within
V
CC
± 0.3 V, the device will be in the standby mode, b ut
the standby current will be greater. The device requires
standard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addres ses remain stable for
t
ACC
+ 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are chan ged. While in sleep
mode, output data is latched and always available to
the system. I
CC4
in the DC Characteristics table
represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby c urrent (I
CC4
). If RESET# is held
at V
IL
but not within VSS±0.3 V, the standby current will
be greater.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embe dded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
Am29LV400 10
PRELIMINARY
Table 2. Am29LV400T Top Boot Block Sector Address Table
Table 3. Am29LV400B Bottom Boot Block Sector Address Table
Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A171:A0 in word mode. See “Word/Byte Configuration”
section for more information.
Sector A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA71110XX 32/16 70000h–77FFFh38000h–3BFFFh
SA8111100 8/4 78000h–79FFFh3C000h–3CFFFh
SA9111101 8/4 7A000h–7BFFFh3D000h–3DFFFh
SA1011111X 16/8 7C000h–7FFFFh3E000h–3FFFFh
Sector A17 A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA000000X 16/8 00000h–03FFFh00000h–01FFFh
SA1000010 8/4 04000h–05FFFh02000h–02FFFh
SA2000011 8/4 06000h–07FFFh03000h–03FFFh
SA30001XX 32/16 08000h–0FFFFh04000h–07FFFh
SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh
11 Am29LV400
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Ta ble 4. In addition, when verifying s ector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
ID
. See “Command Definitions” for
details on using the autoselect mode.
Table 4. Am29LV400 Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
Sector protection/unprotection is implemented using
programming equipment, and requires V
ID
on address
pin A9 and OE#. Publication number 20873 contains
further details; contact an AMD representative to request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to V
ID
. During this mode, formerly protected
sectors can be programmed or erased b y selecting the
sector addresses. Once V
ID
is removed from the RESET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 21 shows the timing diagrams, for this feature.
Description Mode CE# OE# WE#
A17
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
ID
XLXLL X 01h
Device ID:
Am29LV400
(Top Boot Block)
Word L L H
XXVIDXLXLH
22h B9h
Byte L L H X B9h
Device ID:
Am29LV400
(Bottom Boot
Block)
Word L L H
XXV
ID
XLXLH
22h BAh
Byte L L H X BAh
Sector Protection Verification L L H SA X V
ID
XLXHL
X
01h
(protected)
X
00h
(unprotected)
Am29LV400 12
PRELIMINARY
Figure 1. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadverten t writes (refer to Table 5 for command definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up
and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = VIH or WE# = VIH. To initiate a wr ite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20514C-5
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