AMD Am29LV400 Service Manual

查询29LV400BA供应商

PRELIMINARY

Am29LV400

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

ns

— Regulated voltage range: access times as fast

as 90 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— 20 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked via programming

equipment

T emporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Top or bottom boot block configurations

■ Embedded Al gorithms

■ Typical 1,000,000 write cycles per sector

■ Package option

■ Compatibility with JEDEC standards

■ Data# Polling and toggle bits

■ Ready/Busy# pin (RY/BY#)

■ Erase Suspend/Erase Resume

■ Hardware reset pin (RESET#)

available

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

(100,000 cycles minimu m guaranteed)

— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

— Provides a software method of detecting

program or erase operation completion

— Provides a hardware method of detecting

program or erase cycle completion

— Suspends an erase operation to read data fr om,

or program data to, a sector that is not being
erased, then resumes the erase operation

— Hardware method to reset the device to reading

array data

Publication# 20514 Rev: C Amendment/+1
Issue Date: March 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV400 is a 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 48-ball FBGA, 44-pin SO, and
48-pin TSOP packages. The wor d-wide data (x16)

appears on DQ 15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system using only a single 3.0 volt V
supply. No VPP is required for write or erase opera­tions. The device can also be programmed in standard
EPROM programmers.

The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten­tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using
standard micropr ocessor write ti mings. Register c on­tents serve as input to an i nternal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and dat a needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically pre­programs the array (if it is not already programmed) be­fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

CC

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by re ading the DQ7 (D ata# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during p ower transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved via programming equipment.

The Erase Sus pend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two pow er-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device e lectrically erases a ll b its wit hin
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV400 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV400

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 90 100 120 150
Max OE# access time, ns (tOE) 40 40 40 55

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

) 90 100 120 150

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

DQ15 (A-1)

–

Input/Output

Buffers

Data

Latch

V

CC

V

SS

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A17

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

20514C-1

3 Am29LV400

CONNECTION DIAGRAMS

PRELIMINARY

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

NC

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

CE#

SS

CC

SS

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard TSOP

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1

20514C-2

Am29LV400 4

CONNECTION DIAGRAMS

PRELIMINARY

NC

RY/BY#

A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

Bump Side (Bottom) View

FBGA

A1 B1 C1 D1 E1 F1 G1 H1

CE#A0A1A2A4A3

OE# V

SS

A2 B2 C2 D2 E2 F2 G2 H2

DQ9 DQ1DQ8DQ0A5A6A17A7

A3 B3 C3 D3 E3 F3 G3 H3

DQ11 DQ3DQ10DQ2NCNCNCRY/BY#

A4 B4 C4 D4 E4 F4 G4 H4

V

CC

DQ4DQ12DQ5NCNCRESET#WE#

A5 B5 C5 D5 E5 F5 G5 H5

DQ13 DQ6DQ14DQ7A11A10A8A9

A6 B6 C6 D6 E6 F6 G6 H6

BYTE#A16A15A14A12A13

DQ15/A-1 V

SS

5 Am29LV400

20514C-3

PRELIMINARY

Special Handling Instructions for Fine
PItch Ball Grid Array (FBGA)

Special handling is required for Flash Memory products
in FBGA packages.

PIN CONFIGURATION

A0–A17 = 18 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

V

CC

(see Product Selector Guide for speed

options and voltage supply tolerances)

Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be
compromised if the p ackage body is exposed to
temperatures above 150°C fo r prolonged periods of
time.

LOGIC SYMBOL

18

A0–A17

DQ0–DQ15

(A-1)

CE#
OE#

WE#
RESET#
BYTE# RY/BY#

16 or 8

20514C-4

V

SS

= Device ground

NC = Pin not connected internally

Am29LV400 6

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE70RAm29LV400 T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WA = 48-ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package

Am29LV400T70R,
Am29LV400B70R

Am29LV400T80,
Am29LV400B80

Am29LV400T90,
Am29LV400B90

Am29LV400T120,
Am29LV400B120

Valid Combinations

EC, EI, FC,

FI, SC, SI, WAC

EC, EI, EE,

FC, FI, FE,

SC, SI, SE,

WAC, WAI, WAE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV400
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

7 Am29LV400

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the re quirements and us e of the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any ad dressable memory locatio n.
The register is composed of latches that store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Am29LV400 Device Bus Operations

register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. Table 1 lists the device bus operations, the in­puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A

±

V

CC

Standby

Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
T emporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: Addresses are A17:A0 in word mode (BYTE# = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D

IL

0.3 V

XX

VCC ±

0.3 V

ID

), A17:A-1 in byte mode (BYTE# = VIL).

IH

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active an d c ontrol­led by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 ar e ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

. The BYTE# pin determines

IH

whether the device outputs array data in words or
bytes.

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con­tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard

. CE# is the power

IL

(See Note)

IN

IN

X High-Z High-Z High-Z

A

IN

microprocessor read cycles that assert valid addre sses
on the device address inputs produce valid data on the
device data outputs. The device rem ains enabled for
read access until the command register contents are
altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 12 for the timing diagram. I

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

For program op erations, the BYTE# pin deter mines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more in­formation.

An erase operation can erase one sector, multiple sec­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad­dress” consists of the address b its requ ired to uni quely
select a sector. The “Command Definitions” section

, and OE# to VIH.

IL

DQ0–

DQ7

D

OUT

D

IN

D

IN

BYTE#

= V

IH

D

OUT

D

IN

D

IN

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

= Data Out

OUT

IL

in

CC1

Am29LV400 8

PRELIMINARY

has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode . The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, t he system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specificat ions apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mo de. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at VIH, but not within

V

IH

± 0.3 V , t he device will be in the standby mode, but

V

CC

the standby current will be greater . The devi ce requires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

in the DC Characteristics table represents the

I

CC3

standby current specification.

CC

± 0.3 V.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for

+ 30 ns. The automatic sleep mode is

t

ACC

independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are chan ged. While in sleep
mode, output data is latched and alway s available to
the system. I

in the DC Characteristics table

CC4

represents the automatic sleep mode current
specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t
device immediately terminates any oper ation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device a lso resets the internal sta te ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the devic e is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I

but not within VSS±0.3 V , the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operation is complete, which re quires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is co mplete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset opera tion is completed
within a time of t

READY

rithms). The system can read data t

(not during Embedded Algo-

after the RE -

RH

SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 13 for the timing diagram.

RP

, the

Output Disable Mode

When the OE# input is at VIH, output from the device is

9 Am29LV400

PRELIMINARY

Table 2. Am29LV400T Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A17 A16 A15 A14 A13 A12

SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA71110XX 32/16 70000h–77FFFh38000h–3BFFFh
SA8111100 8/4 78000h–79FFFh3C000h–3CFFFh
SA9111101 8/4 7A000h–7BFFFh3D000h–3DFFFh

SA1011111X 16/8 7C000h–7FFFFh3E000h–3FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Table 3. Am29LV400B Bottom Boot Block Sector Address Table

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Sector A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/
Kwords)

SA000000X 16/8 00000h–03FFFh00000h–01FFFh
SA1000010 8/4 04000h–05FFFh02000h–02FFFh
SA2000011 8/4 06000h–07FFFh03000h–03FFFh
SA30001XX 32/16 08000h–0FFFFh04000h–07FFFh
SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A171:A0 in word mode. See “Word/Byte Configuration”
section for more information.

Am29LV400 10

PRELIMINARY

Autoselect Mode

The autoselect mode provides manu facturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding progra mming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID:

Am29LV400
(Top Boot Block)

(11.5 V to 12.5 V) on address pin

ID

Table 4. Am29LV400 Autoselect Codes (High Voltage Method)

A17

A11

to

to

A12

A10 A9

Word L L H

Byte L L H X B9h

XXVIDXLXLH

Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care.
When all necessary bits have be en set as required, the
programming equipment may then read the corre­sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V

. See “Command Definitions” for

ID

details on using the autoselect mode.

A8

to

A7 A6

XLXLL X 01h

ID

A5

to

A2 A1 A0

DQ8

to

DQ15

22h B9h

DQ7

to

DQ0

Device ID:
Am29LV400
(Bottom Boot
Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sec tor. The hard­ware sector unprotection feature re-enables both pro-

Word L L H

Byte L L H X BAh

XXV

XLXLH

ID

XLXHL

ID

through AMD’s ExpressFlash™ Service. Contact a n
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

gram and erase operations in pre viously protected
sectors.

Sector protection/unprotection is implemented using
programming equipment, and requires V

on address

ID

pin A9 and OE# . Publication numb er 20873 contains
further details; contact an AMD representative to re­quest a copy.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased by selec ting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 21 shows the timing diagrams, for this feature.

22h BAh

X

X

. During this mode, formerly protected

ID

is removed from the RE-

ID

01h

(protected)

00h

(unprotected)

11 Am29LV400

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

ID

IH

20514C-5

against inadvertent writes ( refer to Table 5 for com­mand definitions). In add ition, the following hardwar e
data protection mea sures prevent accid ental erasure
or programming, which might otherwise be caused by
spurious system level signals during V

power-up

CC

and power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero wh ile OE# is a
logical one.

Figure 1. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up, the

IL

device does not accept commands on the rising edge
of WE#. The internal state machin e is automatically
reset to reading array data on power-up.

Am29LV400 12