AMD Am29LV320MT, Am29LV320MB Service Manual

查询AM29LV320MB100E供应商

DATASHEET

Am29LV320MT/B

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit

3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Single power supply operation

— 3 V for read, erase, and program operations

■ Manufactured on 0.23 µm MirrorBit process

technology

■ SecSi (Secured Si licon) Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-w ord /16 -by te rand om
Electronic Serial Number, accessible through a
command sequence

— May be programmed and locked at the factory or by

the customer

■ Flexible sector architecture

— Sixty-three 32 Kword/64- Kby te sec tors
— Eight 4 Kword/8 Kbyte boot sectors

■ Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent
write protection

■ Minimum 100,000 erase cycle guaran tee per sect or

■ 20-year data retention at 125°C

PERFORMANCE CHA RA CT ER IST ICS

■ High performance

— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multipl e-w ord /byt e upda tes
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer

■ Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current

■ Package options

— 48-pin TSOP
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

■ Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operat ion is com ple ted
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall

multiple-word programming time
— CFI (Com mon F lash Inte rfac e) com plia nt: a llow s hos t

system to identify and accommodate multiple flash

devices

■ Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group
— Temporary Sector Unprotect: V

changing code in locked sectors
— WP#/ACC input:

Write Protect input (WP#) protects top or bottom two

sectors regardless of sector protection settings

ACC (high voltage) accelerates programming time for

higher throughput during system production
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

-level method of

ID

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 26518 Rev: B Amendment/0
Issue Date: May 16, 2003

DATASHEET

GENERAL DESCRIPTION

The Am29LV320M/TB is a 32 Mbit, 3.0 volt single
power supply flash memory device organized as
2,097,152 words or 4,194,304 bytes. The device has
an 8-bit/16-bit bus and can be programmed either in
the host system or in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.
Note that each a ccess time has a spec ific operat ing
voltage range (V
specified in the Product Selector Guide and the Order-

ing Information sections. The devic e is offered in a

48-pin TSOP, 48-ball Fine-pitch BGA or 64-ball Forti­fied BGA package. Each device has separate chip en­able (CE#), write enable (WE#) and output enable
(OE#) controls.

Each device requires on ly a single 3.0 volt power
supply for both read and write functions. In addition to

input, a high-voltage accelerated program

a V

CC

(ACC) function provides shorter programming times
through increased current on the WP#/ACC input. This
feature is intended to facilitate factory throughput dur­ing system production, but may also be used in the
field if desired.

The device is entirely command set compatible with
the JEDEC single-pow er-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter­nally latch address es and data nee ded for the pro­gramming and erase operations.

The sector erase architec ture allow s memory sec­tors to be erased and reprogrammed without affecting
the data conten ts of oth er se ctors. T he devi ce is f ully
erased when shipped from the factory.

Device programming and erasure are initiated through
command sequences. Once a program or erase oper­ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter­mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com­mand sequence overhead by requiring only two write
cycles to program data instead of four.

) and an I/O voltage range (VIO), as

CC

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.

The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operati on. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro­gram operation.

The hardware RESET# p in terminates any opera tion
in progress and resets the device, after which it is then
ready for a new operation. T he RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.

The device redu ces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.

The Write Protect (WP#) feature protects the top or
bottom two sectors by asserting a logic low on the
WP#/ACC pin. The protected sector will still be pro­tected even during accelerated programming.

The SecSi (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.

AMD MirrorBit flash technology combines years of
Flash memory manufacturing experienc e to produce
the highest levels of quality, reliability and cost effec­tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.

2 Am29LV320MT/B May 16, 2003

DATASHEET

MIRRORBIT 32 MBIT DEVICE FAMILY

Device Bus Sector Architecture Packages VIORY/BY# WP#, ACC WP# Protection

LV033MU x8 Uniform (64 Kbyte)

LV320MT/B x8/x16

LV320MH/L x8/x16 Uniform (64 Kbyte)

Boot (8 x 8 Kbyte

at top & bottom)

40-pin TSOP (std. & rev. pinout),

48-ball FBGA

48-pin TSOP, 48-ball Fine-pitch BGA,

64-ball Fortified BGA

56-pin TSOP (std. & rev. pinout),

64-ball Fortified BGA

Yes Yes ACC only No WP#

No Ye s WP#/ACC pin

Yes Yes WP#/ACC pin

2 x 8 Kbyte

top or bottom

1 x 64 Kbyte

high or low

RELATED DOCUMENTS

To download related documents, click on the following
links or go to www.amd.com
uct Information

→MirrorBit→Flash Information→Tech-

→Flash Memory→Prod-

nical Documentation.

MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read

Implementing a Commo n Layout for AMD Mi rrorBit
and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs
AMD MirrorBit™ White Paper

May 16, 2003 Am29LV320MT/B 3

DATASHEET

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5

Block Diag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operation s ....................... ............................ ..10

Requirements for Reading Array Data ........................ ...........10

Writing Commands/Command Sequences ............................11

Automatic Sleep Mode ................. ............ ............ ..................12

RESET#: Hardware Reset Pi n ................................. ..............12

Output Disable Mode ..............................................................12

Table 2. Am29LV320MT Top Boot Sector Architecture ..................12

Table 3. Am29LV320MB Bottom Boot Sector Architecture .............14

Table 4. Autoselect Codes, (High Voltage Method) .......................16

Sector Group Protection and Unprotection .............................17

Table 5. Am29LV320MT Top Boot Sector Protection .....................17

Table 6. Am29LV320MB Bottom Boot Sector Protection ................17

Write Protect (WP#) ................................................................17

Temporary Sector Group Unprotect ....................................... 18

Figure 1. Temporary Sector Group Unprotect Operation................ 18

Figure 2. In-System Sector Group Protect/Unprotect A lgorit hm s ... 19

SecSi (Secured Silicon) Sector Flash Memory Region ..........20

Table 7. SecSi Sector Contents ......................................................20

Figure 3. SecSi Sector Protect Verify.............................................. 21

Hardware Data Protection ......................................................21

Common Flash Memory Interface (CFI). . . . . . . 21

Command Definitions . . . . . . . . . . . . . . . . . . . . . 24

Reading Array Data ................................................................24

Reset Command ................. .................................. ............ ......25

Autoselect Command Sequence ............................................25

Enter SecSi Sector/Exit SecSi Sector CommandSequence ..25

Word/Byte Program Command Sequence .............................25

Figure 4. Write Buffer Programming Operation............................... 28

Figure 5. Program Operation............................................. ............. 29

Program Suspend/Program Resume Command Sequence ...29

Figure 6. Program Suspend/Program Resume............................... 30

Chip Erase Command Sequence ...........................................30

Sector Erase Command Sequence ........................................30

Figure 7. Erase Operation............................................................... 31

Erase Suspend/Erase Resume Commands ................ ...........31

Write Operation Status . . . . . . . . . . . . . . . . . . . . 34

DQ7: Data# Polling ................................................................. 34

Figure 8. Data# Polling Algorithm ................................................... 34

DQ6: Toggle Bit I ....................................................................35

Figure 9. Toggle Bit Algorithm......................................................... 36

DQ2: Toggle Bit II ...................................................................36

Reading Toggle Bits DQ6/DQ2 ..............................................36

DQ5: Exceeded Timing Limits ................................................ 37

DQ3: Sector Era s e Time r ..................... ... .. .............. ... .. ..........37

DQ1: Write-to-B u ffer A b o rt .................................. .. .. ... ............37

Table 14. Write Operation Sta tus ........................ .............. .............37

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 38

Figure 10. Maximum Negative Overshoot Waveform................... 38

Figure 11. Maximum Positive Overshoot Waveform..................... 38

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. Test Setup..... ............................ ............................ ....... 40

Table 15. Test Specifications ............................................ .............40

Key to Switching Waveforms. . . . . . . . . . . . . . . . 40

Figure 13. Input Waveforms and

Measurement Levels...................................................................... 40

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

Read-Only Operations ...........................................................41

Figure 14. Read Operation Timings. . .............. ....................... ........ 41

Figure 15. Page Read Timings...................................................... 42

Hardware Reset (RESET#) ....................................................43

Figure 16. Reset Timings............................................................... 43

Erase and Program Operations .............................................. 44

Figure 17. Program Operation Timings.......................................... 45

Figure 18. Accelerated Program Timing Diagram.......................... 45

Figure 19. Chip/Sector Erase Operation Timings.......................... 46

Figure 20. Data# Polling Timings (During Embedded Algorithms). 47

Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 48

Figure 22. DQ2 vs. DQ6......................... ........................................ 48

Temporary Sector Unprotect ..................................................49

Figure 23. Temporary Sector Group Unprotect Timing Dia gram ... 49
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 50

Alternate CE# Controlled Erase and ProgramOperations .....51

Figure 25. Alternate CE# Controlled Write (Erase/Program)

OperationTimings....................... .............. ........................... .......... 52

Erase And Programming Performan ce. . . . . . . . 53

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 53

TSOP Pin and BGA Package Capacitance . . . . . 54

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 55

TS 048—48-Pin Standard Pinout Thin Small Outline Package

(TSOP) ................................................................................... 55

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56

TS 048—48-Pin Standard Pinout Thin Small Outline Package

(TSOP) ................................................................................... 56

FBC048—48-Ball Fine-pitch Ball Grid Array (fBGA)

9 x 8 mm P ackage ........... ................... ..................... ............... 5 7

Physical Dimensions
LAA064—64-Ball Fortified Ball Grid Array (FBGA)

13 x 11 mm Package. . . . . . . . . . . . . . . . . . . . . . . 58

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 60

4 Am29LV320MT/B May 16, 2003

DATASHEET

PRODUCT SELECTOR GUIDE

Part Number Am29LV320MT/B

V

= 3.0–3.6 V 90R 100R 110R 120R

Speed
Option

Max. Access Time (ns) 90 100 110 120
Max. CE# Access Time (ns) 90 100 110 120

CC

V

= 2.7–3.6 V 100 110 120

CC

Max. Page access time (t

)25 30 30403040

PACC

Max. OE# Access Time (ns) 25 30 30 40 30 40

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–DQ15 (A-1)

Input/Output

Buffers

Data

Latch

V

CC

V

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

RY/BY#

Sector Switches

SS

Erase Voltage

Generator

State

Control

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

STB

Logic

A20–A0

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

May 16, 2003 Am29LV320MT/B 5

CONNECTION DIAGRAMS

DATASHEET

A15
A14
A13
A12
A11
A10

A9

A8
A19
A20

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18
A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48-Pin Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

48-ball Fine-pitch BGA

Top View, Balls Facing Down

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1

A5 B5 C5 D5 E5 F5 G5 H5

DQ13 DQ6DQ14DQ7A11A10A8A9

A4 B4 C4 D4 E4 F4 G4 H4

V

A3 B3 C3 D3 E3 F3 G3 H3

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

A2 B2 C2 D2 E2 F2 G2 H2

DQ9 DQ1DQ8DQ0A5A6A17A7

A1 B1 C1 D1 E1 F1 G1 H1

OE#

V

CC DQ4DQ12DQ5A19NCRESET#WE#

V

SSBYTE#A16A15A14A12A13

SSCE#A0A1A2A4A3

6 Am29LV320MT/B May 16, 2003

CONNECTION DIAGRAMS

DATASHEET

64-Ball Fortified BGA

Top View, Balls Facing Down

A8

NC

A7

A13

A6
A9

A5

WE#

A4

RY/BY#

A3

A7

A2

A3

A1
NC

B8 C8 D8 E8 F8 G8 H8

NCNCNC

B7 C7 D7 E7 F7 G7 H7

B6 C6 D6 E6 F6 G6 H6

B5 C5 D5 E5 F5 G5 H5

B4 C4 D4 E4 F4 G4 H4

B3 C3 D3 E3 F3 G3 H3

B2 C2 D2 E2 F2 G2 H2

B1 C1 D1 E1 F1 G1 H1

SS

DQ15/A-1BYTE#A16A15A14A12

DQ13DQ14DQ7A11A10A8

DQ12DQ5A19NCRESET#

CC

OE#CE#A0A1A2A4

NCNCNCV

V

SS

DQ6

DQ4V

DQ3DQ11DQ10DQ2A20A18WP#/ACC

DQ1DQ9DQ8DQ0A5A6A17

V

SS

NCNCNCNCNCNCNC

Special Package Handling Instructions

and/or data integrity may be compromi sed if the
package body is exposed to temperatures above 150°C

Special handling is required for Flash Memory products

for prolonged periods of time.

in molded packages (TSOP and BGA). The package

May 16, 2003 Am29LV320MT/B 7

DATASHEET

PIN DESCRIPTION

A20–A0 = 21 Address inputs
DQ14–DQ0 = 15 Data inputs/outputs
DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP#/ACC = Hardware Write Protect input/Pro-

gramming Acceleration input
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
BYTE# = Selects 8-bit or 16-bit mode

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for

speed options and voltage

supply tolerances)

= Device Ground

LOGIC SYMBOL

21

A20–A0

CE#
OE#
WE#

WP#/ACC
RESET#
BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

8 Am29LV320MT/B May 16, 2003

DATASHEET

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29LV320M T 120R PC I

TEMPERATURE RANGE

I = Industrial (–40

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
PC = 64-Ball Fortified Ball Grid Array (

1.0 mm pitch, 13 x 11 mm package (LAA064)

WC = 48-Ball Fine Pitch Ball Grid Array (FBGA),

0.80 mm pitch, 9 x 8 mm package (FBC048)

SPEED OPTION

See Product Selector Guide a nd Valid Combinations

°C to +85°C)

FBGA),

SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = V

T = Top boot sector device, top two address secto rs protected
B = Bottom boot sector device, bottom two address sectors protected

DEVICE NUMBER/DESCRIPTION

Am29LV320MT/B
32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit Boot Sector Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Am29LV320MT90R,
Am29LV320MB90R

Am29LV320MT100,
Am29LV320MB100

Am29LV320MT110,
Am29LV320MB110

Am29LV320MT120,
Am29LV320MB120

Am29LV320MT100R,
Am29LV320MB100R

Am29LV320MT110R,
Am29LV320MB110R

Am29LV320MT120R,
Am29LV320MB120R

Speed

(ns)

90 3.0–3.6 V

100

110

EI

120

100

110

120

V

CC

Range

2.7–3.6 V

3.0–3.6 V

Valid Combinations

Valid Com binations l ist c onfi gurations pl anned to be supported in vol­ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re­leased combinations.

Valid Combinations for

BGA Packages

Order Number Package Markin g

Am29LV320MT90R

Am29LV320MB90R

Am29LV320MT100

Am29LV320MB100

Am29LV320MT110

Am29LV320MB110

Am29LV320MT120

Am29LV320MB120

Am29LV320MT100R

Am29LV320MB100R

Am29LV320MT110R

Am29LV320MB110R

Am29LV320MT120R

Am29LV320MB120R

WCI L320MT90QI

PCI L320MT90NI

WCI L320MB90QI

PCI L320MB10NI

WCI L320MT10UI

PCI L320MT10PI

WCI L320MB10UI

PCI L320MB10PI

WCI L320MT11UI

PCI L320MT11PI

WCI L320MB11UI

PCI L320MB11PI

WCI L320MT12UI

PCI L320MT12PI

WCI L320MB12UI

PCI L320MB12PI

WCI L320MT10QI

PCI L320MT10NI

WCI L320MB10QI

PCI L320MB10NI

WCI L320MT11QI

PCI L320MT11NI

WCI L320MB11QI

PCI L320MB11NI

WCI L320MT12QI

PCI L320MT12NI

WCI L320MB12QI

PCI L320MB12NI

IL

)

Speed

(ns)

90

100

110

120

100

110

120

V

CC

Range

3.0–

3.6 V

2.7–

3.6 V

3.0–

3.6 V

3.0–

3.6 V

May 16, 2003 Am29LV320MT/B 9

DATASHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of
the device bus operations, which are in itiated through
the internal command register. The command register
itself does not occupy any addressabl e memory l oca­tion. The register is a latch used to store the com­mands, along with the ad dress and da ta information
needed to execute the command. The contents of the

Table 1. Device Bus Operations

register serve as inputs to the intern al state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control l evels they requir e, and the resultin g
output. The following subsections de scribe each of
these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET# WP# ACC

Read L L H H
Write (Program/Erase) L H L H (Note 3) X A
Accelerated Program L H L H

±

V

Standby

Output Disable L H H H
Reset X X X L

Sector Group Protect
(Note 2)

Sector Group Unprotect
(Note 2)

T emporary Sector Group
Unprotect

CC

0.3 V

XX

LHL V

LHL V

XXX V

V

CC

0.3 V

ID

ID

ID

±

XX

(Note 3) V

HH

XH

XX
XX

HX

HX

HX A

(Note 2)

SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L

SA, A6=H,
A3=L, A2=L,
A1=H, A0=L

DQ0–

DQ7

A

IN

IN

A

IN

X

X
X

D
(Note 4) (Note 4)
(Note 4) (Note 4)

High-Z High-Z High-Z

High-Z High-Z High-Z
High-Z High-Z High-Z

(Note 4) X X

(Note 4) X X

IN

(Note 4) (Note 4) High-Z

OUT

BYTE#

= V

IH

D

OUT

BYTE#

= V

IL

DQ8–DQ14

= High-Z,

DQ15 = A-1

Legend: L = Logic Low = VIL, H = Logic Hi gh = VIH, VID = 11.5–12.5 V, VHH = 11.5–12. 5 V , X = Do n’t Care , SA = Sect or Addr ess ,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A12 in both modes.

2. The sector protect and sector unprotect functions may al so be i mplemente d via programmi ng equipmen t. See the “Sector Group
Protection and Unprotection” sectio n.

3. If WP# = V

, the first or last sector remains protect ed. I f WP# = VIH, the top two or bottom two sectors wi ll be prot ected or

IL

unprotected as determined by the method d escribe d in “Sector Group Pr otecti on and Unprotect ion ”. All sector s are unprote cted
when shipped from the factory (The SecSi Secto r may be facto ry pr otected depending on ver sion or dered.)

4. D

IN

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

OUT

Word/Byte Configuration

The BYTE# pin controls whether the de vice data I/O
pins operate in the b yte or word confi guration. If the
BYTE# pin is set at logic ‘1’, the device is in word con­figuration, DQ0–DQ15 are active and co ntrolled by
CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

. CE# is the power

IL

10 Am29LV320MT/B May 16, 2003

DATASHEET

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs durin g the power transition. No com­mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 14 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper­ation. This mode provides faster read access speed
for random locations wi thin a page. T he page s ize of
the device is 4 words/8 bytes. The appropriate page is
selected by th e higher addres s bits A(ma x)–A2. A d­dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specif ic wor d withi n a page. This is an
asynchronous operation; the m icroprocesso r supplies
the specific word location.

The random or initial page access is equal to t

and subsequent page read accesses (as long as

t

CE

ACC

or

the locations specified by the microprocessor falls
within that page) is equival ent to t

. When CE# is

PACC

deasserted and reasserted for a subsequent access,
the access time is t

or tCE. Fast page mode ac-

ACC

cesses are obtained by keeping the “read-page ad­dresses” constant and cha nging the “i ntra-read p age”
addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device features an Unlock Bypass mode to facil­itate faster programming. Once the device enters the
Unlock Bypass mo de, only two write cycles are re­quired to program a word or byte, instead of four. The
“Word/Byte Program Co mmand Sequenc e” section
has details on programming data to the device using
both standard and Unlock Bypass command se­quences.

An erase operation can erase one sector, multiple sec­tors, or the entire device. Tables 3 and 2 indicates the
address space that each sector occupies.

Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-

, and OE# to VIH.

IL

acteristics section contains timing spec ification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.

Accelerated Program Operation

The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima­rily intended to allow faster manu facturing throu ghput
at the factory.

If the system asserts V

on this pin, the device auto-

HH

matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protec ted sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle progra m command sequence
as required by the Unlock Bypass mode. Removing

from the WP#/ACC p in returns th e device to nor-

V

HH

mal operation. N ote that the WP# /ACC pin must not

be at V

for operations oth er than acceler ated pro-

HH

gramming, or device damage may result. In addition,
no external pullup is necessary since the WP#/ACC
pin has internal pullup to V

CC

.

Autoselect Functions

If the system writes the autoselect command s e­quence, the device enters the autoselect mo de. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect M ode and Au tose-

lect Command Sequence sections for m ore informa-

tion.

Standby Mode

When the system is n ot reading or wri ting to the de­vice, it can place the device in the standby mode. In
this mode, current consum ption is greatly reduc ed,
and the outputs are placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range tha n

.) If CE# and RESET# are held at VIH, but not within

V

IH

± 0.3 V, the device will be in the s tandby mode,

V

CC

but the standby current will be greater. The device re­quires standard ac cess time (t

) for read access

CE

when the device is in either of these standby modes,
before it is ready to read data.

± 0.3 V.

CC

May 16, 2003 Am29LV320MT/B 11

DATASHEET

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

Refer to the DC Characteristics table for the standby
current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en­ergy consumption. The device automatically enables
this mode when addresses remain stable for t

ACC

+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad­dress access timings provide new data when ad­dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware me thod of re­setting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t
device immediately term inates any operation in
progress, tristates all output pins, and ignores all

RP

, the

read/write command s for the dur ation of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.

Table 2. Am29LV320MT Top Boot Sector Architecture

Sector

SA0 000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA14 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA16 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA17 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA19 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA20 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA21 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA22 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA23 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA24 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA25 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

12 Am29LV320MT/B May 16, 2003

DATASHEET

Table 2. Am29LV320MT Top Boot Sector Architecture (Continued)

Sector

SA28 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA30 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA31 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA32 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D 8000h–1DFFFFh
SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh
SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

May 16, 2003 Am29LV320MT/B 13

DATASHEET

Table 3. Am29LV320MB Bottom Boot Sector Architecture

Sector

SA0 000000000 8/4 000000h–001FFFh 00000h–00FFFh

SA1 000000001 8/4 002000h–003FFFh 01000h–01FFFh

SA2 000000010 8/4 004000h–005FFFh 02000h–02FFFh

SA3 000000011 8/4 006000h–007FFFh 03000h–03FFFh

SA4 000000100 8/4 008000h–009FFFh 04000h–04FFFh

SA5 000000101 8/4 00A000h–00BFFFh 05000h–05FFFh

SA6 000000110 8/4 00C000h–00DFFFh 06000h–06FFFh

SA7 000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh

SA8 000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh

SA9 000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh
SA10 000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh
SA11 000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh
SA12 000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh
SA13 000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh
SA14 000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh
SA15 001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh
SA16 001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh
SA17 001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh
SA18 001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh
SA19 001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA20 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA21 001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA22 001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA23 010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA24 010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA25 010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA26 010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA27 010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA28 010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA29 010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA30 010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA31 011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA32 011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA33 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA34 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA35 011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA36 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA37 011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA38 011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA39 100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA40 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA41 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA42 101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA43 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA44 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA45 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA46 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA47 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA48 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA49 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA50 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA51 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA52 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA53 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

14 Am29LV320MT/B May 16, 2003

DATASHEET

Table 3. Am29LV320MB Bottom Boot Sector Architecture (Continued)

Sector

SA54 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA55 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA56 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA57 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA58 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA59 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA60 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA61 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA62 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA63 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA64 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D 8000h–1DFFFFh
SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA69 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA70 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh

Sector Address

A20–A12

Note: The address range is A20:A-1 in byte mode (BYTE# = VIL) or A20:A0 in word mode (BYTE# = VIH)

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

Address Range

(x16)

May 16, 2003 Am29LV320MT/B 15

DATASHEET

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is prim arily intend ed for progr amming equi p­ment to automatically match a device to be pro­grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register .

When using programming equipment, the autoselect
mode requires V
A6, A3, A2, A1, and A0 must be as shown in Table 4.

on address pin A9. Address pins

ID

In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Tables 2 and 3). Table 4 shows the
remaining address bits that are do n’t care. W hen all
necessary bits have been set as required, the pro­gramming equipment may then read the correspond­ing identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 12 and 13. This
method does not require V

. Refer to t he Aut os ele ct

ID

Command Sequence section for more information.

Tabl e 4. Autoselect Codes, (High Voltage Method)

A21

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X

Cycle 1
Cycle 2 H H L 22 X 1Ah

Device ID

Cycle 3 H H H 22 X

Sector Protection
Verification

SecSi Sector In d i cator
Bit (DQ7), WP#
protects top two
address sector

SecSi Sector Indicator
Bit (DQ7), WP#
protects bottom two
address sector

LLHXX

LLHSAX

LLHXX

LLHXX

to

A15

A14

to

A9A8toA7A6A5to

A10

V

ID

V

ID

V

ID

V

ID

V

ID

XLX L L L 00 X 01h

XLX

XLX L H L X X

XLX L HH X X

XLX L HH X X

A3

toA2A1 A0

A4

LLH 22 X 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

IH

= V

DQ7 to DQ0

IL

00 (bottom boot)

01h (top boot)

01h (protected),

00h (unprotected)

98h (factory locked),

18h (not factory locked)

88h (factory locked),

08h (not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

16 Am29LV320MT/B May 16, 2003

DATASHEET

Sector Group Protection and
Unprotection

The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of fou r
adjacent sectors that are protected or unprotected at
the same time (see Tables 5 and 6). The hardware
sector group unprotection feature re-enables both pro­gram and erase operations in previously protected
sector groups. Sector group protection/unprotection
can be implemented via two methods.

Sector protection/unprotection requires V
SET# pin only, and can be implemented either in-sys­tem or via progr amming eq uipment. Figure 2 sh ows
the algorithms and Figure 24 shows the timing dia­gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro­tected sector groups must first be protected prior to
the first sector group unprotect write cycle.

The device is shipped with all se ctor groups unpro­tected. AMD offers the option of programming and
protecting sector groups at its factory prior to shipping
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.

It is possible to determin e whether a se ctor group is
protected or unprotected. See the Autoselect Mode
section for details.

Table 5. Am29LV320MT Top Boot

Sector Protection

Sector A20–A12

SA0-SA3 0000XXXXXh 256 (4x64) Kbytes
SA4-SA7 0001XXXXXh 256 (4x64) Kbytes

SA8-SA11 0010XXXXXh 256 (4x64) Kbytes
SA12-SA15 0011XXXXXh 256 (4x64) Kbytes
SA16-SA19 0100XXXXXh 256 (4x64) Kbytes
SA20-SA23 0101XXXXXh 256 (4x64) Kbytes
SA24-SA27 0110XXXXXh 256 (4x64) Kbytes
SA28-SA31 0111XXXXXh 256 (4x64) Kbytes

SA32–SA35 1000XXXXXh, 256 (4x64) Kbytes
SA36–SA39 1001XXXXXh 256 (4x64) Kbytes
SA40–SA43 1010XXXXXh 256 (4x64) Kbytes
SA44–SA47 1011XXXXXh 256 (4x64) Kbytes
SA48–SA51 1100XXXXXh 256 (4x64) Kbytes

SA52-SA55 1101XXXXXh 256 (4x64) Kbytes
SA56-SA59 1110XXXXXh 256 (4x64) Kbytes

SA60-SA62

SA63 111111000h 8 Kbytes
SA64 111111001h 8 Kbytes
SA65 111111010h 8 Kbytes

111100XXXh
111101XXXh
111110XXXh

on the RE-

ID

Sector/

Sector Block Size

192 (3x64) Kbytes

Sector A20–A12

SA66 111111011h 8 Kbytes
SA67 111111100h 8 Kbytes
SA68 111111101h 8 Kbytes
SA69 111111110h 8 Kbytes
SA70 111111111h 8 Kbytes

Sector/

Sector Block Size

Table 6. Am29LV320MB Bottom Boot

Sector Protection

Sector A20–A12

SA0 000000000h 8 Kbytes
SA1 000000001h 8 Kbytes
SA2 000000010h 8 Kbytes
SA3 000000011h 8 Kbytes
SA4 000000100h 8 Kbytes
SA5 000000101h 8 Kbytes
SA6 000000110h 8 Kbytes
SA7 000000111h 8 Kbytes

SA8–SA10

SA11–SA14 0001XXXXXh 256 (4x64) Kbytes
SA15–SA18 0010XXXXXh 256 (4x64) Kbytes
SA19–SA22 0011XXXXXh 256 (4x64) Kbytes
SA23–SA26 0100XXXXXh 256 (4x64) Kbytes
SA27-SA30 0101XXXXXh 256 (4x64) Kbytes
SA31-SA34 0110XXXXXh 256 (4x64) Kbytes
SA35-SA38 0111XXXXXh 256 (4x64) Kbytes
SA39-SA42 1000XXXXXh 256 (4x64) Kbytes
SA43-SA46 1001XXXXXh 256 (4x64) Kbytes
SA47-SA50 1010XXXXXh 256 (4x64) Kbytes
SA51-SA54 1011XXXXXh 256 (4x64) Kbytes
SA55–SA58 1100XXXXXh 256 (4x64) Kbytes
SA59–SA62 1101XXXXXh 256 (4x64) Kbytes
SA63–SA66 1110XXXXXh 256 (4x64) Kbytes
SA67–SA70 1111XXXXXh 256 (4x64) Kbytes

000001XXXh,
000010XXXh,

000011XXXh,

Sector/

Sector Block Size

192 (3x64) Kbytes

Write Protect (WP#)

The Write Protect function provides a hardware
method of protecting the top two or bottom two sectors
without using V
vided by the WP#/ACC input.

If the system asserts V
vice disables pro gram a nd er ase func tions in th e first
or last sector independently of whether those sectors
were protected or unprotected usin g the method de­scribed in “Sector Group Protecti on and Unprotec ti on”.
Note that if WP#/ACC is at V
the standby mode, the m aximum input lo ad current is
increased. See the table in “DC Characteristics”.

. WP# is one of two functions pro-

ID

on the WP#/ACC pin, the de-

IL

when the device is in

IL

May 16, 2003 Am29LV320MT/B 17

DATASHEET

If the system asserts V

on the WP#/ACC pin, the de-

IH

vice reverts to whether the top or bottom two sectors
were previously set to be protected or unprotected
using the method described in “Sector Group Protec­tion and Unprotection”. Note: No external pullup is

necessary since the WP#/ACC pin has internal pullup
to V

CC

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacent
sectors that are prote cted or unprotected at the same ti me
(see Table 6).

This feature allo ws tempora ry unprotecti on of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is act ivated by
setting the RESET# p in to V
merly protected sector groups can be programmed o r
erased by selecting the sector group addresses. Once

is removed from the RESET# pi n, all the prev i-

V

ID

ously protected sector groups are protected again.
Figure 1 shows the algorithm, and Figure 23 shows
the timing diagrams, for this feature.

. During this m ode, for-

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V
the first or last sector will remain protected).

2. All previously protect ed sec tor gro ups are prote cte d
once again.

ID

IH

,

IL

Figure 1. T emporary Sector Group

Unprotect Operation

18 Am29LV320MT/B May 16, 2003

DATASHEET

Temporary Sector

Group Unprotect

Mode

Increment

PLSCNT

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

group address

Sector Group Protect:

Write 60h to sector
group address with

A6–A0 = 0xx0010

Wait 150 µs

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Yes

START

Protect all sector

groups: The indicated

ID

Reset

PLSCNT = 1

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sector

No

protected?

Set up first sector

group address

Sector Group

Unprotect:
Write 60h to sector
group address with

A6–A0 = 1xx0010

Wait 15 ms

groups

Yes

Yes

ID

Temporary Sector

No

Group Unprotect

Mode

No

PLSCNT

= 25?

Yes

Device failed

Sector Group

Protect

Algorithm

Read from

sector group address

with A6–A0

= 0xx0010

No

Data = 01h?

Protect

another

sector group?

Remove V

from RESET#

Write reset

command

Sector Group

Protect complete

Yes

No

Verify Sector Group

Unprotect: Write

40h to sector group

Increment

PLSCNT

No

Yes

ID

PLSCNT

= 1000?

Yes

Device failed

Sector Group

address with

A6–A0 = 1xx0010

Read from
sector group
address with

A6–A0 = 1xx0010

No

Data = 00h?

Last sector

Remove V

from RESET#

group

verified?

Yes

Yes

ID

Set up

next sector group

address

No

Unprotect
Algorithm

Write reset

command

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

May 16, 2003 Am29LV320MT/B 19