AMD Advanced Micro Devices AM29LV200BT-90FIB, AM29LV200BT-90FI, AM29LV200BT-90FEB, AM29LV200BB-80FC, AM29LV200BB-80EIB Datasheet
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ADVANCE INFORMATION
Am29LV200B
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sec tor Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3. 0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29LV200 device
■ High performance
— Full voltage range: access times as fast as 80 ns
— Regulated voltage r ange: access times as f ast as
70 ns
■ Ultra low power consumption (typical v alues at 5
MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of loc king a sector to prev ent
any program or erase operat ions within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect featur e allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ Package option
— 48-pin TSOP
— 44-pin SO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detec ting program
or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation t o read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the devic e to reading
array data
■ Unlock Bypass Program Command
— Reduces overall pr ogramming time when issuing
multiple program command sequences
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice. 1/23/98
Publication# 21521 Rev: A Amendment/0
Issue Date: January 1998
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The device is offer ed in 44-pin S O and 48-pin TSO P
packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed insystem using only a single 3.0 volt V
is required for write or erase operations. The device
can also be programmed i n standard EPROM programmers.
This device is manufactured usin g AMD’s 0.35 µm
process technology, and offers all the f eatures an d benefits of the Am29L V200, which was manufactur ed using
0.5 µm process technology. In addition, the
Am29LV200B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
supply. No V
CC
PP
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achiev ed.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device off ers two power-sa ving f eatures. When addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits w ithin
a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
1/23/98 Am29LV200B 2
ADVANCE INFORMATION
PRODUCT SELECTOR GUIDE
Family Part Number Am29LV200B
Speed Options
Max access time, ns (t
Max CE# access time, ns (tCE) 70 80 90 120
Max OE# access time, ns (tOE) 30 30 35 50
Regulated Voltage Range: VCC =3.0–3.6 V -70R
Full Voltage Range: VCC = 2.7–3.6 V -80 -90 -120
) 70 80 90 120
ACC
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0
DQ15 (A-1)
–
Input/Output
Buffers
Data
Latch
V
CC
V
SS
RESET#
WE#
BYTE#
CE#
OE#
RY/BY#
State
Control
Command
Register
PGM Voltage
Generator
Sector Switches
Erase Voltage
Generator
Chip Enable
Output Enable
Logic
STB
A0–A16
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
21521A-1
3 Am29LV200B 1/23/98
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