AMD Am29LV160B Service Manual

查询29LV160B供应商

PRELIMINARY

Am29LV160B

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sec tor Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with high performance 3.3 volt microprocessors

■ Manufactured on 0.35 µm process technology

■ Supports Common Flash Memory Interface

(CFI)

■ High performance

— Full voltage range: access times as f ast as 90 ns — Regulated voltage range: access times as fast

as 80 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 9 mA read current — 20 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

thirty-one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

thirty-one 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

■ Embedded Al gorithms

■ Minimum 1,000,000 write cycle guarantee per

■ Package option

■ CFI (Common Flash Interface) compliant

■ Compatibility with JEDEC standards

■ Data# Polling and toggle bits

■ Ready/Busy# pin (RY/BY#)

■ Erase Suspend/Erase Resume

■ Hardware reset pin (RESET#)

available

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

sector

— 48-ball FBGA — 48-pin TSOP — 44-pin SO

— Provides device-specific information to the

system, allowing host software to easily reconfigure for different Flash devices

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

— Provides a software method of detecting

program or erase operation completion

— Provides a hardware method of detecting

program or erase cycle completion (not available on 44-pin SO)

— Suspends an erase operation t o read data from,

or program data to, a sector that is not being erased, then resumes the erase operation

— Hardware method to reset the de vice to reading

array data

Publication# 21358 Rev: F Amendment/+2 Issue Date: March 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV160B is a 16 Mbit, 3.0 Vo lt-only Flash memor y organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on

DQ15–DQ0; the byte -wide (x8) data appea rs on DQ7–DQ0 . This device is designed to be progr ammed in-sys tem with the standard syste m 3.0 volt V

are not required for write or erase operations. The

device can also be programmed in standard EPROM programmers.

The device offers access times of 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The Am29LV160B is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to t he command register using standard microprocessor write timings. Register contents ser ve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase op erations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already progr ammed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

supply. A 12.0 V VPP or 5.0

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardwar e data pr otecti on measures include a low V

detector that automatically inhibits wr ite operations during power transitions. The hardware sector protection feature disables both program and erase operatio ns in any combination of the sectors of memor y. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. Tr ue background erase can thus be achieved.

The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array dat a. The RESET# pin ma y be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep m ode. The system can also place the de vice into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest lev els of quality, reliability and cost effect iv eness . The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed us ing hot el ec tr on i nject ion.

2 Am29LV160B

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV160B

Speed Option

Max access time, ns (t Max CE# access time, ns (tCE) 80 90 120 Max OE# access time, ns (tOE) 30 35 50

Regulated Voltage Range: VCC =3.0–3.6 V 80R

Full Voltage Range: VCC = 2.7–3.6 V 90 120

) 80 90 120

ACC

Note: See “AC Characteristics ” for full specifications.

BLOCK DIAGRAM

–

DQ15 (A-1)

STB

DQ0

Input/Output

Buffers

Data

Latch

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

Sector Switches

Erase Voltage

Generator

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

A0–A19

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21358F-1

Am29LV160B 3

CONNECTION DIAGRAMS

PRELIMINARY

A15 A14 A13 A12 A11 A10

A9 A8

A19

WE#

RESET#

RY/BY#

A18 A17

A7 A6 A5 A4 A3 A2 A1

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2 DQ9 DQ1 DQ8 DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard TSOP

Reverse TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1

4 Am29LV160B

21358F-2

CONNECTION DIAGRAMS

PRELIMINARY

RESET#

A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

CE#

OE# DQ0 DQ8 DQ1 DQ9 DQ2

DQ10

DQ3

DQ11

10 11 12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

WE# A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

21358F-3

FBGA

Bottom View

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

Special Handling Instructions

Special handling is required for Flash Memory products in FBGA packages.

CE#A0A1A2A4A3

BYTE#A16A15A14A12A13

OE# V

DQ9 DQ1DQ8DQ0A5A6A17A7

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ15/A-1 V

DQ4DQ12DQ5A19NCRESET#WE#

21358F-1

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Am29LV160B 5

PRELIMINARY

PIN CONFIGURATION

A0–A19 = 20 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin RY/BY# = Ready/Busy output

(N/A SO 044)

= 3.0 volt-only single power supply

NC = Pin not connected internally

(see Product Selector Guide for speed

options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

A0–A19

CE# OE#

WE# RESET# BYTE# RY/BY#

16 or 8

DQ0–DQ15

(A-1)

(N/A SO 044)

21358F-4

6 Am29LV160B

PRELIMINARY

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE80RAM29LV160B T

OPTIONAL PROCESSING

Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package

AM29LV160BT80R, AM29LV160BB80R

AM29LV160BT90, AM29LV160BB90

AM29LV160BT120, AM29LV160BB120

Valid Combinations

EC, FC, SC, WCC

EC, EI, EE,

FC, FI, FE,

SC, SI, SE,

WCC, WCI, WCE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV160B 16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am29LV160B 7

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loc ation. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the

Table 1. Am29LV160B Device Bus Operations

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A

Standby Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect

0.3 V

XXX V

VCC ±

0.3 V

register serve as inputs to the internal state machine. The state machine outputs d ictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

DQ8–DQ15

Addresses

(Note 1)

IN IN

X High-Z High-Z High-Z

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Address, A6 = H, A1 = H,

A0 = L

DQ0–

DQ7

OUT

BYTE#

= V

OUT

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

Legend:

L = Logic Low = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V

), A19:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are activ e and c ontrolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-

. CE# is the power

main at V vice outputs array data in word s or b yt e s.

The internal state machine is set for reading array data upon device po wer-u p , or after a hardw are res et. This ensure s that no sp urious alteration of the memory content occurs dur ing the power transition. No command is nece ssary in this mode to ob tain array data. Standard microprocessor read cycles that assert valid addresses on the de vice addr ess inputs produce valid data on the device data outputs. The device remains enab led f or read access until t he command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active current specification for reading array data.

. The BYTE# pin determines whether the de-

CC1

8 Am29LV160B

PRELIMINARY

Writing Commands/Command Sequences

To wr ite a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

, and OE# to VIH.

For program operations, the BYTE# pin deter mines whether the device accepts p rogram data in bytes

or words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 i ndicate the address space that each sector occupies. A “sector address” consists of the addres s bits required t o un iquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the w rite mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

read specifica tions apply. Refer to “Write Ope ration Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device , it can place the device in the standby mode. In this mode, current consumption is gr eatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held at VIH, but not within

± 0.3 V, the device will be in the standby mode, b ut

the standby current will be grea ter. The device req uires standard access time (t

) for read access when the

device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addres ses remain stable for

+ 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are chan ged. While in sleep mode, output data is latched and always available to the system. I represents the automatic sleep mode current specification.

in the DC Characteristics table

CC4

Am29LV160B 9

PRELIMINARY

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of resetting the device to readi ng arr ay data. When the system drives the RESET# pin to V the device immediately terminates any operati on in progress, tristates all data output pins, and ignores all read/wri te attempts for the durati on of the RESET# pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

for at least a p eriod of tRP,

±0.3 V, the device

). If RESET# is held

CC4

memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset oper ation is c omplete . If RESE T# is asserted when a program or erase oper ation is not e xecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin return s to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in t he high impedance state.

10 Am29LV160B

PRELIMINARY

Table 2. Sector Address Tables (Am29LV160BT)

Sector Size

(Kbytes/

Sector A19 A18 A17 A16 A15 A14 A13 A12

SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF

SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF SA34 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section for more

information.

Am29LV160B 11

PRELIMINARY

Table 3. Sector Address Tables (Am29LV160BB)

Sector Size

(Kbytes/

Sector A19 A18 A17 A16 A15 A14 A13 A12

SA00000000X 16/8 000000–003FFF 00000–01FFF

SA100000010 8/4 004000–005FFF 02000–02FFF

SA2 00000011 8/4 006000–007FFF 03000–03FFF

SA3 000001XX 32/16 008000–00FFFF 04000–07FFF

SA4 00001XXX 64/32 010000–01FFFF 08000–0FFFF

SA5 00010XXX 64/32 020000–02FFFF 10000–17FFF

SA6 00011XXX 64/32 030000–03FFFF 18000–1FFFF

SA7 00100XXX 64/32 040000–04FFFF 20000–27FFF

SA8 00101XXX 64/32 050000–05FFFF 28000–2FFFF

SA9 00110XXX 64/32 060000–06FFFF 30000–37FFF SA1000111XXX 64/32 070000–07FFFF 38000–3FFFF SA1101000XXX 64/32 080000–08FFFF 40000–47FFF SA1201001XXX 64/32 090000–09FFFF 48000–4FFFF SA1301010XXX 64/32 0A0000–0AFFFF 50000–57FFF SA1401011XXX 64/32 0B0000–0BFFFF 58000–5FFFF SA1501100XXX 64/32 0C0000–0CFFFF 60000–67FFF SA1601101XXX 64/32 0D0000–0DFFFF 68000–6FFFF SA1701110XXX 64/32 0E0000–0EFFFF 70000–77FFF SA1801111XXX 64/32 0F0000–0FFFFF 78000–7FFFF SA1910000XXX 64/32 100000–10FFFF 80000–87FFF SA2010001XXX 64/32 110000–11FFFF 88000–8FFFF SA2110010XXX 64/32 120000–12FFFF 90000–97FFF SA2210011XXX 64/32 130000–13FFFF 98000–9FFFF SA2310100XXX 64/32 140000–14FFFF A0000–A7FFF SA2410101XXX 64/32 150000–15FFFF A8000–AFFFF SA2510110XXX 64/32 160000–16FFFF B0000–B7FFF SA2610111XXX 64/32 170000–17FFFF B8000–BFFFF SA2711000XXX 64/32 180000–18FFFF C0000–C7FFF SA2811001XXX 64/32 190000–19FFFF C8000–CFFFF SA2911010XXX 64/32 1A0000–1AFFFF D0000–D7FFF SA3011011XXX 64/32 1B0000–1BFFFF D8000–DFFFF SA3111100XXX 64/32 1C0000–1CFFFF E0000–E7FFF SA3211101XXX 64/32 1D0000–1DFFFF E8000–EFFFF SA3311110XXX 64/32 1E0000–1EFFFF F0000–F7FFF SA3411111XXX 64/32 1F0000–1FFFFF F8000–FFFFF

Kwords)

Address Range (in hexadecimal)

Byte Mode (x8) Word Mode (x16)

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section for more

information.

12 Am29LV160B

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for progr amming equipment to automatically match a device to be progr ammed with its correspondi ng programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V A9. Address pins A6, A1, and A0 must be as shown in

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V Device ID:

Am29LV160B (Top Boot Block)

(11.5 V to 12.5 V) on address pin

Table 4. Am29L V160B Autoselect Codes (High Voltage Method)

A19

A11

A12

A10 A9

Word L L H

Byte L L H X C4h

XXVIDXLXLH

Ta ble 4. In addition, when verifying s ector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care . When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require V

. See “Command Definitions” for

details on using the autoselect mode.

A7 A6

XLXLL X 01h

A2 A1 A0

DQ8

DQ15

22h C4h

DQ7

DQ0

Device ID: Am29LV160B (Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection can be implemented via two methods.

The primary method requires V only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard m icroprocessor bus cycle tim-

Word L L H

Byte L L H X 49h

XXVIDXLXLH

XLXHL

ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sect or unprotect write cycle.

The alternate method intended o nly for programming equipment requires V

on address pin A9 and OE#.

This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Details on this method are pro vided in a supplement, publication number 21468. Contact an AMD representativ e to request a copy.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE-

. During this mode, formerly protected

is removed from the RE-

on the RESET# pin

SET# pin to V sectors can be programmed or erased b y selecting the sector addresses. Once V SET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.

22h 49h

01h

(protected)

00h

(unprotected)

Am29LV160B 13

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Figure 1. In-System Sector Protect/Unprotect Algorithms

14 Am29LV160B

Sector Unprotect

complete

21358F-5

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