AMD Am29LV128MH, Am29LV128ML Service Manual

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Am29LV128MH/L

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs, S29GL256N supersedes Am29LV128MH/L and is the factory-recommended migration path. Please refer to the S29GL256N datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 25270 Revision C Amendment 7 Issue Date January 31, 2007

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THIS PAGE LEFT INTENTIONALLY BLANK.

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DATA SHEET

Am29LV128MH/L

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

 Single power supply operation

— 3 volt read, erase, and program operations

 VersatileI/O™ control

— Device generates data output voltages and tolerates

data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the

pin; operates from 1.65 to 3.6 V

 Manufactured on 0.23 µm MirrorBit process

technology

 Secured Silicon Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence

— May be programmed and locked at the factory or by

the customer

 Flexible sector architecture

— Two hundred fifty-six 32 Kword (64 Kbyte) sectors

 Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent write protection

 Minimum 100,000 erase cycle guarantee per sector

 20-year data retention at 125°C

PERFORMANCE CHARACTERISTICS

 High performance

— 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 15 s typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer

 Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current

 Package options

— 56-pin TSOP — 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

 Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall

multiple-word or byte programming time — CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

 Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group — Temporary Sector Group Unprotect: V

of changing code in locked sector groups

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

-level method

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 25270 Rev: C Amendment: 7 Issue Date: January 31, 2007

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DATA SHEET

GENERAL DESCRIPTION

The Am29LV128MH/L is a 128 Mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words or 16,777,216 bytes. The device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V specified in “Product Selector Guide” on page 6 and the “Ordering Information” on page 10. The device is offered in a 56-pin TSOP, 64-ball Fortified BGA. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V

input, a high-voltage accelerated program

(WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

) and an I/O voltage range (VIO), as

of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time.

The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.

The VersatileI/O™ (V

) control allows the host sys-

tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V

pin. Refer to the Ordering Information section for valid V options.

Hardware data protection measures include a low V

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of sector groups

AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

RELATED DOCUMENTS

For a comprehensive information on MirrorBit products, including migration information, data sheets, application notes, and software drivers, please see

www.amd.com tion

→MirrorBit→Flash Information→Technical Docu-

mentation. The following is a partial list of documents

closely related to this product:

MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read

Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

Am29LV256M, 256 Mbit MirrorBit Flash device (in 64-ball, 18 x 12 mm Fortified BGA package)

→Flash Memory→Product Informa-

4 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

TABLE OF CONTENTS

Continuity of Specifications ............................................................. i

For More Information ....................................................................... i

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11

Table 1. Device Bus Operations ...........................................................11

Word/Byte Configuration ........................................................ 11

VersatileIO™ (VIO) Control ........................................................... 11

Requirements for Reading Array Data ......................................... 12

Page Mode Read .................................................................... 12

Writing Commands/Command Sequences .................................. 12

Write Buffer ............................................................................. 12

Accelerated Program Operation ............................................. 12

Autoselect Functions ..............................................................12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ................................................................. 13

RESET#: Hardware Reset Pin .....................................................13

Output Disable Mode ................................................................... 13

Table 2. Sector Address Table .............................................................. 14

Autoselect Mode..................................................................... 20

Table 3. Autoselect Codes, (High Voltage Method) .............................20

Sector Group Protection and Unprotection ..................................21

Table 4. Sector Group Protection/Unprotection Address Table .....21

Write Protect (WP#)................................................................ 22

Temporary Sector Group Unprotect ............................................. 22

Figure 1. Temporary Sector Group Unprotect Operation ................ 22

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 23

Secured Silicon Sector Flash Memory Region ............................. 24

Table 5. Secured Silicon Sector Contents ......................................24

Figure 3. Secured Silicon Sector Protect Verify .............................. 25

Hardware Data Protection ............................................................ 25

Low VCC Write Inhibit ............................................................ 25

Write Pulse “Glitch” Protection ............................................... 25

Logical Inhibit .......................................................................... 25

Power-Up Write Inhibit ............................................................ 25

Common Flash Memory Interface (CFI) . . . . . . . 25

Table 6. CFI Query Identification String .............................. 26

Table 7. System Interface String......................................................26

Table 8. Device Geometry Definition................................... 27

Table 9. Primary Vendor-Specific Extended Query............. 28

Command Definitions . . . . . . . . . . . . . . . . . . . . . 29

Reading Array Data ...................................................................... 29

Reset Command ..........................................................................29

Autoselect Command Sequence .................................................. 29

Enter Secured Silicon Sector/Exit Secured Silicon Sector

Command Sequence ................................................................... 30

Word Program Command Sequence ........................................... 30

Unlock Bypass Command Sequence ..................................... 30

Write Buffer Programming ...................................................... 30

Accelerated Program .............................................................. 31

Figure 4. Write Buffer Programming Operation............................... 32

Figure 5. Program Operation .......................................................... 33

Program Suspend/Program Resume Command Sequence ........33

Figure 6. Program Suspend/Program Resume............................... 34

Chip Erase Command Sequence ................................................. 34

Sector Erase Command Sequence .............................................. 34

Erase Suspend/Erase Resume Commands ................................ 35

Figure 7. Erase Operation.............................................................. 36

Command Definitions ............................................................. 37

Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ................. 37

Table 11. Command Definitions (x8 Mode, BYTE# = V

) ................... 38

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 39

DQ7: Data# Polling ...................................................................... 39

Figure 8. Data# Polling Algorithm .................................................. 39

RY/BY#: Ready/Busy#............................................................ 40

DQ6: Toggle Bit I .......................................................................... 40

Figure 9. Toggle Bit Algorithm........................................................ 41

DQ2: Toggle Bit II ......................................................................... 41

Reading Toggle Bits DQ6/DQ2 .................................................... 41

DQ5: Exceeded Timing Limits ...................................................... 42

DQ3: Sector Erase Timer ............................................................. 42

DQ1: Write-to-Buffer Abort ........................................................... 42

Table 12. Write Operation Status ......................................................... 43

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 44

Figure 10. Maximum Negative Overshoot Waveform ................... 44

Figure 11. Maximum Positive Overshoot Waveform ..................... 44

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 44

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 12. Test Setup.................................................................... 46

Table 13. Test Specifications ......................................................... 46

Key to Switching Waveforms. . . . . . . . . . . . . . . . 46

Figure 13. Input Waveforms and Measurement Levels ................. 46

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47

Read-Only Operations ........................................................... 47

Figure 14. Read Operation Timings ............................................... 47

Figure 15. Page Read Timings ...................................................... 48

Hardware Reset (RESET#) ....................................................49

Figure 16. Reset Timings ............................................................... 49

Erase and Program Operations .............................................. 50

Figure 17. Reset Timings ............................................................... 51

Figure 18. Program Operation Timings .......................................... 52

Figure 19. Accelerated Program Timing Diagram .......................... 52

Figure 20. Chip/Sector Erase Operation Timings .......................... 53

Figure 21. Data# Polling Timings (During Embedded Algorithms). 54

Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 55

Figure 23. DQ2 vs. DQ6................................................................. 55

Temporary Sector Group Unprotect .......................................56

Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 56

Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 57

Alternate CE# Controlled Erase and Program Operations ..... 58

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 59

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 59

Erase And Programming Performance. . . . . . . . 60

TSOP Pin and BGA Package Capacitance . . . . . 61

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 62

LAA064—64-Ball Fortified Ball Grid Array

13 x 11 mm Package .............................................................. 63

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64

January 31, 2007 25270C7 Am29LV128MH/L 5

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PRODUCT SELECTOR GUIDE

Part Num ber Am29LV128MH/L

Regulated Voltage Range

= 3.0–3.6 V

Speed/ Voltage Option

Max. Access Time (ns)

Full Voltage Range V

= 2.7–3.6 V

DATA SHEET

93R

= 3.0–3.6 V

103R

VIO = 2.7–3.6 V

103

(Note 2)

= 2.7–3.6 V

100 110 120

113R

VIO = 1.65–3.6 V

113

(Note 2)

VIO = 1.65–3.6 V

123R

VIO = 1.65–3.6 V

123

(Note 2)

VIO = 1.65–3.6 V

Max. CE# Access Time (ns)

Max. Page access time (t

Max. OE# Access Time (ns)

Notes:

1. See “AC Characteristics” for full specifications.

2. Contact factory for availability and ordering information.

PAC C

)

BLOCK DIAGRAM

RY/BY#

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

State

Control

Command

PGM Voltage

Generator

100 110 120

30 30 40 30 40

DQ0–DQ15 (A-1)

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

STB

Logic

Input/Output

Buffers

Data

Latch

A22–A0

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

6 Am29LV128MH/L 25270C7 January 31, 2007

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CONNECTION DIAGRAMS

A22

A15

A14

A13

A12

A11

A10

A19

A20

WE#

A21

A18 A17

A7 A6 A5 A4 A3 A2

A1 NC NC

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

RESET#

WP#/ACC

RY/BY#

DATA SHEET

56-Pin Standard TSOP

A16

BYTE#

V DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

33 32

CE#

NC NC

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2 DQ9 DQ1 DQ8 DQ0

OE#

CE#

A0 NC V

1 2 3 4 5 6 7 8

9 10 11 12 13 14

56-Pin Reverse TSOP

15 16 17 18 19 20 21 22 23 24 25 26 27 28

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC

January 31, 2007 25270C7 Am29LV128MH/L 7

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CONNECTION DIAGRAMS

DATA SHEET

64- Ball Fortified BGA

Top View, Balls Facing Down

A8 C8

A7 C7 D7 E7 F7 G7 H7

A6 C6 D6 E6 F6 G6 H6

A5 C5 D5 E5 F5 G5 H5

A4 C4 D4 E4 F4 G4 H4

A3 C3 D3 E3 F3 G3 H3

A2 C2 D2 E2 F2 G2 H2

A1 C1 D1 E1 F1 G1 H1

B8 D8 E8 F8 G8 H8

NCA22NC

NCNCNCNCNC

NCV

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

CC DQ4DQ12DQ5A19A21RESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

SSBYTE#A16A15A14A12A13

SSCE#A0A1A2A4A3

Special Package Handling Instructions

package body is exposed to temperatures above

150°C for prolonged periods of time. Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the

8 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

PIN DESCRIPTION

A22–A0 = 23 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)

CE# = Chip Enable input

OE# = Output Enable input

WE# = Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RESET# = Hardware Reset Pin input

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy output

= 3.0 volt-only single power supply

= Output Buffer power

NC = Pin Not Connected Internally

(see Product Selector Guide for speed options and voltage supply tolerances)

= Device Ground

LOGIC SYMBOL

A22–A0

CE#

OE#

WE#

WP#/ACC

RESET#

BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

January 31, 2007 25270C7 Am29LV128MH/L 9

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DATA SHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29LV128MH/L H 123R PC I

TEMPERATURE RANGE

F = Industrial (-40C to 85C) with Pb-free Package I = Industrial (–40

PACKAGE TYPE

E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array (

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

FBGA),

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V

H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV128MH/L 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control,

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Am29LV128MH93R Am29LV128ML93R

Am29LV128MH103R Am29LV128ML103R

Am29LV128MH113R Am29LV128ML113R

Am29LV128MH123R Am29LV128ML123R

Speed

(ns)

90 3.0–3.6 V

100 2.7–3.6 V

EI,

110 1.65–3.6 V

120 1.65–3.6 V

Range

3.0–3.6 V

Valid Combinations for Fortified BGA Package

Order Number Package Marking

Am29LV128MH93R Am29LV128ML93R

Am29LV128MH103R Am29LV128ML103R

Am29LV128MH113R Am29LV128ML113R

Am29LV128MH123R Am29LV128ML123R

PCI, PCF

L128MH93N L128ML93N

L128MH103N L128ML103N

L128MH113N L128ML113N

L128MH123N L128ML123N

I, F

Speed

(ns)

100

110

120

Range

3.0–

3.6V

2.7–

3.6 V

1.65–

3.6 V

1.65–

3.6 V

Range

3.0–

3.6 V

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Notes:

1. For 100, 110, and 120 speed option shown in product selector guide, contact AMD for availability and ordering information.

2. To select product with ESN factory-locked into the Secured Silicon Sector: 1) select order number from the valid combinations given above, 2) add designator

“N” at the end of the order number, and 3) modify the speed option indicator as follows [103R = 10R, 113R = 11R, 123R = 12R, 93R, 103, 113, 123 = no change]. Example: Am29LV128MH12RPCIN. For Fortified BGA packages, modify the speed option indicator as follows: [103N = 10N, 113N = 11N, 123N = 12N, 93N = no change]. The designator “N” will also appear at the end of the package marking. Example: L128MH12NIN.

)

10 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the

Table 1. Device Bus Operations

The state machine outputs dictate the function of the

device. Ta bl e 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

DQ8–DQ15

Operation CE# OE# WE# RESET# WP# ACC

Read L L H H

Write (Program/Erase) L H L H

Accelerated Program L H L H

Standby

Output Disable L H H H

Reset X X X L

Sector Group Protect (Note 2)

Sector Group Unprotect (Note 2)

Temporary Sector Group Unprotect

0.3 V

LHL V

XXX V

VCC ±

0.3 V

(Note 3) L/H

(Note 3) V

DQ0–

DQ7

(Note 4) (Note 4)

XL/H

Addresses

(Note 2)

X H X High-Z High-Z High-Z

X L/H X High-Z High-Z High-Z

SA, A6 =L,

HL/H

A3=L, A2=L, A1=H, A0=L

SA, A6=H, A3=L, A2=L, A1=H, A0=L

(Note 4) X X

(Note 4) (Note 4) High-Z

OUT

BYTE#

= V

OUT

BYTE#

= V

DQ8–DQ14

= High-Z,

DQ15 = A-1

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section.

3. If WP# = V

, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)

4. D

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

VersatileIO™ (VIO) Control

The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O

level that is asserted on V

tion” for V

options on this device.

. See “Ordering Informa-

January 31, 2007 25270C7 Am29LV128MH/L 11

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DATA SHEET

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. See the table, See “Read-Only Operations” on page 47 for timing specifications and Figure 14 for the timing diagram. See the table in “DC Characteristics” on page 45 for the active current specification on reading array data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location.

The random or initial page access is equal to t t

and subsequent page read accesses (as long as

ACC

the locations specified by the microprocessor falls within that page) is equivalent to t

. When CE# is

PAC C

deasserted and reasserted for a subsequent access, the access time is t

or tCE. Fast page mode ac-

ACC

cesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command Sequence” section has de-

, and OE# to VIH.

tails on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Ta bl e 2 indicates the address space that each sector occupies.

See the table in “DC Characteristics” on page 45 for the active current specification for the write mode. “AC

Characteristics” on page 47 contains timing specifica-

tion tables and timing diagrams for write operations.

Write Buffer

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts V

on this pin, the device auto-

matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V

from the WP#/ACC pin returns the device

to normal operation. Note that the WP#/ACC pin must

not be at V

for operations other than accelerated

programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at V

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See “Autoselect Mode” on page 20 and

“Autoselect Command Sequence” on page 29 for

more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V (Note that this is a more restricted voltage range than

± 0.3 V.

12 Am29LV128MH/L 25270C7 January 31, 2007

Page 13

DATA SHEET

VIH.) If CE# and RESET# are held at VIH, but not within V

± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires standard access time (t

) for read access

when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

See the table in “DC Characteristics” on page 45 for the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. See the table in “DC Characteristics” on page 45 for the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby current (I at V

but not within VSS±0.3 V, the standby current will

±0.3 V, the device

). If RESET# is held

CC4

be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

See the tables in “AC Characteristics” on page 47 for RESET# parameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

January 31, 2007 25270C7 Am29LV128MH/L 13

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DATA SHEET

Table 2. Sector Address Table (Sheet 1 of 6)

Sector A22–A15

SA0 0 0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF

SA1 0 0 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF

SA2 0 0 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF

SA3 0 0 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF

SA4 0 0 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF

SA5 0 0 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF

SA6 0 0 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF

SA7 0 0 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF

SA8 0 0 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF

SA9 0 0 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF

SA10 0 0 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF

SA11 0 0 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF

SA12 0 0 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF

SA13 0 0 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF

SA14 0 0 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF

SA15 0 0 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF

SA16 0 0 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF

SA17 0 0 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF

SA18 0 0 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF

SA19 0 0 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF

SA20 0 0 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF

SA21 0 0 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF

SA22 0 0 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF

SA23 0 0 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF

SA24 0 0 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF

SA25 0 0 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF

SA26 0 0 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF

SA27 0 0 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF

SA28 0 0 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF

SA29 0 0 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF

SA30 0 0 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF

SA31 0 0 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF

SA32 0 0 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF

SA33 0 0 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF

SA34 0 0 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF

SA35 0 0 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF

SA36 0 0 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF

SA37 0 0 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF

SA38 0 0 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF

SA39 0 0 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF

SA40 0 0 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF

SA41 0 0 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF

SA42 0 0 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF

SA43 0 0 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF

SA44 0 0 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF

SA45 0 0 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF

SA46 0 0 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

14 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

Table 2. Sector Address Table (Sheet 2 of 6)

Sector A22–A15

SA47 0 0 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF

SA48 0 0 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF

SA49 0 0 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF

SA50 0 0 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF

SA51 0 0 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF

SA52 0 0 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF

SA53 0 0 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF

SA54 0 0 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF

SA55 0 0 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF

SA56 0 0 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF

SA57 0 0 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF

SA58 0 0 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA59 0 0 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA60 0 0 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA61 0 0 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA62 0 0 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA63 0 0 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF

SA64 0 1 0 0 0 0 0 0 64/32 400000–40FFFF 200000–207FFF

SA65 0 1 0 0 0 0 0 1 64/32 410000–41FFFF 208000–20FFFF

SA66 0 1 0 0 0 0 1 0 64/32 420000–42FFFF 210000–217FFF

SA67 0 1 0 0 0 0 1 1 64/32 430000–43FFFF 218000–21FFFF

SA68 0 1 0 0 0 1 0 0 64/32 440000–44FFFF 220000–227FFF

SA69 0 1 0 0 0 1 0 1 64/32 450000–45FFFF 228000–22FFFF

SA70 0 1 0 0 0 1 1 0 64/32 460000–46FFFF 230000–237FFF

SA71 0 1 0 0 0 1 1 1 64/32 470000–47FFFF 238000–23FFFF

SA72 0 1 0 0 1 0 0 0 64/32 480000–48FFFF 240000–247FFF

SA73 0 1 0 0 1 0 0 1 64/32 490000–49FFFF 248000–24FFFF

SA74 0 1 0 0 1 0 1 0 64/32 4A0000–4AFFFF 250000–257FFF

SA75 0 1 0 0 1 0 1 1 64/32 4B0000–4BFFFF 258000–25FFFF

SA76 0 1 0 0 1 1 0 0 64/32 4C0000–4CFFFF 260000–267FFF

SA77 0 1 0 0 1 1 0 1 64/32 4D0000–4DFFFF 268000–26FFFF

SA78 0 1 0 0 1 1 1 0 64/32 4E0000–4EFFFF 270000–277FFF

SA79 0 1 0 0 1 1 1 1 64/32 4F0000–4FFFFF 278000–27FFFF

SA80 0 1 0 1 0 0 0 0 64/32 500000–50FFFF 280000–287FFF

SA81 0 1 0 1 0 0 0 1 64/32 510000–51FFFF 288000–28FFFF

SA82 0 1 0 1 0 0 1 0 64/32 520000–52FFFF 290000–297FFF

SA83 0 1 0 1 0 0 1 1 64/32 530000–53FFFF 298000–29FFFF

SA84 0 1 0 1 0 1 0 0 64/32 540000–54FFFF 2A0000–2A7FFF

SA85 0 1 0 1 0 1 0 1 64/32 550000–55FFFF 2A8000–2AFFFF

SA86 0 1 0 1 0 1 1 0 64/32 560000–56FFFF 2B0000–2B7FFF

SA87 0 1 0 1 0 1 1 1 64/32 570000–57FFFF 2B8000–2BFFFF

SA88 0 1 0 1 1 0 0 0 64/32 580000–58FFFF 2C0000–2C7FFF

SA89 0 1 0 1 1 0 0 1 64/32 590000–59FFFF 2C8000–2CFFFF

SA90 0 1 0 1 1 0 1 0 64/32 5A0000–5AFFFF 2D0000–2D7FFF

SA91 0 1 0 1 1 0 1 1 64/32 5B0000–5BFFFF 2D8000–2DFFFF

SA92 0 1 0 1 1 1 0 0 64/32 5C0000–5CFFFF 2E0000–2E7FFF

SA93 0 1 0 1 1 1 0 1 64/32 5D0000–5DFFFF 2E8000–2EFFFF

SA94 0 1 0 1 1 1 1 0 64/32 5E0000–5EFFFF 2F0000–2F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 15

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DATA SHEET

Table 2. Sector Address Table (Sheet 3 of 6)

Sector A22–A15

SA95 0 1 0 1 1 1 1 1 64/32 5F0000–5FFFFF 2F8000–2FFFFF

SA96 0 1 1 0 0 0 0 0 64/32 600000–60FFFF 300000–307FFF

SA97 0 1 1 0 0 0 0 1 64/32 610000–61FFFF 308000–30FFFF

SA98 0 1 1 0 0 0 1 0 64/32 620000–62FFFF 310000–317FFF

SA99 0 1 1 0 0 0 1 1 64/32 630000–63FFFF 318000–31FFFF

SA100 0 1 1 0 0 1 0 0 64/32 640000–64FFFF 320000–327FFF

SA101 0 1 1 0 0 1 0 1 64/32 650000–65FFFF 328000–32FFFF

SA102 0 1 1 0 0 1 1 0 64/32 660000–66FFFF 330000–337FFF

SA103 0 1 1 0 0 1 1 1 64/32 670000–67FFFF 338000–33FFFF

SA104 0 1 1 0 1 0 0 0 64/32 680000–68FFFF 340000–347FFF

SA105 0 1 1 0 1 0 0 1 64/32 690000–69FFFF 348000–34FFFF

SA106 0 1 1 0 1 0 1 0 64/32 6A0000–6AFFFF 350000–357FFF

SA107 0 1 1 0 1 0 1 1 64/32 6B0000–6BFFFF 358000–35FFFF

SA108 0 1 1 0 1 1 0 0 64/32 6C0000–6CFFFF 360000–367FFF

SA109 0 1 1 0 1 1 0 1 64/32 6D0000–6DFFFF 368000–36FFFF

SA110 0 1 1 0 1 1 1 0 64/32 6E0000–6EFFFF 370000–377FFF

SA111 0 1 1 0 1 1 1 1 64/32 6F0000–6FFFFF 378000–37FFFF

SA112 0 1 1 1 0 0 0 0 64/32 700000–70FFFF 380000–387FFF

SA113 0 1 1 1 0 0 0 1 64/32 710000–71FFFF 388000–38FFFF

SA114 0 1 1 1 0 0 1 0 64/32 720000–72FFFF 390000–397FFF

SA115 0 1 1 1 0 0 1 1 64/32 730000–73FFFF 398000–39FFFF

SA116 0 1 1 1 0 1 0 0 64/32 740000–74FFFF 3A0000–3A7FFF

SA117 0 1 1 1 0 1 0 1 64/32 750000–75FFFF 3A8000–3AFFFF

SA118 0 1 1 1 0 1 1 0 64/32 760000–76FFFF 3B0000–3B7FFF

SA119 0 1 1 1 0 1 1 1 64/32 770000–77FFFF 3B8000–3BFFFF

SA120 0 1 1 1 1 0 0 0 64/32 780000–78FFFF 3C0000–3C7FFF

SA121 0 1 1 1 1 0 0 1 64/32 790000–79FFFF 3C8000–3CFFFF

SA122 0 1 1 1 1 0 1 0 64/32 7A0000–7AFFFF 3D0000–3D7FFF

SA123 0 1 1 1 1 0 1 1 64/32 7B0000–7BFFFF 3D8000–3DFFFF

SA124 0 1 1 1 1 1 0 0 64/32 7C0000–7CFFFF 3E0000–3E7FFF

SA125 0 1 1 1 1 1 0 1 64/32 7D0000–7DFFFF 3E8000–3EFFFF

SA126 0 1 1 1 1 1 1 0 64/32 7E0000–7EFFFF 3F0000–3F7FFF

SA127 0 1 1 1 1 1 1 1 64/32 7F0000–7FFFFF 3F8000–3FFFFF

SA128 1 0 0 0 0 0 0 0 64/32 800000–80FFFF 400000–407FFF

SA129 1 0 0 0 0 0 0 1 64/32 810000–81FFFF 408000–40FFFF

SA130 1 0 0 0 0 0 1 0 64/32 820000–82FFFF 410000–417FFF

SA131 1 0 0 0 0 0 1 1 64/32 830000–83FFFF 418000–41FFFF

SA132 1 0 0 0 0 1 0 0 64/32 840000–84FFFF 420000–427FFF

SA133 1 0 0 0 0 1 0 1 64/32 850000–85FFFF 428000–42FFFF

SA134 1 0 0 0 0 1 1 0 64/32 860000–86FFFF 430000–437FFF

SA135 1 0 0 0 0 1 1 1 64/32 870000–87FFFF 438000–43FFFF

SA136 1 0 0 0 1 0 0 0 64/32 880000–88FFFF 440000–447FFF

SA137 1 0 0 0 1 0 0 1 64/32 890000–89FFFF 448000–44FFFF

SA138 1 0 0 0 1 0 1 0 64/32 8A0000–8AFFFF 450000–457FFF

SA139 1 0 0 0 1 0 1 1 64/32 8B0000–8BFFFF 458000–45FFFF

SA140 1 0 0 0 1 1 0 0 64/32 8C0000–8CFFFF 460000–467FFF

SA141 1 0 0 0 1 1 0 1 64/32 8D0000–8DFFFF 468000–46FFFF

SA142 1 0 0 0 1 1 1 0 64/32 8E0000–8EFFFF 470000–477FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

16 Am29LV128MH/L 25270C7 January 31, 2007

Page 17

DATA SHEET

Table 2. Sector Address Table (Sheet 4 of 6)

Sector A22–A15

SA143 1 0 0 0 1 1 1 1 64/32 8F0000–8FFFFF 478000–47FFFF

SA144 1 0 0 1 0 0 0 0 64/32 900000–90FFFF 480000–487FFF

SA145 1 0 0 1 0 0 0 1 64/32 910000–91FFFF 488000–48FFFF

SA146 1 0 0 1 0 0 1 0 64/32 920000–92FFFF 490000–497FFF

SA147 1 0 0 1 0 0 1 1 64/32 930000–93FFFF 498000–49FFFF

SA148 1 0 0 1 0 1 0 0 64/32 940000–94FFFF 4A0000–4A7FFF

SA149 1 0 0 1 0 1 0 1 64/32 950000–95FFFF 4A8000–4AFFFF

SA150 1 0 0 1 0 1 1 0 64/32 960000–96FFFF 4B0000–4B7FFF

SA151 1 0 0 1 0 1 1 1 64/32 970000–97FFFF 4B8000–4BFFFF

SA152 1 0 0 1 1 0 0 0 64/32 980000–98FFFF 4C0000–4C7FFF

SA153 1 0 0 1 1 0 0 1 64/32 990000–99FFFF 4C8000–4CFFFF

SA154 1 0 0 1 1 0 1 0 64/32 9A0000–9AFFFF 4D0000–4D7FFF

SA155 1 0 0 1 1 0 1 1 64/32 9B0000–9BFFFF 4D8000–4DFFFF

SA156 1 0 0 1 1 1 0 0 64/32 9C0000–9CFFFF 4E0000–4E7FFF

SA157 1 0 0 1 1 1 0 1 64/32 9D0000–9DFFFF 4E8000–4EFFFF

SA158 1 0 0 1 1 1 1 0 64/32 9E0000–9EFFFF 4F0000–4F7FFF

SA159 1 0 0 1 1 1 1 1 64/32 9F0000–9FFFFF 4F8000–4FFFFF

SA160 1 0 1 0 0 0 0 0 64/32 A00000–A0FFFF 500000–507FFF

SA161 1 0 1 0 0 0 0 1 64/32 A10000–A1FFFF 508000–50FFFF

SA162 1 0 1 0 0 0 1 0 64/32 A20000–A2FFFF 510000–517FFF

SA163 1 0 1 0 0 0 1 1 64/32 A30000–A3FFFF 518000–51FFFF

SA164 1 0 1 0 0 1 0 0 64/32 A40000–A4FFFF 520000–527FFF

SA165 1 0 1 0 0 1 0 1 64/32 A50000–A5FFFF 528000–52FFFF

SA166 1 0 1 0 0 1 1 0 64/32 A60000–A6FFFF 530000–537FFF

SA167 1 0 1 0 0 1 1 1 64/32 A70000–A7FFFF 538000–53FFFF

SA168 1 0 1 0 1 0 0 0 64/32 A80000–A8FFFF 540000–547FFF

SA169 1 0 1 0 1 0 0 1 64/32 A90000–A9FFFF 548000–54FFFF

SA170 1 0 1 0 1 0 1 0 64/32 AA0000–AAFFFF 550000–557FFF

SA171 1 0 1 0 1 0 1 1 64/32 AB0000–ABFFFF 558000–55FFFF

SA172 1 0 1 0 1 1 0 0 64/32 AC0000–ACFFFF 560000–567FFF

SA173 1 0 1 0 1 1 0 1 64/32 AD0000–ADFFFF 568000–56FFFF

SA174 1 0 1 0 1 1 1 0 64/32 AE0000–AEFFFF 570000–577FFF

SA175 1 0 1 0 1 1 1 1 64/32 AF0000–AFFFFF 578000–57FFFF

SA176 1 0 1 1 0 0 0 0 64/32 B00000–B0FFFF 580000–587FFF

SA177 1 0 1 1 0 0 0 1 64/32 B10000–B1FFFF 588000–58FFFF

SA178 1 0 1 1 0 0 1 0 64/32 B20000–B2FFFF 590000–597FFF

SA179 1 0 1 1 0 0 1 1 64/32 B30000–B3FFFF 598000–59FFFF

SA180 1 0 1 1 0 1 0 0 64/32 B40000–B4FFFF 5A0000–5A7FFF

SA181 1 0 1 1 0 1 0 1 64/32 B50000–B5FFFF 5A8000–5AFFFF

SA182 1 0 1 1 0 1 1 0 64/32 B60000–B6FFFF 5B0000–5B7FFF

SA183 1 0 1 1 0 1 1 1 64/32 B70000–B7FFFF 5B8000–5BFFFF

SA184 1 0 1 1 1 0 0 0 64/32 B80000–B8FFFF 5C0000–5C7FFF

SA185 1 0 1 1 1 0 0 1 64/32 B90000–B9FFFF 5C8000–5CFFFF

SA186 1 0 1 1 1 0 1 0 64/32 BA0000–BAFFFF 5D0000–5D7FFF

SA187 1 0 1 1 1 0 1 1 64/32 BB0000–BBFFFF 5D8000–5DFFFF

SA188 1 0 1 1 1 1 0 0 64/32 BC0000–BCFFFF 5E0000–5E7FFF

SA189 1 0 1 1 1 1 0 1 64/32 BD0000–BDFFFF 5E8000–5EFFFF

SA190 1 0 1 1 1 1 1 0 64/32 BE0000–BEFFFF 5F0000–5F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 17

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DATA SHEET

Table 2. Sector Address Table (Sheet 5 of 6)

Sector A22–A15

SA191 1 0 1 1 1 1 1 1 64/32 BF0000–BFFFFF 5F8000–5FFFFF

SA192 1 1 0 0 0 0 0 0 64/32 C00000–C0FFFF 600000–607FFF

SA193 1 1 0 0 0 0 0 1 64/32 C10000–C1FFFF 608000–60FFFF

SA194 1 1 0 0 0 0 1 0 64/32 C20000–C2FFFF 610000–617FFF

SA195 1 1 0 0 0 0 1 1 64/32 C30000–C3FFFF 618000–61FFFF

SA196 1 1 0 0 0 1 0 0 64/32 C40000–C4FFFF 620000–627FFF

SA197 1 1 0 0 0 1 0 1 64/32 C50000–C5FFFF 628000–62FFFF

SA198 1 1 0 0 0 1 1 0 64/32 C60000–C6FFFF 630000–637FFF

SA199 1 1 0 0 0 1 1 1 64/32 C70000–C7FFFF 638000–63FFFF

SA200 1 1 0 0 1 0 0 0 64/32 C80000–C8FFFF 640000–647FFF

SA201 1 1 0 0 1 0 0 1 64/32 C90000–C9FFFF 648000–64FFFF

SA202 1 1 0 0 1 0 1 0 64/32 CA0000–CAFFFF 650000–657FFF

SA203 1 1 0 0 1 0 1 1 64/32 CB0000–CBFFFF 658000–65FFFF

SA204 1 1 0 0 1 1 0 0 64/32 CC0000–CCFFFF 660000–667FFF

SA205 1 1 0 0 1 1 0 1 64/32 CD0000–CDFFFF 668000–66FFFF

SA206 1 1 0 0 1 1 1 0 64/32 CE0000–CEFFFF 670000–677FFF

SA207 1 1 0 0 1 1 1 1 64/32 CF0000–CFFFFF 678000–67FFFF

SA208 1 1 0 1 0 0 0 0 64/32 D00000–D0FFFF 680000–687FFF

SA209 1 1 0 1 0 0 0 1 64/32 D10000–D1FFFF 688000–68FFFF

SA210 1 1 0 1 0 0 1 0 64/32 D20000–D2FFFF 690000–697FFF

SA211 1 1 0 1 0 0 1 1 64/32 D30000–D3FFFF 698000–69FFFF

SA212 1 1 0 1 0 1 0 0 64/32 D40000–D4FFFF 6A0000–6A7FFF

SA213 1 1 0 1 0 1 0 1 64/32 D50000–D5FFFF 6A8000–6AFFFF

SA214 1 1 0 1 0 1 1 0 64/32 D60000–D6FFFF 6B0000–6B7FFF

SA215 1 1 0 1 0 1 1 1 64/32 D70000–D7FFFF 6B8000–6BFFFF

SA216 1 1 0 1 1 0 0 0 64/32 D80000–D8FFFF 6C0000–6C7FFF

SA217 1 1 0 1 1 0 0 1 64/32 D90000–D9FFFF 6C8000–6CFFFF

SA218 1 1 0 1 1 0 1 0 64/32 DA0000–DAFFFF 6D0000–6D7FFF

SA219 1 1 0 1 1 0 1 1 64/32 DB0000–DBFFFF 6D8000–6DFFFF

SA220 1 1 0 1 1 1 0 0 64/32 DC0000–DCFFFF 6E0000–6E7FFF

SA221 1 1 0 1 1 1 0 1 64/32 DD0000–DDFFFF 6E8000–6EFFFF

SA222 1 1 0 1 1 1 1 0 64/32 DE0000–DEFFFF 6F0000–6F7FFF

SA223 1 1 0 1 1 1 1 1 64/32 DF0000–DFFFFF 6F8000–6FFFFF

SA224 1 1 1 0 0 0 0 0 64/32 E00000–E0FFFF 700000–707FFF

SA225 1 1 1 0 0 0 0 1 64/32 E10000–E1FFFF 708000–70FFFF

SA226 1 1 1 0 0 0 1 0 64/32 E20000–E2FFFF 710000–717FFF

SA227 1 1 1 0 0 0 1 1 64/32 E30000–E3FFFF 718000–71FFFF

SA228 1 1 1 0 0 1 0 0 64/32 E40000–E4FFFF 720000–727FFF

SA229 1 1 1 0 0 1 0 1 64/32 E50000–E5FFFF 728000–72FFFF

SA230 1 1 1 0 0 1 1 0 64/32 E60000–E6FFFF 730000–737FFF

SA231 1 1 1 0 0 1 1 1 64/32 E70000–E7FFFF 738000–73FFFF

SA232 1 1 1 0 1 0 0 0 64/32 E80000–E8FFFF 740000–747FFF

SA233 1 1 1 0 1 0 0 1 64/32 E90000–E9FFFF 748000–74FFFF

SA234 1 1 1 0 1 0 1 0 64/32 EA0000–EAFFFF 750000–757FFF

SA235 1 1 1 0 1 0 1 1 64/32 EB0000–EBFFFF 758000–75FFFF

SA236 1 1 1 0 1 1 0 0 64/32 EC0000–ECFFFF 760000–767FFF

SA237 1 1 1 0 1 1 0 1 64/32 ED0000–EDFFFF 768000–76FFFF

SA238 1 1 1 0 1 1 1 0 64/32 EE0000–EEFFFF 770000–777FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

18 Am29LV128MH/L 25270C7 January 31, 2007

Page 19

DATA SHEET

Table 2. Sector Address Table (Sheet 6 of 6)

Sector A22–A15

SA239 1 1 1 0 1 1 1 1 64/32 EF0000–EFFFFF 778000–77FFFF

SA240 1 1 1 1 0 0 0 0 64/32 F00000–F0FFFF 780000–787FFF

SA241 1 1 1 1 0 0 0 1 64/32 F10000–F1FFFF 788000–78FFFF

SA242 1 1 1 1 0 0 1 0 64/32 F20000–F2FFFF 790000–797FFF

SA243 1 1 1 1 0 0 1 1 64/32 F30000–F3FFFF 798000–79FFFF

SA244 1 1 1 1 0 1 0 0 64/32 F40000–F4FFFF 7A0000–7A7FFF

SA245 1 1 1 1 0 1 0 1 64/32 F50000–F5FFFF 7A8000–7AFFFF

SA246 1 1 1 1 0 1 1 0 64/32 F60000–F6FFFF 7B0000–7B7FFF

SA247 1 1 1 1 0 1 1 1 64/32 F70000–F7FFFF 7B8000–7BFFFF

SA248 1 1 1 1 1 0 0 0 64/32 F80000–F8FFFF 7C0000–7C7FFF

SA249 1 1 1 1 1 0 0 1 64/32 F90000–F9FFFF 7C8000–7CFFFF

SA250 1 1 1 1 1 0 1 0 64/32 FA0000–FAFFFF 7D0000–7D7FFF

SA251 1 1 1 1 1 0 1 1 64/32 FB0000–FBFFFF 7D8000–7DFFFF

SA252 1 1 1 1 1 1 0 0 64/32 FC0000–FCFFFF 7E0000–7E7FFF

SA253 1 1 1 1 1 1 0 1 64/32 FD0000–FDFFFF 7E8000–7EFFFF

SA254 1 1 1 1 1 1 1 0 64/32 FE0000–FEFFFF 7F0000–7F7FFF

SA255 1 1 1 1 1 1 1 1 64/32 FF0000–FFFFFF 7F8000–7FFFFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 19

Page 20

DATA SHEET

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V A6, A3, A2, A1, and A0 must be as shown in Tab l e 3 In addition, when verifying sector protection, the sector

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X

Cycle 1

Cycle 2 H H L 22 X 12h

Device ID

Cycle 3 H H H 22 X 00h

Sector Group Protection Verification

Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector

Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector

on address pin A9. Address pins

Table 3. Autoselect Codes, (High Voltage Method)

A14

A22

A15

LLHXX

LLHSAX

LLHXX

A9A8toA7A6A5to

A10

X L X L L L 00 X 01h

XL X

XL X L H L X X

XL X L H H X X

address must appear on the appropriate highest order address bits (see Ta bl e 2 ). Tab le 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Ta bl e 1 0 and Tab le 1 1. This method does not require V

. See “Autoselect

Command Sequence” on page 29 for more informa-

tion.

toA2A1 A0

LLH 22 X 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

= V

00h (unprotected)

98h (factory locked),

18h (not factory locked)

88h (factory locked),

08h (not factory locked)

DQ7 to DQ0

01h (protected),

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

20 Am29LV128MH/L 25270C7 January 31, 2007

Page 21

DATA SHEET

Sector Group Protection and Unprotection

The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods.

Sector group protection/unprotection requires V the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 25 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector group must first be protected prior to the first sector group unprotect write cycle.

The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector group is protected or unprotected. See “Autoselect Mode” on page 20 for details.

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group A22–A15

SA0 00000000

SA1 00000001

SA2 00000010

SA3 00000011

SA4–SA7 000001xx

SA8–SA11 000010xx

SA12–SA15 000011xx

SA16–SA19 000100xx

SA20–SA23 000101xx

SA24–SA27 000110xx

SA28–SA31 000111xx

SA32–SA35 001000xx

SA36–SA39 001001xx

SA40–SA43 001010xx

SA44–SA47 001011xx

SA48–SA51 001100xx

SA52–SA55 001101xx

SA56–SA59 001110xx

SA60–SA63 001111xx

SA64–SA67 010000xx

SA68–SA71 010001xx

SA72–SA75 010010xx

SA76–SA79 010011xx

SA80–SA83 010100xx

Sector Group A22–A15

SA84–SA87 010101xx

SA88–SA91 010110xx

SA92–SA95 010111xx

SA96–SA99 011000xx

SA100–SA103 011001xx

SA104–SA107 011010xx

SA108–SA111 011011xx

SA112–SA115 011100xx

SA116–SA119 011101xx

SA120–SA123 011110xx

SA124–SA127 011111xx

SA128–SA131 100000xx

SA132–SA135 100001xx

SA136–SA139 100010xx

SA140–SA143 100011xx

SA144–SA147 100100xx

SA148–SA151 100101xx

SA152–SA155 100110xx

SA156–SA159 100111xx

SA160–SA163 101000xx

SA164–SA167 101001xx

SA168–SA171 101010xx

SA172–SA175 101011xx

SA176–SA179 101100xx

SA180–SA183 101101xx

SA184–SA187 101110xx

SA188–SA191 101111xx

SA192–SA195 110000xx

SA196–SA199 110001xx

SA200–SA203 110010xx

SA204–SA207 110011xx

SA208–SA211 110100xx

SA212–SA215 110101xx

SA216–SA219 110110xx

SA220–SA223 110111xx

SA224–SA227 111000xx

SA228–SA231 111001xx

SA232–SA235 111010xx

SA236–SA239 111011xx

SA240–SA243 111100xx

SA244–SA247 111101xx

SA248–SA251 111110xx

SA252 11111100

SA253 11111101

SA254 11111110

SA255 11111111

January 31, 2007 25270C7 Am29LV128MH/L 21

Page 22

DATA SHEET

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or last sector group without using V

. Write Protect is one of two functions pro-

vided by the WP#/ACC input.

If the system asserts V

on the WP#/ACC pin, the de-

vice disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that if WP#/ACC is at V

when the

device is in the standby mode, the maximum input load current is increased. See the table in “DC Char-

acteristics” on page 45

If the system asserts V

on the WP#/ACC pin, the de-

vice reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that WP# has an internal pullup;

when unconnected, WP# is at V

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to V merly protected sector groups can be programmed or erased by selecting the sector group addresses. Once V

is removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 1

. During this mode, for-

shows the algorithm, and Figure 24 shows the timing diagrams, for this feature.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector Group

Unprotect Completed

(Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V the first or last sector will remain protected).

2. All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group

Unprotect Operation

22 Am29LV128MH/L 25270C7 January 31, 2007

Page 23

DATA SHEET

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Group

Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 μs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Group

PLSCNT = 1

RESET# = V

Wait 1 μs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Unprotect

Algorithm

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

January 31, 2007 25270C7 Am29LV128MH/L 23

Page 24

DATA SHEET

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.

AMD offers the device with the Secured Silicon Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked.

Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.

The Secured Silicon sector address space in this device is allocated as follows:

Table 5. Secured Silicon Sector Contents

Secured Silicon Sector Address

Range

000000h–000007h

000008h–00007Fh Unavailable

The system accesses the Secured Silicon Sector through a command sequence (see “Enter Secured

Silicon Sector/Exit Secured Silicon Sector Command Sequence” on page 30). After the system

has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from

Customer

Lockable

Determined by

customer

ESN Factory

Locked

ESN

ExpressFlash

Factory Locked

ESN or

determined by

customer

Determined by

customer

the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.

Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory

Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte Secured Silicon sector.

Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following procedures:

 Write the three-cycle Enter Secured Silicon Sector

Region command sequence, and then follow the in-system sector protect algorithm as shown in

Figure 2, except that RESET# may be at either V

or VID. This allows in-system protection of the Se-

cured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector.

 To verify the protect/unprotect status of the Secured

Silicon Sector, follow the algorithm shown in

Figure 3.

Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.

Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your local AMD sales representative for details on ordering ESN Factory Locked devices.

Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from AMD’s factory with the Secured Silicon Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service.

24 Am29LV128MH/L 25270C7 January 31, 2007

Page 25

DATA SHEET

START

RESET# =

or V

Wait 1 μs

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

Figure 3. Secured Silicon Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tab l e 1 0 and

Ta bl e 1 1 for command definitions). In addition, the fol-

lowing hardware data protection measures prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during V

power-up and power-down transitions, or

from system noise.

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V

is greater than V

LKO

. The system must provide the proper signals to the control pins to prevent unintentional writes when V greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up,

the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Ta bl e 6 , Ta bl e 7 , Ta bl e 8 , and Ta bl e 9 . To terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tab le 6 , Tab le 7 ,

Ta bl e 8 , and Ta bl e 9 . The system must write the reset

command to return the device to reading array data.

For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.

January 31, 2007 25270C7 Am29LV128MH/L 25

Page 26

DATA SHEET

Table 6. CFI Query Identification String

Addresses (x16) Data Description

10h 11h 12h

13h 14h

15h 16h

17h 18h

19h 1Ah

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

Query Unique ASCII string “QRY”

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Table 7. System Interface String

Addresses (x16) Data Description

Min. (write/erase)

1Bh 0027h

1Ch 0036h

1Dh 0000h V

1Eh 0000h VPP Max. voltage (00h = no VPP pin present)

D7–D4: volt, D3–D0: 100 millivolt

VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt

Min. voltage (00h = no VPP pin present)

1Fh 0007h Typical timeout per single byte/word write 2N µs

20h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 000Ah Typical timeout per individual block erase 2N ms

22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 0001h Max. timeout for byte/word write 2N times typical

24h 0005h Max. timeout for buffer write 2N times typical

25h 0004h Max. timeout per individual block erase 2

times typical

26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

26 Am29LV128MH/L 25270C7 January 31, 2007

Page 27

DATA SHEET

Table 8. Device Geometry Definition

Addresses (x16) Data Description

27h 0018h Device Size = 2N byte

28h 29h

2Ah 2Bh

2Ch 0001h

2Dh 2Eh 2Fh 30h

31h 32h 33h 34h

35h 36h 37h 38h

39h 3Ah 3Bh 3Ch

0002h 0000h

0005h 0000h

00FFh 0000h 0000h 0001h

0000h 0000h 0000h 0000h

Flash Device Interface description (refer to CFI publication 100)

Max. number of byte in multi-byte write = 2 (00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot device)

Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

January 31, 2007 25270C7 Am29LV128MH/L 27

Page 28

DATA SHEET

Table 9. Primary Vendor-Specific Extended Query

Addresses (x16) Data Description

40h 41h 42h

43h 0031h Major version number, ASCII

44h 0033h Minor version number, ASCII

45h 0008h

46h 0002h

47h 0001h

48h 0001h

49h 0004h

4Ah 0000h

4Bh 0000h

0050h 0052h 0049h

Query-unique ASCII string “PRI”

Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect 0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect 00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme 04 = 29LV800 mode

Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type 00 = Not Supported, 01 = Supported

4Ch 0001h

4Dh 00B5h

4Eh 00C5h

4Fh

50h 0001h

0004h/

0005h

Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect

Program Suspend

00h = Not Supported, 01h = Supported

28 Am29LV128MH/L 25270C7 January 31, 2007

Page 29

DATA SHEET

COMMAND DEFINITIONS

Writing specific address and data commands or sequences into the command register initiates device operations. Ta b le 10 and Tabl e 11 defines the valid register command sequences. Writing incorrect ad-

dress and data values or writing them in the improper sequence may place the device in an unknown state.

A reset command is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. See “AC Characteristics” on page 47 for timing diagrams.

Reading Array Data

The device is “automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Com-

mands” on page 35 for more information.

The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, “Reset Command,” for more information.

written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).

Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected.

Ta bl e 1 0 and Tab le 1 1 show the address and data re-

quirements. This method is an alternative to that shown in Tab le 3 , which is intended for PROM programmers and requires V autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing.

on address pin A9. The

See “Reading Array Data” on page 29 in the Device

Bus Operations section for more information. “See the

table, “Read-Only Operations” on page 47 for the read parameters, and Figure 14 shows the timing diagram.

Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is

January 31, 2007 25270C7 Am29LV128MH/L 29

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence:

 A read cycle at address XX00h returns the manu-

facturer code.

 Three read cycles at addresses 01h, 0Eh, and 0Fh

return the device code.

 A read cycle to an address containing a sector ad-

dress (SA), and the address 02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected.

The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).

Page 30

DATA SHEET

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation.

Ta bl e 1 0 and Ta bl e 1 1 show the address and data re-

quirements for both command sequences. See also

“Secured Silicon Sector Flash Memory Region” on

page 24 for further information. Note: The write buffer,

ACC function, and unlock bypass modes are not available when the Secured Silicon Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Ta bl e 1 0 and Tab le 1 1 show the address and data requirements for the word program command sequence.

data is still “0.” Only erase operations can convert a “0” to a “1.”

Note: Single byte programming is not supported in x8-mode. Write buffer programming must be used during x8-mode operation.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tabl e 1 0 and Ta bl e 1 1 show the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode.

When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” on page 39 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort.

The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits A dress/data pairs must fall within the selected-write-buffer-page. The system then writes the

MAX–A4

. All subsequent ad-

30 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order.

The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.

Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed.

Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming.

The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command.

The Write Buffer Programming Sequence can be aborted in the following ways:

 Load a value that is greater than the page buffer

size during the Number of Locations to Program step.

 Write to an address in a sector different than the

one specified during the Write-Buffer-Load command.

 Write an Address/Data pair to a different

write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation.

 Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode.

Accelerated Program

The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V

on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V

for operations

other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at V

Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

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Page 32

Write “Write to Buffer”

command and

Sector Address

DATA SHEET

Ye s

(Note 1)

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

WC = 0 ?

Abort Write to

Buffer Operation?

Write next address/data pair

WC = WC - 1

Write program buffer to

flash sector address

Read DQ7 - DQ0 at

Last Loaded Address

DQ7 = Data?

DQ5 = 1?DQ1 = 1?

Ye s

Part of “Write to Buffer” Command Sequence

Write to a different

sector address

Write to buffer ABORTED. Must write “Write-to-buffer

Abort Reset” command

sequence to return

to read mode.

Notes:

1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.

2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified.

3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command.

4. See Ta bl e 1 0 and Ta b le 1 1 for command sequences required for write buffer programming.

Read DQ7 - DQ0 with address = Last Loaded

Address

(Note 2)

(Note 3)

DQ7 = Data?

FAIL or ABORT PASS

Ye s

Figure 4. Write Buffer Programming Operation

32 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Ta bl e 1 0 and Tab l e 1 1 for program command sequence.

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Figure 5. Program Operation

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 μs maximum (5 μs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command.

After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region.

The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.

After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” on page 39 for more information.

The system must write the Program Resume command to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.

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Program Operation

or Write-to-Buffer

Sequence in Progress

Write address/data

XXXh/B0h

Wait 15 μs

Read data as

required

reading?

Done

DATA SHEET

Write Program Suspend Command Sequence

Command is also valid for Erase-suspended-program operations

Autoselect and SecSi Sector read operations are also allowed

Data cannot be read from erase- o program-suspended sectors

When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” on page 39 for information on these status bits.

Any commands written during the chip erase operation are ignored.However, note that a hardware reset im- mediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Note that the Se-

cured Silicon Sector, autoselect, and CFI functions are unavailable when an program operation is in progress.

Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams.

Yes

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Write Program Resume Command Sequence

Figure 6. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Ta bl e 1 0 and

Ta bl e 1 1 show the address and data requirements for

the chip erase command sequence.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Ta bl e 9 and Ta bl e 1 0 show the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets the device to the read mode. The system must re-

write the command sequence and any additional addresses and commands. Note that the Secured Silicon

Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress.

34 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. See “Write Operation Sta-

tus” on page 39 for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.

When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” on page 39 for information on these status bits.

After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. See

“Write Operation Status” on page 39 for more informa-

tion.

In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance will not be significantly impacted.

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START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Erasure Completed

DATA SHEET

Embedded Erase algorithm in progress

Yes

Figure 7. Erase Operation

Notes:

1. See Ta b le 1 0 and Tab l e 1 1 for erase command sequence.

2. See the section on DQ3 for information on the sector erase timer.

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DATA SHEET

Command Definitions

Table 10. Command Definitions (x16 Mode, BYTE# = VIH)

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001

Device ID (Note 9) 4 555 AA 2AA 55 555 90 X01 227E X0E 2212 X0F 2200 Secured Silicon Sector Factory

Protect (Note 10)

Sector Group Protect Verify (Note 12)

Autoselect (Note 8)

Enter Secured Silicon Sector Region 3 555 AA 2AA 55 555 88

Exit Secured Silicon Sector Region 4 555 AA 2AA 55 555 90 XXX 00

Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 11) 3 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD

Program Buffer to Flash 1 SA 29

Write to Buffer Abort Reset (Note 13) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass Program (Note 14) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Program/Erase Suspend (Note 16) 1 XXX B0 Program/Erase Resume (Note 17) 1 XXX 30

CFI Query (Note 18) 1 55 98

Legend:

X = Don’t care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 555 AA 2AA 55 555 90 X03 (Note 10)

4 555 AA 2AA 55 555 90 (SA)X02 00/01

Bus Cycles (Notes 2–5)

SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A22–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Ta b l e 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, and WC.

5. Unless otherwise noted, address bits A22–A11 are don’t cares.

6. No unlock or command cycles required when device is in read mode.

7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high while the device is providing status information.

8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

9. The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the

lowest address sector, the data is 88h for factory locked and 08h for not factor locked.

11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21.

12. The data is 00h for an unprotected sector and 01h for a protected sector.

13. Command sequence resets device for next command after aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

17. The Erase Resume command is valid only during the Erase Suspend mode.

18. Command is valid when device is ready to read array data or when device is in autoselect mode.

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DATA SHEET

Table 11. Command Definitions (x8 Mode, BYTE# = VIL)

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID (Note 9) 4 AAA AA 555 55 AAA 90 X02 7E X1C 12 X1E 00

Secured Silicon Sector Factory Protect (Note 10)

Sector Group Protect Verify (Note 12)

Autoselect (Note 8)

Enter Secured Silicon Sector Region 3 AAA AA 555 55 AAA 88

Exit Secured Silicon Sector Region 4 AAA AA 555 55 AAA 90 XXX 00

Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 11) 3 AAA AA 555 55 SA 25 SA BC PA PD WBL PD

Program Buffer to Flash 1 SA 29

Write to Buffer Abort Reset (Note 13) 3 AAA AA 555 55 AAA F0 Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass Program (Note 14) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

Program/Erase Suspend (Note 16) 1 XXX B0 Program/Erase Resume (Note 17) 1 XXX 30

CFI Query (Note 18) 1 AA 98

Legend:

WE# or CE# pulse, whichever happens first.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

4 AAA AA 555 55 AAA 90 X06 (Note 10)

4 AAA AA 555 55 AAA 90 (SA)X04 00/01

Bus Cycles (Notes 2–5)

SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A22–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Ta b l e 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.

5. Unless otherwise noted, address bits A22–A11 are don’t cares.

6. No unlock or command cycles required when device is in read mode.

8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

9. The device ID must be read in three cycles.

10. If WP# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the

lowest address sector, the data is 88h for factory locked and 08h for not factor locked.

11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37.

12. The data is 00h for an unprotected sector group and 01h for a protected sector group.

13. Command sequence resets device for next command after aborted write-to-buffer operation.

14. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

17. The Erase Resume command is valid only during the Erase Suspend mode.

18. Command is valid when device is ready to read array data or when device is in autoselect mode.

38 Am29LV128MH/L 25270C7 January 31, 2007

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DATA SHEET

WRITE OPERATION STATUS

The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Ta b le 1 2 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode.

valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.

Ta bl e 1 2 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 21

in the AC Characteristics section shows the Data# Polling timing diagram.

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Yes

PASS

Figure 8. Data# Polling Algorithm

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DATA SHEET

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Tab le 12 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7. See “DQ7: Data# Polling” on page 39.

If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Ta bl e 1 2 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 22 in

the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. See “DQ2:

Toggle Bit II” on page 41.

40 Am29LV128MH/L 25270C7 January 31, 2007

Page 41

START

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

DATA SHEET

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Tab le 1 2 to compare outputs for DQ2 and DQ6.

Figure 9 shows the toggle bit algorithm in flowchart

form, and “DQ2: Toggle Bit II” explains the algorithm. See also the “RY/BY#: Ready/Busy#” subsection.

Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and

DQ6 in graphical form.

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information.

Program/Erase

Operation Complete

Figure 9. Toggle Bit Algorithm

Reading Toggle Bits DQ6/DQ2

Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform

January 31, 2007 25270C7 Am29LV128MH/L 41

Page 42

DATA SHEET

other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.”

In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See “Sector Erase Command Se-

quence” on page 34.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted.

Ta bl e 1 2 shows the status of DQ3 relative to the other

status bits.

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See “Write Buffer

Programming” on page 30 for more details.

42 Am29LV128MH/L 25270C7 January 31, 2007

Page 43

DATA SHEET

Table 12. Write Operation Status

DQ7

Status

Standard

Mode

Program

Suspend

Mode

Erase

Suspend

Mode

Write-to-

Buffer

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0

Program-

Suspend

Read

Erase-

Suspend

Read

Erase-Suspend-Program (Embedded Program)

Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0 Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0

Program-Suspended Sector

Non-Program Suspended Sector

Erase-Suspended Sector

Non-Erase Suspended Sector

(Note 2) DQ6

1 No toggle 0 N/A Toggle N/A 1

DQ7# Toggle 0 N/A N/A N/A 0

DQ5

(Note 1) DQ3

Invalid (not allowed) 1

Data 1

DQ2

(Note 2) DQ1 RY/BY#

January 31, 2007 25270C7 Am29LV128MH/L 43

Page 44

DATA SHEET

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

A9, OE#, ACC, and RESET#

(Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V

All other pins (Note 1) . . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot V Maximum DC voltage on input or I/O pins is V See Figure 10. During voltage transitions, input or I/O pins may overshoot to V See Figure 11.

2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

to –2.0 V for periods of up to 20 ns.

+2.0 V for periods up to 20 ns.

+0.5 V

+0.5 V.

to –2.0 V for

+0.8 V

–0.5 V

–2.0 V

+2.0 V

+0.5 V

2.0 V

20 ns

Figure 10. Maximum Negative

Overshoot Waveform

20 ns

Figure 11. Maximum Positive

Overshoot Waveform

20 ns

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . . . . . . –40°C to +85°C

Supply Voltages

(regulated voltage range) . . . . . . . . . . . . . . . . 3.0–3.6 V

(full voltage range) . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V

(Note 2) . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V (Note 3)

Notes:

1. Operating ranges define those limits between which the functionality of the device is guaranteed.

2. See “Ordering Information” on page 10 for valid VCC/VIO range combinations. The I/Os will not operate at 3V when

= 1.8V.

3. 100R parts have a V

44 Am29LV128MH/L 25270C7 January 31, 2007

range from 2.7–3.6 V.

Page 45

DC CHARACTERISTICS

CMOS Compatible

DATA SHEET

Parameter

Symbol

LIT

CC1

CC2

CC3

CC4

CC5

CC6

CC7

IL1

IH1

IL2

IH2

OH1

OH2

LKO

Parameter Description

(Notes)

= VSS to VCC,

Input Load Current (1)

= VCC

A9, ACC Input Load Current VCC = V

Output Leakage Current

OUT

= V

Reset Leakage Current VCC = V

VCC Active Read Current (2, 3)

CE# = V

Test Conditions Min Typ Max Unit

max

; A9 = 12.5 V 35 µA

CC max

= VSS to VCC,

CC max

; RESET# = 12.5 V 35 µA

CC max

5 MHz 3 34

OE# = VIH,

IL,

1 MHz 13 43

±1.0 µA

1 MHz 4 50

Initial Page Read Current (2, 3) CE# = V

OE# = V

IL,

mA10 MHz 40 80

10 MHz 3 20

Intra-Page Read Current (2, 3) CE# = V

VCC Active Write Current (3, 4) CE# = V

VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = V

VCC Reset Current (3) RESET# = V

= V

Automatic Sleep Mode (3, 5)

WP# = V

OE# = V

IL,

OE# = V

IL,

± 0.3 V; V

± 0.3 V, WP# = V

= V

33 MHz 6 40 mA

50 60 mA

± 0.3 V,

15µA

Input Low Voltage 1(6, 7) –0.5 0.8 V

Input High Voltage 1 (6, 7) 1.9

0.5

Input Low Voltage 2 (6, 8) –0.5 0.3 x VIOV

Input High Voltage 2 (6, 8) 1.9 VIO + 0.5 V

Voltage for ACC Program Acceleration

Voltage for Autoselect and Temporary Sector Unprotect

Output Low Voltage (10) IOL = 4.0 mA, VCC = V

Output High Voltage

= 2.7–3.6 V 11.5 12.5 V

0.15 x V

= –2.0 mA, VCC = V

IOH = –100 µA, VCC = V

CC min

= V

0.85 V

VIO–0.4 V

Low VCC Lock-Out Voltage (9) 2.3 2.5 V

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP# = V

2. The ICC current listed is typically less than 2 mA/MHz, with OE# at V

3. Maximum I

4. I

progress.

is ± 5.0 µA.

specifications are tested with VCC = VCCmax.

active while Embedded Erase or Embedded Program is in

5. Automatic sleep mode enables the low power mode when addresses remain stable for t

6. If V

7. V

8. V

9. Not 100% tested.

10. Includes RY/BY#

< VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO.

Maximum V

voltage requirements.

for these connections is VIO + 0.3 V

+ 30 ns.

ACC

January 31, 2007 25270C7 Am29LV128MH/L 45

Page 46

TEST CONDITIONS

DATA SHEET

3.3 V

Table 13. Test Specifications

Test Condition All Speeds Unit

Device

Under

Te s t

Note: Diodes are IN3064 or equivalent

6.2 kΩ

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

2.7 kΩ

Output Load 1 TTL gate

Output Load Capacitance, C (including jig capacitance)

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement reference levels (See Note)

Output timing measurement reference levels

Note: If VIO < VCC, the reference level is 0.5 VIO.

Steady

Changing from H to L

30 pF

1.5 V

0.5 V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V

Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

1.5 V 0.5 V

Figure 13. Input Waveforms and Measurement Levels

Changing from L to H

OutputMeasurement LevelInput

46 Am29LV128MH/L 25270C7 January 31, 2007

Page 47

AC CHARACTERISTICS

Read-Only Operations

DATA SHEET

Param ete r

JEDEC Std. 93R

AVAVtRC

AVQVtACC

ELQVtCE

GLQVtOE

EHQZtDF

GHQZtDF

AXQXtOH

Description Test Setup

Read Cycle Time (Note 1) Min 90 100 110 120 ns

Address to Output Delay CE#, OE# = VILMax 90 100 110 120 ns

Chip Enable to Output Delay OE# = V

Page Access Time Max 25 30 30 40 30 40 ns

PAC C

Output Enable to Output Delay Max 25 30 30 40 30 40 ns

Chip Enable to Output High Z (Note 1) Max 16 ns

Output Enable to Output High Z (Note 1) Max 16 ns

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First

Output Enable Hold Time

OEH

(Note 1)

Read Min 0 ns

Toggle and Data# Polling

Max 90 100 110 120 ns

Min 0 ns

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 12 and Ta b l e 1 3 for test specifications.

3. AC Specifications listed are tested with V

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Speed Options

103,

103R 113 113R 123 123R Unit

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

ACC

OEH

HIGH Z

Figure 14. Read Operation Timings

Output Valid

HIGH Z

January 31, 2007 25270C7 Am29LV128MH/L 47

Page 48

AC CHARACTERISTICS

DATA SHEET

A22-A2

A0*

ACC

Data Bus

CE#

OE#

* Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

Same Page

PAC C

Ab Ac

PAC C

Qa Qb Qc Qd

48 Am29LV128MH/L 25270C7 January 31, 2007

Page 49

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

DATA SHEET

Description All Speed Options UnitJEDEC Std.

Ready

RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note)

RESET# Pulse Width Min 500 ns

Reset High Time Before Read (See Note) Min 50 ns

RESET# Low to Standby Mode Min 20 μs

RPD

RY/BY# Recovery Time Min 0 ns

Max 20 μs

Max 500 ns

Note:

1. Not 100% tested.

2. AC Specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

RY/BY#

CE#, OE#

RESET#

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

RY/BY#

CE#, OE#

RESET#

Figure 16. Reset Timings

January 31, 2007 25270C7 Am29LV128MH/L 49

Page 50

DATA SHEET

AC CHARACTERISTICS

Erase and Program Operations

Parameter Speed Options

JEDEC Std. Description 93R 103, 103R 113, 113R 123, 123R Unit

AVAV

AVW L

WLAX

DVW H

WHDX

GHWL

ELWL

WHEH

WLWH

WHDL

WHWH1tWHWH1

WHWH2tWHWH2

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” on page 60 for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation

5. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

6. AC Specifications listed are tested with V

7. When using the program suspend/resume feature, if the suspend command is issued within t re-applied upon resuming the programming operation. If the suspend command is issued after t again prior to reading the status bits upon resuming.

Write Cycle Time (Note 1) Min 90 100 110 120 ns

Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 15 ns

ASO

Address Hold Time Min 45 ns

Address Hold Time From CE# or OE# high

AHT

during toggle bit polling

Data Setup Time Min 45 ns

Data Hold Time Min 0 ns

Output Enable High during toggle bit polling Min 20 ns

OEPH

Read Recovery Time Before Write

GHWL

(OE# High to WE# Low)

CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 35 ns

Write Pulse Width High Min 30 ns

WPH

Min 0 ns

Write Buffer Program Operation (Notes 2, 3) Typ 240 µs

Effective Write Buffer Program Operation (Notes 2, 4)

Accelerated Effective Write Buffer Program Operation (Notes 2, 4)

Single Byte/Word Program Operation (Note 2, 5)

Accelerated Single Byte/Word Programming Operation (Note 2, 5)

Per Byte Typ 7.5

Per Word Typ 15

Per Byte Typ 6.25 µs

Per Word Typ 12.5 µs

Byte Typ 60

Word Typ 60

Byte Typ 54 µs

Word Typ 54 µs

Sector Erase Operation (Note 2) Typ 0.5 sec

VHHVHH

VCSVCC

BUSY

POLL

Rise and Fall Time (Note 1) Min 250 ns

Setup Time (Note 1) Min 50 µs

Erase/Program Valid to RY/BY# Delay Max 90 ns

Program Valid Before Status Polling (Note 7) Max 4 µs

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

, t

POLL

must be fully

POLL

, t

is not required

POLL

µs

50 Am29LV128MH/L 25270C7 January 31, 2007

Page 51

RY/BY#

CE#, OE#

RESET#

RY/BY#

DATA SHEET

Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

CE#, OE#

RESET#

Figure 17. Reset Timings

January 31, 2007 25270C7 Am29LV128MH/L 51

Page 52

AC CHARACTERISTICS

DATA SHEET

Addresses

CE#

OE#

WE#

Data

RY/BY#

Program Command Sequence (last two cycles)

PA PA

WPH

555h

A0h

VCS

Read Status Data (last two cycles)

POLL

WHWH1

BUSY

Status

OUT

otes:

. PA = program address, PD = program data, D . Illustration shows device in word mode.

Figure 18. Program Operation Timings

or V

ACC

IH V

VHH

Figure 19. Accelerated Program Timing Diagram

is the true data at the program address.

OUT

VHH

or V

52 Am29LV128MH/L 25270C7 January 31, 2007

Page 53

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

DATA SHEET

555h for chip erase

Addresses

2AAh SA

CE#

OE#

WE#

Data

WPH

30h

10 for Chip Erase

BUSY

55h

WHWH2

Progress

Complete

RY/BY#

VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data. See “Write Operation Status” on page 39.

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

January 31, 2007 25270C7 Am29LV128MH/L 53

Page 54

AC CHARACTERISTICS

Addresses

POLL

CE#

OE#

WE#

DQ15 and DQ7

OEH

ACC

DATA SHEET

VA VA

Complement

Tru e

Valid Data

High Z

DQ14–DQ8, DQ6–DQ0

BUSY

Status Data

Tru e

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

54 Am29LV128MH/L 25270C7 January 31, 2007

Page 55

AC CHARACTERISTICS

DATA SHEET

Addresses

CE#

WE#

OE#

DQ6/DQ2

RY/BY#

Valid Data

OEH

AHT

ASO

OEPH

Valid

Status

(first read) (second read) (stops toggling)

Valid

Status

CEPH

AHT

Valid

Status

Valid Data

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase Suspend Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

January 31, 2007 25270C7 Am29LV128MH/L 55

Page 56

AC CHARACTERISTICS

Temporary Sector Group Unprotect

Parameter

DATA SHEET

All Speed OptionsJEDEC Std Description Unit

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

RSP

Unprotect

Note:

1. Not 100% tested.

2. AC Specifications listed are tested with V

RESET#

VSS, VIL, or V

VIDR

CE#

WE#

RSP

Min 4 µs

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

VSS, VIL,

or V

VIDR

Program or Erase Command Sequence

RRB

RY/BY#

Figure 24. Temporary Sector Group Unprotect Timing Diagram

56 Am29LV128MH/L 25270C7 January 31, 2007

Page 57

AC CHARACTERISTICS

RESET#

DATA SHEET

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Group Protect or Unprotect Verify

Data

60h 60h 40h

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector Group Protect and Unprotect Timing Diagram

Status

January 31, 2007 25270C7 Am29LV128MH/L 57

Page 58

DATA SHEET

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter Speed Options

JEDEC Std. Description 93R 103, 103R 113, 113R 123, 123R Unit

AVAV

AVW L

ELAX

DVEH

EHDX

GHEL

Write Cycle Time (Note 1) Min 90 100 110 120 ns

Address Setup Time Min 0 ns

Address Hold Time Min 45 ns

Data Setup Time Min 45 ns

Data Hold Time Min 0 ns

Read Recovery Time Before Write

GHEL

(OE# High to WE# Low)

Min 0 ns

WLEL

EHWH

ELEH

EHEL

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 45 ns

CE# Pulse Width High Min 30 ns

CPH

Write Buffer Program Operation (Notes 2, 3) Typ 240 µs

Per Byte Typ 7.5 µs

Per Word Typ 15 µs

Per Byte Typ 6.25 µs

Per Word Typ 12.5 µs

WHWH1tWHWH1

Effective Write Buffer Program Operation (Notes 2, 4)

Accelerated Effective Write Buffer Program Operation (Notes 2, 4)

Single Word Program Operation (Note 2, 5) Typ 60 µs

WHWH2tWHWH2

POLL

Accelerated Single Word Programming Operation (Note 2, 5)

Sector Erase Operation (Note 2) Typ 0.5 sec

Program Valid before Status Polling (Note 7) Max 4 µs

Ty p 5 4 µ s

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 60 for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.

6. AC Specifications listed are tested with V

7. When using the program suspend/resume feature, if the suspend command is issued within t re-applied upon resuming the programming operation. If the suspend command is issued after t

= VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

, t

POLL

must be fully

POLL

, t

is not required

POLL

again prior to reading the status bits upon resuming.

58 Am29LV128MH/L 25270C7 January 31, 2007

Page 59

AC CHARACTERISTICS

DATA SHEET

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program 2AA for erase

PA for program SA for sector erase 555 for chip erase

GHEL

CPH

A0A0 for program 5555 for erase

POLL

WHWH1 or 2

BUSY

PD for program 3030 for sector erase 1010 for chip erase

Data# Polling

DQ7#,

DQ15

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D

is the data written to the device.

OUT

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V (including A9, OE#, and RESET#)

Input voltage with respect to V

VCC Current –100 mA +100 mA

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

on all pins except I/O pins

on all I/O pins –1.0 V VCC + 1.0 V

–1.0 V 12.5 V

January 31, 2007 25270C7 Am29LV128MH/L 59

Page 60

DATA SHEET

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.5 3.5 sec

Chip Erase Time 128 256 sec

Single Word Program Time (Note 3)60600µs

Accelerated Single Word Program Time (Note 3)

Total Write Buffer Program Time (Note 4) 240 1200 µs

Effective Write Buffer Program Time (Note 5)

Total Accelerated Write Buffer Program Time (Note 4)

Effective Accelerated Write Buffer Program Time (Note 5)

Chip Program Time 126 292 sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h.

2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles.

3. Word programming specification is based upon a single word programming operation not utilizing the write buffer.

4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.

5. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

6. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed.

7. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

8. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Ta b l e 1 1 for further information on command definitions.

9. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Per Byte 7.5 38 µs

Per Word 15 75 µs

Per Byte 6.25 33 µs

Per Word 12.5 65 µs

54 540 µs

200 1040 µs

Excludes 00h programming

prior to erasure (Note 6)

Excludes system level

overhead (Note 8)

60 Am29LV128MH/L 25270C7 January 31, 2007

Page 61

DATA SHEET

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0

BGA 4.2 5 pF

TSOP 8.5 12 pF

TSOP 6 7.5 pF

OUT

Output Capacitance V

OUT

= 0

BGA 5.4 6.5 pF

TSOP 7.5 9 pF

IN2

Control Pin Capacitance VIN = 0

BGA 3.9 4.7 pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C10Years

125°C20Years

January 31, 2007 25270C7 Am29LV128MH/L 61

Page 62

DATA SHEET

PHYSICAL DIMENSIONS

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)

PACKAGE

JEDEC

SYMBOL

TS/TSR 56

MO-142 (B) EC

MIN.

---

0.05

0.95

0.50 BASIC

NOM.

---

1.00

0.20 0.230.17

0.22 0.270.17

--- 0.160.10

--- 0.210.10

20.00 20.2019.90

18.40 18.5018.30

14.00 14.1013.90

0.60 0.700.50

3˚ 5˚0˚

--- 0.200.08

MAX.

1.20

0.15

1.05

NOTES:

1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE.

9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3160\38.10A

62 Am29LV128MH/L 25270C7 January 31, 2007

Page 63

DATA SHEET

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array 13 x 11 mm Package

January 31, 2007 25270C7 Am29LV128MH/L 63

Page 64

DATA SHEET

REVISION SUMMARY

Revision A (October 3, 2001)

Initial release as abbreviated Advance Information data sheet.

Revision A+1 (March 20, 2002)

Distinctive Characteristics

Clarified description of Enhanced VersatileIO control.

Product Selector Guide

Removed the 98R, 108, 108R, 118, 118R, 128, and 128R Speed Options.

Replaced Note #2.

Product Selector Guide and Read Only Operations

Added a 30 ns Page Access time and Output Enable Access time to the 113R and 123R Speed Options.

Ordering Information

Corrected device density in device number/description.

Physical Dimensions

Added drawing that shows both TS056 and TSR056 specifications.

Revision B (July 1, 2002)

Expanded data sheet to full specification version.

Revision B+1 (September 16, 2002)

Distinctive Characteristics, Physical Dimensions

Added 80-Ball Fine-Pitch BGA.

Product Selector Guide

Added 80-Ball Fine-Pitch BGA. Added Note #1. Added 103, 108, 113, 118, 123, 128 regulated OPNs. Changed all OPNs that end with 4 or 9 to 3 or 8.

Program Suspend/Program Resume Command Sequence

Changed 1ms to 15μs maximum, with a typical of 5 μs.

Erase Suspend/Erase Resume Commands

Added that the device requires a typical of 5 μs.

Read-Only Operations, Erase Program Operations, and Alternate CE# Controlled Erase and Program Operations

Added regulated OPNs. Changed all OPNs that end with 4 or 9 to 3 or 8.

Revision B+2 (November 11, 2002)

Global

Removed the Enhanced VI/O option and changed it to VI/O only.

Ordering Information

Modified Order numbers and package markings to reflect the removal of speed options. Modified the V ranges. Added Notes #1 and #2.

Table 4. Secured Silicon Sector Contents

Added x8 and x16

Operating Ranges

Changed the V

Added V

supply range to 1.65–3.6 V.

(regulated voltage range) and VIO (full volt-

age range).

DC Characteristics

Removed V

, V

IL1

, VIH, VOL, and VOH from table and added

, V

IH1

IL2

, VOL, V

IH2

OH1

, and V

from the

OH2

CMOS table in the Am29LV640MH/L datasheet.

Erase and Programming Performance

Changed the typicals and/or maximums of Chip Erase Time, Sector Erase Time, Effective Write Buffer Program Time, Program Time, and Accelerated Program Time to TBD.

Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the factory.

Added second bullet, Secured Silicon sector-protect verify text and figure 3.

Secured Silicon Sector Flash Memory Region, and Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence

Noted that the ACC function and unlock bypass modes are not available when the Secured Silicon sector is enabled.

Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence

Distinctive Characteristics

Changed the typical sector erase time to TBD. Changed the typical write buffer word programming

Noted that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress.

time to TBD.

64 Am29LV128MH/L 25270C7 January 31, 2007

Page 65

DATA SHEET

Common Flash Memory Interface (CFI)

Changed wording in last sentence of third paragraph from, “...the autoselect mode.” to “...reading array data.” Changed CFI website address

Revision B+3 (December 2, 2002)

Global

Added sector group protection throughout datasheet and added Table 4.

Product Selector Guide

Added V

Ordering Information

Corrected typos in V

Figure 6. Program Suspend/Program Resume

Change wait time to 15

Operating Ranges

Corrected typos in V range.

s to table and removed Note #2

ranges. Removed Notes #1 and

μs.

ranges. Removed full voltage

Input values in the t

WHWH

1 and t

2 parameters in

WHWH

the Alternate CE# Controlled Erase and Program Options table that were previously TBD. Also added Note

Erase and Programming Performance

Input values into table that were previously TBD. Added note 4.

Revision C (May 16, 2003)

Global

Converted to full data sheet version. Modified Secured Silicon Sector Flash Memory Region section to include ESN references. Changed data sheet title to Am29LV128MH/L.

Erase and Programming Performance

Input values into table that were previously TBD. Modified notes.

Revision C+1 (June 11, 2003)

Product Selector Guide

Added Note 2 to 113 and 123 speed grades

DC Characteristics

Changed V

IH1

and V

minimum to 1.9. Removed

IH2

typos in notes.

Read-Only Characteristics

Added a 30 ns option to t

and tOE standard in ta-

PAC C

ble. Added note #3.

Hardware Reset, Erase and Program Operations, Temporary Sector Unprotect, and Alternate CE# Controlled Erase and Program Operations

Added Note.

Revision B+4 (February 14, 2003)

Distinctive Characteristics

Corrected performance characteristics.

Product Selector Guide

Removed 93R speed option. Added Note 2.

Ordering Information

Corrected Valid Combination to reflect speed option changes. Added Note.

AC Characteristics

Removed 93, 93R speed option. Added Note.

Input values in the t the Erase and Program Options table that were previously TBD. Also added notes 5 and 6.

WHWH

1 and t

2 parameters in

WHWH

Ordering Information

Modified speed grade options available, changed speed grades mentioned in Note.

AC Characteristics, Erase and Program Operations and Alternate CE# Controlled Erase and Program Operations

Changed t

Accelerated Effective Write Buffer

WHWH1

Program Operations value

Revision C+2 (September 9, 2003)

Global

Added 90 ns speed options and Ordering Part Numbers

Ordering Information

Added Note regarding Ordering Part Numbers.

Program Suspend/Program Resume Command Sequence

Modified last paragraph.

Command Definitions, Table 10

Modified First Addr for Program/Erase Suspend and Resume.

AC Characteristics

Added T

, T

BUSY

specs.

January 31, 2007 25270C7 Am29LV128MH/L 65

Page 66

DATA SHEET

Revision C+3 (February 27, 2004)

Global

Changed Datasheet to Advanced Information.

Table 1, Device Bus Operations

Modified ACC column to replace instances of X to L/H.

Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory

Removed second paragraph.

Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence

Added (write buffer) to last sentence of first paragraph.

Write Buffer Programming

Removed last paragraph.

Table 10 & Table 11, Command Definitions

Replaced the Addr information for both Program/Erase Suspend and Program/Erase Resume from BA to XXX.

Erase Suspend/Erase Resume Commands

Added note on flash device performance during suspend/erase mode

AC Characteristics - Erase and Program Operations

Added t

information.

POLL

Added notation referencing superceding documentation.

Revision C+4 (October 26, 2004)

Added Pb free options to the ordering information and valid combinations table.

Revision C+5 (January 11, 2005)

Changed notation referencing superceding documentation.

Revision C+6 (October 28, 2005)

Revision C7 (January 31, 2007)

Global

Removed Preliminary designation from document. Changed SecSi Sector to Secured Silicon Sector.

Erase and Program Operations table

Changed t

to a maximum specification.

BUSY

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.

Trademarks

Copyright © 2001–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Copyright © 2005–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

66 Am29LV128MH/L 25270C7 January 31, 2007

AMD Am29LV128MH, Am29LV128ML Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual