AMD Am29LV128MH, Am29LV128ML Service Manual

查询AM29LV128MH100EF供应商

Am29LV128MH/L

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,
S29GL256N supersedes Am29LV128MH/L and is the factory-recommended migration path. Please
refer to the S29GL256N datasheet for specifications and ordering information. Availability of this
document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 25270 Revision C Amendment 7 Issue Date January 31, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV128MH/L

128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control

This product has been retired and is not recommended for designs. For new and current designs, S29GL256N supersedes Am29LV128MH/L and is the factory-rec­ommended migration path. Please refer to the S29GL256N datasheet for specifications and ordering information. Availability of this document is retained for refer­ence and historical purposes only

DISTINCTIVE CHARACTERISTICS

..

ARCHITECTURAL ADVANTAGES

 Single power supply operation

— 3 volt read, erase, and program operations

 VersatileI/O™ control

— Device generates data output voltages and tolerates

data input voltages on the CE# and DQ
inputs/outputs as determined by the voltage on the

pin; operates from 1.65 to 3.6 V

V

IO

 Manufactured on 0.23 µm MirrorBit process

technology

 Secured Silicon Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence

— May be programmed and locked at the factory or by

the customer

 Flexible sector architecture

— Two hundred fifty-six 32 Kword (64 Kbyte) sectors

 Compatibility with JEDEC standards

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent
write protection

 Minimum 100,000 erase cycle guarantee per sector

 20-year data retention at 125°C

PERFORMANCE CHARACTERISTICS

 High performance

— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 s typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer

 Low power consumption (typical values at 3.0 V, 5

MHz)

— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current

 Package options

— 56-pin TSOP
— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

 Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall

multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

 Hardware features

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group
— Temporary Sector Group Unprotect: V

of changing code in locked sector groups

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

-level method

ID

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 25270 Rev: C Amendment: 7
Issue Date: January 31, 2007

DATA SHEET

GENERAL DESCRIPTION

The Am29LV128MH/L is a 128 Mbit, 3.0 volt single
power supply flash memory devices organized as
8,388,608 words or 16,777,216 bytes. The device has
a 16-bit wide data bus that can also function as an
8-bit wide data bus by using the BYTE# input. The de­vice can be programmed either in the host system or
in standard EPROM programmers.

An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
specified in “Product Selector Guide” on page 6 and
the “Ordering Information” on page 10. The device is
offered in a 56-pin TSOP, 64-ball Fortified BGA. Each
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a V

input, a high-voltage accelerated program

CC

(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.

The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter­nally latch addresses and data needed for the pro­gramming and erase operations.

) and an I/O voltage range (VIO), as

CC

of memory. This can be achieved in-system or via pro­gramming equipment.

The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The Program Sus-
pend/Program Resume feature enables the host sys­tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.

The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.

The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.

The Secured Silicon Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.

The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.

The sector erase architecture allows memory sec­tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.

Device programming and erasure are initiated through
command sequences. Once a program or erase oper­ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter­mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com­mand sequence overhead by requiring only two write
cycles to program data instead of four.

The VersatileI/O™ (V

) control allows the host sys-

IO

tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V

IO

pin.
Refer to the Ordering Information section for valid V
options.

Hardware data protection measures include a low
V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups

AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec­tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.

RELATED DOCUMENTS

For a comprehensive information on MirrorBit prod­ucts, including migration information, data sheets, ap­plication notes, and software drivers, please see

www.amd.com
tion

→MirrorBit→Flash Information→Technical Docu-

mentation. The following is a partial list of documents

closely related to this product:

MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read

IO

Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

Am29LV256M, 256 Mbit MirrorBit Flash device
(in 64-ball, 18 x 12 mm Fortified BGA package)

→Flash Memory→Product Informa-

4 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

TABLE OF CONTENTS

Continuity of Specifications ............................................................. i

For More Information ....................................................................... i

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11

Table 1. Device Bus Operations ...........................................................11

Word/Byte Configuration ........................................................ 11

VersatileIO™ (VIO) Control ........................................................... 11

Requirements for Reading Array Data ......................................... 12

Page Mode Read .................................................................... 12

Writing Commands/Command Sequences .................................. 12

Write Buffer ............................................................................. 12

Accelerated Program Operation ............................................. 12

Autoselect Functions ..............................................................12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ................................................................. 13

RESET#: Hardware Reset Pin .....................................................13

Output Disable Mode ................................................................... 13

Table 2. Sector Address Table .............................................................. 14

Autoselect Mode..................................................................... 20

Table 3. Autoselect Codes, (High Voltage Method) .............................20

Sector Group Protection and Unprotection ..................................21

Table 4. Sector Group Protection/Unprotection Address Table .....21

Write Protect (WP#)................................................................ 22

Temporary Sector Group Unprotect ............................................. 22

Figure 1. Temporary Sector Group Unprotect Operation ................ 22

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 23

Secured Silicon Sector Flash Memory Region ............................. 24

Table 5. Secured Silicon Sector Contents ......................................24

Figure 3. Secured Silicon Sector Protect Verify .............................. 25

Hardware Data Protection ............................................................ 25

Low VCC Write Inhibit ............................................................ 25

Write Pulse “Glitch” Protection ............................................... 25

Logical Inhibit .......................................................................... 25

Power-Up Write Inhibit ............................................................ 25

Common Flash Memory Interface (CFI) . . . . . . . 25

Table 6. CFI Query Identification String .............................. 26

Table 7. System Interface String......................................................26

Table 8. Device Geometry Definition................................... 27

Table 9. Primary Vendor-Specific Extended Query............. 28

Command Definitions . . . . . . . . . . . . . . . . . . . . . 29

Reading Array Data ...................................................................... 29

Reset Command ..........................................................................29

Autoselect Command Sequence .................................................. 29

Enter Secured Silicon Sector/Exit Secured Silicon Sector

Command Sequence ................................................................... 30

Word Program Command Sequence ........................................... 30

Unlock Bypass Command Sequence ..................................... 30

Write Buffer Programming ...................................................... 30

Accelerated Program .............................................................. 31

Figure 4. Write Buffer Programming Operation............................... 32

Figure 5. Program Operation .......................................................... 33

Program Suspend/Program Resume Command Sequence ........33

Figure 6. Program Suspend/Program Resume............................... 34

Chip Erase Command Sequence ................................................. 34

Sector Erase Command Sequence .............................................. 34

Erase Suspend/Erase Resume Commands ................................ 35

Figure 7. Erase Operation.............................................................. 36

Command Definitions ............................................................. 37

Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ................. 37

Table 11. Command Definitions (x8 Mode, BYTE# = V

) ................... 38

IL

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 39

DQ7: Data# Polling ...................................................................... 39

Figure 8. Data# Polling Algorithm .................................................. 39

RY/BY#: Ready/Busy#............................................................ 40

DQ6: Toggle Bit I .......................................................................... 40

Figure 9. Toggle Bit Algorithm........................................................ 41

DQ2: Toggle Bit II ......................................................................... 41

Reading Toggle Bits DQ6/DQ2 .................................................... 41

DQ5: Exceeded Timing Limits ...................................................... 42

DQ3: Sector Erase Timer ............................................................. 42

DQ1: Write-to-Buffer Abort ........................................................... 42

Table 12. Write Operation Status ......................................................... 43

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 44

Figure 10. Maximum Negative Overshoot Waveform ................... 44

Figure 11. Maximum Positive Overshoot Waveform ..................... 44

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 44

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 12. Test Setup.................................................................... 46

Table 13. Test Specifications ......................................................... 46

Key to Switching Waveforms. . . . . . . . . . . . . . . . 46

Figure 13. Input Waveforms and Measurement Levels ................. 46

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47

Read-Only Operations ........................................................... 47

Figure 14. Read Operation Timings ............................................... 47

Figure 15. Page Read Timings ...................................................... 48

Hardware Reset (RESET#) ....................................................49

Figure 16. Reset Timings ............................................................... 49

Erase and Program Operations .............................................. 50

Figure 17. Reset Timings ............................................................... 51

Figure 18. Program Operation Timings .......................................... 52

Figure 19. Accelerated Program Timing Diagram .......................... 52

Figure 20. Chip/Sector Erase Operation Timings .......................... 53

Figure 21. Data# Polling Timings (During Embedded Algorithms). 54

Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 55

Figure 23. DQ2 vs. DQ6................................................................. 55

Temporary Sector Group Unprotect .......................................56

Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 56

Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 57

Alternate CE# Controlled Erase and Program Operations ..... 58

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 59

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 59

Erase And Programming Performance. . . . . . . . 60

TSOP Pin and BGA Package Capacitance . . . . . 61

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 62

LAA064—64-Ball Fortified Ball Grid Array

13 x 11 mm Package .............................................................. 63

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64

January 31, 2007 25270C7 Am29LV128MH/L 5

PRODUCT SELECTOR GUIDE

Part Num ber Am29LV128MH/L

Regulated Voltage Range

= 3.0–3.6 V

V

Speed/
Voltage
Option

Max. Access Time (ns)

CC

Full Voltage Range
V

= 2.7–3.6 V

CC

DATA SHEET

93R

= 3.0–3.6 V

V

IO

90

103R

VIO = 2.7–3.6 V

103

(Note 2)

= 2.7–3.6 V

V

IO

100 110 120

113R

VIO = 1.65–3.6 V

113

(Note 2)

VIO = 1.65–3.6 V

123R

VIO = 1.65–3.6 V

123

(Note 2)

VIO = 1.65–3.6 V

Max. CE# Access Time (ns)

Max. Page access time (t

Max. OE# Access Time (ns)

Notes:

1. See “AC Characteristics” for full specifications.

2. Contact factory for availability and ordering information.

PAC C

)

90

25

25

BLOCK DIAGRAM

RY/BY#

V

CC

V

SS

RESET#

WE#

WP#/ACC

BYTE#

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

100 110 120

30 30 40 30 40

30 30 40 30 40

DQ0–DQ15 (A-1)

Sector Switches

V

Erase Voltage

IO

Generator

Chip Enable

Output Enable

STB

Logic

Input/Output

Buffers

Data

Latch

A22–A0

VCC Detector

Timer

STB

Y-Decoder

X-Decoder

Address Latch

Y-Gating

Cell Matrix

6 Am29LV128MH/L 25270C7 January 31, 2007

CONNECTION DIAGRAMS

1

NC

2

A22

3

A15

4

A14

5

A13

6

A12

7

A11

8

A10

9

A9

10

A8

11

A19

12

A20

13

WE#

A21

A18
A17

A7
A6
A5
A4
A3
A2

A1
NC
NC

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

RESET#

WP#/ACC

RY/BY#

DATA SHEET

56-Pin Standard TSOP

56

NC

55

NC

54

A16

53

BYTE#

52

V
DQ15/A-1

51

DQ7

50

DQ14

49

DQ6

48

DQ13

47

DQ5

46

DQ12

45

DQ4

44

V

43

DQ11

42

DQ3

41

DQ10

40

DQ2

39

DQ9

38

DQ1

37

DQ8

36

DQ0

35

OE#

34

V

33
32

CE#

31

A0

30

NC

29

V

SS

CC

SS

IO

NC
NC

A16

BYTE#

V

DQ15/A-1

SS

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

SS

CE#

A0
NC
V

1
2
3
4
5
6
7
8

9
10
11
12
13
14

56-Pin Reverse TSOP

15
16
17
18
19
20
21
22
23
24
25
26
27
28

IO

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC

January 31, 2007 25270C7 Am29LV128MH/L 7

CONNECTION DIAGRAMS

DATA SHEET

64- Ball Fortified BGA

Top View, Balls Facing Down

A8 C8

A7 C7 D7 E7 F7 G7 H7

A6 C6 D6 E6 F6 G6 H6

A5 C5 D5 E5 F5 G5 H5

A4 C4 D4 E4 F4 G4 H4

A3 C3 D3 E3 F3 G3 H3

A2 C2 D2 E2 F2 G2 H2

A1 C1 D1 E1 F1 G1 H1

B8 D8 E8 F8 G8 H8

NC

V

V

NC

B7

B6

B5

B4

B3

B2

B1

NCA22NC

V

IO

SS

NCNCNCNCNC

NCV

V

IO

NC

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

V

CC DQ4DQ12DQ5A19A21RESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE#

NC

SSBYTE#A16A15A14A12A13

SSCE#A0A1A2A4A3

Special Package Handling Instructions

package body is exposed to temperatures above

150°C for prolonged periods of time.
Special handling is required for Flash Memory products
in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the

8 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

PIN DESCRIPTION

A22–A0 = 23 Address inputs

DQ14–DQ0 = 15 Data inputs/outputs

DQ15/A-1 = DQ15 (Data input/output, word mode),

A-1 (LSB Address input, byte mode)

CE# = Chip Enable input

OE# = Output Enable input

WE# = Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RESET# = Hardware Reset Pin input

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy output

V

= 3.0 volt-only single power supply

CC

V

= Output Buffer power

IO

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for
speed options and voltage
supply tolerances)

= Device Ground

LOGIC SYMBOL

23

A22–A0

CE#

OE#

WE#

WP#/ACC

RESET#

V

IO

BYTE#

16 or 8

DQ15–DQ0

(A-1)

RY/BY#

January 31, 2007 25270C7 Am29LV128MH/L 9

DATA SHEET

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29LV128MH/L H 123R PC I

TEMPERATURE RANGE

F = Industrial (-40C to 85C) with Pb-free Package
I = Industrial (–40

PACKAGE TYPE

E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
PC = 64-Ball Fortified Ball Grid Array (

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

FBGA),

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V

IL

H = Uniform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control,

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

Speed

(ns)

90 3.0–3.6 V

100 2.7–3.6 V

EI,

FI

EF

110 1.65–3.6 V

120 1.65–3.6 V

V

IO

Range

V

CC

Range

3.0–3.6 V

Valid Combinations for
Fortified BGA Package

Order Number Package Marking

Am29LV128MH93R
Am29LV128ML93R

Am29LV128MH103R
Am29LV128ML103R

Am29LV128MH113R
Am29LV128ML113R

Am29LV128MH123R
Am29LV128ML123R

PCI,
PCF

L128MH93N
L128ML93N

L128MH103N
L128ML103N

L128MH113N
L128ML113N

L128MH123N
L128ML123N

I,
F

Speed

(ns)

90

100

110

120

V

IO

Range

3.0–

3.6V

2.7–

3.6 V

1.65–

3.6 V

1.65–

3.6 V

V

CC

Range

3.0–

3.6 V

Valid Combinations

Valid Combinations list configurations planned to be supported in vol­ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re­leased combinations.

Notes:

1. For 100, 110, and 120 speed option shown in product selector guide, contact AMD for availability and ordering information.

2. To select product with ESN factory-locked into the Secured Silicon Sector: 1) select order number from the valid combinations given above, 2) add designator

“N” at the end of the order number, and 3) modify the speed option indicator as follows [103R = 10R, 113R = 11R, 123R = 12R, 93R, 103, 113, 123 = no
change]. Example: Am29LV128MH12RPCIN. For Fortified BGA packages, modify the speed option indicator as follows: [103N = 10N, 113N = 11N, 123N =
12N, 93N = no change]. The designator “N” will also appear at the end of the package marking. Example: L128MH12NIN.

)

10 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca­tion. The register is a latch used to store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Device Bus Operations

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Ta bl e 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

DQ8–DQ15

Operation CE# OE# WE# RESET# WP# ACC

Read L L H H

Write (Program/Erase) L H L H

Accelerated Program L H L H

±

V

Standby

Output Disable L H H H

Reset X X X L

Sector Group Protect
(Note 2)

Sector Group Unprotect
(Note 2)

Temporary Sector Group
Unprotect

CC

0.3 V

XX

LHL V

LHL V

XXX V

VCC ±

0.3 V

(Note 3) L/H

(Note 3) V

ID

ID

ID

DQ0–

DQ7

D

(Note 4) (Note 4)

(Note 4) (Note 4)

XL/H

HH

Addresses

(Note 2)

A

IN

A

IN

A

IN

X H X High-Z High-Z High-Z

X L/H X High-Z High-Z High-Z

X L/H X High-Z High-Z High-Z

SA, A6 =L,

HL/H

HL/H

HL/H

A3=L, A2=L,
A1=H, A0=L

SA, A6=H,
A3=L, A2=L,
A1=H, A0=L

A

IN

(Note 4) X X

(Note 4) X X

(Note 4) (Note 4) High-Z

OUT

BYTE#

= V

IH

D

OUT

BYTE#

= V

IL

DQ8–DQ14

= High-Z,

DQ15 = A-1

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

= Address In, DIN = Data In, D

A

IN

= Data Out

OUT

Notes:

1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.

3. If WP# = V

, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as

IL

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
Secured Silicon Sector may be factory protected depending on version ordered.)

4. D

IN

or D

as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con­figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.

VersatileIO™ (VIO) Control

The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O

level that is asserted on V

tion” for V

options on this device.

IO

. See “Ordering Informa-

IO

January 31, 2007 25270C7 Am29LV128MH/L 11

DATA SHEET

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com­mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. See
the table, See “Read-Only Operations” on page 47 for
timing specifications and Figure 14 for the timing dia­gram. See the table in “DC Characteristics” on
page 45 for the active current specification on reading
array data.

Page Mode Read

The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper­ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad­dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.

The random or initial page access is equal to t
t

and subsequent page read accesses (as long as

CE

ACC

or

the locations specified by the microprocessor falls
within that page) is equivalent to t

. When CE# is

PAC C

deasserted and reasserted for a subsequent access,
the access time is t

or tCE. Fast page mode ac-

ACC

cesses are obtained by keeping the “read-page ad­dresses” constant and changing the “intra-read page”
addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device features an Unlock Bypass mode to facili­tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a word or byte, instead of four. The
“Word Program Command Sequence” section has de-

, and OE# to VIH.

IL

tails on programming data to the device using both
standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec­tors, or the entire device. Ta bl e 2 indicates the address
space that each sector occupies.

See the table in “DC Characteristics” on page 45 for
the active current specification for the write mode. “AC

Characteristics” on page 47 contains timing specifica-

tion tables and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.

Accelerated Program Operation

The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima­rily intended to allow faster manufacturing throughput
at the factory.

If the system asserts V

on this pin, the device auto-

HH

matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to re­duce the time required for program operations. The
system would use a two-cycle program command se­quence as required by the Unlock Bypass mode. Re­moving V

from the WP#/ACC pin returns the device

HH

to normal operation. Note that the WP#/ACC pin must

not be at V

for operations other than accelerated

HH

programming, or device damage may result. WP# has
an internal pullup; when unconnected, WP# is at V

.

IH

Autoselect Functions

If the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. See “Autoselect Mode” on page 20 and

“Autoselect Command Sequence” on page 29 for

more information.

Standby Mode

When the system is not reading or writing to the de­vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than

± 0.3 V.

IO

12 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

VIH.) If CE# and RESET# are held at VIH, but not within
V

± 0.3 V, the device will be in the standby mode, but

IO

the standby current will be greater. The device re­quires standard access time (t

) for read access

CE

when the device is in either of these standby modes,
before it is ready to read data.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

See the table in “DC Characteristics” on page 45 for
the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en­ergy consumption. The device automatically enables
this mode when addresses remain stable for t

ACC

+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad­dress access timings provide new data when ad­dresses are changed. While in sleep mode, output
data is latched and always available to the system.
See the table in “DC Characteristics” on page 45 for
the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re­setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V

but not within VSS±0.3 V, the standby current will

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.

The RESET# pin may be tied to the system reset cir­cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

See the tables in “AC Characteristics” on page 47 for
RESET# parameters and to Figure 16 for the timing di­agram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.

January 31, 2007 25270C7 Am29LV128MH/L 13

DATA SHEET

Table 2. Sector Address Table (Sheet 1 of 6)

Sector A22–A15

SA0 0 0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF

SA1 0 0 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF

SA2 0 0 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF

SA3 0 0 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF

SA4 0 0 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF

SA5 0 0 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF

SA6 0 0 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF

SA7 0 0 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF

SA8 0 0 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF

SA9 0 0 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF

SA10 0 0 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF

SA11 0 0 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF

SA12 0 0 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF

SA13 0 0 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF

SA14 0 0 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF

SA15 0 0 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF

SA16 0 0 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF

SA17 0 0 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF

SA18 0 0 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF

SA19 0 0 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF

SA20 0 0 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF

SA21 0 0 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF

SA22 0 0 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF

SA23 0 0 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF

SA24 0 0 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF

SA25 0 0 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF

SA26 0 0 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF

SA27 0 0 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF

SA28 0 0 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF

SA29 0 0 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF

SA30 0 0 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF

SA31 0 0 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF

SA32 0 0 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF

SA33 0 0 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF

SA34 0 0 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF

SA35 0 0 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF

SA36 0 0 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF

SA37 0 0 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF

SA38 0 0 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF

SA39 0 0 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF

SA40 0 0 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF

SA41 0 0 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF

SA42 0 0 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF

SA43 0 0 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF

SA44 0 0 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF

SA45 0 0 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF

SA46 0 0 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

14 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

Table 2. Sector Address Table (Sheet 2 of 6)

Sector A22–A15

SA47 0 0 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF

SA48 0 0 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF

SA49 0 0 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF

SA50 0 0 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF

SA51 0 0 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF

SA52 0 0 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF

SA53 0 0 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF

SA54 0 0 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF

SA55 0 0 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF

SA56 0 0 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF

SA57 0 0 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF

SA58 0 0 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF

SA59 0 0 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF

SA60 0 0 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF

SA61 0 0 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF

SA62 0 0 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF

SA63 0 0 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF

SA64 0 1 0 0 0 0 0 0 64/32 400000–40FFFF 200000–207FFF

SA65 0 1 0 0 0 0 0 1 64/32 410000–41FFFF 208000–20FFFF

SA66 0 1 0 0 0 0 1 0 64/32 420000–42FFFF 210000–217FFF

SA67 0 1 0 0 0 0 1 1 64/32 430000–43FFFF 218000–21FFFF

SA68 0 1 0 0 0 1 0 0 64/32 440000–44FFFF 220000–227FFF

SA69 0 1 0 0 0 1 0 1 64/32 450000–45FFFF 228000–22FFFF

SA70 0 1 0 0 0 1 1 0 64/32 460000–46FFFF 230000–237FFF

SA71 0 1 0 0 0 1 1 1 64/32 470000–47FFFF 238000–23FFFF

SA72 0 1 0 0 1 0 0 0 64/32 480000–48FFFF 240000–247FFF

SA73 0 1 0 0 1 0 0 1 64/32 490000–49FFFF 248000–24FFFF

SA74 0 1 0 0 1 0 1 0 64/32 4A0000–4AFFFF 250000–257FFF

SA75 0 1 0 0 1 0 1 1 64/32 4B0000–4BFFFF 258000–25FFFF

SA76 0 1 0 0 1 1 0 0 64/32 4C0000–4CFFFF 260000–267FFF

SA77 0 1 0 0 1 1 0 1 64/32 4D0000–4DFFFF 268000–26FFFF

SA78 0 1 0 0 1 1 1 0 64/32 4E0000–4EFFFF 270000–277FFF

SA79 0 1 0 0 1 1 1 1 64/32 4F0000–4FFFFF 278000–27FFFF

SA80 0 1 0 1 0 0 0 0 64/32 500000–50FFFF 280000–287FFF

SA81 0 1 0 1 0 0 0 1 64/32 510000–51FFFF 288000–28FFFF

SA82 0 1 0 1 0 0 1 0 64/32 520000–52FFFF 290000–297FFF

SA83 0 1 0 1 0 0 1 1 64/32 530000–53FFFF 298000–29FFFF

SA84 0 1 0 1 0 1 0 0 64/32 540000–54FFFF 2A0000–2A7FFF

SA85 0 1 0 1 0 1 0 1 64/32 550000–55FFFF 2A8000–2AFFFF

SA86 0 1 0 1 0 1 1 0 64/32 560000–56FFFF 2B0000–2B7FFF

SA87 0 1 0 1 0 1 1 1 64/32 570000–57FFFF 2B8000–2BFFFF

SA88 0 1 0 1 1 0 0 0 64/32 580000–58FFFF 2C0000–2C7FFF

SA89 0 1 0 1 1 0 0 1 64/32 590000–59FFFF 2C8000–2CFFFF

SA90 0 1 0 1 1 0 1 0 64/32 5A0000–5AFFFF 2D0000–2D7FFF

SA91 0 1 0 1 1 0 1 1 64/32 5B0000–5BFFFF 2D8000–2DFFFF

SA92 0 1 0 1 1 1 0 0 64/32 5C0000–5CFFFF 2E0000–2E7FFF

SA93 0 1 0 1 1 1 0 1 64/32 5D0000–5DFFFF 2E8000–2EFFFF

SA94 0 1 0 1 1 1 1 0 64/32 5E0000–5EFFFF 2F0000–2F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 15

DATA SHEET

Table 2. Sector Address Table (Sheet 3 of 6)

Sector A22–A15

SA95 0 1 0 1 1 1 1 1 64/32 5F0000–5FFFFF 2F8000–2FFFFF

SA96 0 1 1 0 0 0 0 0 64/32 600000–60FFFF 300000–307FFF

SA97 0 1 1 0 0 0 0 1 64/32 610000–61FFFF 308000–30FFFF

SA98 0 1 1 0 0 0 1 0 64/32 620000–62FFFF 310000–317FFF

SA99 0 1 1 0 0 0 1 1 64/32 630000–63FFFF 318000–31FFFF

SA100 0 1 1 0 0 1 0 0 64/32 640000–64FFFF 320000–327FFF

SA101 0 1 1 0 0 1 0 1 64/32 650000–65FFFF 328000–32FFFF

SA102 0 1 1 0 0 1 1 0 64/32 660000–66FFFF 330000–337FFF

SA103 0 1 1 0 0 1 1 1 64/32 670000–67FFFF 338000–33FFFF

SA104 0 1 1 0 1 0 0 0 64/32 680000–68FFFF 340000–347FFF

SA105 0 1 1 0 1 0 0 1 64/32 690000–69FFFF 348000–34FFFF

SA106 0 1 1 0 1 0 1 0 64/32 6A0000–6AFFFF 350000–357FFF

SA107 0 1 1 0 1 0 1 1 64/32 6B0000–6BFFFF 358000–35FFFF

SA108 0 1 1 0 1 1 0 0 64/32 6C0000–6CFFFF 360000–367FFF

SA109 0 1 1 0 1 1 0 1 64/32 6D0000–6DFFFF 368000–36FFFF

SA110 0 1 1 0 1 1 1 0 64/32 6E0000–6EFFFF 370000–377FFF

SA111 0 1 1 0 1 1 1 1 64/32 6F0000–6FFFFF 378000–37FFFF

SA112 0 1 1 1 0 0 0 0 64/32 700000–70FFFF 380000–387FFF

SA113 0 1 1 1 0 0 0 1 64/32 710000–71FFFF 388000–38FFFF

SA114 0 1 1 1 0 0 1 0 64/32 720000–72FFFF 390000–397FFF

SA115 0 1 1 1 0 0 1 1 64/32 730000–73FFFF 398000–39FFFF

SA116 0 1 1 1 0 1 0 0 64/32 740000–74FFFF 3A0000–3A7FFF

SA117 0 1 1 1 0 1 0 1 64/32 750000–75FFFF 3A8000–3AFFFF

SA118 0 1 1 1 0 1 1 0 64/32 760000–76FFFF 3B0000–3B7FFF

SA119 0 1 1 1 0 1 1 1 64/32 770000–77FFFF 3B8000–3BFFFF

SA120 0 1 1 1 1 0 0 0 64/32 780000–78FFFF 3C0000–3C7FFF

SA121 0 1 1 1 1 0 0 1 64/32 790000–79FFFF 3C8000–3CFFFF

SA122 0 1 1 1 1 0 1 0 64/32 7A0000–7AFFFF 3D0000–3D7FFF

SA123 0 1 1 1 1 0 1 1 64/32 7B0000–7BFFFF 3D8000–3DFFFF

SA124 0 1 1 1 1 1 0 0 64/32 7C0000–7CFFFF 3E0000–3E7FFF

SA125 0 1 1 1 1 1 0 1 64/32 7D0000–7DFFFF 3E8000–3EFFFF

SA126 0 1 1 1 1 1 1 0 64/32 7E0000–7EFFFF 3F0000–3F7FFF

SA127 0 1 1 1 1 1 1 1 64/32 7F0000–7FFFFF 3F8000–3FFFFF

SA128 1 0 0 0 0 0 0 0 64/32 800000–80FFFF 400000–407FFF

SA129 1 0 0 0 0 0 0 1 64/32 810000–81FFFF 408000–40FFFF

SA130 1 0 0 0 0 0 1 0 64/32 820000–82FFFF 410000–417FFF

SA131 1 0 0 0 0 0 1 1 64/32 830000–83FFFF 418000–41FFFF

SA132 1 0 0 0 0 1 0 0 64/32 840000–84FFFF 420000–427FFF

SA133 1 0 0 0 0 1 0 1 64/32 850000–85FFFF 428000–42FFFF

SA134 1 0 0 0 0 1 1 0 64/32 860000–86FFFF 430000–437FFF

SA135 1 0 0 0 0 1 1 1 64/32 870000–87FFFF 438000–43FFFF

SA136 1 0 0 0 1 0 0 0 64/32 880000–88FFFF 440000–447FFF

SA137 1 0 0 0 1 0 0 1 64/32 890000–89FFFF 448000–44FFFF

SA138 1 0 0 0 1 0 1 0 64/32 8A0000–8AFFFF 450000–457FFF

SA139 1 0 0 0 1 0 1 1 64/32 8B0000–8BFFFF 458000–45FFFF

SA140 1 0 0 0 1 1 0 0 64/32 8C0000–8CFFFF 460000–467FFF

SA141 1 0 0 0 1 1 0 1 64/32 8D0000–8DFFFF 468000–46FFFF

SA142 1 0 0 0 1 1 1 0 64/32 8E0000–8EFFFF 470000–477FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

16 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

Table 2. Sector Address Table (Sheet 4 of 6)

Sector A22–A15

SA143 1 0 0 0 1 1 1 1 64/32 8F0000–8FFFFF 478000–47FFFF

SA144 1 0 0 1 0 0 0 0 64/32 900000–90FFFF 480000–487FFF

SA145 1 0 0 1 0 0 0 1 64/32 910000–91FFFF 488000–48FFFF

SA146 1 0 0 1 0 0 1 0 64/32 920000–92FFFF 490000–497FFF

SA147 1 0 0 1 0 0 1 1 64/32 930000–93FFFF 498000–49FFFF

SA148 1 0 0 1 0 1 0 0 64/32 940000–94FFFF 4A0000–4A7FFF

SA149 1 0 0 1 0 1 0 1 64/32 950000–95FFFF 4A8000–4AFFFF

SA150 1 0 0 1 0 1 1 0 64/32 960000–96FFFF 4B0000–4B7FFF

SA151 1 0 0 1 0 1 1 1 64/32 970000–97FFFF 4B8000–4BFFFF

SA152 1 0 0 1 1 0 0 0 64/32 980000–98FFFF 4C0000–4C7FFF

SA153 1 0 0 1 1 0 0 1 64/32 990000–99FFFF 4C8000–4CFFFF

SA154 1 0 0 1 1 0 1 0 64/32 9A0000–9AFFFF 4D0000–4D7FFF

SA155 1 0 0 1 1 0 1 1 64/32 9B0000–9BFFFF 4D8000–4DFFFF

SA156 1 0 0 1 1 1 0 0 64/32 9C0000–9CFFFF 4E0000–4E7FFF

SA157 1 0 0 1 1 1 0 1 64/32 9D0000–9DFFFF 4E8000–4EFFFF

SA158 1 0 0 1 1 1 1 0 64/32 9E0000–9EFFFF 4F0000–4F7FFF

SA159 1 0 0 1 1 1 1 1 64/32 9F0000–9FFFFF 4F8000–4FFFFF

SA160 1 0 1 0 0 0 0 0 64/32 A00000–A0FFFF 500000–507FFF

SA161 1 0 1 0 0 0 0 1 64/32 A10000–A1FFFF 508000–50FFFF

SA162 1 0 1 0 0 0 1 0 64/32 A20000–A2FFFF 510000–517FFF

SA163 1 0 1 0 0 0 1 1 64/32 A30000–A3FFFF 518000–51FFFF

SA164 1 0 1 0 0 1 0 0 64/32 A40000–A4FFFF 520000–527FFF

SA165 1 0 1 0 0 1 0 1 64/32 A50000–A5FFFF 528000–52FFFF

SA166 1 0 1 0 0 1 1 0 64/32 A60000–A6FFFF 530000–537FFF

SA167 1 0 1 0 0 1 1 1 64/32 A70000–A7FFFF 538000–53FFFF

SA168 1 0 1 0 1 0 0 0 64/32 A80000–A8FFFF 540000–547FFF

SA169 1 0 1 0 1 0 0 1 64/32 A90000–A9FFFF 548000–54FFFF

SA170 1 0 1 0 1 0 1 0 64/32 AA0000–AAFFFF 550000–557FFF

SA171 1 0 1 0 1 0 1 1 64/32 AB0000–ABFFFF 558000–55FFFF

SA172 1 0 1 0 1 1 0 0 64/32 AC0000–ACFFFF 560000–567FFF

SA173 1 0 1 0 1 1 0 1 64/32 AD0000–ADFFFF 568000–56FFFF

SA174 1 0 1 0 1 1 1 0 64/32 AE0000–AEFFFF 570000–577FFF

SA175 1 0 1 0 1 1 1 1 64/32 AF0000–AFFFFF 578000–57FFFF

SA176 1 0 1 1 0 0 0 0 64/32 B00000–B0FFFF 580000–587FFF

SA177 1 0 1 1 0 0 0 1 64/32 B10000–B1FFFF 588000–58FFFF

SA178 1 0 1 1 0 0 1 0 64/32 B20000–B2FFFF 590000–597FFF

SA179 1 0 1 1 0 0 1 1 64/32 B30000–B3FFFF 598000–59FFFF

SA180 1 0 1 1 0 1 0 0 64/32 B40000–B4FFFF 5A0000–5A7FFF

SA181 1 0 1 1 0 1 0 1 64/32 B50000–B5FFFF 5A8000–5AFFFF

SA182 1 0 1 1 0 1 1 0 64/32 B60000–B6FFFF 5B0000–5B7FFF

SA183 1 0 1 1 0 1 1 1 64/32 B70000–B7FFFF 5B8000–5BFFFF

SA184 1 0 1 1 1 0 0 0 64/32 B80000–B8FFFF 5C0000–5C7FFF

SA185 1 0 1 1 1 0 0 1 64/32 B90000–B9FFFF 5C8000–5CFFFF

SA186 1 0 1 1 1 0 1 0 64/32 BA0000–BAFFFF 5D0000–5D7FFF

SA187 1 0 1 1 1 0 1 1 64/32 BB0000–BBFFFF 5D8000–5DFFFF

SA188 1 0 1 1 1 1 0 0 64/32 BC0000–BCFFFF 5E0000–5E7FFF

SA189 1 0 1 1 1 1 0 1 64/32 BD0000–BDFFFF 5E8000–5EFFFF

SA190 1 0 1 1 1 1 1 0 64/32 BE0000–BEFFFF 5F0000–5F7FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 17

DATA SHEET

Table 2. Sector Address Table (Sheet 5 of 6)

Sector A22–A15

SA191 1 0 1 1 1 1 1 1 64/32 BF0000–BFFFFF 5F8000–5FFFFF

SA192 1 1 0 0 0 0 0 0 64/32 C00000–C0FFFF 600000–607FFF

SA193 1 1 0 0 0 0 0 1 64/32 C10000–C1FFFF 608000–60FFFF

SA194 1 1 0 0 0 0 1 0 64/32 C20000–C2FFFF 610000–617FFF

SA195 1 1 0 0 0 0 1 1 64/32 C30000–C3FFFF 618000–61FFFF

SA196 1 1 0 0 0 1 0 0 64/32 C40000–C4FFFF 620000–627FFF

SA197 1 1 0 0 0 1 0 1 64/32 C50000–C5FFFF 628000–62FFFF

SA198 1 1 0 0 0 1 1 0 64/32 C60000–C6FFFF 630000–637FFF

SA199 1 1 0 0 0 1 1 1 64/32 C70000–C7FFFF 638000–63FFFF

SA200 1 1 0 0 1 0 0 0 64/32 C80000–C8FFFF 640000–647FFF

SA201 1 1 0 0 1 0 0 1 64/32 C90000–C9FFFF 648000–64FFFF

SA202 1 1 0 0 1 0 1 0 64/32 CA0000–CAFFFF 650000–657FFF

SA203 1 1 0 0 1 0 1 1 64/32 CB0000–CBFFFF 658000–65FFFF

SA204 1 1 0 0 1 1 0 0 64/32 CC0000–CCFFFF 660000–667FFF

SA205 1 1 0 0 1 1 0 1 64/32 CD0000–CDFFFF 668000–66FFFF

SA206 1 1 0 0 1 1 1 0 64/32 CE0000–CEFFFF 670000–677FFF

SA207 1 1 0 0 1 1 1 1 64/32 CF0000–CFFFFF 678000–67FFFF

SA208 1 1 0 1 0 0 0 0 64/32 D00000–D0FFFF 680000–687FFF

SA209 1 1 0 1 0 0 0 1 64/32 D10000–D1FFFF 688000–68FFFF

SA210 1 1 0 1 0 0 1 0 64/32 D20000–D2FFFF 690000–697FFF

SA211 1 1 0 1 0 0 1 1 64/32 D30000–D3FFFF 698000–69FFFF

SA212 1 1 0 1 0 1 0 0 64/32 D40000–D4FFFF 6A0000–6A7FFF

SA213 1 1 0 1 0 1 0 1 64/32 D50000–D5FFFF 6A8000–6AFFFF

SA214 1 1 0 1 0 1 1 0 64/32 D60000–D6FFFF 6B0000–6B7FFF

SA215 1 1 0 1 0 1 1 1 64/32 D70000–D7FFFF 6B8000–6BFFFF

SA216 1 1 0 1 1 0 0 0 64/32 D80000–D8FFFF 6C0000–6C7FFF

SA217 1 1 0 1 1 0 0 1 64/32 D90000–D9FFFF 6C8000–6CFFFF

SA218 1 1 0 1 1 0 1 0 64/32 DA0000–DAFFFF 6D0000–6D7FFF

SA219 1 1 0 1 1 0 1 1 64/32 DB0000–DBFFFF 6D8000–6DFFFF

SA220 1 1 0 1 1 1 0 0 64/32 DC0000–DCFFFF 6E0000–6E7FFF

SA221 1 1 0 1 1 1 0 1 64/32 DD0000–DDFFFF 6E8000–6EFFFF

SA222 1 1 0 1 1 1 1 0 64/32 DE0000–DEFFFF 6F0000–6F7FFF

SA223 1 1 0 1 1 1 1 1 64/32 DF0000–DFFFFF 6F8000–6FFFFF

SA224 1 1 1 0 0 0 0 0 64/32 E00000–E0FFFF 700000–707FFF

SA225 1 1 1 0 0 0 0 1 64/32 E10000–E1FFFF 708000–70FFFF

SA226 1 1 1 0 0 0 1 0 64/32 E20000–E2FFFF 710000–717FFF

SA227 1 1 1 0 0 0 1 1 64/32 E30000–E3FFFF 718000–71FFFF

SA228 1 1 1 0 0 1 0 0 64/32 E40000–E4FFFF 720000–727FFF

SA229 1 1 1 0 0 1 0 1 64/32 E50000–E5FFFF 728000–72FFFF

SA230 1 1 1 0 0 1 1 0 64/32 E60000–E6FFFF 730000–737FFF

SA231 1 1 1 0 0 1 1 1 64/32 E70000–E7FFFF 738000–73FFFF

SA232 1 1 1 0 1 0 0 0 64/32 E80000–E8FFFF 740000–747FFF

SA233 1 1 1 0 1 0 0 1 64/32 E90000–E9FFFF 748000–74FFFF

SA234 1 1 1 0 1 0 1 0 64/32 EA0000–EAFFFF 750000–757FFF

SA235 1 1 1 0 1 0 1 1 64/32 EB0000–EBFFFF 758000–75FFFF

SA236 1 1 1 0 1 1 0 0 64/32 EC0000–ECFFFF 760000–767FFF

SA237 1 1 1 0 1 1 0 1 64/32 ED0000–EDFFFF 768000–76FFFF

SA238 1 1 1 0 1 1 1 0 64/32 EE0000–EEFFFF 770000–777FFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

18 Am29LV128MH/L 25270C7 January 31, 2007

DATA SHEET

Table 2. Sector Address Table (Sheet 6 of 6)

Sector A22–A15

SA239 1 1 1 0 1 1 1 1 64/32 EF0000–EFFFFF 778000–77FFFF

SA240 1 1 1 1 0 0 0 0 64/32 F00000–F0FFFF 780000–787FFF

SA241 1 1 1 1 0 0 0 1 64/32 F10000–F1FFFF 788000–78FFFF

SA242 1 1 1 1 0 0 1 0 64/32 F20000–F2FFFF 790000–797FFF

SA243 1 1 1 1 0 0 1 1 64/32 F30000–F3FFFF 798000–79FFFF

SA244 1 1 1 1 0 1 0 0 64/32 F40000–F4FFFF 7A0000–7A7FFF

SA245 1 1 1 1 0 1 0 1 64/32 F50000–F5FFFF 7A8000–7AFFFF

SA246 1 1 1 1 0 1 1 0 64/32 F60000–F6FFFF 7B0000–7B7FFF

SA247 1 1 1 1 0 1 1 1 64/32 F70000–F7FFFF 7B8000–7BFFFF

SA248 1 1 1 1 1 0 0 0 64/32 F80000–F8FFFF 7C0000–7C7FFF

SA249 1 1 1 1 1 0 0 1 64/32 F90000–F9FFFF 7C8000–7CFFFF

SA250 1 1 1 1 1 0 1 0 64/32 FA0000–FAFFFF 7D0000–7D7FFF

SA251 1 1 1 1 1 0 1 1 64/32 FB0000–FBFFFF 7D8000–7DFFFF

SA252 1 1 1 1 1 1 0 0 64/32 FC0000–FCFFFF 7E0000–7E7FFF

SA253 1 1 1 1 1 1 0 1 64/32 FD0000–FDFFFF 7E8000–7EFFFF

SA254 1 1 1 1 1 1 1 0 64/32 FE0000–FEFFFF 7F0000–7F7FFF

SA255 1 1 1 1 1 1 1 1 64/32 FF0000–FFFFFF 7F8000–7FFFFF

Sector Size

(Kbytes/Kwords)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

January 31, 2007 25270C7 Am29LV128MH/L 19

DATA SHEET

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector group protection verifica­tion, through identifier codes output on DQ7–DQ0.
This mode is primarily intended for programming
equipment to automatically match a device to be pro­grammed with its corresponding programming algo­rithm. However, the autoselect codes can also be
accessed in-system through the command register.

When using programming equipment, the autoselect
mode requires V
A6, A3, A2, A1, and A0 must be as shown in Tab l e 3 In
addition, when verifying sector protection, the sector

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X

Cycle 1

Cycle 2 H H L 22 X 12h

Device ID

Cycle 3 H H H 22 X 00h

Sector Group
Protection Verification

Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects highest
address sector

Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects lowest
address sector

on address pin A9. Address pins

ID

Table 3. Autoselect Codes, (High Voltage Method)

A14

A22

to

to

A15

LLHXX

LLHSAX

LLHXX

LLHXX

A9A8toA7A6A5to

A10

V

ID

V

ID

V

ID

V

ID

V

ID

X L X L L L 00 X 01h

XL X

XL X L H L X X

XL X L H H X X

XL X L H H X X

address must appear on the appropriate highest order
address bits (see Ta bl e 2 ). Tab le 3 shows the remain­ing address bits that are don’t care. When all neces­sary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Ta bl e 1 0 and Tab le 1 1.
This method does not require V

. See “Autoselect

ID

Command Sequence” on page 29 for more informa-

tion.

A3

toA2A1 A0

A4

LLH 22 X 7Eh

DQ8 to DQ15

BYTE#

= V

BYTE#

IH

= V

IL

00h (unprotected)

98h (factory locked),

18h (not factory locked)

88h (factory locked),

08h (not factory locked)

DQ7 to DQ0

01h (protected),

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

20 Am29LV128MH/L 25270C7 January 31, 2007