AMD Advanced Micro Devices AM29LV081B-80FIB, AM29LV081B-80FI, AM29LV081B-80FEB, AM29LV081B-80FE, AM29LV081B-80FCB Datasheet
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ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice.
Publication# 21525 Rev: A Amendment/0
Issue Date: January 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV081B
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-onl y Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Optimized architecture for Miniature Card and
mass storage applications
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage r ange: 3.0 to 3.6 v olt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29LV081 device
■ High performance
— Full voltage range: ac cess times as f ast as 80 ns
— Regulated voltage range: access times as fast
as 70 ns
■ Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■ Flexible sector architecture
— Sixteen 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
T emporary Sector Unprotect feature allo ws code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ Package option
— 40-pin TSOP
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the de vice t o reading
array data
2 Am29LV081B
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29LV081B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
a single, 3.0 volt V
CC
supply to perform read, program,
and erase operations. A stand ard EPROM programmer can also be used to program and erase the
device.
This device is manufactured usin g AMD’s 0.35 µm
process technology, and offers all the f eatures an d benefits of the Am29L V081, which was manufactur ed using
0.5 µm process technology. In addition, the
Am29LV081B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait s tates. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls .
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set c ompatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two
write cycles to program data instead of four.
Device erasure occurs by ex ecuting the erase command
sequence. This initiates the Embedded Erase algorithm—an i nternal algorithm that autom atically prepro grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector er ase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power tran sitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achiev ed.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offer s two power-sa ving f eatures. When addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
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