AMD Advanced Micro Devices AM29LV081-100FC, AM29LV081-100EIB, AM29LV081-100EI, AM29LV081-100EEB, AM29LV081-100EE Datasheet

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PRELIMINARY

Am29LV081

8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Optimized architecture for Miniature Card and

mass storage applications

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage r ange: 3.0 to 3.6 v olt read and

write operations and for compatibility with high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

— Regulated voltage range: access times as fast

as 90 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 10 mA read current — 20 mA program/erase current

■ Flexible sector architecture

— Sixteen 64 Kbyte sectors — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector (using programming equipment) to prevent any program or erase operations within that sector

T emporary Sector Unprotect feat ure allows code changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Typ ical 1,000,000 write cycles per sector

(100,000 cycles minimu m guaranteed)

■ Package option

— 40-pin TSOP

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the de vi ce to reading

array data

Publication# 20977 Rev: C Amendment/+1 Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV081 is a n 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes. The device is offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V and erase operations. A stand ard EPROM programmer can also be used to program and erase the device.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wai t states . To eliminate b us c ontention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup- ply for both read and wr ite functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microproc essor write timing s. Register contents serve as input to an internal sta te-machine that co ntrols the erase and programming circuit ry. Write cycles also internally latch addresses and data needed f or the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by ex ecuting the erase command sequence. This initiates the Embedded Erase algorithm—an i nternal algorithm that autom atically prepro grams the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

supply to perform read, program,

The host system can detect whether a program or erase operation is complete by obser ving the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase archite cture allo ws m emory sect ors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measur es include a low

detector that automatically in hibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operations in any combination of the sectors of memory. This is achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any s ector that is not selected for erasure. True background erase can thus be achie ved.

The hardware RESET# pi n terminates any operation in progress and resets the internal state machine to reading array dat a. The RESET# pin ma y be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When addresses have been stable for a specified amount of time, the device enters the automatic sleep m ode. The system can also place the de vice into the standby mode. Power consump tion is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing exper ience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bit s with in a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29LV081

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV081

Speed Options

Max access time, ns (t Max CE# access time, ns (tCE) 90 100 120 150 Max OE# access time, ns (tOE) 40 40 50 55

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

) 90 100 120 150

ACC

Note: See “AC Characte r ist ics ” for full specifications.

BLOCK DIAGRAM

DQ0

DQ7

–

Input/Output

Buffers

Data

RESET#

WE#

CE#

OE#

RY/BY#

State

Control

Command

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

STB

A0–A19

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

20977C-1

Am29LV081 3

CONNECTION DIAGRAMS

PRELIMINARY

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RESET#

RY/BY#

A18

A7 A6 A5 A4 A3 A2 A1

A17 V

NC A19 A10

DQ7 DQ6 DQ5 DQ4

DQ3 DQ2 DQ1 DQ0

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Standard TSOP

Reverse TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17 V

NC A19 A10 DQ7 DQ6 DQ5 DQ4 V

NC DQ3 DQ2 DQ1 DQ0 OE#

CE# A0

A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1

4 Am29LV081

20977C-2

PRELIMINARY

PIN CONFIGURATION

A0–A19 = 20 addresses DQ0–DQ7 = 8 data inputs/outputs CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

NC = Pin not connected internally

(see Product Selector Guide for speed options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

A0–A19

CE# OE#

WE# RESET#

DQ0–DQ7

RY/BY#

20977C-3

Am29LV081 5

PRELIMINARY

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE-90RAm29LV081

OPTIONAL PROCESSING

Blank = Standa rd Pro ces sin g B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

Am29LV081-90R V

= 3.0–3.6 V

Am29LV081-100 Am29LV081-120 Am29LV081-150

Valid Combinations

EC, EI, FC, FI

EC, EI, EE,

FC, FI, FE

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV081 8 Megabit (1 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

6 Am29LV081

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the commands, along with the address and data information needed to execute the command. The contents of

Table 1. Am29LV081 Device Bus Operations

Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7

Read L L H H A Write L H L H A

Standby Output Disable L H H H X High-Z

Reset X X X L X High-Z Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: Addresses are A19–A0.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

VCC ±

0.3 V

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control lev els t he y requ ire , and t he resulting output. The following subsections describe each of these operations in further detail.

= Data Out

OUT

VCC ±

0.3 V

IN IN

X High-Z

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output control and gates arra y data to the output pins . WE# should remain at V

The internal state machi ne is set for reading array data upon de vic e power-up, or after a har dw ar e res et. This ensures that no spurious alteration of the memory content occurs duri ng the power transition. No command is necessar y in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the de vice addr ess inputs produce valid da ta on the de vice da ta outputs . The de vice remains enabled for read access until the c ommand register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 12 for the timing diagram. I

CC1

the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

An erase operation can erase one sect or, multiple sectors, or the entire de v ice. Tabl e 2 indicat es the address

, and OE# to VIH.

space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a se ctor or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I

read specifica tions apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device , it can place the device in the standby mode. In this mode, current consumption is gr eatly reduced, and the

Am29LV081 7

PRELIMINARY

outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pin s are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

± 0.3 V, the device will be in the stan dby mode, but

the standby current will be greater. The device requires standard access time (t

) for read access whe n the

device is in either of these st andby modes, before it is ready to read data.

If the device is deselected during erasure or program ming, the device draws active current until the operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specifications.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de vice automatically enab les this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard addres s access timings provide new data when address es are changed. While in sleep mode, output data is latched and always available to the system. I

in the DC

CC5

Characteristics table represents the autom atic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of resetting the device to readi ng arr ay data. When the system drives the RESET# pin to V the device immediately terminates any operation in

for at least a p eriod of tRP,

progress, tristates all data output pins, and ignores all read/write attempts for the duration o f the RESET# pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset oper ation is c omplete . If RESE T# is asserted when a program or erase oper ation is not e xecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin returns to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in t he high impedance state.

8 Am29LV081

PRELIMINARY

Table 2. Am29LV081 Sector Address Table

A19 A18 A17 A16 A15 A14 A13 Sector Size Address Range

SA00000XXX 64 Kbytes 00000h-0FFFFh SA10001XXX 64 Kbytes 10000h-1FFFFh SA20010XXX 64 Kbytes 20000h-2FFFFh SA30011XXX 64 Kbytes 30000h-3FFFFh SA40100XXX 64 Kbytes 40000h-4FFFFh SA50101XXX 64 Kbytes 50000h-5FFFFh SA60110XXX 64 Kbytes 60000h-6FFFFh SA70111XXX 64 Kbytes 70000h-7FFFFh SA81000XXX 64 Kbytes 80000h-8FFFFh

SA91001XXX 64 Kbytes 90000h-9FFFFh SA101010XXX 64 Kbytes A0000h-AFFFFh SA111011XXX 64 Kbytes B0000h-BFFFFh SA121100XXX 64 Kbytes C0000h-CFFFFh SA131101XXX 64 Kbytes D0000h-DFFFFh SA141110XXX 64 Kbytes E0000h-EFFFFh SA151111XXX 64 Kbytes F0000h-FFFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for progr amming equipment to automatically match a device to be progr ammed with its correspondi ng programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V

(11.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in Table

3. In addition, when verifying sector protection, the sec-

Table 3. Am29LV081 Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V Device ID: Am29LV081 L L H X X V

Sector Protection Verification L L H SA X V

tor address must appear on the appr opriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via th e command register, as shown in Table 4. This method does not require V

. See “Command Definitions” for

details on using the autoselect mode.

A19

A13

A12

A10 A9

A7 A6

XLXLL 01h

XLXLH 38h

XLXHL

A2 A1 A0

(protected)

(unprotected)

DQ7

DQ0

01h

00h

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Am29LV081 9

PRELIMINARY

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection must be implemented using programming equipment.The procedure requires a high voltage (V

) on address pin A9 and OE#. De-

tails on this method are pro vided in a supplement, publication number 21225. Contact an AMD representative to request a copy.

Temporary Sector Unprotect

This feature allows temporary unpr otection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V

. During this mode, formerly protected

sectors can be programmed or erased by sele cting the sector addresses. Once V

is removed from the RE-

SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 19 shows the timing diagrams, for this feature.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent wri tes (refer to Table 4 for command definitions). In additio n, the following hardware data protection mea sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V power-down transitions, or from system noise.

power-up and

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = VIH or WE# = VIH. To initiate a write c y-

cle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up W rite Inhibit

If WE# = CE# = V

and OE# = VIH during powe r

up, the device does not accept commands on the rising edge of WE#. The inter nal state machine is automatically reset to reading array data on power-up.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

20977C-4

Figure 1. Temporary Sector Unprotect Operation

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

10 Am29LV081

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or sequences into the command register initiates device operations. Table 4 defi nes the valid register co mmand sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after comp leting an Embe dded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, exc ept that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

must

The system able the dev ice f or reading arra y data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Arr a y Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 12 shows the timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, t he reset c ommand be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

See the applicable “AC Characteristics” section for parameters, and to the F igu re 1 3 f or the timing wav eforms.

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. T ab le 4 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requi res V on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect m ode, and the system may read at any address any number of times, without initiating anot her command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h i n it, ret urns 01h if that sec tor is protected, or 00h if it is unprotected. Refer to Table 2 for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-u p command. The program address and data are w ritten next, which in turn initiate the Embedded Program al-

not

gorithm. The system is controls or timings. The device automatically provides internally generated program pulses and v erify the programmed cell margin. Table 4 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation b y using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

Any commands written to the dev ice during the Embedded Program Algorithm are ignored. Note that a

required to provide further

Am29LV081 11

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