AMD Advanced Micro Devices AM29LV081-100FC, AM29LV081-100EIB, AM29LV081-100EI, AM29LV081-100EEB, AM29LV081-100EE Datasheet

PRELIMINARY

Am29LV081

8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Optimized architecture for Miniature Card and

mass storage applications

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage r ange: 3.0 to 3.6 v olt read and

write operations and for compatibility with high
performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

ns

— Regulated voltage range: access times as fast

as 90 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— 20 mA program/erase current

■ Flexible sector architecture

— Sixteen 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector (using
programming equipment) to prevent any
program or erase operations within that sector

T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Typ ical 1,000,000 write cycles per sector

(100,000 cycles minimu m guaranteed)

■ Package option

— 40-pin TSOP

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the de vi ce to reading

array data

Publication# 20977 Rev: C Amendment/+1
Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV081 is a n 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. This device requires only
a single, 3.0 volt V
and erase operations. A stand ard EPROM pro­grammer can also be used to program and erase the
device.

The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wai t states . To eliminate b us c onten­tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and wr ite functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co n­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by ex ecuting the erase command
sequence. This initiates the Embedded Erase algo­rithm—an i nternal algorithm that autom atically prepro ­grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.

supply to perform read, program,

CC

The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measur es include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This is achieved via programming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any s ector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consump tion is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing exper ience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bit s with in
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

2 Am29LV081

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV081

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 90 100 120 150
Max OE# access time, ns (tOE) 40 40 50 55

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

) 90 100 120 150

ACC

Note: See “AC Characte r ist ics ” for full specifications.

BLOCK DIAGRAM

DQ0

DQ7

–

Input/Output

Buffers

Data

V

CC

V

SS

RESET#

WE#

CE#

OE#

RY/BY#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

STB

A0–A19

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

20977C-1

Am29LV081 3

CONNECTION DIAGRAMS

PRELIMINARY

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

A18

A7
A6
A5
A4
A3
A2
A1

A17
V

SS

NC
A19
A10

DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC

DQ3
DQ2
DQ1
DQ0

CE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Standard TSOP

Reverse TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A17
V

SS

NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
OE#

V

SS

CE#
A0

A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1

4 Am29LV081

20977C-2

PRELIMINARY

PIN CONFIGURATION

A0–A19 = 20 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed
options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

20

A0–A19

CE#
OE#

WE#
RESET#

8

DQ0–DQ7

RY/BY#

20977C-3

Am29LV081 5

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE-90RAm29LV081

OPTIONAL PROCESSING

Blank = Standa rd Pro ces sin g
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

Am29LV081-90R
V

= 3.0–3.6 V

CC

Am29LV081-100
Am29LV081-120
Am29LV081-150

Valid Combinations

EC, EI, FC, FI

EC, EI, EE,

FC, FI, FE

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV081
8 Megabit (1 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

6 Am29LV081

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29LV081 Device Bus Operations

Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7

Read L L H H A
Write L H L H A

Standby
Output Disable L H H H X High-Z

Reset X X X L X High-Z
Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: Addresses are A19–A0.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

VCC ±

0.3 V

XX

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.

D

D

= Data Out

OUT

OUT

VCC ±

0.3 V

ID

IN
IN

X High-Z

XX

IN

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output con­trol and gates arra y data to the output pins . WE# should
remain at V

.

IH

The internal state machi ne is set for reading array
data upon de vic e power-up, or after a har dw ar e res et.
This ensures that no spurious alteration of the mem­ory content occurs duri ng the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the de vice addr ess inputs pro­duce valid da ta on the de vice da ta outputs . The de vice
remains enabled for read access until the c ommand
register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 12 for the timing diagram. I

CC1

in

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

An erase operation can erase one sect or, multiple sec­tors, or the entire de v ice. Tabl e 2 indicat es the address

, and OE# to VIH.

IL

space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. See the “Command Definitions” section for
details on erasing a se ctor or the entire chip, or sus­pending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifica tions apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is gr eatly reduced, and the

Am29LV081 7

PRELIMINARY

outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V

CC

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

V

IH

± 0.3 V, the device will be in the stan dby mode, but

V

CC

the standby current will be greater. The device requires
standard access time (t

) for read access whe n the

CE

device is in either of these st andby modes, before it is
ready to read data.

If the device is deselected during erasure or program ­ming, the device draws active current until the
operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specifications.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enab les
this mode when addresses remain stable for t

ACC

+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when address es are
changed. While in sleep mode, output data is latched
and always available to the system. I

in the DC

CC5

Characteristics table represents the autom atic sleep
mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system
drives the RESET# pin to V
the device immediately terminates any operation in

for at least a p eriod of tRP,

IL

progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine
whether the reset oper ation is c omplete . If RESE T# is
asserted when a program or erase oper ation is not e x­ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V

(not during Embed-

READY

.

IH

RH

after

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

8 Am29LV081

PRELIMINARY

Table 2. Am29LV081 Sector Address Table

A19 A18 A17 A16 A15 A14 A13 Sector Size Address Range

SA00000XXX 64 Kbytes 00000h-0FFFFh
SA10001XXX 64 Kbytes 10000h-1FFFFh
SA20010XXX 64 Kbytes 20000h-2FFFFh
SA30011XXX 64 Kbytes 30000h-3FFFFh
SA40100XXX 64 Kbytes 40000h-4FFFFh
SA50101XXX 64 Kbytes 50000h-5FFFFh
SA60110XXX 64 Kbytes 60000h-6FFFFh
SA70111XXX 64 Kbytes 70000h-7FFFFh
SA81000XXX 64 Kbytes 80000h-8FFFFh

SA91001XXX 64 Kbytes 90000h-9FFFFh
SA101010XXX 64 Kbytes A0000h-AFFFFh
SA111011XXX 64 Kbytes B0000h-BFFFFh
SA121100XXX 64 Kbytes C0000h-CFFFFh
SA131101XXX 64 Kbytes D0000h-DFFFFh
SA141110XXX 64 Kbytes E0000h-EFFFFh
SA151111XXX 64 Kbytes F0000h-FFFFFh

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin A9.

ID

Address pins A6, A1, and A0 must be as shown in Table

3. In addition, when verifying sector protection, the sec-

Table 3. Am29LV081 Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID: Am29LV081 L L H X X V

Sector Protection Verification L L H SA X V

tor address must appear on the appr opriate highest
order address bits (see Table 2). Table 3 shows the re­maining address bits that are don’t care. When all nec­essary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via th e
command register, as shown in Table 4. This method
does not require V

. See “Command Definitions” for

ID

details on using the autoselect mode.

A19

to

A13

A12

to

A10 A9

A8

to

A7 A6

XLXLL 01h

ID

XLXLH 38h

ID

XLXHL

ID

A5

to

A2 A1 A0

(protected)

(unprotected)

DQ7

to

DQ0

01h

00h

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Am29LV081 9

PRELIMINARY

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection must be implemented
using programming equipment.The procedure requires
a high voltage (V

) on address pin A9 and OE#. De-

ID

tails on this method are pro vided in a supplement, pub­lication number 21225. Contact an AMD representative
to request a copy.

Temporary Sector Unprotect

This feature allows temporary unpr otection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V

. During this mode, formerly protected

ID

sectors can be programmed or erased by sele cting the
sector addresses. Once V

is removed from the RE-

ID

SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing diagrams, for this feature.

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent wri tes (refer to Table 4 for com­mand definitions). In additio n, the following hardware
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.

power-up and

CC

Logical Inhibit

Write cycles are inhibited by holding any one of OE#
= V

, CE# = VIH or WE# = VIH. To initiate a write c y-

IL

cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up W rite Inhibit

If WE# = CE# = V

and OE# = VIH during powe r

IL

up, the device does not accept commands on the
rising edge of WE#. The inter nal state machine is
automatically reset to reading array data on
power-up.

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

ID

IH

20977C-4

Figure 1. Temporary Sector Unprotect Operation

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

10 Am29LV081

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. Table 4 defi nes the valid register co mmand
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, exc ept that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

must

The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Figure 12 shows the timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

See the applicable “AC Characteristics” section for pa­rameters, and to the F igu re 1 3 f or the timing wav eforms.

must

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 4 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requi res V
on address bit A9.

The autoselect command sequence is initiated by writ­ing two unlock cycles, followed by the autoselect com­mand. The device then enters the autoselect m ode,
and the system may read at any address any number
of times, without initiating anot her command sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h i n it, ret urns 01h if that sec ­tor is protected, or 00h if it is unprotected. Refer to
Table 2 for valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

ID

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-u p
command. The program address and data are w ritten
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. Table 4 shows the address and
data requirements for the byte program command se­quence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation b y using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

Any commands written to the dev ice during the Em­bedded Program Algorithm are ignored. Note that a

required to provide further

Am29LV081 11

PRELIMINARY

hardware reset immediately terminates the program-

ming operation. The program command sequenc e
should be reinitiated once the de vi ce has reset t o read­ing array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Figure 2 illustrates the algorithm for the program oper­ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 fo r
timing diagrams.

START

Write Program

Command Sequence

unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does

not

require the system to
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can determine the status of the erase op­eration by using DQ7, DQ6, DQ2, or RY/B Y#. See
“Write Operation Status” for information on these sta­tus bits. When the Embedded Erase algorithm is com­plete, the device returns to reading array data and
addresses are no longer latched.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Table 4 for program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

20977C-5

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements for the sector erase co mmand sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sector s. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase comm and is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the

require the system to preprogram

12 Am29LV081

PRELIMINARY

system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immediately ter m inates the op­eration. The Sector Erase command sequence s hould
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched. The system can determine the sta­tus of the erase operation b y usi ng DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa­tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 15 for timing diagrams.

if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more informa­tion.

The system may also write the autos elect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the devic e reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to in­terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately ter minates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the eras e
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure . (The devi ce “erase
suspends” all sectors selected fo r erasure.) Nor mal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See Table 4 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

20977C-6

Figure 3. Erase Operation

Am29LV081 13

PRELIMINARY

Table 4. Am29LV081 Command Definitions

Command

Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Auto­select
(Note 7)

Program 4 XXX AA XXX 55 XXX A0 PA PD
Chip Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 XXX 10
Sector Erase 6 XXX AA XXX 55 XXX 80 XXX AA XXX 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Manufacturer ID 4 XXX AA XXX 55 XXX 90 X00 01
Device ID 4 XXX AA XXX 55 XXX 90 X01 38

Sector Protect Verify
(Note 8)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

XXX

4

XXX XXX XXX 01

AA

XXX

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Bus Cycles (Notes 2-4)

55

XXX

90

(SA)

X02

00

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A13 uniquely select any sector.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles
are write operations.

4. All address bits are don’t cares for unlock and command
cycles, except when SA or PA required.

5. No unlock or command cycles required when reading array
data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).

7. The fourth cycle of the autoselect command sequence is a
read cycle.

8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.

9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

10. The Erase Resume command is valid only dur ing the Erase
Suspend mode.

14 Am29LV081

PRELIMINARY

WRITE OPERATION STATUS

The device provides s everal bits to deter mine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Tabl e 5 and the f ollo wing subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for deter mining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

Table 5 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com­pleted, or whether the dev ice is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se­quence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algor ithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

No

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 16, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.

Am29LV081 15

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

20977C-7

Figure 4. Data# Polling Algorithm

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 5 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 shows R Y/BY# for read, reset, program, and
erase operations, respectively.

CC

.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether a n Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the s ector erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cyc les to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

Table 5 shows the outputs for Toggle Bit I on DQ6.
Refer to Figure 5 f or the toggle bit alg orithm, and to the
Figure 17 in the “AC Characteristics” section for the
timing diagram. Figure 18 shows the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus ­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to c ompare output s
for DQ2 and DQ6.

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to Figure 17 f or the toggle bit timing diagr am. Fig­ure 18 shows the differenc es between DQ2 and DQ6 in
graphical form.

After an erase command sequence is written, if all s ec­tors selected for eras ing are protected , DQ6 toggles for

approximately 100 µs, then returns to readi ng array
data. If not all selected sectors are protected, the Em­bedded Erase algorithm erases the unprotected sec­tors, and ignores the selected sectors that are
protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. Whenever
the system initially begins rea ding toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com­pare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully c ompleted the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to readi ng
array data.

16 Am29LV081

PRELIMINARY

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform o ther
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

START

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

No

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” T his is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase o peration can

change a “0” back to a “1.” Under this condition, the
device halts the oper ation, and when the operatio n has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue

the reset command to return th e device to reading
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine w hether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0”
to “1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Erase Command Sequence” section.

After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has bee n
accepted, the system software should che ck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 5 shows the outputs for DQ3.

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

20977C-8

Figure 5. Toggle Bit Algorithm

Am29LV081 17

PRELIMINARY

Table 5. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

18 Am29LV081

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V

CC

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1) . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is V
During voltage transitions, input or I/O pins may overshoot
to V

+2.0 V for periods up to 20 ns. See Figure 7.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.

to –2.0 V for periods of up

SS

+0.5 V

CC

+0.5 V.

CC

SS

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

20977C-9

Figure 6. Maximum Negative Overshoot

Waveform\

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

20977C-10

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

VCC Supply Voltages

for regulated voltage range. . . . .+3.0 V to +3.6 V

V

CC

for full v oltage range. . . . . . . . . .+2.7 V to +3.6 V

V

CC

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

Am29LV081 19

PRELIMINARY

DC CHARACTERISTICS
CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

V

IN

V

= VCC

CC

= VSS to VCC,

V

OUT

V

= V

CC

CE# = V

max

; A9 = 12.5 V 35 µA

CC max

CC max

5 MHz 10 16

OE#

IL,

= VIH

1 MHz 2 4

±1.0 µA

±1.0 µA

I

I

I

CC1

I

LIT

LO

LI

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Note 1)

mA

V
V

V

I

CC2

I

CC3

I

CC4

I

CC5

V
V

V

V

IL

IH

ID

OL

OH1

OH2

LKO

VCC Active Write Current
(Notes 2 and 4)

VCC Standby Current

VCC Standby Current During Reset

Automatic Sleep Mode (Note 3)

Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and

Temporary Sector Unprotect
Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

CE# = V

VCC = V
CE#, RESET# = V

V

CC

RESET# = V
VIH = V

V

IL

V

CC

IOH = –2.0 mA, VCC = V
IOH = –100 µA, VCC = V

OE#

IL,

= VIH

;

= V

= V

CC max

CC max

CC

± 0.3 V

SS

SS

± 0.3 V;

CC

;

± 0.3 V

±0.3 V

= 3.3 V 11.5 12.5 V

0.45 V

CC min

0.85 V

CC min

VCC–0.4

CC min

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

CC

CC

ACC

20 30 mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

VCC + 0.3 V

V

+ 30 ns.

20 Am29LV081

PRELIMINARY

DC CHARACTERISTICS (Continued)
Zero Power Flash

25

20

15

10

Supply Current in mA

5

0

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 8. I

Current vs. Time (Showing Active an d Automatic Sleep Currents)

CC1

15

10

5

Supply Current in mA

0

1 2345

3

Frequency in MHz

V

6

.

V

7

2.

20977C-11

Note: T = 25 °C

Figure 9. Typical I

Am29LV081 21

vs. Frequency

CC1

20977C-12

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kΩ

PRELIMINARY

3.3 V

2.7 kΩ
Output Load 1 TTL gate

Output Load Capacitance, C
(including jig capacitance)

Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V

Table 6. Test Specifications

-90R,

Test Condition

-100

L

-120,

-150 Unit

30 100 pF

Note: Diodes are IN3064 or equivalent

Figure 10. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

20977C-13

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 V

1.5 V

KS000010-PAL

3.0 V

0.0 V

1.5 V 1.5 V

Figure 11. Input Waveforms and Measurement Levels

22 Am29LV081

OutputMeasurement LevelInput

20977C-14

AC CHARACTERISTICS
Read Operations

PRELIMINARY

Parameter

JEDEC Std Test Setup -90R -100 -120 -150 Unit

t

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

Read Cycle Time (Note 1) Min 90 100 120 150 ns

RC

t

Address to Output Delay

ACC

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 40 40 50 55 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 30 30 30 40 ns

DF

t

Output Enable to Output High Z (Note 1) Max 30 30 30 40 ns

DF

Description

CE# = V
OE# = V

IL

Max 90 100 120 150 ns

IL

Max 90 100 120 150 ns

IL

Speed Option

Read Min 0 ns

Output Enable

t

t

AXQX

OEH

Hold Time (Note 1)

Output Hold Time From Addresses, CE# or

t

OH

OE#, Whichever Occurs First (Note 1)

Toggle and
Data# Polling

Min 10 ns

Min 0 ns

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 6 for test specifications.

t

RC

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 12. Read Operations Timings

t

DF

t

OH

HIGH Z

20977C-15

Am29LV081 23

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

PRELIMINARY

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns

t

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RESET# Low to Standby Mode Min 20 µs

t

RPD

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 13. RESET# Timings

t

RB

20977C-16

24 Am29LV081

AC CHARACTERISTICS
Erase/Program Operations

Parameter

t

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

t

GHWL

Write Cycle Time (Note 1) Min 90 100 120 150 ns

WC

t

Address Setup Time Min 0 ns

AS

t

Address Hold Time Min 50 50 50 65 ns

AH

t

Data Setup Time Min 50 50 50 65 ns

DS

t

Data Hold Time Min 0 ns

DH

Output Enable Setup Time Min 0 ns

OES

Read Recovery Time Before Write
(OE# High to WE# Low)

PRELIMINARY

-90R -100 -120 -150JEDEC Std Description Unit

Min 0 ns

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1tWHWH1

t

WHWH2tWHWH2

t

CS

t

CH

t

WP

t

WPH

t

VCSVCC

t

RB

t

BUSY

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 50 50 50 65 ns
Write Pulse Width High Min 30 30 30 35 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 1 sec

Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29LV081 25

AC CHARACTERISTICS

PRELIMINARY

Addresses

CE#

OE#

WE#

Data

RY/BY#

V

CC

t

VCS

Program Command Sequence (last two cycles)

DH

t

AS

PA PA

t

AH

t

CH

t

WPH

PD

t

BUSY

t

WC

XXXh

t

GHWL

t

CS

t

WP

t

DS

t

A0h

Read Status Data (last two cycles)

PA

t

WHWH1

Status

D

OUT

t

RB

Note: PA = program address, PD = program data, D

Figure 14. Program Operation Timings

is the true data at the program address.

OUT

20977C-17

26 Am29LV081

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

PRELIMINARY

Addresses

CE#

OE#

WE#

Data

RY/BY#

V

CC

t

VCS

t

WC

XXXh SA

555h for chip erase

t

GHWL

t

CH

t

WP

t

t

CS

t

DS

t

WPH

DH

55h

t

AS

t

AH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

VA

In

Progress

VA

Complete

t

RB

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

20977C-18

Figure 15. Chip/Sector Erase Operation Timings

Am29LV081 27

AC CHARACTERISTICS

Z

Z

Addresses

t

ACC

CE#

t

CH

OE#

t

OEH

WE#

DQ7

PRELIMINARY

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

20977C-19

Figure 16. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: VA = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

20977C-20

Figure 17. Toggle Bit Timings (During Embedded Algorithms)

28 Am29LV081

PRELIMINARY

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.

Erase

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Figure 18. DQ2 vs. DQ6

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

Erase

20977C-21

t

VIDR

t

RSP

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

Unprotect

Min 4 µs

12 V

0 or 3 V

t

VIDR

t

VIDR

0 or 3 V

Program or Erase Command Sequence

t

RSP

20977C-22

Figure 19. Temporary Sector Unprotect Timing Diagram

Am29LV081 29

PRELIMINARY

AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations

Parameter

-90R -100 -120 -150JEDEC Std Description Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 90 100 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 50 50 50 65 ns
Data Setup Time Min 50 50 50 65 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

(OE# High to WE# Low)

Min 0 ns

WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 50 50 50 65 ns
CE# Pulse Width High Min 30 30 30 35 ns
Programming Operation (Note 2) Typ 9 µs

Sector Erase Operation (Note 2) Typ 1 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

30 Am29LV081

AC CHARACTERISTICS

XXX for program
XXX for erase

PRELIMINARY

PA for program
SA for sector erase
XXX for chip erase

Data# Polling

Addresses

WE#

OE#

CE#

Data

RESET#

RY/BY#

PA

t

WC

t

WH

t

WS

t

RH

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

PD for program
30 for sector erase
10 for chip erase

t

BUSY

WHWH1 or 2

DQ7# D

OUT

Notes:

1. P A = program address, PD = program data, DQ7# = complement of the data written to the device, D

device, XXX = address don’t care.

2. Figure indicates the last two bus cycles of the command sequence.

Figure 20. Alternate CE# Controlled Write Operation Timings

= data written to the

OUT

20977C-23

Am29LV081 31

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 15 s
Chip Erase Time 16 s
Byte Programming Time 9 300 µs

Chip Programming Time
(Note 3)

927s

Excludes 00h programming
prior to erasure (Note 4)

Excludes system level
overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.7 V, 100,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 4
for further information on command definitions.

6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V
(including A9, OE#, and RESE T#)

on all pins except I/O pins

SS

–1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

Current –100 mA +100 mA

V

CC

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

32 Am29LV081

PRELIMINARY

PHYSICAL DIMENSIONS

TS 040—40-Pin Standard TSOP (measured in millimeters)

Pin 1 I.D.

1

40

0.95

1.05

9.90

10.10

0.50 BSC

20

18.30

18.50

19.80

20.20

1.20

MAX

0˚
5˚

21

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

0.05

0.15

0.08

0.20

0.10

0.21

16-038-TSOP-1_AE
TS 040
2-27-97 lv

Am29LV081 33

PRELIMINARY

PHYSICAL DIMENSIONS

TSR040—40-Pin Reverse TSOP (measured in millimeters)

Pin 1 I.D.

1

40

0.95

1.05

9.90

10.10

0.50 BSC

20

18.30

18.50

19.80

20.20

1.20

MAX

0˚
5˚

21

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

0.05

0.15

0.08

0.20

0.10

0.21

16-038-TSOP-1_AE
TSR040
2-27-97 lv

34 Am29LV081

PRELIMINARY

REVISION SUMMARY FOR AM29LV081
Revision C

Global

Revised formatting to be cons istent with other current

3.0 volt-only data sheets.

Revision C+1

DC Characteristics

Changed Note 1 to indicate that OE# is at V
listed current.

AC Characteristics

Erase/Program Operations; Altern ate CE# Controlled
Erase/Program Operations :

ence for t

WHWH1

and t

Corrected the notes refer-

. These parameters are

WHWH2

for t he

IH

100% tested. Corrected the note reference for t

VCS

This parameter is not 100% tested.

Figure 14, Program Operation Timings; Figure 15, Chip/Sector Erase Operation Timings

The first cycle of the addresses waveform should indi-

cate XXXh; that is, addresses are don’t care for that
cycle.

Figure 20, Alternate CE# Controlled Write Operation Timings

The first cycle of the addresses waveform should indi­cate XXXh. The second cycle of the waveform should
indicate XXXh for chip er ase. Addr esses are don’t care
in these cases.

Temporary Sector Unprotect Table

Added note reference for t

. This parameter is not

VIDR

100% tested.

.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29LV081 35