AMD Am29LV033C Service Manual

Am29LV033C

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the docu ment is ma rked with the name o f the comp any that o riginally developed the specification, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Publication Number 22268 Revision B Amendment +2 Issue Date November 7, 2000

Am29LV033C

32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly z ero

■ Package options

— 63-ball FBGA — 40-pin TSOP

■ Compatible with JEDEC standards

— Pinout and software co mpatible with

single-pow er-supply flash standard

■ Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applicati ons

— Regulated voltage ra nge: 3.0 to 3.6 volt read and

write operations and for compatibility with high performance 3.3 volt microprocessors

■ Flexible sector architecture

— Sixty-four 64 Kbyte sectors

■ Manufactured on 0.32 µm process technology

PERFORMANCE CHARACTERISTICS

■ High performance

— Access ti mes as fast as 70 ns — Program time: 7 µs/byte typical ut ilizin g Acc ele rate

function

■ Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode

■ Minimum 1 million write cycles guaranteed

per sector

■ 20-year data retention at 125

— Reliab le operation for the life of the system

SOFTWARE FEATURES

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow prog ramming

in same bank

■ Data# Polling and Toggle Bits

— Provid es a s of tw ar e me th od o f d etec ti ng t he s ta tus

of program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

■ ACC input pin

— Acceleration (ACC) function provides accelerated

program time s

■ Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing dat a

in protected sectors in-system

■ Command sequence optimized for mass st orage

— Specific addresses not required for unlock cycles

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.

Publication# 22268 Rev: B Amendment/+2 Issue Date: Novembe 7, 2000

GENERAL DESCRIPTION

The Am29LV033C is a 32 Mbit, 3.0 Volt-only F lash memory orga nized as 4,194,3 04 by tes. The d evice is offered in 63-ball FBGA and 40-pin TSOP packages.

The byte-wide (x8 ) data appears on D Q7–DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers.

The standard device off ers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup- ply for both read and write functions. Internally generated and regulate d voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algor ithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an interna l algorithm th at automatically preprograms the array (if it is not already prog rammed) before executing the erase operation. During erase, the device automatically times the erase pulse w idths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data # Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architect ure allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not sele cted for erasure. True background erase can thus be achieved.

The hardware RESE T# pin term inates any operation in progress an d resets the inte rnal state m achine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29LV033C

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . .2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8

Standard Products ..................................................8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29LV033C Device Bus Operations ............9

Requirements for Reading Array Data ...................9

Writing Commands/Command Sequences ............9

Accelera te d Pro g r a m O p er a t i o n ...... .. ...................10

Program and Erase Operation Status ..................10

Standby Mode ........................ ......................... .....10

Automatic Sleep Mode ............................ .............10

RESET#: Hardware Reset Pin .............................10

Output Disable Mode ............................................11

Table 2. Am29LV033C Sector Address Table ............11

Autoselect Mode ...................................................13

Table 3. Am29LV033C Autoselect Codes

(High Voltage Method) ................................................13

Sector/Sector Block Protection and Unprotection 13

Table 4. Sector Block Addres ses for

Protection/Unprotec tion .... ..... ..... ..... ..... ..... ..... ...... ..... ..14

Temporary Sector/Sector Block Unprotect ...........14

Figure 1. Temporary Sector Unprotect Operation....... 14

Figure 2. In-System Sector Protect/

Unprotect Algorithms................................................... 15

Hardware Data Protection ....................................16

Low V

Write Pulse “Glitch” Protection .............................16

Logical Inhibit ....................................................... 16

Power-Up Write Inhibit .........................................16

Common Flash Memory Interface (CFI) . . . . . . .16

Command Definitions . . . . . . . . . . . . . . . . . . . . . .19

Reading Array Data .............................................. 19

Reset Command ....... ............... ............... .............19

Autoselect Command Sequence ........ .............. ....19

Byte Program Command Sequence .....................19

Unlock Bypass Command Sequence ...................20

Accelera te d Pro g r a m O p er a t i o n s .........................2 0

Chip Erase Command Sequence .........................20

Sector Erase Command Sequence ................. .....21

Erase Suspend/Erase Resume Commands .........21

Write Operation Status . . . . . . . . . . . . . . . . . . . . .24

DQ7: Data# Po l l in g ............... ................................24

Write Inhibit ............................................16

Table 5. CFI Query Identificat ion String ............... ..... ..16

Table 6. System Interface Str ing .................................17

Table 7. Device Geometry Definit ion ........ ..... ...... ..... ..17

Table 8. Primary Vendor-Specific Extended Query ....18

Figure 3. Program Operation ...................................... 20

Figure 4. Erase Operation.......................... ..... ...... ..... . 22

Table 9. Am29LV033C Command Definitions ...........23

Figure 5. Data# Polling Algorithm................................ 24

RY/BY#: Ready/Busy# .........................................25

DQ6: Toggle Bit I ..................................................25

DQ2: Toggle Bit II ................................................. 25

Reading Toggle Bits DQ6/DQ2 ............................25

DQ5: Exceeded Timing Limits ....... .......................26

DQ3: Sector Erase Timer .....................................26

Figure 6. Toggle Bit Algorithm..................................... 26

Table 10. Write Operation Status .......... ..... ..... ..... ..... .. 27

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 28

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29

CMOS Compatible ...............................................29

Zero Power Flash .................................................30

Figure 9. I

and Automatic Sleep Currents) ................................... 30

Figure 10. Typical I

Current vs. Time (Showing Active

CC1

vs. Frequency ......................... 30

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. Test Setup.................................. ..... ..... ..... . 31

Table 11. Test Specifications ......................................31

Key to Switching Waveforms . . . . . . . . . . . . . . . 31

Figure 12. Input Waveforms and

Measurement Levels................................................... 31

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Operations ................................. .................32

Figure 13. Read Operations Timings .......................... 32

Hardware Reset (RESET#) ................. .................33

Figure 14. RESET# Timings........................................ 33

Erase/Program Operations ...................................34

Figure 15. Program Operation Timings....................... 35

Figure 16. Accelerated Program Timing Diagram....... 35

Figure 17. Chip/Sector Erase Operation Timings........ 36

Figure 18. Data# Polling Timings (During

Embedded Algorithms)................................................ 37

Figure 19. Toggle Bit Timings (During

Embedded Algorithms)................................................ 37

Figure 20. DQ2 vs. DQ6................................... ..... ..... . 37

Figure 21. Temporary Sector/Sector

Block Unprotect Timing Diagram................................. 38

Figure 22. Sector Protect/Unprotect

Timing Diagram........................................................... 39

Figure 23. Alternate CE# Controlled Write

Operation Timings....................................................... 41

Erase and Programming Performance . . . . . . . 42

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 42

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 42

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43

TS 040—40-Pin Standard TSOP .........................43

TSR040—40-Pin Reverse TSOP ........................44

FBD063—63-Ball Fine-Pitch Ball Grid Array

(FBGA) 8 x 14 mm ...............................................45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision B (January 3, 2000) ...............................46

Revision B+1 (February 21, 2000) .......................46

Revision B+2 (November 7, 2000) .......................46

Am29LV033C 3

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV033C

Speed Option Full Voltage Range: V

Max Access Time (ns) 70 90 120 CE# Access (ns) 70 90 120 OE# Access (ns) 30 40 50

= 2.7–3.6 V -70 -90 -120

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

Input/Output

Buffers

Data

Latch

RESET#

WE#

ACC

CE#

OE#

RY/BY#

State

Control

Command

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A21

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

4 Am29LV033C

CONNECTION DIAGRAMS

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RESET#

ACC

RY/BY#

A18

A7 A6 A5 A4 A3 A2 A1

A17 V

A20 A19

A10 DQ7 DQ6 DQ5 DQ4

A21 DQ3 DQ2 DQ1 DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40-Pin Standard TSOP

40-Pin Reverse TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17 V

A20 A19 A10 DQ7 DQ6 DQ5 DQ4 V

A21 DQ3 DQ2 DQ1

DQ0 OE#

CE# A0

A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1

Am29LV033C 5

CONNECTION DIAGRAMS

63-Ball FBGA (Top View, Balls Down)

A8 B8

NC* NC*

A7 B7

NC*NC*

NC*

A1 B1

NC* NC*

C7 D7 E7

A14 A13 A15 A16 A17 NC A20 V

C6 D6 E6 F6 G6 H6 J6 K6

A9 A8 A11 A12 A19 A10 DQ6 DQ7 C5 D5 E5 F5 G5 H5 J5 K5

WE# RESET# NC NC DQ5 NC V

C4 D4 E4

RY/BY# ACC NC NC DQ2 DQ3 V

C3 D3 A7 A18 A6 A5 DQ0 NC NC DQ1

C2 D2

A3 A4 A2 A1 A0 CE# OE# V

* Balls are shorted together via the substrate but not connected to the die.

F7 G7 H7 J7 K7

F4 G4 H4 J4 K4

DQ4

A21

L8 M8

NC* NC*

L7 M7

NC* NC*

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

6 Am29LV033C

PIN CONFIGURATION

A0–A21 = 22 addresses DQ0–DQ7 = 8 data inputs/outputs CE# = Chip enable OE# = Output enable

LOGIC SYMBOL

A0–A21

DQ0–DQ7

WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy output ACC = Hardware Acc e l eration Pin

= 3.0 volt-only single power supply

(see Product Selector Guide for speed options and voltage supply t olerances)

= Device ground

NC = Pin not connected internally

CE# OE#

WE# RESET# ACC

RY/BY#

Am29LV033C 7

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

Am29LV033C -70 E C

TEMPERATURE RANGE

I = Industrial (–40 E = Extended (–55

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

WD = 63-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 14 mm package (FBD063)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV033C 32 Megabit (4 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program and Erase

°C to +85°C)

°C to +125°C)

Valid Combinations for TSOP Packages

AM29LV033C-70 EI, FI AM29LV033C-90 AM29LV033C-120

Valid Combinations

Valid Combinations list configurations planned to be supported in volume f or this device. Consult the local AMD sales office to confirm av ailability of specific valid combinations and to check on newly released combinations.

EI, EE,

FI, FE

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29LV033C-70 WDI L033C70V I AM29LV033C-90 AM29LV033C-120 L033C12V

WDI,

WDE

L033C90V

I, E

8 Am29LV033C

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressa ble memor y loc ation. The register is composed of l atches that store the commands, along with the a ddress an d data inform ation needed to execute the command. The contents of

Table 1. Am29LV033C Device Bus Operations

Operation CE# OE# WE# RESET# Addresses DQ0–DQ7

the register ser ve as inputs to th e intern al state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Read L L H H A Write (Note 1) L H L H A

Standby

Output Disable L H H H X High-Z Reset X X X L X High-Z Sector/Sector Block Protect

(Note 2) Sector/Sector Block Unprotect

(Note 2) Te mp orary Sector/Sector Block

Unprotect

0.3 V

LHLV

XXXV

0.3 V

Sector Addresses,

A6 = L, A1 = H, A0 = L

Sector Addresses

A6 = H, A1 = H, A0 = L

X High-Z

OUT

, D

OUT

, D

OUT

Legend:

L = Logic Low = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, D

= Data In, D

= Data Out

OUT

Notes:

1. When the ACC pin is at V

, the device enters the accelerated program mode. See “Accelerated Program Operations” for

more information.

2. The sector protect and sector unprotect functions may also be implemented vi a progr amming equi pment. See the “Sect or/Sector Block Protection and Unprote ction” secti on.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading arr ay data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica-

. CE# is the power

Am29LV033C 9

tions and to Figure 13 for the timing diagram. I

CC1

the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

The device f eatures an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The “Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sectors, or the entire de vi ce. Table 2 indicates the address

, and OE# to VIH.

space that each sector occupies. A “sector address ” consists of the address bits required to uniquely select a sector. The “Comm and D efinitio ns” s ection has de tails on erasing a sector or the entire chip , or suspending/resuming the erase operation.

After the system wr ites the autosele ct command s equence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the ACC pin. This function is prim arily intended to allow faster manufacturing throughput at the factory.

If the system a sser t s V

on this pin, the device auto-

matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected s ectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cyc le program comm and seq uence as required by the Unlock Bypass mode. Removing

from the ACC pin returns the device to normal op-

eration. Note that the ACC pin must not be at V

for operations other than accelerated programming, or device damage may result.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Op-

eration Status” for more information, and to “AC Characteristics” for timing diagrams .

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pin s are both held at V (Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at VIH, but not within

± 0.3 V, the device will be in the standby mode , b ut

± 0.3 V.

the standby current will be greater. The device requires standard access time (t

) for read access

when the device is in either of these standby modes, before it is ready to read data.

The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mod e minimizes Fla sh device energy consumption. The device automatica lly enables this mode when addresses remain stable for

+ 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in the DC Characteristics table

CC4

represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write comm ands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to acce pt another command sequenc e, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby cu rrent ( I

but not within VSS±0.3 V, the standby current will

at V

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin rema ins a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The sys-

READ Y

tem can thus monitor RY/BY# to deter mine whethe r the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed

, the

10 Am29LV033C

within a time of t rithms). The system can rea d data t SET# pin returns to V

Refer to the AC Characteristics tables for RESET# pa-

(not during Em bedded Algo-

READY

after the R E-

Output Disable Mode

When the OE# input is at VIH, output from the devi ce is disabled. The output pins are placed in the high impedance state.

rameters and to Figure 14 for the timing diagram.

Table 2. Am29LV033C Sector Address Table

Address Range

Sector A21 A20 A19 A18 A17 A16

SA0 000000 000000–00FFFF SA1 000001 010000–01FFFF SA2 000010 020000–02FFFF SA3 000011 030000–03FFFF SA4 000100 040000–04FFFF SA5 000101 050000–05FFFF SA6 000110 060000–06FFFF SA7 000111 070000–07FFFF SA8 001000 080000–08FFFF

SA9 001001 090000–09FFFF SA10 001010 0A0000–0AFFFF SA11 001011 0B0000–0BFFFF SA12 001100 0C0000–0CFFFF SA13 001101 0D0000–0DFFFF SA14 001110 0E0000–0EFFFF SA15 001111 0F0000–0FFFFF SA16 010000 100000–10FFFF SA17 010001 110000–11FFFF SA18 010010 120000–12FFFF SA19 010011 130000–13FFFF SA20 010100 140000–14FFFF SA21 010101 150000–15FFFF SA22 010110 160000–16FFFF SA23 010111 170000–17FFFF SA24 011000 180000–18FFFF SA25 011001 190000–19FFFF SA26 011010 1A0000–1AFFFF SA27 011011 1B0000–1BFFFF SA28 011100 1C0000–1CFFFF SA29 011101 1D0000–1DFFFF SA30 011110 1E0000–1EFFFF SA31 011111 1F0000–1FFFFF

(in hexadecimal)

Am29LV033C 11

Table 2. Am29LV033C Sector Address Table (Continued)

Address Range

Sector A21 A20 A19 A18 A17 A16

SA32 100000 200000–20FFFF SA33 100001 210000–21FFFF SA34 100010 220000–22FFFF SA35 100011 230000–23FFFF SA36 100100 240000–24FFFF SA37 100101 250000–25FFFF SA38 100110 260000–26FFFF SA39 100111 270000–27FFFF SA40 101000 280000–28FFFF SA41 101001 290000–29FFFF SA42 101010 2A0000–2AFFFF SA43 101011 2B0000–2BFFFF SA44 101100 2C0000–2CFFFF SA45 101101 2D0000–2DFFFF SA46 101110 2E0000–2EFFFF SA47 101111 2F0000–2FFFFF SA48 110000 300000–30FFFF SA49 110001 310000–31FFFF SA50 110010 320000–32FFFF SA51 110011 330000–33FFFF SA52 110100 340000–34FFFF SA53 110101 350000–35FFFF SA54 110110 360000–36FFFF SA55 110111 370000–37FFFF SA56 111000 380000–38FFFF SA57 111001 390000–39FFFF SA58 111010 3A0000–3AFFFF SA59 111011 3B0000–3BFFFF SA60 111100 3C0000–3CFFFF SA61 111101 3D0000–3DFFFF SA62 111110 3E0000–3EFFFF SA63 111111 3F0000–3FFFFF

(in hexadecimal)

Note: All sectors are 64 Kbytes in size.

12 Am29LV033C

Autoselect Mode

The autoselect mode provides manufacturer and device identification, a nd sector pr otection verificatio n,

through identifier codes output on DQ7–DQ0. This mode is prima rily intende d for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register .

When using programming equipment, the autoselect mode requires V A9. Address pins A6, A1, and A0 must be as shown in Table 3. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table ). Table 3 shows

Description CE# OE# WE#

(11.5 V to 12.5 V) on address pin

Table 3. Am29LV033C Autoselect Codes (High Voltage Method)

A21

A16

the remaining address bits that are don’t care. When all necessar y bits have been set as required , the programming equipment may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command re gister, as shown in Table 9. This meth od does not require V

. See “Writing specific addr ess

and data commands or s equences into the co mmand register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data.” for details on using the autoselect mode.

A15

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X V Device ID: Am29LV033C L L H X X V

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector/Sector Block Protection and Unprotection

(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more a djace nt secto rs that a re protected or unprotected at the same time (see Table 4).

The hardware sector protection feature disables both program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods.

The primary method requires V only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 22 shows the timing diagram. This method uses standard microprocessor bus cycle tim-

on the RESET# pin

ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.

The alternate method intended only for programming equipment requires V This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 22269 contains further details; contact an AMD representative to request a copy.

The device is shipped with all sec tors unprotected. AMD offers the option of programmi ng and pro tecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

XLXLL 01h

XLXLH A3h

XLXHL

01h

(protected)

00h

(unprotected)

on address pin A9 and OE#.

Am29LV033C 13

Table 4. Sector Block Addresses for

Protection/Unprotection

Sector/

Sector Block A21–A16

SA0

SA1-SA3

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA60-SA62

SA63

000000 64 Kbytes

000001,000010,

000011

000100, 000101,

000110, 000111

001000, 001001,

001010, 001011

001100, 001101,

001110, 001111

010000, 010001,

010010, 010011

010100, 010101,

010110, 010111

011000, 011001,

011010, 011011

011100, 011101,

011110, 011111

100000, 100001,

100010, 100011

100100, 100101,

100110, 100111

101000, 101001,

101010, 101011

101100, 101101,

101110, 101111

110000, 110001,

110010, 110011

110100, 110101,

110110, 110111

111000, 111001,

111010, 111011

111100, 111101,

111110 111111 64 Kbytes

Sector/

Sector Block Size

192 (3x64) Kbytes

256 (4x64) Kbytes

192 (4x64) Kbytes

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table

4). This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased b y selecting the sector addresses. Once V SET# pin, all the previously protected s ectors are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature.

. During this mode, former ly prot ected

is removed from the RE-

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

Figure 1. Temporary Sector Unprotect Operation

14 Am29LV033C

again.

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