AMD Advanced Micro Devices AM29LV017B-90WCI, AM29LV017B-90WCEB, AM29LV017B-90WCE, AM29LV017B-90WCCB, AM29LV017B-90WCC Datasheet

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PRELIMINARY

Am29LV017B

16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt -only Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3. 6 volt read

and write operations and for compatibility with high performance 3.3 volt microprocessors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Manufactured on 0.35 µm process technology

■ High performance

— Full voltage range: ac cess times as f ast as 90 ns — Regulated voltage range: access times as fast

as 80 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 9 mA read current — 15 mA program/erase current

■ Flexible sector architecture

— Thirty-two 64 Kbyte sectors — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sector

Sectors can be locked in-system or via programming equipment

T emporary Sector Unprotect feat ure allows code changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall progr amming time when

issuing multiple program command sequences

■ Minimum 1,000,000 write cycle guarantee per

sector

■ Package option

— 48-ball FBGA — 40-pin TSOP

■ CFI (Common Flash Interface) compliant

— Provides device-specific information to the

system, allowing host software to easily reconfigure for different Flash devices

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the de vi ce to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed product without notice.

Publication# 21415 Rev: C Amendment/+2 Issue Date: March 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV017B is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes. The device is offered in 48-ball FBGA and 40-pin TSOP p ackages.

The byte-wide (x8) data appears on DQ7–DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers.

The standard device off ers access times of 80, 90, and 120 ns, allowing high speed microprocessors to operate without wait s tates. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two write cycles to program data instead of four.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already progr ammed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pi n terminates any operation in progress and resets the internal state machine to reading array dat a. The RESET# pin ma y be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep m ode. The system can also place the de vice into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases a ll bit s within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

Am29LV017B 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV017B

Speed Option

Max access time, ns (t Max CE# access time, ns (tCE) 80 90 120 Max OE# access time, ns (tOE) 30 35 50

Regulated Voltage Range: VCC =3.0–3.6 V -80R

Full Voltage Range: VCC = 2.7–3.6 V -90 -120

) 80 90 120

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

Input/Output

Buffers

Data

Latch

RESET#

WE#

CE#

OE#

RY/BY#

State

Control

Command

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A20

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21415C-1

3 Am29LV017B

CONNECTION DIAGRAMS

PRELIMINARY

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RESET#

RY/BY#

A18

A7 A6 A5 A4 A3 A2 A1

A17 V

A20 A19

A10 DQ7 DQ6 DQ5 DQ4

NC DQ3 DQ2 DQ1 DQ0 OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40-Pin Standard TSOP

40-Pin Reverse TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17 V

A20 A19 A10 DQ7 DQ6 DQ5 DQ4 V

NC DQ3 DQ2 DQ1 DQ0 OE#

CE# A0

A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1

48-Ball FBGA (Bottom View)

A1 B1 A3 A4 A2 A1 A0 CE# OE# V

A2 B2C1C2D1D2E1E2F1F2G1G2 A7 A18 A6 A5 DQ0 NC NC DQ1

A3 B3 C3 D3 E3 F3 G3 H3

RY/BY# NC NC NC DQ2 DQ3 V

A4 B4 C4 D4 E4 F4 G4 H4

WE# RESET# NC NC DQ5 NC V

A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A11 A12 A19 A10 DQ6 DQ7

A6 B6 C6 D6 E6 F6 G6 H6

A14 A13 A15 A16 A17 NC A20 V

Am29LV017B 4

DQ4

21415C-2

PRELIMINARY

Special Handling Instructions for FBGA Packages

Special handling is required for Flash Memory products in FBGA packages.

PIN CONFIGURATION

A0–A20 = 21 addresses DQ0–DQ7 = 8 data inputs/outputs CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy output

= 3.0 volt-only single power supply

NC = Pin not connected internally

(see Product Selector Guide for speed options and voltage supply toleranc es)

= Device ground

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

LOGIC SYMBOL

A0–A20

DQ0–DQ7

CE# OE#

WE# RESET#

RY/BY#

21415C-3

5 Am29LV017B

PRELIMINARY

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in s everal packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE-80RAm29LV017B

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package

DEVICE NUMBER/DESCRIPTION

Am29LV017B 16 Megabit (2 M x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Am29LV017B-80R EC, FC, WCC Am29LV017B-90 EC, EI, EE,

Am29LV017B-120

FC, FI, FE,

WCC, WCI, WCE

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Am29LV017B 6

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loc ation. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the

Table 1. Am29LV017B Device Bus Operations

Operation CE# OE# WE# RESET# Addresses DQ0–DQ7

Read L L H H A Write L H L H A

Standby Output Disable L H H H X High-Z

Reset X X X L X High-Z Sector Protect (See Note) L H L V

Sector Unprotect (See Note) L H L V Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

VCC ±

0.3 V

register serve as inputs to the internal state machine. The state machine outputs d ictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

, D

= Data Out

OUT

VCC ±

0.3 V

IN IN

X High-Z

Sector Addresses,

A6 = L, A1 = H, A0 = L

Sector Addresses

A6 = H, A1 = H, A0 = L

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the dev ice. OE# is the output control and gates array data to the output pins. WE# should remain at V

The internal state machine is set for reading arr ay data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address input s produc e valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active current specification for reading array data.

. CE# is the power

CC1

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

The device features an Unlock Bypass mode to facil- itate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The “Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sectors, or the entire de vi ce. Table 2 indicat es the addres s space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this

, and OE# to VIH.

7 Am29LV017B

PRELIMINARY

mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write m ode. The “AC

Characteristics” section contains timing specification tables and timing diagrams for w r ite operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device , it can place the device in the standby mode. In this mode, current consumption is great ly reduc ed, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pin s are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

± 0.3 V, the device will be in the standb y mode, b ut

the standby current will be greater. The device requires standard access time (t

) for read access when the

device is in either of these standby modes, before it is ready to read data.

The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addres ses remain stable for

+ 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new data when addresses are chan ged. While in sleep mode, output data is latched and always available to the system. I

in the DC Characteristics table

CC4

represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardw are method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t

, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t rithms). The system can read data t SET# pin returns to V

(not during Embe dded Algo-

READY

after the RE-

Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in t he high impedance state.

Am29LV017B 8

PRELIMINARY

Table 2. Am29LV017B Sector Address Table

Address Range

Sector A20 A19 A18 A17 A16

SA0 00000 000000–00FFF F SA1 00001 010000–01FFFF SA2 00010 020000–02FFFF SA3 00011 030000–03FFFF SA4 00100 040000–04FFFF SA5 00101 050000–05FFFF SA6 00110 060000–06FFFF SA7 00111 070000–07FFFF SA8 01000 080000–08FFFF

SA9 01001 090000–09FFFF SA1001010 0A0000–0AFFFF SA1101011 0B0000–0BFFFF SA1201100 0C0000–0CFFFF SA1301101 0D0000–0DFFFF SA1401110 0E0000–0EFFFF SA1501111 0F0000–0FFFFF SA1610000 100000–10FFFF SA1710001 110000–11FFFF SA1810010 120000–12FFFF SA1910011 130000–13FFFF SA2010100 140000–14FFFF SA2110101 150000–15FFFF SA2210110 160000–16FFFF SA2310111 170000–17FFFF SA2411000 180000–18FFFF SA2511001 190000–19FFFF SA2611010 1A0000–1AFFFF SA2711011 1B0000–1BFFFF SA2811100 1C0000–1CFFFF SA2911101 1D0000–1DFFFF SA3011110 1E0000–1EFFFF SA3111111 1F0000–1FFFFF

(in hexadecimal)

9 Am29LV017B

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for progr amming equipment to automatically match a device to be progr ammed with its correspondi ng programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V A9. Address pins A6, A1, and A0 must be as shown in

(11.5 V to 12.5 V) on address pin

Table 3. In addition, when verifying sector protec tion, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 sho ws the remaining address bits that are don’t c are. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 8. This method does not require V details on using the autoselect mode.

Table 3. Am29LV017B Autoselect Codes (High Voltage Method)

A20

A15

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V Device ID: Am29LV0 17B L L H X X V

Sector Protection Verification L L H SA X V

A16

A10 A9

. See “Command Definitions” for

A7 A6

XLXLL 01h

XLXLH C8h

XLXHL

A2 A1 A0

DQ7

DQ0

01h

(protected)

00h

(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sect or. The hardware sector unprotection feature re-enables both pro-

through AMD’s ExpressFlash™ Servic e. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

gram and erase operations in previously protected sectors. Sector protection/unprotecti on can be implemented via two methods.

The primary method requires V

on the RESET# pin

only, and c an be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 21 shows the timing diagram. This method uses standard m icroprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro tect write cycle.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased b y selecting the sector addresses. Once V SET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 20 shows the tim ing diagrams, for this feature.

The alternate method intended on ly for programming equipment requires V

on address pin A9 and OE#.

This method is compatible with programmer routines written for earlier 3.0 v olt-only AMD flash de vices. Publication number 21587 contains further details; contact an AMD representative to request a copy.

. During this mode, formerly protected

is removed from the RE-

The device is shipped with all s ectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

Am29LV017B 10

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Figure 1. In-System Sector Protect/Unprotect Algorithms

11 Am29LV017B

Sector Unprotect

complete

21415C-4

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

21415C-5

against inadverten t writes (refer to Table 8 for command definitions). In addition, the following hardwar e data protection mea sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V

power-up

and power-down transitions, or from system noise.

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

, CE# = VIH or WE# = VIH. To initiate a writ e cy-

= V

cle, CE# and WE# must be a logical zero while OE# is a logical one.

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during powe r

up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

Am29LV017B 12

+ 27 hidden pages