AMD Advanced Micro Devices AM29LV010BT-70FIB, AM29LV010BT-70FI, AM29LV010BT-70FEB, AM29LV010BT-70FE, AM29LV010BT-70FC Datasheet

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Am29LV010B
1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Uni form Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

Single power supply operation
— Full voltage range: 2.7 to 3. 6 volt read and write
operations for battery-powered applications
— Regulated voltage r ange: 3.0 to 3.6 v olt read and
write operations and for compatibility with high performance 3.3 volt microprocessors
Manufactured on 0.35 µm process technology
High performance
— Full voltage range: ac cess times as f ast as 55 ns — Regulated voltage range: access times as fast
as 45 ns
Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/erase current
Flexible sector architecture
— Eight 16 Kbyte — Supports full chip erase — Sector Protection features:
Hardware method of loc king a sector to prevent any program or erase operat ions within that sector
Sectors can be locked in-system or via programming equipment
T emporary Sector Unprotect feat ure allows code changes in previously locked sectors
Unlock Bypass Mode Program Command
— Reduces overall programming time when
issuing multiple program command sequences
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
Minimum 1,000,000 write cycle guarantee per
sector
Package option
— 32-pin TSOP — 32-pin PLCC
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
Erase Suspend/Erase Resume
— Supports reading data from or programming
data to a sector that is not being erased
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed product without notice.
Publication# 22140 Rev: A Amendment/0 Issue Date: April 1998
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GENERAL DESCRIPTION

The Am29LV010B is a 1 Mbit, 3.0 Volt-only Flash memory devic e organized as 131,072 bytes. T he Am29LV010B has a uniform sector architecture.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7– DQ0. All read, erase, and program operations are accomplished using only a single power supply. The device can also be programmed in s tandard EPROM programmers.
The standard Am29LV010B offers access times of 45, 55, 70, and 120 ns (90 and 100 ns parts are also avail­able), allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
The device requires only a single power supply (2.7 V–3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com­mands are written to the command regis ter using standard micropr ocessor wri te timings. Register co n­tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two write cycles to program data instead of four.
Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that auto matically preprograms the arra y (if it is not already progr ammed) before e xecuting the er ase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the de vice is ready to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures includ e a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector protection feature disables both program and erase
operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True backgro und eras e can thus be achie ved.
The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of time, the device enters the automatic sleep m ode. The system can also place the de vice into the standby mode. Power consumption is greatly redu ced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron injection.
Am29LV010B 2
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PRODUCT SELECTOR GUIDE

Family Part Number Am29LV010B
Speed Options
Max access time, ns (t Max CE# access time, ns (tCE) 45 55 70 120 Max OE# access time, ns (tOE) 30 30 35 50
Regulated Voltage Range: VCC =3.0–3.6 V -45R
Full Voltage Range: VCC = 2.7–3.6 V -55 -70 -120
) 45 55 70 120
ACC
Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0
DQ7
V
CC
V
SS
WE#
CE#
OE#
State
Control
Command
Register
PGM Voltage
Generator
Sector Switches
Erase Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Input/Output
Buffers
Data
Latch
A0–A16
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
22140A-1
3 Am29LV010B
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