Page 1
查询Am29LV008BB-120EC供应商
PRELIMINARY
Am29LV008B
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3. 6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3. 6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29LV008 device
■ High performance
— Full voltage range: ac cess times as f ast as 80 ns
— Regulated voltage range: access times as fast
as 70 ns
■ Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
■ Top or bottom boot block configurations
■ Embedded Al gorithms
■ Minimum 1,000,000 write cycle guarantee per
■ Package option
■ Compatibility with JEDEC standards
■ Data# Polling and toggle bits
■ Ready/Busy# pin (RY/BY#)
■ Erase Suspend/Erase Resume
■ Hardware reset pin (RESET#)
— Reduces overall programming time when
issuing multiple program command sequences
available
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
sector
— 40-pin TSOP
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— Provides a software method of detecting
program or erase operation completion
— Provides a hardware method of detecting
program or erase cycle completion
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
— Hardware method to reset the de vi ce to reading
array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication# 21524 Rev: B Amendment/+1
Issue Date: March 1998
Page 2
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV008B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
a single, 3.0 volt V
and erase operations. A stand ard EPROM programmer can also be used to program and erase the
device.
This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the features and
benefits of the Am29LV008, which was manufactured
using 0.5 µm process technology. In addition, the
Am29LV008B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait s tates. To eliminate bus contention the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two
write cycles to program data instead of four.
Device erasure occurs by ex ecuting the erase command
sequence. This initiates the Embedded Erase algorithm—an i nternal algorithm that autom atically prepro grams the array (if it is not already programmed) before
supply to perform read, program,
CC
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases a ll bit s within
a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
2 Am29LV008B
Page 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Am29LV008B
Speed Options
Max access time, ns (t
Max CE# access time, ns (tCE) 70 80 90 120
Max OE# access time, ns (tOE) 30 30 35 50
Regulated Voltage Range: VCC =3.0–3.6 V -70R
Full Voltage Range: VCC = 2.7–3.6 V -80 -90 -120
) 70 80 90 120
ACC
Note: See “AC Characte r ist ics ” for full specifications.
BLOCK DIAGRAM
DQ0
DQ7
–
Input/Output
Buffers
Data
Latch
V
CC
V
SS
RESET#
WE#
CE#
OE#
RY/BY#
State
Control
Command
Register
PGM Voltage
Generator
Sector Switches
Erase Voltage
Generator
Chip Enable
Output Enable
Logic
STB
A0–A19
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
21524B-1
Am29LV008B 3
Page 4
CONNECTION DIAGRAMS
PRELIMINARY
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
CE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Standard TSOP
Reverse TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
4 Am29LV008B
21524B-2
Page 5
PRELIMINARY
PIN CONFIGURATION
A0–A19 = 20 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
= 3.0 volt-only single power supply
V
CC
V
SS
NC = Pin not connected internally
(see Product Selector Guide for speed
options and voltage supply toleranc es)
= Device ground
LOGIC SYMBOL
20
A0–A19
CE#
OE#
WE#
RESET#
8
DQ0–DQ7
RY/BY#
21524B-3
Am29LV008B 5
Page 6
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in s everal packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
CE-70RAm29LV008B T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
Am29LV008BT-70R,
Am29LV008BB-70R
Am29LV008BT-80,
Am29LV008BB-80
Am29LV008BT-90,
Am29LV008BB-90
Am29LV008BT-120,
Am29LV008BB-120
Valid Combinations
EC, EI, FC, FI
EC, EI, EE, FC, FI, FE
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV008B
8 Megabit (1 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
6 Am29LV008B
Page 7
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory loc ation.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
Table 1. Am29LV008B Device Bus Operations
Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0–DQ7
Read L L H H A
Write L H L H A
Standby
Output Disable L H H H X High-Z
Reset X X X L X High-Z
Sector Protect (Note 2) L H L V
Sector Unprotect (Note 2) L H L V
Temporary Sector Unprotect X X X V
Legend:
L = Logic Low = V
Notes:
1. Addresses are A19–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D
IL
VCC ±
0.3 V
XX
register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.
D
D
D
, D
IN
D
, D
IN
D
= Data Out
OUT
OUT
IN
OUT
OUT
IN
VCC ±
0.3 V
ID
ID
ID
IN
IN
X High-Z
Sector Address, A6 = L,
A1 = H, A0 = L
Sector Address, A6 = H,
A1 = H, A0 = L
A
IN
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
.
IH
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the mem ory
content occurs during the power transition. No
command is neces sary in this mode to obtain ar ray
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table fo r timing specifications and to Figure 13 for the timing waveforms. I
the DC Characteristics table represents the active
current specification for reading array data.
. CE# is the power
IL
CC1
in
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
The Am29LV008B is manufactured on AMD’s new 0.35
µm process technol ogy and offers an Unlock Bypass
mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles
are required to program a byte, instead of four. Devices
manufactured on AMD’s 0.5 µm process technology require a four-bus-cycle command sequence for each byte
programmed. The “Byte Program Command Sequence”
section has details on programm ing data to the device
using both standard and U nlock Bypass command sequences.
An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
, and OE# to VIH.
IL
Am29LV008B 7
Page 8
PRELIMINARY
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the devi ce enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the Autoselect Mode and
Autoselect Command Sequence sections for more
information.
in the DC Characteristics table represents the
I
CC2
active current specification for the write mode. The “A C
Characteristics” section contains timing specification
tables and timing diagrams for w r ite operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
.) If CE# and RESET# ar e held a t VIH, but not within
V
IH
± 0.3 V, the device will be in the standb y mode, b ut
V
CC
the standby current will be greater. The device requires
standard access time (t
) for read access when the
CE
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics table, I
CC3
and I
CC4
repre-
sents the standby current s pecification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addres ses remain stable for
t
+ 30 ns. The automatic sleep mode is inde-
ACC
pendent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data
when addresses are changed. While in sleep mode,
output data is latched and always available to the
system. I
in the DC Characteristics table represents
CC5
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby c urrent (I
but not within VSS±0.3 V, the standby current will
at V
IL
±0.3 V, the device
SS
). If RESET# is held
CC4
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
RESET# pin returns to V
(not during Embe dded Algo-
READY
.
IH
after the
RH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
8 Am29LV008B
Page 9
PRELIMINARY
Table 2. Am29LV008BT Top Boot Block Sector Address Table
Sector Size
Sector A19 A18 A17 A16 A15 A14 A13
SA00000XXX 64 00000h–0FFFFh
SA10001XXX 64 10000h–1FFFFh
SA20010XXX 64 20000h–2FFFFh
SA30011XXX 64 30000h–3FFFFh
SA40100XXX 64 40000h–4FFFFh
SA50101XXX 64 50000h–5FFFFh
SA60110XXX 64 60000h–6FFFFh
SA70111XXX 64 70000h–7FFFFh
SA81000XXX 64 80000h–8FFFFh
SA91001XXX 64 90000h–9FFFFh
SA101010XXX 64 A0000h–AFFFFh
SA111011XXX 64 B0000h–BFFFFh
SA121100XXX 64 C0000h–CFFFFh
SA131101XXX 64 D0000h–DFFFFh
SA141110XXX 64 E0000h–EFFFFh
SA1511110XX 32 F0000h–F7FFFh
SA161111100 8 F8000h–F9FFFh
SA171111101 8 FA000h–FBFFFh
SA18111111X 16 FC000h–FFFFFh
(Kbytes)
Address Range
(in hexadecimal)
Table 3. Am29LV008BB Bottom Boot Block Sector Address Table
Sector Size
Sector A19 A18 A17 A16 A15 A14 A13
SA0000000X 16 00000h-03FFFh
SA10000010 8 04000h-05FFFh
SA20000011 8 06000h-07FFFh
SA300001XX 32 08000h-0FFFFh
SA40001XXX 64 10000h-1FFFFh
SA50010XXX 64 20000h-2FFFFh
SA60011XXX 64 30000h-3FFFFh
SA70100XXX 64 40000h-4FFFFh
SA80101XXX 64 50000h-5FFFFh
SA90110XXX 64 60000h-6FFFFh
SA100111XXX 64 70000h-7FFFFh
SA111000XXX 64 80000h-8FFFFh
SA121001XXX 64 90000h-9FFFFh
SA131010XXX 64 A0000h-AFFFFh
SA141011XXX 64 B0000h-BFFFFh
SA151100XXX 64 C0000h-CFFFFh
SA161101XXX 64 D0000h-DFFFFh
SA171110XXX 64 E0000h-EFFFFh
SA181111XXX 64 F0000h-FFFFFh
(Kbytes)
Address Range
(in hexadecimal)
Am29LV008B 9
Page 10
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection ver ification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in
(11.5 V to 12.5 V) on address pin
ID
Table 4. In addition, when verifying sector protec tion,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
details on using the autoselect mode.
Table 4. Am29LV008B Autoselect Codes (High Voltage Method)
A19
A12
to
to
Description CE# OE# WE#
Manufacturer ID: AMD L L H X X V
Device ID: Am29LV0 08B T
(Top Boot Block)
Device ID: Am29LV0 08B B
(Bottom Boot Block)
LLHXXV
LLHXXVIDXLXLH 37h
A13
A10 A9
. See “Command Definitions” for
ID
A8
to
A7 A6
XLXLL 01h
ID
XLXLH 3Eh
ID
A5
to
A2 A1 A0
DQ7
to
DQ0
Sector Protection Verification L L H SA X V
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sect or. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection/unprotection can be implemented via
The primary method requires V
only, and c an be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and Figure 21 shows the waveform. This
method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first be protected prior to th e first s ector unprotec t
write cycle.
The alternate method intended o nly for programming
equipment requires V
This method is compatible with programmer routines
written for earlie r 3.0 volt-only AMD flash devices.
Details on this method are provided in a supplement,
publication number 20875. Contact an AMD representative to request a cop y.
ID
two methods.
XLXHL
on the RESET# pin
ID
on address pin A9 and OE#.
ID
01h
(protected)
00h
(unprotected)
10 Am29LV008B
Page 11
PRELIMINARY
Temporary Sector
Unprotect Mode
Increment
PLSCNT
START
PLSCNT = 1
RESET# = V
Wait 1 µs
No
First Write
Cycle = 60h?
Yes
Set up sector
address
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
START
Protect all sectors:
The indicated portion
of the sector protect
ID
Reset
PLSCNT = 1
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = V
Wait 1 µs
First Write
Cycle = 60h?
No
All sectors
protected?
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 15 ms
Yes
Yes
ID
No
Temporary Sector
Unprotect Mode
No
PLSCNT
= 25?
Yes
Device failed
Sector Protect
Algorithm
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
No
Data = 01h?
Protect another
sector?
Remove V
from RESET#
Write reset
command
Sector Protect
complete
Yes
No
Verify Sector
Unprotect: Write
40h to sector
Increment
PLSCNT
No
Yes
ID
PLSCNT
= 1000?
Yes
Device failed
Sector Unprotect
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
No
Data = 00h?
Last sector
verified?
Remove V
from RESET#
Yes
Yes
Set up
next sector
address
No
ID
Algorithm
Write reset
command
Sector Unprotect
complete
Figure 1. In-System Sector Protect/Unprotect Algorithms
Am29LV008B 11
21524B-4
Page 12
PRELIMINARY
Temporary Sector Unprotect
This feature allows temporary unpr otection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to V
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
. During this mode, formerly protected
ID
START
RESET# = V
(Note 1)
Perform Erase or
Program Operations
RESET# = V
Temporary Sector
Unprotect Completed
(Note 2)
ID
IH
21524B-5
sectors can be programmed or erased b y selecting the
sector addresses. Once V
is removed from the RE-
ID
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the tim ing diagrams, for this feature.
against inadverten t writes (refer to Table 5 for command definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
power-up
CC
and power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
Write Inhibit
CC
is less than V
CC
, the device does not ac-
LKO
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
. The system must provide the
LKO
CC
proper signals to the control pins to prevent unintentional writes when V
is greater than V
CC
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 2. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defin es the v al i d regist er command
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = VIH during power up , the
IL
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
data after comp leting an Embedded Program o r
Embedded Erase algorithm.
After the device accepts an Era se Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a program ming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
must
The system
issue the reset command to reenable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
12 Am29LV008B
Page 13
PRELIMINARY
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
See the applicable “AC Characteristics” for parameters,
and to Figure 14 for the timing wavrforms.
must
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 5 shows the address and data requirements . This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Tables 2
and 3 for valid sector addresses.
ID
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bu s-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
not
gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 5 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indic ate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or w ords t o the device faster than using the
standard program command sequence. The unloc k b ypass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the prog ram
address and data. Additional data is programmed in
the same manner. This mode dispenses with t he i nitial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. The Command Definitions table shows the
requirements for the command sequence.
During the unlo ck bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
required to provide further
Am29LV008B 13
Page 14
PRELIMINARY
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Add resses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and Figure 15 for timing diagrams.
START
Write Program
Command Sequence
Data Poll
Embedded
Program
algorithm
in progress
Increment Address
Note: See Table 5 for program command sequence.
No
from System
Verify Data?
Yes
Last Address?
Yes
Programming
Completed
No
21524B-6
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
not
algorithm. The device does
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and ve rifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con-
require the system to
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip eras e operat ion immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or R Y/BY#. See “ Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched.
Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up c ommand. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase co mmand sequence.
not
The device does
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the num ber of
sectors may be from one sector to all sectors . The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sec tor Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not m onitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
require the system to preprogram
14 Am29LV008B
Page 15
PRELIMINARY
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .
Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immedia tely terminates the
operation. The Sec tor Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched. The system can determin e the
status of the erase operati on by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to “Write Operation Status” for information on these status bits.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing wavefor ms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-care s” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure . (The devi ce “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is er ase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is complete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can dete rmine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command c an be written after the
device has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
No
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Data = FFh?
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
21524B-7
Figure 4. Erase Operation
Am29LV008B 15
Page 16
PRELIMINARY
Table 5. Am29LV008B Command Definitions
Command
Sequence
(Note 1)
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Autoselect
(Note 7)
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 9) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 10 ) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 11) 1 XXX B0
Erase Resume (Note 12) 1 XXX 30
Device ID, Top Boot Block 4 555 AA 2AA 55 555 90 X01 3E
Device ID, Bottom Boot Block 4 555 AA 2AA 55 555 90 X01 37
Sector Protect Verify
(Note 8)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Cycles
4 555 AA 2AA 55 555 90
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Bus Cycles (Notes 2-4)
(SA)
X02
00
01
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A19–A11 are don’t cares for unlock and
command cycles.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
10. The Unlock Bypass Rese t command is required to return to
reading array data when the device is in the unlock bypass
mode.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
12. The Erase Resume command is valid only dur ing the Erase
Suspend mode.
16 Am29LV008B
Page 17
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to deter mine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and t he f ollowing s ubsections describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all s ectors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the
following
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
read cycles. This is because DQ7
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
FAIL
Yes
Yes
PASS
21524B-8
Figure 5. Data# Polling Algorithm
Am29LV008B 17
Page 18
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, se veral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 13, 14,
15 and 16 shows R Y/BY# for read, reset, program, and
erase operations, respectively.
CC
.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whethe r an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Table 6 shows the outputs for Toggle Bit I on DQ6.
Refer to Figure 6 shows the toggle bit algorithm and to
Figure 18 in the “AC Characteristics” section for the
timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical for m. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.
DQ2 toggles w hen the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which s ectors are selected for erasure.
Thus, both status bits are requ ired f or sector and mode
information. Refer to Table 6 to compare outputs for
DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to Figure 18 f or the toggle bit timing diagram. Figure 19 shows the differenc es between DQ2 and DQ6 in
graphical form.
After an erase command sequence is written, if all s ectors selected for eras ing are protected , DQ6 toggles for
approximately 100 µs, then returns to readi ng array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: D ata# Polling).
If a program address falls within a pro tected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever
the system initially begins rea ding toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would compare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to readi ng
array data.
18 Am29LV008B
Page 19
PRELIMINARY
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, determining the status as described in the previous paragraph. Alterna tively, it may choose to perfor m other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
START
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
No
(Notes
1, 2)
No
Program/Erase
Operation Complete
No
Toggle Bit
= Toggle?
Yes
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase o peration can
change a “0” back to a “1.” Under this condition, the
device halts the oper ation, and when the operatio n has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return th e device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine w hether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0”
to “1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Erase Command Sequence” section.
After the sector erase command sequenc e is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Sus pend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should che ck the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
21524B-9
Figure 6. Toggle Bit Algorithm
Am29LV008B 19
Page 20
PRELIMINARY
Table 6. Write Operation Status
DQ7
Standard
Mode
Erase
Suspend
Mode
Operation
Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
(Note 2) DQ6
1 No toggle 0 N/A Toggle 1
Data Data Data Data Data 1
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
DQ5
(Note 1) DQ3
DQ2
(Note 2) RY/BY#
20 Am29LV008B
Page 21
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
V
CC
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1) . . . . . –0.5 V to V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, input or I/O pins may undershoot V
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is V
During voltage transitions, input or I/O pins may overshoot
to V
+2.0 V for periods up to 20 ns. See Figure 8.
CC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
to –2.0 V for periods of up
SS
+0.5 V
CC
+0.5 V.
CC
SS
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
20 ns
21524B-10
Figure 7. Maximum Negative Overshoot
V
CC
+2.0 V
V
CC
+0.5 V
2.0 V
Waveform
20 ns
20 ns
20 ns
21524B-11
Figure 8. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
Industrial (I) Devices
Ambient Temperature (T
Extended (E) Devices
Ambient Temperature (T
Supply Voltages
V
CC
for regulated voltage range. . . . .+3.0 V to +3.6 V
V
CC
VCC for full v oltage range. . . . . . . . . .+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
) . . . . . . . . . . . 0°C to +70°C
A
) . . . . . . . . . –40°C to +85°C
A
) . . . . . . . . –55°C to +125°C
A
Am29LV008B 21
Page 22
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
= VSS to VCC,
V
I
I
LIT
I
LO
I
CC1
LI
Input Load Current
A9 Input Load Current VCC = V
Output Leakage Current
VCC Active Read Current
(Note 1)
IN
V
= VCC
CC
= VSS to VCC,
V
OUT
V
= V
CC
CE# = V
max
; A9 = 12.5 V 35 µA
CC max
CC max
5 MHz 7 12
OE#
IL,
= VIH
1 MHz 2 4
±1.0 µA
±1.0 µA
mA
V
V
V
I
CC2
I
CC3
I
CC4
I
CC5
V
V
V
V
OH1
OH2
LKO
OL
VCC Active Write Current
(Notes 2 and 4)
VCC Standby Current
VCC Standby Current During Reset
Automatic Sleep Mode (Note 3)
IL
IH
ID
Input Low Voltage –0.5 0.8 V
Input High Voltage 0.7 x V
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage IOL = 4.0 mA, VCC = V
Output High Voltage
Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V
CE# = V
V
CC
CE#, RESET# = V
VCC = V
RESET# = V
V
IH
V
IL
= V
= V
= V
IL,
CC max
CC max
CC
± 0.3 V
SS
OE#
= VIH
;
;
± 0.3 V
SS
± 0.3 V;
CC
±0.3 V
VCC = 3.3 V 11.5 12.5 V
0.45 V
CC min
I
= –2.0 mA, VCC = V
OH
IOH = –100 µA, VCC = V
CC min
CC min
0.85 V
VCC–0.4
Notes:
1. The I
2. I
current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
CC
active while Embedded Erase or Embedded Program is in progress.
CC
3. Automatic sleep mode enables the low power mode when addresses remain stable for t
4. Not 100% tested.
CC
CC
ACC
15 30 mA
0.2 5 µA
0.2 5 µA
0.2 5 µA
VCC + 0.3 V
V
+ 30 ns.
22 Am29LV008B
Page 23
PRELIMINARY
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
Supply Current in mA
0
0 500 1000 1500 2000 2500 3000 3500 4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
10
8
6
4
Supply Current in mA
2
0
12345
21524B-12
3.6 V
2.7 V
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical I
Am29LV008B 23
vs. Frequency
CC1
21524B-13
Page 24
TEST CONDITIONS
Device
Under
Test
C
L
6.2 kΩ
PRELIMINARY
3.3 V
2.7 kΩ
Output Load 1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Table 7. Test Specifications
-70R,
Test Condition
L
-90,
-80
30 100 pF
-120 Unit
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
21524B-14
Input timing measurement
reference levels
Output timing measurement
reference levels
Steady
Changing from H to L
Changing from L to H
1.5 V
1.5 V
KS000010-PAL
3.0 V
0.0 V
1.5 V 1.5 V
Figure 12. Input Waveforms and Measurement Levels
24 Am29LV008B
OutputMeasurement LevelInput
21524B-15
Page 25
AC CHARACTERISTICS
Read Operations
PRELIMINARY
Parameter
JEDEC Std Test Setup -70R -80 -90 -120 Unit
t
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
Read Cycle Time (Note 1) Min 70 80 90 120 ns
RC
t
Address to Output Delay
ACC
t
Chip Enable to Output Delay OE# = V
CE
t
Output Enable to Output Delay Max 30 30 35 50 ns
OE
t
Chip Enable to Output High Z (Note 1) Max 25 25 30 30 ns
DF
t
Output Enable to Output High Z (Note 1) Max 25 25 30 30 ns
DF
Description
CE# = V
OE# = V
IL
Max 70 80 90 120 ns
IL
Max 70 80 90 120 ns
IL
Speed Option
Read Min 0 ns
Output Enable
t
t
AXQX
OEH
Hold Time (Note 1)
Output Hold Time From Addresses, CE# or
t
OH
OE#, Whichever Occurs First (Note 1)
Toggle and
Data# Polling
Min 10 ns
Min 0 ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
t
RC
Addresses
CE#
OE#
WE#
Outputs
RESET#
RY/BY#
0 V
Addresses Stable
t
ACC
t
OE
t
OEH
t
CE
HIGH Z
Output Valid
Figure 13. Read Operations Timings
t
DF
t
OH
HIGH Z
21524B-16
Am29LV008B 25
Page 26
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
PRELIMINARY
Description All Speed OptionsJEDEC Std Test Setup Unit
t
READY
t
READY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
RESET# Pulse Width Min 500 ns
RP
RESET# High Time Before Read (See Note) Min 50 ns
t
RH
RESET# Low to Standby Mode Min 20 µs
t
RPD
RY/BY# Recovery Time Min 0 ns
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
t
RP
t
Ready
Max 20 µs
Max 500 ns
t
RH
RY/BY#
CE#, OE#
RESET#
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
t
RP
Figure 14. RESET# Timings
t
RB
21524B-17
26 Am29LV008B
Page 27
AC CHARACTERISTICS
Erase/Program Operations
Parameter
t
t
AVAV
t
AVWL
t
WLAX
t
DVWH
t
WHDX
t
GHWL
t
t
GHWL
Write Cycle Time (Note 1) Min 70 80 90 120 ns
WC
t
Address Setup Time Min 0 ns
AS
t
Address Hold Time Min 45 45 45 50 ns
AH
t
Data Setup Time Min 35 35 45 50 ns
DS
t
Data Hold Time Min 0 ns
DH
Output Enable Setup Time Min 0 ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
PRELIMINARY
-70R -80 -90 -120JEDEC Std Description Unit
Min 0 ns
t
ELWL
t
WHEH
t
WLWH
t
WHWL
t
WHWH1tWHWH1
t
WHWH2tWHWH2
t
CS
t
CH
t
WP
t
WPH
t
VCSVCC
t
RB
t
BUSY
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 35 35 35 50 ns
Write Pulse Width High Min 30 ns
Programming Operation (Note 2) Typ 9 µs
Sector Erase Operation (Note 2) Typ 0.7 sec
Setup Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 90 ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29LV008B 27
Page 28
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
PRELIMINARY
Read Status Data (last two cycles)
Addresses
CE#
OE#
WE#
Data
RY/BY#
V
CC
t
VCS
t
WC
555h
t
GHWL
t
CS
t
WP
t
DS
A0h
t
DH
t
AS
PA PA
t
AH
t
CH
t
WHWH1
t
WPH
PD
t
BUSY
PA
Status
D
OUT
t
RB
Note: PA = program address, PD = program data, D
Figure 15. Program Operation Timings
is the true data at the program address.
OUT
21524B-18
28 Am29LV008B
Page 29
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) Read Status Data
PRELIMINARY
Addresses
CE#
OE#
WE#
Data
RY/BY#
V
CC
t
VCS
t
WC
2AAh SA
555h for chip erase
t
GHWL
t
CH
t
WP
t
t
CS
t
DS
t
WPH
DH
55h
t
AS
t
AH
30h
10 for Chip Erase
t
BUSY
t
WHWH2
VA
In
Progress
VA
Complete
t
RB
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
21524B-19
Figure 16. Chip/Sector Erase Operation Timings
Am29LV008B 29
Page 30
AC CHARACTERISTICS
Z
Z
Addresses
t
ACC
CE#
t
CH
OE#
t
OEH
WE#
DQ7
PRELIMINARY
t
RC
VA
t
CE
t
OE
t
DF
t
OH
Complement
VA VA
Complement
True
Valid Data
High
DQ0–DQ6
t
BUSY
Status Data
Status Data
True
Valid Data
High
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21524B-20
Figure 17. Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
CE#
OE#
WE#
DQ6/DQ2
RY/BY#
t
CH
t
BUSY
t
OEH
High Z
t
ACC
VA
t
CE
t
OE
t
DF
t
OH
(first read) (second read) (stops toggling)
VA VA
Valid Status
VA
Valid DataValid StatusValid Status
Note: VA = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21524B-21
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
30 Am29LV008B
Page 31
PRELIMINARY
AC CHARACTERISTICS
Enter
Embedded
Erasing
WE#
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Erase
Erase
Suspend
Erase Suspend
Enter Erase
Suspend Program
Read
Figure 19. DQ2 vs. DQ6
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Complete
Temporary Sector Unprotect
Parameter
All Speed OptionsJEDEC Std Description Unit
Erase
21524B-22
t
VIDR
t
RSP
Note: Not 100% tested.
RESET#
CE#
WE#
RY/BY#
VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector
Unprotect
Min 4 µs
12 V
0 or 3 V
t
VIDR
t
VIDR
0 or 3 V
Program or Erase Command Sequence
t
RSP
21524B-23
Figure 20. Temporary Sector Unprotect Timing Diagram
Am29LV008B 31
Page 32
AC CHARACTERISTICS
V
ID
V
RESET#
IH
PRELIMINARY
SA, A6,
A1, A0
Valid* Valid* Valid*
Sector Protect/Unprotect Verify
Data
60h 60h 40h
1 µs
Sector Protect: 100 µs
Sector Unprotect: 10 ms
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. Sector Protect/Unprotect Timing Diagram
Status
21524B-24
32 Am29LV008B
Page 33
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
70R 80 90 120JEDEC Std Description Unit
t
AVAV
t
AVEL
t
ELAX
t
DVEH
t
EHDX
t
GHEL
t
WLEL
t
EHWH
t
ELEH
t
EHEL
t
WHWH1
t
WHWH2
t
WC
t
AS
t
AH
t
DS
t
DH
t
OES
t
GHEL
t
WS
t
WH
t
CP
t
CPH
t
WHWH1
t
WHWH2
Write Cycle Time (Note 1) Min 70 80 90 120 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 45 50 ns
Data Setup Time Min 35 35 45 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 35 35 35 50 ns
CE# Pulse Width High Min 30 ns
Programming Operation
(Note 2)
Typ 9 µs
Sector Erase Operation (Note 2) Typ 0.7 sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29LV008B 33
Page 34
AC CHARACTERISTICS
555 for program
2AA for erase
PRELIMINARY
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
WE#
OE#
CE#
Data
RESET#
RY/BY#
PA
t
WC
t
WH
t
WS
t
RH
t
AS
t
GHEL
t
CP
t
CPH
t
DS
t
DH
A0 for program
55 for erase
t
AH
t
PD for program
30 for sector erase
10 for chip erase
BUSY
t
WHWH1 or 2
DQ7# D
OUT
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, D
to the device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 22. Alternate CE# Controlled Write Operation Timings
is the data written
OUT
21524B-25
34 Am29LV008B
Page 35
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 15 s
Chip Erase Time 14 s
Byte Programming Time 9 300 µs
Chip Programming Time
(Note 3)
927s
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V
= 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to V
(including A9, OE#, and RESE T#)
on all pins except I/O pins
SS
–1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
Current –100 mA +100 mA
V
CC
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V
Control Pin Capacitance VIN = 0 7.5 9 pF
= 0 8.5 12 pF
OUT
C
C
C
IN
OUT
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
= 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C 10 Years
125°C 20 Years
Am29LV008B 35
Page 36
PRELIMINARY
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP (measured in millimeters)
Pin 1 I.D.
1
40
0.95
1.05
9.90
10.10
0.50 BSC
20
18.30
18.50
19.80
20.20
1.20
MAX
0˚
5˚
21
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering.
0.05
0.15
0.08
0.20
0.10
0.21
16-038-TSOP-1_AE
TS 040
2-27-97 lv
36 Am29LV008B
Page 37
PRELIMINARY
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse TSOP (measured in millimeters)
Pin 1 I.D.
1
40
0.95
1.05
9.90
10.10
0.50 BSC
20
18.30
18.50
19.80
20.20
1.20
MAX
0˚
5˚
21
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering.
0.05
0.15
0.08
0.20
0.10
0.21
16-038-TSOP-1_AE
TSR040
2-27-97 lv
Am29LV008B 37
Page 38
PRELIMINARY
REVISION SUMMARY FOR AM29LV008B
Revision B
Distinctive Characteristics
Changed typical read and program/era se current specifications.
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Figure 1, In-System Sector Protect/Unprotect
Algorithm
Corrected A6 to 0, Changed wait specification to 150
µs on sector protect and 15 ms on sector unprotect.
DC Characteristics
Changed typical read and program/era se current specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:
Changed tCP to 35 ns for 70R, 80, and 90 speed
options.
Erase and Programming Performance
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Revision B+1
Figure 1, In-System Sector Protect/Unprotect
Algorithms
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect anot her sector?” back to setting up the next sector address.
DC Characteristics
Changed Note 1 to indicate that OE# is at V
listed current.
AC Characteristics:
Erase/Program Operations; Altern ate CE# Controlled
Erase/Program Operations:
ence for t
WHWH1
and t
Corrected the notes refer-
. These parameters are
WHWH2
100% tested. Corrected the note reference for t
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for t
. This parameter is not
VIDR
100% tested.
Figure 21, Sector Protect/Unpro tect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
for t he
IH
VCS
.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cycles.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
38 Am29LV008B
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