AMD Advanced Micro Devices AM29LV004T-90RFIB, AM29LV004T-90RFEB, AM29LV004T-90RFCB, AM29LV004T-90RFC, AM29LV004T-90REIB Datasheet

PRELIMINARY

This document contains in formation on a product under development at Adv anced Micro Device s . The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

Publication# 20510 Rev: D Amendment/+1
Issue Date: March 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29LV004

4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memo r y

DISTINCTIVE CHARACTERISTICS

■ Single p ower supply operation

— Full vol t ag e r ange : 2. 7 t o 3.6 v o l t re ad an d w r ite

operations f or battery-powered app licati ons

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with
high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

ns

— Regulated voltage range: access times as fast

as 90 ns

■ Ultra low power consumptio n (typical values at

5 MHz)

— 200 nA Automatic Sleep mo de current
— 200 nA sta ndby mode current
— 10 mA read current
— 20 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

preve nt any program or erase operations within

that sector

Sectors can be locked via programming

equipment

T empor ary Sect or Unprote ct featu re allows c ode

changes in previously locked sectors

■ Top or bottom boot block configurations

available

■ Embedded Algorithms

— Embedded Erase al gorithm automatically

preprograms and erases the entire chi p or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies d ata at sp ecified addresses

■ Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■ Package option

— 40-pin TSOP

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write p r otection

■ Data# Polling a nd toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Bu sy # pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Su s pe nd/E r as e Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

2 Am29LV004

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV004 is an 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)

data appe ars on DQ7 –DQ 0. This devic e requ ires onl y
a single, 3.0 volt V

CC

supply to pe rf o rm r ea d, pr og ra m,
and erase operations. A stan dard EPROM pro­grammer can als o be us ed to pr ogram a nd erase the
device.

The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten­tion the d evice ha s separat e chip en able (CE #), writ e
enable (WE#) and outp ut enabl e (OE#) controls.

The device requires only a single 3.0 volt power sup-
ply for both rea d an d write fu nct ions. Interna l ly g en er ­ated and r egulated voltages a re provided for th e
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands ar e w ri tt en to th e c om ma nd re gi s ter us i ng st a n­dard micr opro cess or wr ite timi ngs. R egi ster c ont ents
serve as input to an internal state-machine that con­trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
progra mming and e rase o pera tion s. Re ading d ata ou t
of the de vice is s imilar to readin g from o ther Flas h or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matical ly time s the program pulse widths and ver ifies
proper cell margin.

Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo­rithm—an internal algorithm that automatically prepro­grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.

The host system can detect whether a program or
erase op eratio n is co mpl ete by o bse rving th e RY/B Y#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been com p lete d, the devic e is re ady to read a rra y
data o r accept another command.

The sector erase architecture allows memory sect ors
to be er ased and reprog rammed withou t affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a l ow
V

CC

detector that au tomatically inhibits write opera­tions during power transitions. The hardware sector
protection feature disables both program and erase
operat ions in any combina tion of the s ectors of m em­ory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates a ny operatio n
in progress and resets the internal state machine to
reading array data. The RESET# pin may b e ti ed to t he
system reset circuitry. A system reset would thus als o
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When
addres ses have been stable for a s p ec i fied amount o f
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power co nsumpt ion is greatly reduc ed in bot h
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all b its with in
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV004 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29LV004

Speed Options

Regulated Voltage Range: VCC =3.0–3.6 V -90R

Full Voltage Range: VCC = 2.7–3.6 V -100 -120 -150

Max access time, ns (t

ACC

) 90 100 120 150
Max CE# access time, ns (tCE) 90 100 120 150
Max OE# access time, ns (tOE) 40 40 40 55

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

Register

V

CC

V

SS

WE#

CE#

OE#

STB

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

21522A-1

4 Am29LV004

PRELIMINARY

CONNECTION DIAGRAMS

1

16

2
3
4
5
6
7
8

17
18
19
20

9
10
11
12
13
14
15

40

25

39
38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A5

A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

A18

A7
A6

A4
A3
A2
A1

A17

DQ0

V

SS

NC
NC
A10
DQ7
DQ6
DQ5

OE#
V

SS

CE#
A0

DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1

1

16

2
3
4
5
6
7
8

17
18
19
20

9
10
11
12
13
14
15

40

25

39
38
37
36
35
34
33
32
31
30
29
28
27
26

24
23
22
21

A16

A5

A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6

A4
A3
A2
A1

A17

DQ0

V

SS

NC
NC

A10
DQ7
DQ6
DQ5

CE#

V

SS

CE#

A0

DQ4

V

CC

V

CC

NC
DQ3
DQ2
DQ1

21522A-2

Reverse TSOP

Standard TSOP

Am29LV004 5

PRELIMINARY

PIN CONFIGURATION

A0–A18 = 19 addresse s
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
V

CC

= 3.0 volt-only single power supply

(see Product Selector Guide for speed
options and voltage supply tolerances)

V

SS

= Device ground

NC = Pin not connected internally

LOGIC SYMBOL

21522A-3

19

8

DQ0–DQ7

A0–A18

CE#
OE#

WE#
RESET#

RY/BY#

6 Am29LV004

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD sta nd ar d p rod ucts are av a il ab le i n seve ral packa ge s and opera ti ng ra ng es. The order nu mb er (Valid Co mb i ­nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DE SCRIP TION

Am29LV004
4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

CET

Am29LV004

-90R

OPTIONAL PROCESSING

Blank = Standard Proces sing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

Valid Combinations

Am29LV004T-70R,
Am29LV004B-70R

EC, EI, FC, FI

Am29LV004T-80,
Am29LV004B-80

EC, EI, EE, FC, FI, FE

Am29LV004T-90,
Am29LV004B-90

Am29LV004T-120,
Am29LV004B-120

Am29LV004 7

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memo ry location.
The reg iste r is co mposed of lat che s that store the co m­mands, along with the address and data information
needed to execu te the com mand . The co nte nts of th e

register serve a s input s to the inter nal sta te mac hine.
The state machine outputs dictate the function of the
device. Table 1 lists the devi ce bus op erat ions , the in­puts and control levels they require, and the resulting
output. The following subsections describe eac h of
these operations in further detail.

Table 1. Am29LV004 Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

OUT

= Data Out

Note: Addresses are A18–A0.

Requirements for Reading Array Data

To read array dat a from the ou tputs, the sys tem must
drive the CE# and OE # pins to V

IL

. CE# is the power
control an d sel ects the de vice . OE# is th e outpu t con­trol and gates array data to the output pins. WE#
should remain at V

IH

.

The internal state machine is set for reading array
data upon devic e power-up, or aft er a hardware re set .
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessary i n this mode to obtain array
data. Standard micropr ocessor read cycles that as­sert valid addresses on the device add ress inputs pr o­duce valid data on the device data outputs. The
device remains enabled for read access unt il the com­mand register contents are altered.

See “R ead ing Ar ray Data” fo r more info rmatio n. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 12 for the timing diagram. I

CC1

in

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory ), the sy stem m ust drive WE# an d
CE# to V

IL

, and OE# to VIH.

An eras e op e ra tio n ca n er ase on e s ect or, multipl e se c­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad­dress” cons ists of the address bits required to uniquely
select a sector. The “Command Defini tions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can th en re ad aut ose lect codes fr om th e inter ­nal register (which is separate from the memory array)
on DQ7– DQ0 . St anda rd r ead cycle ti ming s ap ply in this
mode. Re fer to th e “ Autosele ct Mo de” an d “ Au to select
Command Sequence” sections for more information.

I

CC2

in the DC Charac teristics table represents the ac­tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specificati ons apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Operation CE# OE# WE# RESET# Addresses (See Note) DQ0–DQ7

Read L L H H A

IN

D

OUT

Write L H L H A

IN

D

IN

Standby

V

CC

±

0.3 V

XX

VCC ±

0.3 V

X High-Z

Output Disable L H H H X High-Z
Reset X X X L X High-Z
Temporary Sector Unprotect X X X V

ID

A

IN

D

IN

8 Am29LV004

PRELIMINARY

Standby Mode

When th e sy st em is not read ing or wr itin g to the dev ice,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The dev ice en ter s t he CM OS st an dby mode wh en the
CE# and RESET# pins are both held at V

CC

± 0.3 V.
(Note th at thi s is a mor e res trict ed vol tage rang e tha n
V

IH

.) If CE# and RESET# are held at VIH, but no t wit hin

V

CC

± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t

CE

) for read access when the
device is i n e ith er of these st and by modes, before it is
ready to read data.

If the device i s desele cte d during erasur e or pro gram ­ming, the device draws active current until the
operation is completed.

In the DC C haracte ristic s tabl es, I

CC3

and I

CC4

repre-

sents the standby current specification.

Automatic Sleep Mode

The au tomatic sl eep mode m inimizes F lash devi ce
energy co nsumption. The device autom atically
enables this mode when addresses remain stable for
t

ACC

+ 30 ns. The automatic sleep mode is indepen­dent of the CE # , WE #, an d O E # co ntr ol s i gn als. St an ­dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system. I

CC5

in the DC Characteristics table represents the auto­matic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the RE-

SET# pin is driven low for at least a per iod of t

RP

, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET #
pulse. When RESET# is held at V

SS

±0.3 V, the device

draws CMOS standby current (I

CC4

). If RESET# is held

at V

IL

but no t wi t hin VSS±0.3 V, the standby current will

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system rese t would thus also res et th e Flas h
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

READY

(during Embedded Algorithms ). The
system can thus m onitor RY/BY# to determine
whether the reset op erati on is c ompl ete. If R ESET # is
asserted when a prog ram or erase operati on is not ex ­ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t

READY

(not during Embed-

ded Algorithms). The system can read data t

RH

after

the RESET# pin returns to V

IH

.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabl e d . Th e o ut p ut pi n s ar e pl a c ed i n t he h igh i m ped­ance state.

Am29LV004 9

PRELIMINARY

Table 2. Am29LV004T Top Boot Block Sector Address Table

Table 3. Am29LV004B Bottom Boot Block Sector Address Table

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to auto mati ca lly match a de vice to b e pr ogra mmed with
its corresponding programming al gorithm. However,
the aut osel ect co des can also be a cces sed in -sy stem
through the command register.

When using programming equipment, the autoselect
mode requires V

ID

(1 1.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in Table

4. In addition, when verifying sector protection, the sec-

tor address must appear on the appropriate highest
order address bits (see Tables 2 and 3). Table 4 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding iden­tifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V

ID

. See “Command Definitions” for

details on using the autoselect mode.

Sector A18 A17 A16 A15 A14 A13

Sector Size

(Kbytes)

Address Range

(in hexadecimal)

SA0 0 0 0 X X X 64 00000h-0FFFFh
SA1 0 0 1 X X X 64 10000h-1FFFFh
SA2 0 1 0 X X X 64 20000h-2FFFFh
SA3 0 1 1 X X X 64 30000h-3FFFFh
SA4 1 0 0 X X X 64 40000h-4FFFFh
SA5 1 0 1 X X X 64 50000h-5FFFFh
SA6 1 1 0 X X X 64 60000h-6FFFFh
SA7 1 1 1 0 X X 32 70000h-77FFFh
SA8 1 1 1 1 0 0 8 78000h-79FFFh
SA9 1 1 1 1 0 1 8 7A000h-7BFFFh

SA10 1 1 1 1 1 X 16 7C000h-7FFFFh

Sector A18 A17 A16 A15 A14 A13

Sector Size

(Kbytes)

Address Range

(in hexadecimal)

SA0 0 0 0 0 0 X 16 00000h-03FFFh
SA1 0 0 0 0 1 0 8 04000h-05FFFh
SA2 0 0 0 0 1 1 8 06000h-07FFFh
SA3 0 0 0 1 X X 32 08000h-0FFFFh
SA4 0 0 1 X X X 64 10000h-1FFFFh
SA5 0 1 0 X X X 64 20000h-2FFFFh
SA6 0 1 1 X X X 64 30000h-3FFFFh
SA7 1 0 0 X X X 64 40000h-4FFFFh
SA8 1 0 1 X X X 64 50000h-5FFFFh
SA9 1 1 0 X X X 64 60000h-6FFFFh

SA10 1 1 1 X X X 64 70000h-7FFFFh

10 Am29LV004

PRELIMINARY

Table 4. Am29LV004 Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hard­ware sector unprotection feature re-enables both pro­gram and eras e operat ions in p reviou sly prot ected
sectors.

The device is shipped with all secto rs unprotected .
AMD offers the option of progra mming and prote cting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.

It is p ossi ble t o det ermi ne wh ethe r a s ector is p rotec ted
or unprotected. See “Autoselect Mo de” for details.

Sector protection/unprotection must be implemented
using programming equipment.The procedure requires
a high voltage (V

ID

) on addr ess pin A9 a nd OE#. De ­tails on this method are provided in a supplement, pub­licat ion n umbe r 20 874. Cont act an A MD re pre senta tive
to request a copy .

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector U n pr ote ct m od e i s a cti va ted by s e tting th e R E­SET# pin t o V

ID

. During thi s mod e, form erly pr otecte d
sector s can b e pr o gr amm ed or er as ed by s ele ct i ng t he
sector addres ses. Once V

ID

is remove d fro m the RE -

SET# pin, all the previously protected sectors are
protected a gain. Figure 1 sh ows the algorithm, a nd
Figure 19 shows the timing diagrams, for this feature.

Description CE# OE# WE#

A18

to

A13

A12

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ7

to

DQ0

Manufacturer ID: AMD L L H X X V

ID

XLXLL 01h

Device ID: Am29LV004T
(Top Boot Block)

LLHXXV

ID

XLXLH B5h

Device ID: Am29LV004B
(Bottom Boot Block)

LLHXXV

ID

XLXLH B6h

Sector Protection Verification L L H SA X V

ID

XLXHL

01h

(protected)

00h

(unprotected)

START

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

ID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

Figure 1. Temporary Sector Unprotect Operation

21522A-4

Am29LV004 11

PRELIMINARY

Hardware Data Protection

The command sequence requir ement of unlock cycle s
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com­mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or prog ramm ing, w hich m ig ht othe rwis e be ca use d by
spurious system level signals during V

CC

power-up

and power-down transition s, or from system noise.

Low V

CC

Write I nhibit

When V

CC

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

CC

is greater t han V

LKO

. The system must p rovide the
proper signals to the control pins to prevent uninten­tional writes when V

CC

is greater than V

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
V

IL

, CE# = VIH or WE# = VIH. To initiate a writ e cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL

and OE# = VIH during po wer up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific ad dress and data commands or se­quences into the command register initiates device op­erations. Table 5 defines the valid register command
sequences. W riting incor rect ad dress and da ta val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after d evice power- up. N o comm ands ar e requ ired t o
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the de vice enters the E rase Suspend m ode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-susp ended sectors, the device outputs
status data. After completing a programming opera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

The syst em

must

issue the reset command to re-en­able the device for reading array data if DQ5 goes high,
or while in the a utoselect mode. Se e the “R eset C om ­mand” section, next.

See also “Requirements for Reading Array Data” in the
“Devic e B u s Op er at io ns ” section f or m ore i n for ma tion.
The Read Operations table provides the read parame­ters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de­vice to r ea di n g a rr ay da ta. A dd re ss bits ar e do n’t car e
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until t he operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programmi ng begins. This resets the device to
reading a rray data (a lso applie s to programm ing in
Erase Su spend mode ). Once p rogrammin g begins,
however, the device ignores r eset co m mand s until th e
operat ion i s comp l et e.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command

must

be written to re turn to re ading ar ray data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the res et comm and r eturn s th e devic e to re ad­ing array data (also applies during Erase Suspend).