AMD Am29LV004B Service Manual

ADVANCE INFORMATION

Am29LV004B

4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage r ange: 3.0 to 3.6 v olt read and

write operations and for compatibility with high
performance 3.3 volt microprocessors

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29LV004 device

■ High performance

— Full voltage range: ac cess times as f ast as 80 ns
— Regulated voltage range: access times as fast

as 70 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

available

■ Embedded Al gorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ Minimum 1,000,000 write cycle guarantee per

sector

■ Package option

— 40-pin TSOP

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

■ Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the de vi ce to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 21522 Rev: A Amendment/0
Issue Date: January 1998

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29LV004B is an 4 Mbit, 3.0 volt-only Flash
memory organiz ed as 524,288 bytes. The devi ce is
offered in a 40-pin TSOP package. The byte-wide (x8)

data appears on DQ7–DQ0. This device requires only
a single, 3.0 volt V
and erase operations. A stand ard EPROM pro­grammer can also be used to program and erase the
device.

This device is manufactured usin g AMD’s 0.35 µm
process technology, and offers all the f eatures an d ben­efits of the Am29L V004, which was manufactur ed using

0.5 µm process technology. In addition, the
Am29LV004B features unlock bypass programming
and in-system sector protection/unprotection.

The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.

The device requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co n­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by ex ecuting the erase command
sequence. This initiates the Embedded Erase algo­rithm—an i nternal algorithm that autom atically prepro ­grams the array (if it is not already programmed) before

supply to perform read, program,

CC

executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achiev ed.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

2 Am29LV004B

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV004B

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 70 80 90 120
Max OE# access time, ns (tOE) 30 30 35 50

Regulated Voltage Range: VCC =3.0–3.6 V -70R

Full Voltage Range: VCC = 2.7–3.6 V -80 -90 -120

) 70 80 90 120

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

DQ7

–

Input/Output

Buffers

Data

Latch

V

CC

V

SS

RESET#

WE#

CE#

OE#

RY/BY#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A18

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21522A-1

Am29LV004B 3

CONNECTION DIAGRAMS

ADVANCE INFORMATION

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RESET#

NC

RY/BY#

A18

A7
A6
A5
A4
A3
A2
A1

A17
V

SS

NC
NC

A10
DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0

CE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Standard TSOP

Reverse TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A17
V

SS

NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V

CC

V

CC

NC
DQ3
DQ2
DQ1
DQ0
OE#

V

SS

CE#
A0

A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1

4 Am29LV004B

21522A-2

ADVANCE INFORMATION

PIN CONFIGURATION

A0–A18 = 19 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed
options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

19

A0–A18

CE#
OE#

WE#
RESET#

8

DQ0–DQ7

RY/BY#

21522A-3

Am29LV004B 5

ADVANCE INFORMATION

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

Am29LV004B

-70R

CET

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LV004B
4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Am29LV004BT-70R,
Am29LV004BB-70R

Am29LV004BT-80,
Am29LV004BB-80

Am29LV004BT-90,
Am29LV004BB-90

Am29LV004BT-120,
Am29LV004BB-120

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

EC, EI, FC, FI

EC, EI, EE, FC, FI, FE

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Valid Combinations

6 Am29LV004B

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