AMD Advanced Micro Devices AM29LV002T-90RFIB, AM29LV002T-90RFI, AM29LV002T-90RFEB, AM29LV002T-90RFE, AM29LV002T-90RFC Datasheet

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PRELIMINARY

Am29LV002

2 Megabi t (256 K x 8-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single p ower su pply operation

— Full vol t ag e r ange : 2. 7 t o 3.6 v o l t re ad an d w r ite

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read

and write operations and for compatibility with high performance 3.3 volt microprocessors

■ High performance

— Full voltage range: access times as fast as 100

— Regulated voltage range: access times as fast

as 90 ns

■ Embedded Algorithms

— Embedded Erase a lgorithms au tomatically

preprogram and erase the entire chip or any combination of designated sectors

— Embedded Program algorithms automatically

write and veri fy bytes or w ords at specified addres ses

■ Typical 1,000,000 write cycles per sector

(100,000 cycles minimum guaranteed)

■ Package option

— 40-pin TSOP

■ Ultra low power consumption (typical values at

5 MHz)

— Automatic Sleep Mode: 200 nA — Standby mode: 200 nA — Read mode: 10 mA — Program/erase mode: 20 mA

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyt e sectors

— Supports control code and data storage on a

single device

— Sector Protection features:

A hardware method of locking a sector to preve nt any prog ram or erase operations within that sector

T empor ary Sect or Unprote ct featu re allows c ode changes in previously locked sectors

■ Top or bottom boot block confi gurations

available

■ Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation compl etion

■ Ready/Bu sy # pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■ Erase Su s pe nd/E r as e Resume featur e

— Suspends an erase operation to read data from,

or program data to, a sector that is not being erased, then resumes the erase operation

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to the read

mode

Issu e Date: March 1998

.Publication# 21191 Rev: C Amendment/+2

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV002 is a 2 Mbit, 3.0 Volt-only Flash memory organized as 262,144 bytes. The device is offered in a 40-pin TSOP package. The byt e-wide (x8)

data appears on DQ7– DQ0. All read, program, an d erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers.

The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. T o eliminate bus contention the d evice ha s separat e chip en able (CE #), writ e enable (WE#) and output enable (OE#) controls .

The device requires only a single 3.0 volt power sup- ply for both rea d an d write functions. Inte rna l ly g en er ated and r egulated voltages a re provided for th e program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the er ase and programming ci rcuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data ou t of the de vice is si milar to r eading fr om othe r Flash or EPR O M dev ic es.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatical ly time s the program pulse widths and ver ifies proper cell margin.

Device erasure occurs by executing the erase command se quence. T his init iates th e Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device au tom atically time s th e e ra se pulse widths an d verifies proper cell margin.

The host system can detect whether a program or erase op eratio n is co mpl ete by o bse rving th e RY/B Y# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been com p lete d, the device i s re ad y to rea d a rra y data o r accept another command.

The sector erase architecture allow s memo ry s ector s to be er ased and reprog rammed withou t affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low V

detector that au tomatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operat ions in any combina tion of the s ectors of m emory. This is achieved via programming eq uipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates a ny operatio n in progress and resets the internal state machine to reading array data. The RESET# pin may b e ti ed to t he system reset circuitry. A system reset would thus als o reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When addres ses have be en stable for a s p ec if ied a mo un t o f time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power co nsumpt ion is greatly reduc ed in bot h these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits w ithin a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29LV002

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV002 Ordering Part Number: VCC = 3.0–3.6 V (regulated voltage range) -90R

VCC = 2.7–3.6 V (full voltage range) -100 -120 -150 Max access time (ns) 90 100 120 150 CE# access time (ns) 90 100 120 150 OE# access time (ns) 40 40 50 55

BLOCK DIAGRAM

RESET#

WE#

CE OE

A0–A17

RY/BY#

State

Control

Command

PGM Voltage

Generator

TimerVCC Detector

Sector

Switches

Erase Voltage

Generator

Output Enable

STB

Chip Enable

Logic

Y-Decoder

Address Latch

Input/Output

STB

DQ0–DQ7

Buffers

Data Latch

Y-Gating

Cell MatrixX-Decoder

21191C-1

Am29LV002 3

CONNECTION DIAGRAMS

PRELIMINARY

A16 A15 A14 A13 A12 A11

A9 A8

WE#

RESET#

RY/BY#

A7 A6 A5 A4 A3 A2 A1

A17 V

NC NC

A10 DQ7 DQ6 DQ5 DQ4

NC DQ3 DQ2 DQ1 DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Standard 40-Pin TSOP

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A17 V

NC NC A10 DQ7 DQ6 DQ5 DQ4 V

NC DQ3 DQ2 DQ1 DQ0 OE#

CE# A0

A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1

Reverse 40-Pin TSOP

4 Am29LV002

21191C-2

PRELIMINARY

PIN CONFIGURATION

A0–A17 = 18 add re ss e s DQ0–DQ7 = 8 data inputs/o utputs CE# = Chip enable WE# = Write enable OE# = Output enable RESET# = Reset pin RY/BY# = Ready/Busy# pin V

= 3.0 volt-only single power supply

NC = Pin not connected internally

(see Product Selector Guide for speed

options and voltage supply tolerances)

= Device ground

LOGIC SYMBOL

A0–A17

CE# OE#

WE# RESET# RY/BY#

DQ0–DQ7

21191C-3

Am29LV002 5

PRELIMINARY

ORDERING INFORMATION Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE-90RAM29LV002 T

OPTIONAL PROCESSING

Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

AM29LV002T-90R, AM29LV002B-90R

= 3.0–3.6 V

AM29LV002T-100, AM29LV002B-100

AM29LV002T-120, AM29LV002B-120

AM29LV002T-150, AM29LV002B-150

Valid Combinations

EC, EI, FC, FI

EC, EI, EE,

FC, FI, FE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector B = Bottom Sector

DEVICE NUMBER/DE SCRIP TION

Am29LV002 2 Megabit (256 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Program and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

6 Am29LV002

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memo ry location. The reg iste r is co mposed of lat che s that store the co mmands, along with the address and data information needed to execu te the com mand . The co nte nts of th e

Table 1. Am29LV002 Device Bus Operations

Operation CE# OE# WE# RESET# Addresses DQ0–DQ7

Read L L H H A Write L H L H A

Standby Output Disable L H H H X High-Z

Reset X X X L X High-Z Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

0.3 V

register serve a s input s to the inter nal sta te mac hine. The state machine outputs dictate the function of the device. Table 1 lists the devi ce bus op erat ions , the inputs and control levels they require, and the resulting output. The following subsections describe eac h of these operations in further detail.

= Data Out

OUT

VCC ±

0.3 V

IN IN

X High-Z

Requirements for Reading Array Data

To read arra y data from the ou tputs, the sys tem must drive the CE# and OE # pins to V

. CE# is the power

control an d sel ects the de vice . OE# is th e outpu t control and gates array data to the output pins. WE# should remain at V

The int er na l st a te ma c hin e i s s et f or re ad i ng ar ra y da ta upon d evic e p ower-up, or a fter a ha rd w ar e res et. This ensures that no spurious alteration of the memory content oc cur s du ring the pow er tra nsi tion . N o comma nd i s necessary in this mod e to obtain array da ta. Stand ard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered .

See “R ead ing Ar ray Data” fo r more info rmatio n. Refer to the AC Read Operations table for timing specifications and to Figure 12 for the timing waveforms. I

CC1

the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory ), the sy stem m ust drive WE# an d CE# to V

, and OE# to VIH.

An eras e op e ra tio n ca n er ase on e s ect or, multipl e s ectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consist s of the address bits required to uniquely select a sector. See the “Command Definitions” section for d eta i ls o n er asi n g a se c t or o r th e e nt ire c h ip, or su spending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can th en re ad aut ose lect codes fr om th e inter nal register (which is separate from the memory array) on DQ7– DQ0 . St anda rd r ead cycle ti ming s ap ply in this mode. Re fer to th e “ Autoselect Mode” and “Auto sel e ct Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The AC Charac ter isti cs se ctio n co ntai ns tim ing speci fi cati on tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I read specificati ons apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.

Am29LV002 7

PRELIMINARY

Standby Mode

When th e sy st em is not read ing or wr itin g to the dev ice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The dev ice en ter s t he CM OS st an dby mode wh en th e CE# and RESET# pins are both held at V

± 0.3 V. (Note th at thi s is a mor e res trict ed vol tage rang e tha n V

.) If CE# and RESET# are held at VIH, but no t wit hin

± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires standard access time (t

) for read access when the

device is i n e ith er of these stand by modes, b efore it is ready to read data.

If the device i s desele cte d during erasur e or pro gram ming, the device draws active current until the operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specifications.

Automatic Sleep Mode

The au tomatic sl eep mode m inimizes F lash devi ce energy co nsumption. The device automatically enables this mode when addresses remain stable for t

+ 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in the D C Characteris tics table

CC5

represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system

drives the RESET# pin to V

for at le ast a per iod of tRP,

the device immediately terminates any operation in progress , tri states all da ta output p ins, and igno res all read/write atte mpts for the durati on of the RESET# pulse. The device also resets the internal state machine to reading array data. The oper ation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET # pulse. When RESET# is held at V

draws CMOS standby current (I at V

but no t wi t hin VSS±0.3 V, the standby current will

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system rese t would thus also res et th e Flas h memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, whi ch requires a time of t

(durin g Embedde d Algorit hms). The

READY

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY # pin is “1 ”), the re set oper ation is c omplet ed within a time of t rithms). The system can read data t SET# pin returns to V

(not during Embedded Algo-

READY

after the RE-

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabl e d . Th e o ut p ut pi n s ar e pl a c ed i n t he h igh i m pedance state.

8 Am29LV002

PRELIMINARY

Table 2. Secto r Add re ss Tables (Am29LV002T)

Sector A17 A16 A15 A14 A13 Sector Size Address Range

SA0 0 0 X X X 64 Kbytes 00000h–0FFFFh SA1 0 1 X X X 64 Kbytes 10000h–1FFFFh SA2 1 0 X X X 64 Kbytes 20000h–2FFFFh SA3 1 1 0 X X 32 Kbytes 30000h–37FFFh SA411100 8 Kbytes 38000h–39FFFh SA511101 8 Kbytes 3A000h–3BFFFh SA61111X 16 Kbytes 3C000h–3FFFFh

Table 3. Sector Add ress Tables (Am29LV002B)

Sector A17 A16 A15 A14 A13 Sector Size Address Range

SA00000X 16 Kbytes 00000h–03FFFh SA100010 8 Kbytes 04000h–05FFFh SA200011 8 Kbytes 06000h–07FFFh SA3 0 0 1 X X 32 Kbytes 08000h–0FFFFh SA4 0 1 X X X 64 Kbytes 10000h–1FFFFh SA5 1 0 X X X 64 Kbytes 20000h–2FFFFh SA6 1 1 X X X 64 Kbytes 30000h–3FFFFh

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to auto mati ca lly match a de vice to b e pr ogra mmed with its corresponding programming al gorithm. However, the aut osel ect co des can also be a cces sed in -sy stem through the command register.

When using programming equipment, the autoselect mode requires V

(11.5 V to 12. 5 V) on addr ess pin

A9. Addre ss pins A6, A1, and A0 must be as sho wn i n Table 4. In addition, when verifying sector protection,

the sector ad dress must app ear on the appro priate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require V

. See “Command Definitions” for

details on using the autoselect mode.

Am29LV002 9

PRELIMINARY

Table 4. Am29LV002 Autoselect Codes (High Voltage Method)

Description CE# OE# WE#

A17

A13

A12

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X V Device ID: Am29LV002T

(Top Boot Block) Device ID: Am29LV002B

(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

LLHXXV

XLXLL 01h

XLXLH 40h

XLXLH C2h

XLXHL

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and eras e operat ions in p reviou sly prot ected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (V OE#. D eta ils o n this method ar e pr ovid ed i n a sup pl e ment, publication number 21224. Contact an AMD representative to request a copy.

The device is shipped with all secto rs unprotected . AMD offers the option of progra mming and prote cting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.

) on address pin A9 and

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

01h

(protected)

00h

(unprotected)

It is p ossi ble t o det ermi ne wh ethe r a s ector is p rotec ted or unprotected. See “Autoselect Mode” for details .

Notes:

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

ously protected sectors to change data in-system. The Sector U n pr ote ct m od e i s a cti va ted by s e tting th e R ESET# pin t o V

. During thi s mod e, form erly pr otecte d

Figure 1. Temporary Sector Un protec t Operation

sector s can b e pr o gr amm ed or er as ed by s ele ct i ng t he sector addres ses. Once V

is remove d fro m the RE -

SET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 19 shows the timing waveforms, for this feature.

10 Am29LV002

21191C-4

again.

PRELIMINARY

Hardware Data Protection

The command sequence requir ement of unlock cycle s for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or prog ramm ing, w hich m ig ht othe rwis e be ca use d by spurious system level signals during V

power-up

and power-down transition s, or from system noise.

Low V

When V cept any write cycles. This protects data during V

Write I nhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater t han V

. The system must p rovide the

LKO

COMMAND DEFINITIONS

Writing specific ad dress and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. W riting incor rect ad dress and da ta val- ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after d evice power- up. N o comm ands ar e requ ired t o retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the dev ice enters the Erase Susp end m ode . The sys tem can read ar ray data using th e standa rd read timings, except that if it reads at an address within erasesuspended sectors, the device outpu ts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/ Erase Resume Commands” for more information on this mode.

The system ble the device for reading array data if DQ5 goes high, or while in the a utoselect mode. Se e the “R eset C om mand” section, next.

must

iss ue t he r eset comm a nd t o re-ena -

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

, CE# = VIH or WE# = VIH. To initiate a write cycle ,

CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during po wer up, the

device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

See also “Requirements for Reading Array Data” in the “Devic e B u s Op er at io ns ” section f or m ore in for ma t ion . The Read Operations table provides the read parameters, and Figure 12 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to r ea di n g a rr ay da ta. A dd re ss bits are do n’ t car e for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This reset s the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is compl ete.

The reset command may be written between the sequence cycles in a program command sequence before programmi ng begins. This resets the device to reading a rray data (a lso applie s to programm ing in Erase Su spend mode ). Once p rogrammin g begins, however, the device ignores r eset co m mand s until th e operat ion i s comp l et e.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command be written to re turn to re ading ar ray data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the res et comm and r eturn s th e devic e to re ading array data (also applies during Erase Suspend).

See “AC Characteristics” for parameters, and to Figure 13 for the timing diagram.

must

Am29LV002 11

+ 23 hidden pages