AMD Am29LV001B Service Manual

查询AM29LV001B供应商

PRELIMINARY

Am29LV001B

1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sec tor Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— Full voltage range: 2.7 to 3. 6 volt read and write

operations for battery-powered applications

— Regulated voltage r ange: 3.0 to 3.6 v olt read and

write operations and for compatibility with high
performance 3.3 volt microprocessors

■ Manufactured on 0.35 µm process technology

■ High performance

— Full voltage range: ac cess times as f ast as 55 ns
— Regulated voltage range: access times as fast

as 45 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current

■ Flexible sector architecture

— One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte
— Supports full chip erase
— Sector Protection features:

Hardware method of loc king a sector to prevent
any program or erase operat ions within that
sector

Sectors can be locked in-system or via
programming equipment

T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors

■ Unlock Bypass Mode Program Co mmand

■ Top or bottom boot block configurations

■ Embedded Al gorithms

■ Minimum 1,000,000 write cycle guarantee per

■ Package option

■ Compatibility with JEDEC standards

■ Data# Polling and toggle bits

■ Erase Suspend/Erase Resume

■ Hardware reset pin (RESET#)

— Reduces overall programming time when

issuing multiple program command sequences

available

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

sector

— 32-pin TSOP
— 32-pin PLCC

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

— Provides a software method of detecting

program or erase operation completion

— Supports reading data from or programming

data to a sector that is not being erased

— Hardware method for resetting the device to

reading array data

Publication# 21557 Rev: C Amendment/0
Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash
memory devic e organized as 131,072 bytes. T he
Am29LV001B has a boot sector architecture.

The device is offered in 32-pin PLCC and 32-pin TSOP

packages. The byte-wide (x8) data appears on DQ7–
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in s tandard EPROM
programmers.

The standard Am29LV001B offers access times of 45,
55, 70, and 90 ns, allowing high speed m icroproces­sors to operate without wait states. To eliminate bus
contention, the device has separate chip enab le (CE#),
write enable (WE#) and output enable (OE#) controls.

The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.

The Am29LV001B is entirely command set compatible
with the JEDEC single-power-supply Flash
standard. Commands are written to t he command reg­ister using standard microprocessor write timings. Reg­ister contents ser ve as input to an internal state­machine that controls the erase and programming cir­cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase op era­tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
preprograms the array (if it is not already prog rammed)
before e xecuting the erase operation. During erase, the

device automatically tim es the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measur es include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a
sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron
injection.

Am29LV001B 2

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29LV001B

Speed Options

Max access time, ns (t
Max CE# access time, ns (tCE) 45 55 70 90
Max OE# access time, ns (tOE) 25 30 30 35

Regulated Voltage Range: VCC =3.0–3.6 V -45R

Full Voltage Range: VCC = 2.7–3.6 V -55 -70 -90

) 45 55 70 90

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

V

RESET#

WE#

CC

V

SS

CE#

OE#

State

Control

Command

Register

PGM Voltage

Generator

Sector Switches

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data

Latch

A0–A16

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21557C-1

3 Am29LV001B

CONNECTION DIAGRAMS

PRELIMINARY

A11

A9

A8
A13
A14

NC

WE#

V

CC

RESET#

A16
A15
A12

A7

A6

A5

A4

OE#

A10

CE#

DQ7
DQ6
DQ5
DQ4

DQ3

V

DQ2
DQ1
DQ0

SS

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin Standard TSOP

32-Pin Reverse TSOP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#

DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

A11
A9
A8
A13
A14
NC
WE#
V

CC

RESET#
A16
A15
A12
A7
A6
A5
A4

A7
A6
A5

A4
A3
A2
A1
A0

DQ0

CC

WE#

RESET#

5
6

7

8
9
10

11
12
13

14

A12

A15

Am29LV001

15

DQ1

DQ2

A16

13130234

PLCC

17

SS

V

DQ3

32

18

V

19 2016

DQ4

DQ5

NC

29
28
27

26
25
24
23
22
21

DQ6

A14
A13

A8

A9
A11
OE#

A10
CE#
DQ7

Am29LV001B 4

21557C-2

PRELIMINARY

PIN CONFIGURATION

A0–A16 = 17 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin not connected internally

(see Product Selector Guide for speed
options and voltage supply toleranc es)

= Device ground

LOGIC SYMBOL

17

A0–A16

CE#
OE#

WE#
RESET#

8

DQ0–DQ7

21557C-3

5 Am29LV001B

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE-45RAm29LV001B T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

Am29LV001BT-45R,
Am29LV001BB-45R,

Am29LV 00 1B T-55,
Am29LV 00 1B B-5 5,

Am29LV 00 1B T-70,
Am29LV 00 1B B-7 0,

Am29LV 00 1B T-90,
Am29LV 00 1B B-9 0,

Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

EC, FC, JC

EC, EI, EE,
FC, FI, FE,

JC, JI, JE

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am29LV001B 6

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29LV001B Device Bus Operations

Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0–DQ7

Read L L H H A
Write L H L H A
Standby VCC ± 0.3 V X X VCC ± 0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V
Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Notes:

1. Addresses are A16–A0.

2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by
using programming equipment. See the “Sector Protection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.

IN
IN

ID

ID

ID

Sector Address, A6 = L,

A1 = H, A0 = L

Sector Address, A6 = H,

A1 = H, A0 = L

A

IN

D

D

IN

D

IN

= Data Out

OUT

OUT

D

, D

, D
D

IN

OUT

OUT

IN

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates arra y data to the output pins . WE# should
remain at V

.

IH

The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con­tent occurs dur ing the power transi tion. No com mand
is necessary in this mode to o btai n array data. Stand­ard microprocessor read cycles that assert valid ad­dresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 13 for the timing diagram. I

the DC Characteristics table represents the active c ur­rent specification for reading array data.

. CE# is the power

IL

CC1

in

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

The device f eatures an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re­quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sec­tors, or the entire device. Table 2 indicate the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de­tails on erasing a sector or the entire chip, or suspend­ing/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-

, and OE# to VIH.

IL

7 Am29LV001B

PRELIMINARY

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for w r ite operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the de­vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs ar e placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V
(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held a t VIH, but not within

V

IH

± 0.3 V, the device will be in the standb y mode, but

V

CC

the standby current will be greater. The device requires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, RE­SET#: Hardware Reset Pin.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

CC

± 0.3 V.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enables
this mode when addresses remain stable f or t

ACC

+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I

CC5

in the DC
Characteristics table represents the automatic sleep
mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardw are method of reset­ting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby c urrent (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.The system may use
the RESET# pin to force the device into the standby
mode. Refer to the “ Standby Mode” section for more in­formation.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 14 for the timing diagram.

RP

, the

in the DC Characteristics table represents the

I

CC3

standby current specification.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

Am29LV001B 8

PRELIMINARY

Table 2. Am29LV001B Top Boot Sector Architecture

Sector Size

Sector A16 A15 A14 A13 A12

SA0 0 0 0 X X 16 Kbytes 00000h–03FFFh
SA1 0 0 1 X X 16 Kbytes 04000h–07FFFh
SA2 0 1 0 X X 16 Kbytes 08000h–0BFFFh
SA3 0 1 1 X X 16 Kbytes 0C000h–0FFFFh
SA4 1 0 0 X X 16 Kbytes 10000h–13FFFh
SA5 1 0 1 X X 16 Kbytes 14000h–17FFFh
SA6 1 1 0 X X 16 Kbytes 18000h–1BFFFh
SA7 1 1 1 0 0 4 Kbytes 1C000h–1CFFFh
SA8 1 1 1 0 1 4 Kbytes 1D000h–1DFFFh
SA9 1 1 1 1 X 8 Kbytes 1E000h–1FFFFh

(Kbytes)

Address Range

(in hexadecimal)

Table 3. Am29LV001B Bottom Boot Sector Architecture

Sector Size

Sector A16 A15 A14 A13 A12

SA0 0 0 0 0 X 8 Kbytes 00000h–01FFFh
SA1 0 0 0 1 0 4 Kbytes 02000h–02FFFh
SA2 0 0 0 1 1 4 Kbytes 03000h–03FFFh
SA3 0 0 1 X X 16 Kbytes 04000h–07FFFh
SA4 0 1 0 X X 16 Kbytes 08000h–0BFFFh
SA5 0 1 1 X X 16 Kbytes 0C000h–0FFFFh
SA6 1 0 0 X X 16 Kbytes 10000h–13FFFh
SA7 1 0 1 X X 16 Kbytes 14000h–17FFFh
SA8 1 1 0 X X 16 Kbytes 18000h–1BFFFh
SA9 1 1 1 X X 16 Kbytes 1C000h–1FFFFh

(Kbytes)

Address Range (in

hexadecimal)

9 Am29LV001B

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in

(11.5 V to 12.5 V) on address pin

ID

Table 4. In addition, when verifying sector protection,
the sector addres s must appear on the appropriate
highest order address bits (see Table 2). Table 4 s hows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
details on using the autoselect mode.

Table 4. Am29LV001B Autoselect Codes

A16

A11

to

to

Description CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID: Am29LV001B T

(Top Boot Block)
Device ID: Am29LV001B B

(Bottom Boot Block)

LLHXXV

LLHXXVIDXLXLH 6Dh

A12

A10 A9

. See “Command Definitions” for

ID

A8

to

A7 A6

XLXLL 01h

ID

XLXLH EDh

ID

A5

to

A2 A1 A0

DQ7

to

DQ0

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors. Sector protection/unprotecti on can be imple­mented via two methods.

The primary method requires V
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo­rithms and Figure 21 shows the timing diagram. This
method uses standard m icroprocessor bus cycle tim­ing. For sector unprotect, all unprotec ted sectors must
first be protected prior to the first sector unpro tect write
cycle.

The alternate method intended on ly for programming
equipment requires V

on address pin A9, OE#, and

ID

RESET#. This method is compatible with programmer

on the RESET# pin

ID

The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased b y selecting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the tim ing diagrams, for this feature.

XLXHL

ID

routines written for earlier 3.0 volt-only AMD flash de­vices. Publication number 2 2134 contains fur ther de­tails; contact an AMD representati ve to r equest a cop y.

01h

(protected)

00h

(unprotected)

. During this mode, formerly protected

ID

is removed from the RE-

ID

Am29LV001B 10

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector
address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Figure 1. In-System Sector Protect/Unprotect Algorithms

11 Am29LV001B

Sector Unprotect

complete

21557C-4

PRELIMINARY

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

ID

IH

21557C-5

Figure 2. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection

against inadverten t writes (refer to Table 5 for com­mand definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up W rite Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. Table 5 de fines the valid register co mmand
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend com­mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-su spended sectors, the device outputs
status data. After completing a programming o pera­tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.

must

The system

issue the reset command to re-ena­ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements f o r Reading A rr ay Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame­ters, and Figure 13 shows the timing diagram.

Am29LV001B 12