AMD Am29LL800B Service Manual

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ADVANCE INFORMATION

Am29LL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— 2.2 to 2.7 volt read and write operations for

battery-powered applications

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29LL800 device

■ High performance

— Access times as fast as 150 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 75 nA Automatic Sleep mode current — 75 nA standby mode current — 7 mA read current — 15 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall progr amming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

■ Embedded Al gorithms

■ Minimum 1,000,000 write cycle guarantee per

■ Package option

■ Compatibility with JEDEC standards

■ Data# Polling and toggle bits

■ Ready/Busy# pin (RY/BY#)

■ Erase Suspend/Erase Resume

■ Hardware reset pin (RESET#)

available

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

sector

— 48-pin TSOP — 44-pin SO

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

— Provides a software method of detecting

program or erase operation completion

— Provides a hardware method of detecting

program or erase cycle completion

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being erased, then resumes the erase operation

— Hardware method to reset the de vi ce to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 21518 Rev: A Amendment/+3 Issue Date: March 1998

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ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29LL800B is an 8 M bit, 2.2 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO and 48-pin TSOP packages. The word-wide data (x16) appears on

DQ15–DQ0; the byte-wide (x8) data appears on DQ7– DQ0. This device requires only a single, 2.2 volt V supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

This device is manufactured using AMD’ s 0. 35 µm process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using

0.5 µm process technology. In addition, the Am29LL800B features unlock bypass programming and in-system sector protection/unprotection.

The standard device offers access times of 150 and 200 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 2. 2 v o lt po wer sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microproc essor write timing s. Register contents serve as input to an internal sta te-machine that co ntrols the erase and programming circuit ry. Write cycles also internally latch addresses and data needed f or the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requir ing only two write cycles to program data instead of four.

Device erasure occurs by ex ecuting the erase command sequence. This initiates the Embedded Erase algorithm—an i nternal algorithm that autom atically prepro grams the array (if it is not already programmed) before

executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase archite cture allo ws m emory sect ors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase

operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achiev ed.

The hardware RESET# pi n terminates any operation in progress and resets the internal state machine to reading array dat a. The RESET# pin ma y be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When addresses have been stable for a specified amount of time, the device enters the automatic sleep m ode. The system can also place the de vice into the standby mode. Power consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

2 Am29LL800B

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ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Family Part Number Am29LL800B Speed Options -150 -200 Max access time, ns (t Max CE# access time, ns (tCE) 150 200 Max OE# access time, ns (tOE) 55 55

) 150 200

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

–

DQ15 (A-1)

DQ0

Input/Output

Buffers

Data

STB

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

Sector Switches

Erase Voltage

Generator

PGM Voltage

Generator

Chip Enable

Output Enable

A0–A18

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

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Am29LL800B 3

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CONNECTION DIAGRAMS

ADVANCE INFORMATION

A15 A14 A13 A12 A11 A10

A8 NC NC

WE#

RESET#

NC NC

RY/BY#

A18 A17

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18

Standard TSOP

Reverse TSOP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

A16 BYTE# V

DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#

CE# A0

A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1

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CONNECTION DIAGRAMS

ADVANCE INFORMATION

A18 A17

A7 A6 A5 A4 A3 A2 A1 A0

CE#

OE# DQ0 DQ8 DQ1 DQ9 DQ2

DQ3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

RY/BY#

DQ10 DQ11

PIN CONFIGURATION

A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

LOGIC SYMBOL

A0–A18

16 or 8

DQ0–DQ15

(A-1)

BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output

= 2.2–2.7 V, single power supply

= Device ground

NC = Pin not connected internally

CE# OE#

WE# RESET# BYTE# RY/BY#

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ADVANCE INFORMATION

ORDERING INFORMATION Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.

CE-150Am29LL800B T

OPTIONAL PROCESSING

Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

Am29LL800BT-150, Am29LL800BB-150

Am29LL800BT-200, Am29LL800BB-2 00

Valid Combinations

EC, EI, FC, FI, SC, SI

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LL800B 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

2.2 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

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ADVANCE INFORMATION

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the commands, along with the address and data information needed to execute the command. The contents of

Table 1. Am29LL800B Device Bus Operations

Operation CE# OE# WE# RESET #

Read L L H H A

Write L H L H A Standby Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

, H = Logic High = VIH, VID = 10.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

VCC ±

0.3 V

VCC ±

0.3 V

), A18:A-1 in byte mode (BYTE# = VIL).

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control lev els t he y requ ire , and t he resulting output. The following subsections describe each of these operations in further detail.

DQ8–DQ15

Addresses

Sector Addresses,

A6 = L, A1 = H,

Sector Addresses,

A6 = H, A1 = H,

(Note 1)

IN IN

X High-Z High-Z High-Z

A0 = L

DQ0–

DQ7

OUT

BYTE#

= V

DQ8–DQ14 = High-Z,

OUT

DQ15 = A-1

BYTE#

= V

= Data Out

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates arra y data to the output pins . WE# should remain at V

. The BYTE# pin determines whether the

device outputs array data in words or bytes.

. CE# is the power

Am29LL800B 7

The internal state machine is set for reading array data upon device po wer-u p , or after a hardw are res et. This ensure s that no sp urious alteration of the memory content occurs dur ing the power transition. No command is nece ssary in this mode to ob tain array data. Standard microprocessor read cycles that assert valid addresses on the de vice addr ess inputs produce valid dat a on the de vice da ta outputs . The de vice remains enabled for read access until the command register contents are altered.

See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 14 for the timing diagram. I

CC1

the DC Characteristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

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ADVANCE INFORMATION

sectors of memory), the system must drive WE# and CE# to V

, and OE# to VIH.

For program operations, the BYT E# pin determin es whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more information.

The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 indic ate the address space that each sector occupies. A “sector address” consists of the addres s bits required t o un iquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the w rite mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteristics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held at VIH, but not within

± 0.3 V, the device will be in the standby mode, b ut

the standby current will be grea ter. The device requires standard access time (t

) for read access when the

device is in either of these standby modes, before it is ready to read data.

The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de vice automatically enables this mode when addresses remain stable f or t ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard addres s access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

CC4

Characteristics table represents the automatic sleep

+ 30

ACC

in the DC

8 Am29LL800B

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ADVANCE INFORMATION

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t device immediately terminates any operation in progress, tristates all output pins, and igno res all read/write commands for the duration of the RESET# pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V

draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

±0.3 V, the device

). If RESET# is held

CC4

be greater. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. During power-up, the

, the

system must ensure that RESET# is high t

RSTW

before asserting a valid address (see Fi gure 1 and the Erase/Program Operations table).

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether the reset oper ation is c omplete . If RESE T# is asserted when a program or erase oper ation is not e xecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t ded Algorithms). The system can read data t the RESET# pin returns to V

(not during Embed-

READY

after

Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in t he high impedance state.

RESET#

Address

Data

2.2 – 2.7 V

0 V

ACC

RSTW

Figure 1. Power-up and Reset Timings

VALID

VALID OUTPUT

Am29LL800B 9

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ADVANCE INFORMATION

Table 2. Am29LL800BT Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh SA10001XXX 64/32 10000h–1FFFFh08000h–0FFFFh SA20010XXX 64/32 20000h–2FFFFh10000h–17FFFh SA30011XXX 64/32 30000h–3FFFFh18000h–1FFFFh SA40100XXX 64/32 40000h–4FFFFh20000h–27FFFh SA50101XXX 64/32 50000h–5FFFFh28000h–2FFFFh SA60110XXX 64/32 60000h–6FFFFh30000h–37FFFh SA70111XXX 64/32 70000h–7FFFFh38000h–3FFFFh SA81000XXX 64/32 80000h–8FFFFh40000h–47FFFh

SA91001XXX 64/32 90000h–9FFFFh48000h–4FFFFh SA101010XXX 64/32 A0000h–AFFFFh50000h–57FFFh SA111011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh SA121100XXX 64/32 C0000h–CFFFFh60000h–67FFFh SA131101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh SA141110XXX 64/32 E0000h–EFFFFh70000h–77FFFh SA1511110XX 32/16 F0000h–F7FFFh78000h–7BFFFh SA161111100 8/4 F8000h–F9FFFh7C000h–7CFFFh SA171111101 8/4 FA000h–FBFFFh7D000h–7DFFFh SA18111111X 16/8 FC000h–FFFFFh7E000h–7FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Table 3. Am29LL800BB Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA0000000X 16/8 00000h–03FFFh00000h–01FFFh

SA10000010 8/4 04000h–05FFFh02000h–02FFFh

SA20000011 8/4 06000h–07FFFh03000h–03FFFh

SA300001XX 32/16 08000h–0FFFFh04000h–07FFFh

SA40001XXX 64/32 10000h–1FFFFh08000h–0FFFFh

SA50010XXX 64/32 20000h–2FFFFh10000h–17FFFh

SA60011XXX 64/32 30000h–3FFFFh18000h–1FFFFh

SA70100XXX 64/32 40000h–4FFFFh20000h–27FFFh

SA80101XXX 64/32 50000h–5FFFFh28000h–2FFFFh

SA90110XXX 64/32 60000h–6FFFFh30000h–37FFFh SA100111XXX 64/32 70000h–7FFFFh38000h–3FFFFh SA111000XXX 64/32 80000h–8FFFFh40000h–47FFFh SA121001XXX 64/32 90000h–9FFFFh48000h–4FFFFh SA131010XXX 64/32 A0000h–AFFFFh50000h–57FFFh SA141011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh SA151100XXX 64/32 C0000h–CFFFFh60000h–67FFFh SA161101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh SA171110XXX 64/32 E0000h–EFFFFh70000h–77FFFh SA181111XXX 64/32 F0000h–FFFFFh78000h–7FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section for more information.

10 Am29LL800B

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ADVANCE INFORMATION

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This mode is primarily intended for progr amming equipment to automatically match a device to be progr ammed with its correspondi ng programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V A1, and A0 must be as shown in Table 4. In addition,

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V Device ID:

Am29LL800B (Top Boot Block)

on address pin A9. Address pins A6,

Table 4. Am29LL800B Autoselect Codes (High Voltage Method)

A18

A11

A12

A10 A9

Word L L H

Byte L L H X EAh

XXVIDXLXLH

when verifying sector protection, the sector address must appear on the appropria te highest order address bits (see Tables 2 and 3). Ta ble 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require V

. See “Command Definitions” for

details on using the autoselect mode.

A7 A6

XLXLL X 01h

A2 A1 A0

DQ8

DQ15

22h EAh

DQ7

DQ0

Device ID: Am29LL800B (Bottom Boot Block)

Sector Protection Verification

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sect or. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotecti on can be implemented via two methods.

The primary method requires V only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard m icroprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro tect write cycle.

The alternate method intended on ly for programming equipment requires V This method is compatible with programmer routines

Word L L H

Byte L L H X 6Bh

XXV

LLHSAXV

XLXLH

XLXHL

The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an AMD representative for details.

It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.

on the RESET# pin

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased b y selecting the sector addresses. Once V SET# pin, all the previously protected sectors are

on address pin A9 and OE#.

protected again. Figure 3 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature.

written for earlier 3.0 v olt-only AMD flash de vices. Publication number 21466 contains further details; contact an AMD representative to request a copy.

22h 6Bh

X 01h protected X 00h unprotected

. During this mode, formerly protected

is removed from the RE-

Am29LL800B 11

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ADVANCE INFORMATION

Temporary Sector

Unprotect Mode

Increment

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

START

Protect all sectors:

The indicated portion

of the sector protect

Reset

PLSCNT = 1

Yes

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

All sectors protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Temporary Sector

Unprotect Mode

Set up

next sector

address

Algorithm

Write reset

command

Figure 2. In-System Sector Protect/Unprotect Algorithms

12 Am29LL800B

Sector Unprotect

complete

21518A-4

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ADVANCE INFORMATION

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

21518A-5

Figure 3. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent wri tes (refer to Table 5 for com-

mand definitions). In addition, the following hardwar e data protection mea sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V

power-up and

power-down transitions, or from system noise.

Low V

When V cept any write cycles. This protects data during V

Write Inhibit

is less than V

, the device does not ac-

LKO

power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent unintentional writes when V

is greater than V

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

, CE# = VIH or WE# = VIH. To initiat e a wr ite cy-

= V

cle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during powe r

up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific addre ss and data commands or sequences into the command register initiates device operations. Table 5 defines the valid regi ster command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after comp leting an Embe dded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard

read timings, except that if it reads at an address within erase-su spended sectors, the device outputs status data. After completing a programming o peration in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

must

The system

issue the reset command to re-enable the dev ice f or reading arra y data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.

See also “Requirements f o r Reading A rr ay Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 14 shows the timing diagram.

Reset Command

Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care for this command.

Am29LL800B 13

Page 14

ADVANCE INFORMATION

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, t he reset c ommand be written to return to reading array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and de vices c odes, and determine whether or not a sector is protected. T ab le 5 shows the address and data requirements . This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V on address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect m ode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code . A read cycle containing a sector address (SA) and the address 02h in word mode (or 0 4h in byte mode) r eturns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses.

ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 shows the address and da ta requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation b y using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the de vice has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence an d across sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indic ate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or w ords t o the device faster than us ing the standard program command sequence. The unloc k b ypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the prog ram address and data. Additional data is programmed in the same manner. This mode dispenses with t he i nitial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 shows the re quirements for the command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The

not

system is

14 Am29LL800B

required to provide further controls or tim-

During the unlo ck bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. The de vice then returns to reading array data.

Figure 4 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams.

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ADVANCE INFORMATION

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See Table 5 for program command sequence.

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

21518A-6

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle oper ation. The chip er ase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase

not

algorithm. The device does preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and ve rifies the entire memory for an all zero data patter n prior to electr ical erase. The system is not required to provide any controls or timings during these operations. Table 5 shows the address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a har dware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, t o ensure data int eg rity.

require the system to

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See

“Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.

Figure 5 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 19 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5 shows the address and data requirements for the sector erase co mmand sequence.

not

The device does the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the s ector for an all zero data pattern prior to electrical erase. The system is not required to provide a ny controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sector s. The time between these additional cycl es must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disab led during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence

and any additional sector addresses and commands. The system can monitor DQ3 to determine if the s ector

erase timer has timed out. (See the “DQ3 : Sector Erase Timer” section.) The tim e-out begins from the rising edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, on ly the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.

require the system to preprogram

Am29LL800B 15

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ADVANCE INFORMATION

When the Embedded Erase algorithm is complete, the device returns to reading arra y data and addresses are no longer latched. The system can determine the status of the erase operation b y usi ng DQ7, DQ6, DQ2, or

RY/BY#. (Refer to “Write Op eration St atus” f or inf ormation on these status bits.)

Figure 5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 19 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend comm and is ignored if written dur ing the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the er ase oper at ion. Addresses are “don’t-cares” when writing the Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the de vice requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation.

the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.

The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operati on. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFH?

Erasure Completed

Yes

Embedded Erase algorithm in progress

After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure . (The devi ce “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read arra y data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information.

The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to

21518A-7

Notes:

1. See Table 5 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 5. Erase Operation

16 Am29LL800B

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ADVANCE INFORMATION

Table 5. Am29LL800B Command Definitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID, Top Boot Block

Device ID, Bottom Boot Block

Autoselect (Note 8)

Sector Protect Verify (Note 9)

Program

Unlock Bypass Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00 Chip Erase

Sector Erase Erase Suspend (Note 12) 1 XXX B0

Erase Resume (Note 13) 1 XXX 30

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

Legend:

X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

555

2AA

Bus Cycles (Notes 2-5)

555

90 X00 01

X01 22EA

X02

X01 226B

X02

(SA)

X02

(SA)

X04

A0 PA PD

555

6B XX00 XX01

00 01

2AA

555

55 SA 30

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.

Notes:

1. See Table 1 for descripti on of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.

5. Address bits A18–A11 are don’t cares for unlock and command cycles., unless SA or PA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status da ta).

8. The fourth cycle of the autoselect command sequence is a read cycle.

Am29LL800B 17

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

13. The Erase Resume command is valid only during the Erase Suspend mode.

Page 18

ADVANCE INFORMATION

WRITE OPERATION STATUS

The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the f ollo wing subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence.

START

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

Yes

During the Em bedded Program algor ithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1

µs, then the device returns to reading

array data. During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” o r “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all s ectors selected for erasing are protected, Data# Polling on DQ7 is active f or appro ximately 100

µs, then the de-

vice returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read va lid data at DQ7– DQ0 on the

following

read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as serted low. Figure 20, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics” section illustrates this.

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

FAIL

Yes

PASS

21518A-8

Figure 6. Data# Polling Algorithm

Table 6 shows th e outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm.

18 Am29LL800B

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ADVANCE INFORMATION

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing or programming. (T his includes programming in the Erase Suspend mode.) If th e output is high (Ready) , the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. Figures 15, 18 and 19 shows RY/BY# for reset, program, and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indic ates whether an Embedde d Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or eras e operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system ma y use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling.

Table 6 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 21 in the

“AC Characteristics” section shows the toggle bit ti ming diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a par ticular sect or is actively erasing (that is, the Embedded Erase algo rithm is in pro gress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of t he final WE# pulse in the command sequence.

DQ2 toggles w hen the system reads at addresses within those sector s that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6.

Figure 7 shows the toggle bit algorithm in flowchar t form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all s ectors selected for eras ing are protected , DQ6 toggles for approximately 100 data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is activ ely erasing (that is , the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a pro tected sector, DQ6 toggles for approximately 1 command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

µs, then returns to reading array

µs after the program

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially begins rea ding toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to readi ng array data.

Am29LL800B 19

Page 20

ADVANCE INFORMATION

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through success ive read cycle s, determining the status as described in the previous paragraph. Alterna tively, it may choose to pe rform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).

START

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

(Notes 1, 2)

Program/Erase

Operation Complete

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not Complete, Write Reset Command

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure condition that indicates the pro gram or er ase cycle w as not successfully completed.

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.” Under both these conditions, t he system must issue the

reset command to return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine w hether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the “Sector Erase Command Sequence” section.

After the sector erase command sequenc e is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Sus pend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ens ure the command has been accepted, the system software should che ck the s tatus of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.

Notes:

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

21518A-9

Figure 7. Toggle Bit Algorithm

20 Am29LL800B

Page 21

ADVANCE INFORMATION

Table 6. Write Operation Status

DQ7

Standard Mode

Erase Suspend Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase

Suspended Sector Reading within Non-Erase

Suspended Sector Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Am29LL800B 21

Page 22

ADVANCE INFORMATION

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . .–0.5 V to +3.6 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1) . . . . . –0.5 V to V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During voltage transitions, input or I/O pins may undershoot V to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC voltage on input or I/O pins is V During voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 9.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot V to 20 ns. See Figure 8. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

to –2.0 V for periods of up

+0.5 V

+0.5 V.

20 ns

+0.8 V

–0.5 V –2.0 V

20 ns

Figure 8. Maximum Negative Overshoot

20 ns

21518A-10

Waveform

20 ns

+2.0 V

+0.5 V

2.0 V 20 ns

20 ns

21518A-11

Figure 9. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T

VCC Supply Voltages

for all devices . . . . . . . . . . . . . . .+2.2 V to +2.7 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

22 Am29LL800B

) . . . . . . . . . –40°C to +85°C

Page 23

ADVANCE INFORMATION

DC CHARACTERISTICS CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

LIT

CC1

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current (Note 1)

= VCC

CC max

= VSS to VCC,

OUT

= V

CC max

CE# = V

IL,

Byte Mode

CE# = V

IL,

Word Mode

max

±1.0 µA

; A9 = 10.0 V 35 µA

±1.0 µA

OE#

= VIH,

5 MHz 7 12 1 MHz 2 4

OE#

= VIH,

5 MHz 7 12 1 MHz 2 4

V V V

CC2

CC3

CC4

CC5

V V

OH1

OH2

LKO

VCC Active Write Current (Notes 2 and 4)

VCC Standby Current

VCC Reset Current

Automatic Sleep Mode (Note 3)

Input Low Voltage –0.5 0.8 V Input High Voltage 0.7 x V Voltage for Autoselect and

Temporary Sector Unprotect Output Low Voltage IOL = 4.0 mA, VCC = V

Output High Voltage

Low VCC Lock-Out Voltage (Note 4)

CE# = V

VCC = V CE#, RESET# = V

RESET# = V VIH = V

IOH = –2.0 mA, VCC = V IOH = –100 µA, VCC = V

OE#

IL,

= VIH

;

= V

CC max

± 0.3 V

± 0.3 V;

;

± 0.3 V

±0.3 V

= 2.7 V 9.5 10.5 V

0.45 V

CC min

0.85 V

CC min

VCC–0.4

CC min

1.0 1.5 V

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 2.5 V.

active while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

4. Not 100% tested.

ACC

15 30 mA

0.075 5 µA

VCC + 0.3 V

+ 30 ns.

Am29LL800B 23

Page 24

ADVANCE INFORMATION

DC CHARACTERISTICS (Continued) Zero Power Flash

Supply Current in mA

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

Supply Current in mA

12345

21518A-12

2.7 V

2.2 V

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I

vs. Frequency

CC1

24 Am29LL800B

21518A-13

Page 25

TEST CONDITIONS

ADVANCE INFORMATION

Table 7. Test Specifications

2.5 V

Test Condition -150 -200 Unit

Device

Under

Test

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

2.7 kΩ

21518A-14

Output Load 1 TTL gate Output Load Capacitance, C

(including jig capacitance) Input Rise and Fall Times 5 ns Input Pulse Levels 0.0–2.4 V

Input timing measurement reference levels

Output timing measurement reference levels

Steady

Changing from H to L

Changing from L to H

50 pF

1.0 V

2.5 V

0.0 V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

1.0 V 1.0 V

Figure 13. Input Waveforms and Measurement Levels

KS000010-PAL

OutputMeasurement LevelInput

21518A-15

Am29LL800B 25

Page 26

AC CHARACTERISTICS Read Operations

ADVANCE INFORMATION

Parameter

JEDEC Std Test Setup -150 -200 Unit

AVAV

AVQV

ELQV

GLQV

EHQZ

GHQZ

Read Cycle Time (Note 1) Min 150 200 ns

Address to Output Delay

ACC

Chip Enable to Output Delay OE# = V

Output Enable to Output Delay Max 55 ns

Chip Enable to Output High Z (Note 1) Max 40 ns

Output Enable to Output High Z (Note 1) Max 40 ns

Description

CE# = V OE# = V

Max 150 200 ns

Speed Option

Read Min 0 ns

Output Enable

AXQX

OEH

Hold Time (Note 1)

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

Toggle and Data# Polling

Min 10 ns

Min 0 ns

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 7 for test specifications.

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

ACC

OEH

HIGH Z

Output Valid

Figure 14. Read Operations Timings

HIGH Z

21518A-16

26 Am29LL800B

Page 27

AC CHARACTERISTICS Hardware Reset (RESET#)

Parameter

ADVANCE INFORMATION

Description All Speed OptionsJEDEC Std Test Setup Unit

READY

RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns

RESET# High Time Before Read (See Note) Min 50 ns

RESET# Low to Standby Mode Min 20 µs

RPD

RY/BY# Recovery Time Min 0 ns

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

Ready

Max 20 µs

Max 500 ns

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

Ready

Figure 15. RESET# Timings

21518A-17

Am29LL800B 27

Page 28

ADVANCE INFORMATION

AC CHARACTERISTICS Word/Byte Configuration (BYTE#)

Parameter

-150 -200JEDEC Std Description Unit

ELFL/tELFH

FLQZ

FHQV

BYTE#

Switching

from word

to byte

mode

CE# to BYTE# Switching Low or High Max 5 ns BYTE# Switching Low to Output HIGH Z Max 40 40 ns BYTE# Switching High to Output Active Min 150 200 ns

CE#

OE#

BYTE#

DQ0–DQ14

DQ15/A-1

ELFL

ELFH

Data Output

(DQ0–DQ14)

DQ15

Output

FLQZ

Data Output

(DQ0–DQ7)

Address

Input

BYTE#

Switching

from byte

to word

DQ0–DQ14

Data Output (DQ0–DQ7)

mode

DQ15/A-1

Address

Input

FHQV

Figure 16. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

SET

(tAS)

HOLD

(tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 17. BYTE# Timings for Write Operations

Data Output

(DQ0–DQ14)

DQ15

Output

21518A-18

21518A-19

28 Am29LL800B

Page 29

ADVANCE INFORMATION

AC CHARACTERISTICS Erase/Program Operations

Parameter

-150 -200JEDEC Std Description Unit

AVAV

AVWL

WLAX

DVWH

WHDX

GHWL

ELWL

WHEH

WLWH

WHWL

t t t

OES

GHWL

WPH

Write Cycle Time (Note 1) Min 150 200 ns

Address Setup Time Min 0 ns

Address Hold Time Min 65 ns

Data Setup Time Min 65 ns

Data Hold Time Min 0 ns

Output Enable Setup Time (Note 1) Min 0 ns Read Recovery Time Before Write

(OE# High to WE# Low) CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 65 ns

Write Pulse Width High Min 35 ns

Byte Typ 9

WHWH1

WHWH2

WHWH1

WHWH2

VCS

BUSY

RSTW

Programming Operation (Note 2)

Word Typ 11 Sector Erase Operation (Note 2) Typ 0.7 sec VCC Setup Time (Note 1) Min 50 µs Recovery Time from RY/BY# Min 0 ns

Program/Erase Valid to RY/BY# Delay Min 90 ns RESET# High to Address Valid Min 200 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Min 0 ns

µs

Am29LL800B 29

Page 30

AC CHARACTERISTICS

ADVANCE INFORMATION

Addresses

CE#

OE#

WE#

Data

RY/BY#

Program Command Sequence (last two cycles)

555h

GHWL

PA PA

WPH

A0h

VCS

Read Status Data (last two cycles)

WHWH1

BUSY

Status

OUT

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

is the true data at the program address.

OUT

21518A-20

30 Am29LL800B

Page 31

AC CHARACTERISTICS

Erase Command Sequence (last two cycles) Read Status Data

ADVANCE INFORMATION

Addresses

CE#

OE#

WE#

Data

RY/BY#

VCS

2AAh SA

555h for chip erase

GHWL

WPH

55h

30h

10 for Chip Erase

BUSY

WHWH2

Progress

Complete

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 19. Chip/Sector Erase Operation Timings

21518A-21

Am29LL800B 31

Page 32

AC CHARACTERISTICS

Addresses

CE#

OE#

OEH

WE#

DQ7

ADVANCE INFORMATION

ACC

Complement

VA VA

Complement

True

Valid Data

High

DQ0–DQ6

BUSY

Status Data

True

Valid Data

High

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21518A-22

Figure 20. Data# Polling Timings (During Embedded Algorithms)

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

BUSY

OEH

High Z

ACC

(first read) (second read) (stops toggling)

VA VA

Valid Status

Valid DataValid StatusValid Status

Note: VA = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

21518A-23

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

32 Am29LL800B

Page 33

ADVANCE INFORMATION

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Erase

Suspend

Erase Suspend

Enter Erase

Suspend Program

Read

Figure 22. DQ2 vs. DQ6

Erase Suspend Program

Erase Suspend

Read

Erase

Resume

Erase

Complete

21518A-24

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

Erase

VIDR

RSP

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

VID Rise and Fall Time (See Note) Min 500 ns RESET# Setup Time for Temporary Sector

Unprotect

Min 4 µs

10 V

0 or 2.5 V

VIDR

0 or 2.5 V

Program or Erase Command Sequence

RSP

21518A-25

Figure 23. Temporary Sector Unprotect Timing Diagram

Am29LL800B 33

Page 34

AC CHARACTERISTICS

ESET#

ADVANCE INFORMATION

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 100 µs

Sector Unprotect: 10 ms

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector Protect/Unprotect Timing Diagram

Status

21518A-26

34 Am29LL800B

Page 35

ADVANCE INFORMATION

AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations

Parameter

-150 -200JEDEC Std Description Unit

AVAV

AVEL

ELAX

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH

EHEL

WHWH1

WHWH2

OES

GHEL

CPH

WHWH1

WHWH2

Write Cycle Time (Note 1) Min 150 200 ns Address Setup Time Min 0 ns Address Hold Time Min 65 ns Data Setup Time Min 65 ns Data Hold Time Min 0 ns Output Enable Setup Time Min 0 ns Read Recovery Time Before Write

(OE# High to WE# Low) WE# Setup Time Min 0 ns WE# Hold Time Min 0 ns CE# Pulse Width Min 65 ns CE# Pulse Width High Min 35 ns

Programming Operation (Note 2)

Byte Typ 9

Word Typ 11

Sector Erase Operation (Note 2) Typ 0.7 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Min 0 ns

µs

Am29LL800B 35

Page 36

AC CHARACTERISTICS

555 for program 2AA for erase

ADVANCE INFORMATION

PA for program SA for sector erase 555 for chip erase

Data# Polling

Addresses

WE#

OE#

CE#

Data

RESET#

RY/BY#

GHEL

CPH

A0 for program 55 for erase

BUSY

PD for program 30 for sector erase 10 for chip erase

WHWH1 or 2

DQ7# D

OUT

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, D

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 25. Alternate CE# Controlled Write Operation Timings

= data written to the device.

OUT

21518A-27

36 Am29LL800B

Page 37

ADVANCE INFORMATION

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s Chip Erase Time 14 s Byte Programming Time 9 300 µs

Word Programming Time 11 360 µs Chip Programming Time

(Note 2)

Byte Mode 9 27 s

Word Mode 5.8 17.4 s

Excludes 00h programming prior to erasure

Excludes system level overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 2.5 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 2.2 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description Min Max

Input voltage with respect to V (including A9, OE#, and RESE T#)

on all pins except I/O pins

–1.0 V 12.5 V

Input voltage with respect to V

Current –100 mA +100 mA

on all I/O pins –1.0 V VCC + 1.0 V

Includes all pins except VCC. Test conditions: VCC = 2.5 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years 125°C 20 Years

Am29LL800B 37

Page 38

ADVANCE INFORMATION

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in millimeters)

Pin 1 I.D.

18.30

18.50

19.80

20.20

1.20 MAX

0.25MM (0.0098") BSC

* For reference only. BSC is an ANSI standard for Basic Space Centering

0° 5°

0.50

0.70

0.08

0.20

11.90

12.10

0.10

0.21

0.95

1.05

0.50 BSC

0.05

0.15

16-038-TS48-2 TS 048 DA101 8-8-94 ae

TSR048—48-Pin Reverse TSOP (measured in millimeters)

Pin 1 I.D.

18.30

18.50

19.80

20.20

1.20

MAX

0.25MM (0.0098") BSC

* For reference only. BSC is an ANSI standard for Basic Space Centering

0° 5°

0.50

0.70

11.90

12.10

0.08

0.20

0.10

0.21

0.95

1.05

SEATING PLANE

0.50 BSC

0.05

0.15

16-038-TS48 TSR048 DA104 8-8-94 ae

38 Am29LL800B

Page 39

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

2.17

2.45

13.10

13.50

1.27 NOM.

TOP VIEW

28.00

28.40

0.35

0.50

SIDE VIEW

0.10

0.35

2.80

MAX.

15.70

16.30

SEATING PLANE

0° 8°

0.10

0.21

0.60

1.00

END VIEW

16-038-SO44-2 SO 044 DA82 11-9-95 lv

Am29LL800B 39

Page 40

ADVANCE INFORMATION

REVISION SUMMARY FOR AM29LL800B Revision A+1

Distinctive Characteristics

Ultra low power consumption bullet: The typical Automatic Sleep Mode and standby mode currents are both 75 nA.

DC Characteristics, CMOS Compatible

, I

The typical current for I

CC3

CC4

, and I

is 75 nA.

CC5

Revision A+2

Reset Command

Deleted last paragraph in section, which applied to RESET#, not the reset command.

Revision A+3

Figure 2, In-System Sector Protect/Unprotect Algorithms

In the sector protect algorithm, added a “PLSCNT=1” box in the path from “Protect another sector?” back to setting up the next sector address.

DC Characteristics

Changed Note 1 to indicate that OE# is at V listed current.

for t he

Erase and Program Operations; Alternate CE# Controlled Erase/Program Operations

Corrected the notes ref erence f or t

WHWH1

and t

WHWH2

These parameters are 100% tested. Corre cted the note reference for t tested. Removed t

. This parameter is not 100%

VCS

parameters from CE# Con-

OEH

trolled Erase/Program Operatio ns table f or consistenc y with other data sheets.

Temporary Sector Unprotect Table

Added note reference for t

. This parameter is not

VIDR

100% tested.

Figure 23, Temporary Sector Unprotect Timing Diagram

Changed the high voltage (V

) on the RESET# wave-

form to 10 V.

Figure 24, Sector Protect/Unprotect Timing Diagram

A valid address is not required for the first write cycle; only the data 60h.

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cycles.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

40 Am29LL800B

AMD Am29LL800B Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual