AMD Am29LL800B Service Manual

查询AM29LL800B供应商

ADVANCE INFORMATION

Am29LL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 2.2 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

— 2.2 to 2.7 volt read and write operations for

battery-powered applications

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29LL800 device

■ High performance

— Access times as fast as 150 ns

■ Ultra low power consumption (typical values at

5 MHz)

— 75 nA Automatic Sleep mode current
— 75 nA standby mode current
— 7 mA read current
— 15 mA program/erase current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

T emporary Sector Unprotect feat ure allows code

changes in previously locked sectors

■ Unlock Bypass Program Command

— Reduces overall progr amming time when

issuing multiple program command sequences

■ Top or bottom boot block configurations

■ Embedded Al gorithms

■ Minimum 1,000,000 write cycle guarantee per

■ Package option

■ Compatibility with JEDEC standards

■ Data# Polling and toggle bits

■ Ready/Busy# pin (RY/BY#)

■ Erase Suspend/Erase Resume

■ Hardware reset pin (RESET#)

available

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

sector

— 48-pin TSOP
— 44-pin SO

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

— Provides a software method of detecting

program or erase operation completion

— Provides a hardware method of detecting

program or erase cycle completion

— Suspends an erase operati on to read dat a from,

or program data to, a sector that is not being
erased, then resumes the erase operation

— Hardware method to reset the de vi ce to reading

array data

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you ev aluate this product. AMD reserves the right to change or dis continue work on thi s proposed
product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 21518 Rev: A Amendment/+3
Issue Date: March 1998

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29LL800B is an 8 M bit, 2.2 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO and 48-pin
TSOP packages. The word-wide data (x16) appears on

DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device requires only a single, 2.2 volt V
supply to perform read, program, and erase opera­tions. A standard EPROM programmer can also be
used to program and erase the device.

This device is manufactured using AMD’ s 0. 35 µm pro­cess technology, and offers all the features and bene­fits of the Am29LV800, which was manufactured using

0.5 µm process technology. In addition, the
Am29LL800B features unlock bypass programming
and in-system sector protection/unprotection.

The standard device offers access times of 150 and
200 ns, allowing high speed microprocessors to oper­ate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.

The device requires only a single 2. 2 v o lt po wer sup-
ply for both read and write functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co n­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requir ing only two
write cycles to program data instead of four.

Device erasure occurs by ex ecuting the erase command
sequence. This initiates the Embedded Erase algo­rithm—an i nternal algorithm that autom atically prepro ­grams the array (if it is not already programmed) before

CC

executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.

The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achiev ed.

The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The device off ers two power-sa ving f eatures. When ad­dresses have been stable for a specified amount of
time, the device enters the automatic sleep m ode.
The system can also place the de vice into the standby
mode. Power consumption is greatly reduced in both
these modes.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun­neling. The data is programmed using hot electron in­jection.

2 Am29LL800B

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Family Part Number Am29LL800B
Speed Options -150 -200
Max access time, ns (t
Max CE# access time, ns (tCE) 150 200
Max OE# access time, ns (tOE) 55 55

) 150 200

ACC

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

–

DQ15 (A-1)

DQ0

Input/Output

Buffers

Data

STB

V

CC

V

SS

RESET#

WE#

BYTE#

CE#

OE#

RY/BY#

State

Control

Command

Register

Sector Switches

Erase Voltage

Generator

PGM Voltage

Generator

Chip Enable

Output Enable

A0–A18

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

21518A-1

Am29LL800B 3

CONNECTION DIAGRAMS

ADVANCE INFORMATION

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

A18
A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#

V

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

CE#

SS

CC

SS

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15

16
17
18

19

20

21

22

23

24

Standard TSOP

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1

4 Am29LL800B

21518A-2

CONNECTION DIAGRAMS

ADVANCE INFORMATION

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

RY/BY#

DQ10
DQ11

PIN CONFIGURATION

A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

SO

44

RESET#

43

WE#

42

A8

41

A9

40

A10

39

A11

38

A12

37

A13

36

A14

35

A15

34

A16

33

BYTE#

32

V

SS

DQ15/A-1

31

DQ7

30

DQ14

29

DQ6

28

DQ13

27

DQ5

26

DQ12

25

DQ4

24

V

23

CC

LOGIC SYMBOL

19

A0–A18

16 or 8

DQ0–DQ15

(A-1)

BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output

= 2.2–2.7 V, single power supply

V

CC

V

SS

= Device ground

NC = Pin not connected internally

CE#
OE#

WE#
RESET#
BYTE# RY/BY#

21518A-3

Am29LL800B 5

ADVANCE INFORMATION

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the elements below.

CE-150Am29LL800B T

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

Am29LL800BT-150,
Am29LL800BB-150

Am29LL800BT-200,
Am29LL800BB-2 00

Valid Combinations

EC, EI, FC, FI, SC, SI

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29LL800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

2.2 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

6 Am29LL800B

ADVANCE INFORMATION

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29LL800B Device Bus Operations

Operation CE# OE# WE# RESET #

Read L L H H A

Write L H L H A
Standby
Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

Notes:

1. Addresses are A18:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.

, H = Logic High = VIH, VID = 10.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, D

IL

VCC ±

0.3 V

XX

VCC ±

0.3 V

), A18:A-1 in byte mode (BYTE# = VIL).

IH

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.

DQ8–DQ15

Addresses

Sector Addresses,

A6 = L, A1 = H,

ID

Sector Addresses,

A6 = H, A1 = H,

ID

ID

(Note 1)

IN
IN

X High-Z High-Z High-Z

A0 = L

A0 = L

A

IN

DQ0–

DQ7

D

OUT

D

IN

D

IN

D

OUT

D

IN

D

OUT

D

IN

BYTE#

= V

IH

D

,

,

DQ8–DQ14 = High-Z,

OUT

D

IN

XX

XX

XX

DQ15 = A-1

BYTE#

= V

IL

= Data Out

OUT

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the by te or word configur a­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con­trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates arra y data to the output pins . WE# should
remain at V

. The BYTE# pin determines whether the

IH

device outputs array data in words or bytes.

. CE# is the power

IL

Am29LL800B 7

The internal state machine is set for reading array
data upon device po wer-u p , or after a hardw are res et.
This ensure s that no sp urious alteration of the mem­ory content occurs dur ing the power transition. No
command is nece ssary in this mode to ob tain array
data. Standard microprocessor read cycles that as­sert valid addresses on the de vice addr ess inputs pro­duce valid dat a on the de vice da ta outputs . The de vice
remains enabled for read access until the command
register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to Figure 14 for the timing diagram. I

CC1

in

the DC Characteristics table represents the active cur­rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing

ADVANCE INFORMATION

sectors of memory), the system must drive WE# and
CE# to V

, and OE# to VIH.

IL

For program operations, the BYT E# pin determin es
whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in­formation.

The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un­lock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “Word/Byte
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.

An erase operation can erase one sect or, multiple sec­tors, or the entire device. Tables 2 and 3 indic ate the
address space that each sector occupies. A “sector ad­dress” consists of the addres s bits required t o un iquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation

CC

Status” for more information, and to “AC Characteris­tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the de­vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V

CC

± 0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# ar e held at VIH, but not within

V

IH

± 0.3 V, the device will be in the standby mode, b ut

V

CC

the standby current will be grea ter. The device requires
standard access time (t

) for read access when the

CE

device is in either of these standby modes, before it is
ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, RE­SET#: Hardware Reset Pin.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

in the DC Characteristics table represents the

I

CC3

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The de vice automatically enables
this mode when addresses remain stable f or t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I

CC4

Characteristics table represents the automatic sleep

+ 30

ACC

in the DC

8 Am29LL800B

ADVANCE INFORMATION

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to reading array data. When the RE­SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and igno res all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

draws CMOS standby current (I

but not within VSS±0.3 V, the standby current will

at V

IL

±0.3 V, the device

SS

). If RESET# is held

CC4

be greater.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory. During power-up, the

RP

, the

system must ensure that RESET# is high t

RSTW

before
asserting a valid address (see Fi gure 1 and the
Erase/Program Operations table).

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine
whether the reset oper ation is c omplete . If RESE T# is
asserted when a program or erase oper ation is not e x­ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V

(not during Embed-

READY

.

IH

RH

after

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

RESET#

V

CC

Address

Data

2.2 – 2.7 V

0 V

t

CE

t

ACC

t

RSTW

Figure 1. Power-up and Reset Timings

VALID

VALID OUTPUT

Am29LL800B 9

ADVANCE INFORMATION

Table 2. Am29LL800BT Top Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh
SA10001XXX 64/32 10000h–1FFFFh08000h–0FFFFh
SA20010XXX 64/32 20000h–2FFFFh10000h–17FFFh
SA30011XXX 64/32 30000h–3FFFFh18000h–1FFFFh
SA40100XXX 64/32 40000h–4FFFFh20000h–27FFFh
SA50101XXX 64/32 50000h–5FFFFh28000h–2FFFFh
SA60110XXX 64/32 60000h–6FFFFh30000h–37FFFh
SA70111XXX 64/32 70000h–7FFFFh38000h–3FFFFh
SA81000XXX 64/32 80000h–8FFFFh40000h–47FFFh

SA91001XXX 64/32 90000h–9FFFFh48000h–4FFFFh
SA101010XXX 64/32 A0000h–AFFFFh50000h–57FFFh
SA111011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh
SA121100XXX 64/32 C0000h–CFFFFh60000h–67FFFh
SA131101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh
SA141110XXX 64/32 E0000h–EFFFFh70000h–77FFFh
SA1511110XX 32/16 F0000h–F7FFFh78000h–7BFFFh
SA161111100 8/4 F8000h–F9FFFh7C000h–7CFFFh
SA171111101 8/4 FA000h–FBFFFh7D000h–7DFFFh
SA18111111X 16/8 FC000h–FFFFFh7E000h–7FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Table 3. Am29LL800BB Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Sector A18 A17 A16 A15 A14 A13 A12

SA0000000X 16/8 00000h–03FFFh00000h–01FFFh

SA10000010 8/4 04000h–05FFFh02000h–02FFFh

SA20000011 8/4 06000h–07FFFh03000h–03FFFh

SA300001XX 32/16 08000h–0FFFFh04000h–07FFFh

SA40001XXX 64/32 10000h–1FFFFh08000h–0FFFFh

SA50010XXX 64/32 20000h–2FFFFh10000h–17FFFh

SA60011XXX 64/32 30000h–3FFFFh18000h–1FFFFh

SA70100XXX 64/32 40000h–4FFFFh20000h–27FFFh

SA80101XXX 64/32 50000h–5FFFFh28000h–2FFFFh

SA90110XXX 64/32 60000h–6FFFFh30000h–37FFFh
SA100111XXX 64/32 70000h–7FFFFh38000h–3FFFFh
SA111000XXX 64/32 80000h–8FFFFh40000h–47FFFh
SA121001XXX 64/32 90000h–9FFFFh48000h–4FFFFh
SA131010XXX 64/32 A0000h–AFFFFh50000h–57FFFh
SA141011XXX 64/32 B0000h–BFFFFh58000h–5FFFFh
SA151100XXX 64/32 C0000h–CFFFFh60000h–67FFFh
SA161101XXX 64/32 D0000h–DFFFFh68000h–6FFFFh
SA171110XXX 64/32 E0000h–EFFFFh70000h–77FFFh
SA181111XXX 64/32 F0000h–FFFFFh78000h–7FFFFh

Kwords)

Address Range (in hexadecim al )

(x8)

Address Range

(x16)

Address Range

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section for more information.

10 Am29LL800B

ADVANCE INFORMATION

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A1, and A0 must be as shown in Table 4. In addition,

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID:

Am29LL800B
(Top Boot Block)

on address pin A9. Address pins A6,

ID

Table 4. Am29LL800B Autoselect Codes (High Voltage Method)

A18

A11

to

to

A12

A10 A9

Word L L H

Byte L L H X EAh

XXVIDXLXLH

when verifying sector protection, the sector address
must appear on the appropria te highest order address
bits (see Tables 2 and 3). Ta ble 4 shows the remaining
address bits that are don’t care. When all necessary bits
have been set as required, the programming equipment
may then read the corresponding identifier code on
DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V

. See “Command Definitions” for

ID

details on using the autoselect mode.

A8

to

A7 A6

XLXLL X 01h

ID

A5

to

A2 A1 A0

DQ8

to

DQ15

22h EAh

DQ7

DQ0

to

Device ID:
Am29LL800B
(Bottom Boot
Block)

Sector Protection
Verification

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sect or. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors. Sector protection/unprotecti on can be imple­mented via two methods.

The primary method requires V
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo­rithms and Figure 24 shows the timing diagram. This
method uses standard m icroprocessor bus cycle tim­ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unpro tect write
cycle.

The alternate method intended on ly for programming
equipment requires V
This method is compatible with programmer routines

Word L L H

Byte L L H X 6Bh

XXV

LLHSAXV

XLXLH

ID

XLXHL

ID

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

on the RESET# pin

ID

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE­SET# pin to V
sectors can be programmed or erased b y selecting the
sector addresses. Once V
SET# pin, all the previously protected sectors are

on address pin A9 and OE#.

ID

protected again. Figure 3 shows the algorithm, and
Figure 23 shows the timing diagrams, for this feature.

written for earlier 3.0 v olt-only AMD flash de vices. Pub­lication number 21466 contains further details; contact
an AMD representative to request a copy.

22h 6Bh

X 01h protected
X 00h unprotected

. During this mode, formerly protected

ID

is removed from the RE-

ID

Am29LL800B 11

ADVANCE INFORMATION

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 µs

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

No

All sectors
protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector
address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Figure 2. In-System Sector Protect/Unprotect Algorithms

12 Am29LL800B

Sector Unprotect

complete

21518A-4