AMD Advanced Micro Devices AM29F800BT-90SEB, AM29F800BT-90SE, AM29F800BT-90SCB, AM29F800BT-90SC, AM29F800BT-90FIB Datasheet
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PRELIMINARY
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F800 device
■ High performance
— Access times as fast as 55 ns
■ Low power consumption (typical values at 5
MHz)
— 1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 progr am/erase cycles per
sector guaranteed
■ Package option
— 48-pin TSOP
— 44-pin SO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset p in (RESET#)
— Hardware method to reset the de vice t o reading
array data
Publication# 21504 Rev: C Amendment/+1
Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flas h
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO and 48-pin
TSOP packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt V
A 12.0 V V
is not required for write or erase opera-
PP
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.35 µm
process technology, and off ers all the f eatures and benefits of the Am29F800, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 70, 90,
120, and 150 ns, allowing high speed microprocessors
to operate without wai t states . To eliminate b us contention the device has separate chip enable (CE#), wr ite
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and wr ite functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co ntrols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
supply.
CC
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any s ector that is not selected for
erasure. True background erase can thus be achie ved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consum ption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases al l
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
2 Am29F800B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Am29F800B
Speed Option
Max access time, ns (t
Max CE# access time, ns (tCE) 55 70 90 120 150
Max OE# access time, ns (tOE) 30 30 35 50 55
VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -70 -90 -120 -150
) 55 70 90 120 150
ACC
Note: See “AC Character ist ics ” for full specifications.
BLOCK DIAGRAM
–
DQ15 (A-1)
STB
DQ0
Input/Output
Buffers
Data
Latch
V
CC
V
SS
RESET#
WE#
BYTE#
CE#
OE#
RY/BY#
State
Control
Command
Register
Sector Switches
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
A0–A18
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
21504C-1
Am29F800B 3
CONNECTION DIAGRAMS
PRELIMINARY
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin TSOP—Standard Pinout
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-Pin TSOP—Reverse Pinout
4 Am29F800B
21504C-2
CONNECTION DIAGRAMS
PRELIMINARY
SO
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
PIN CONFIGURATION
A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
= +5.0 V single power supply
V
CC
V
SS
NC = Pin not connected internally
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
= Device ground
LOGIC SYMBOL
19
A0–A18
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
21504C-3
16 or 8
DQ0–DQ15
(A-1)
21504C-4
Am29F800B 5
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
CE-70Am29F800B T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
Am29F800BT-55,
Am29F800BB-55
Am29F800BT- 70,
Am29F800BB-70
Am29F800BT-90,
Am29F800BB-90
Am29F800BT-120,
Am29F800BB-120
Valid Combinations
EC, EI, FC, FI, SC, SI
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F800BT-150,
Am29F800BB-150
6 Am29F800B
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1. Am29F800B Device Bus Operations
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
DQ8–DQ15
OUT
D
D
BYTE#
= V
IH
High-Z
High-Z
IN
IN
X
BYTE#
Operation CE# OE# WE# RESET# A0–A18 DQ0–DQ7
Read L L H H A
Write L H L H A
CMOS Standby V
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note)
Legend:
L = Logic Low = V
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
IL
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are activ e and c ontrolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessar y in this mode to obtain array
.
IH
± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
CC
XXX V
ID
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
. CE# is the power
IL
sectors of memory), the system must drive WE# and
CE# to V
, and OE# to VIH.
IL
An erase operation can erase one sect or, multiple sectors, or the entire de vice. The Sector Address Tabl es indicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
IN
IN
A
IN
D
OUT
D
IN
D
IN
= Data Out, AIN = Address In
OUT
in the DC Characteristics
CC1
= V
D
data. Standard microprocessor read cycles that as-
IL
Am29F800B 7
PRELIMINARY
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
in the DC Characteristics table represents the ac-
I
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restrict ed voltage range than V
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t
) for read access when
CE
the device is in either of these standb y modes, bef ore it
is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program ming, the device draws active current until the
operation is completed.
± 0.5 V. (Note
CC
. The device re-
IH
IH
In the DC Characteristics tables, I
CC3
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to readin g arr ay data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
, the device enters
IL
the TTL standby mode; if RESET# is held at V
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
.)
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V
(not during Embe dded Algo-
READY
.
IH
RH
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
represents the
RP
SS
after the RE-
,
±
8 Am29F800B
PRELIMINARY
Table 2. Am29F800BT Top Boot Block Sector Address Table
Sector Size
(Kbytes/
Sector A18 A17 A16 A15 A14 A13 A12
SA0 0 0 0 0 X X X 64/32 00000h–07FFFh 00000h–0FFFFh
SA1 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh
SA2 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh
SA3 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh
SA4 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh
SA5 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh
SA6 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh
SA7 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh
SA8 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh
SA9 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh
SA10 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
SA11 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA12 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA13 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
Kwords)
Address Range (in hexadecim al )
(x16)
Address Range
(x8)
Address Range
SA14 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA15 1 1 1 1 0 X X 32/16 78000h–7BFFFh F0000h–F7FFFh
SA16 1 1 1 1 1 0 0 8/4 7C000h–7CFFFh F8000h–F9FFFh
SA17 1 1 1 1 1 0 1 8/4 7D000h–7DFFFh FA000h–FBFFFh
SA18 1 1 1 1 1 1 X 16/8 7E000h–7FFFFh FC000h–FFFFFh
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Am29F800B 9
PRELIMINARY
Table 3. Am29F800BB Bottom Boot Block Sector Address Table
Sector Size
(Kbytes/
Sector A18 A17 A16 A15 A14 A13 A12
SA0000000X 16/8 00000h–01FFFh 00000h–03FFFh
SA1 0 0 0 0 0 1 0 8/4 02000h–02FFFh 04000h–05FFFh
SA2 0 0 0 0 0 1 1 8/4 03000h–03FFFh 06000h–07FFFh
SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh
SA4 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh
SA5 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh
SA6 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh
SA7 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh
SA8 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh
SA9 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh
SA10 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh
SA11 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh
SA12 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh
SA13 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
Kwords)
Address Range (in hexadecim al )
(x16)
Address Range
(x8)
Address Range
SA14 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA15 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA16 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
SA17 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA18 1 1 1 1 X X X 64/32 78000h–7FFFFh F0000h–FFFFFh
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
(11.5 V to 12.5 V) on address pin
ID
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Definitions table. This method does not require V
. See
ID
“Command Definitions” for details on using the autoselect mode.
10 Am29F800B
PRELIMINARY
Table 4. Am29F800B Autoselect Codes (High Voltage Method)
Description Mode CE# OE# WE#
A18
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
Device ID:
Am29F800B
(Top Boot Block)
Device ID:
Am29F800B
(Bottom Boot Block)
Sector Protection Verification L L H SA X V
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Word L L H
XXV
Byte L L H X D6h
Word L L H
XXV
Byte L L H X 58h
XLXLL X 01h
ID
XLXLH
ID
XLXLH
ID
XLXHL
ID
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a cop y of the appropriate
document.
) on address pin A9 and the
ID
22h D6h
22h 58h
X
X
START
RESET# = V
(Note 1)
Perform Erase or
Program Operations
RESET# = V
ID
IH
01h
(protected)
00h
(unprotected)
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
The Sector Unprotect mode is acti v ated b y setti ng the
RESET# pin to V
tected sectors can be programmed or erased by selecting the sector addresses. Once V
from the RESET# pin, all the previously protected
sectors are protec ted again. Figure 1 shows the algorithm, and the Temporar y Sector Unprotect diagram
shows the timing wavefor ms, for this feature.
. During this mode, formerly pro-
ID
is removed
ID
Am29F800B 11
Temporary Sector
Unprotect
Completed (Note 2)
21504C-5
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
PRELIMINARY
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures pre vent accidental eras ure or programming, which might otherwise be caus ed by spurious system level signals during V
power-up and
CC
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
Write Inhibit
CC
is less than V
CC
, the device does not ac-
LKO
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
. The system must provide the
LKO
CC
COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
proper signals to the control pins to prevent unintentional writes when V
is greater than V
CC
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = VIH during power up , the
IL
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
ters, and Read Operation T imings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend m ode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information
on this mode.
must
The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
issue the reset command to re-en-
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
12 Am29F800B
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