AMD Advanced Micro Devices AM29F800BT-90DPC1, AM29F800BT-90DGI1, AM29F800BT-90DGC1, AM29F800BT-120DGE1, AM29F800BT-120DGC1 Datasheet
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SUPPLEMENT
Am29F800B Known Good Die
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory—Die Revision 1
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F800 device
■ High performance
— 90 or 120 ns access time
■ Low power consumption (typical values at 5
MHz)
—1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycles per sector
guaranteed
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset p in (RESET#)
— Hardware method to reset the de vice t o reading
array data
5/4/98
Publication# 21631 Rev: A Amendment/+2
Issue Date: April 1998
SUPPLEMENT
GENERAL DESCRIPTION
The Am29F800B in Known Good Die (KGD) form is a
8 Mbit, 5.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same reliability and quality as AMD products in packaged form.
Am29F800B Features
The Am29F800B is an 8 Mbit, 5.0 volt-only Flas h
memory organized as 1,048,576 bytes or 524,288
words. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed
in-system with the standard system 5.0 volt V
supply. A 12.0 V VPP is not required for write or erase
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.35 µm
process technology, and off ers all the f eatures and benefits of the Am29F800, which was manufactured using
0.5 µm process technology.
CC
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and wr ite functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an in ternal algorithm that autom atically
preprograms the array (if it is not already prog rammed)
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any s ector that is not selected for
erasure. True background erase can thus be achie ved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consum ption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases al l
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F800B data sheet, PID 21504, for full
electrical specifications on the Am29F800B in KGD
for m .
2 Am29F800B Known Good Die 5/4/98
SUPPLEMENT
PRODUCT SELECTOR GUIDE
Family Part Number Am29F800B KGD
Speed Option (V
Max access time, ns (t
= 5.0 V ± 10%) -90 -120
CC
) 90 120
ACC
Max CE# access time, ns (tCE) 90 120
Max OE# access time, ns (tOE) 35 50
DIE PHOTOGRAPH DIE PAD LOCATIONS
Orientation relative
to leading edge of
tape and reel
9876543214443424140393837
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12
36
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AMD logo loca tio n
13
2120191817161514
22
Orientation relative
to top left corner of
Gel-Pak
5/4/98 Am29F800B Known Good Die 3
32
313029282726252423
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