AMD Advanced Micro Devices AM29F400BT-90SIB, AM29F400BT-90SI, AM29F400BT-90SEB, AM29F400BT-90SCB, AM29F400BT-90SC Datasheet
...
PRELIMINARY
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 5.0 Volt-only Boot Sec tor Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F400 device
■ High performance
— Access times as fast as 55 ns
■ Low power consumption (typical values at 5
MHz)
— 1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 progr am/erase cycles per
sector guaranteed
■ Package option
— 48-pin TSOP
— 44-pin SO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operati on to read dat a from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the de vice t o reading
array data
Publication# 21505 Rev: C Amendment/+2
Issue Date: April 1998
PRELIMINARY
GENERAL DESCRIPTION
The Am29F400B is a 4 M bit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offer ed in 44-pin S O and 48-pin TSO P
packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt V
A 12.0 V V
is not required for write or erase opera-
PP
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the f eatures and benefits of the Am29F400, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 60, 70,
90, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command regis ter using
standard micropr ocessor wri te timings. Register co ntents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase co mmand sequence. This initiates the Embedded Erase
supply.
CC
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and
DQ6/DQ2 (toggle) status bits. After a program or
erase cycle has been completed, the de vice i s ready to
read array data or accept another command.
The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection meas ures include a low
detector that automatically in hibits write opera-
V
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the devi ce into the standb y mode.
Pow er cons umption is g reatly r educed in this mode .
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all b i ts wi thin a se c tor
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
2 Am29F400B
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number Am29F400B
Speed Option
Max access time, ns (t
Max CE# access time, ns (tCE) 55 60 70 90 120 150
Max OE# access time, ns (tOE) 30 30 30 35 50 55
VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -60 -70 -90 -120 -150
) 55 60 70 90 120 150
ACC
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
–
DQ15 (A-1)
STB
DQ0
Input/Output
Buffers
Data
Latch
V
CC
V
SS
RESET#
WE#
BYTE#
CE#
OE#
RY/BY#
State
Control
Command
Register
Sector Switches
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
A0–A17
VCC Detector
Timer
STB
Address Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
21505C-1
Am29F400B 3
CONNECTION DIAGRAMS
PRELIMINARY
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin TSOP—Standard Pinout
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
48-Pin TSOP—Reverse Pinout
4 Am29F400B
21505C-2
CONNECTION DIAGRAMS
PRELIMINARY
SO
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
21505C-3
PIN CONFIGURATION
A0–A17 = 18 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
= +5.0 V single power supply
V
CC
V
SS
NC = Pin not connected internally
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
= Device ground
LOGIC SYMBOL
18
A0–A17
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
16 or 8
DQ0–DQ15
(A-1)
21505C-4
Am29F400B 5
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
CE-55Am29F400B T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commerc ial (0°C to +70° C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
Am29F400BT-55,
Am29F400BB-55
Am29F400BT-60,
Am29F400BB-60
Am29F400BT-70,
Am29F400BB-70
Am29F400BT-90,
Am29F400BB-90
Am29F400BT-120,
Am29F400BB-120
Valid Combinations
EC, EI, FC, FI, SC, SI
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DES CR IP TIO N
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F400BT-150,
Am29F400BB-150
6 Am29F400B
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1. Am29F400B Device Bus Operations
Operation CE# OE# WE# RESET# A0–A17 DQ0–DQ7
Read L L H H A
Write L H L H A
±
V
CMOS Standby
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note)
CC
0.5 V
XXX V
XX
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.
DQ8–DQ15
VCC ±
0.5 V
ID
BYTE#
= V
IN
IN
X High-Z High-Z High-Z
A
IN
D
OUT
D
D
IN
IN
D
OUT
D
D
BYTE#
= V
IH
High-Z
High-Z
IN
High-Z
IN
IL
Legend:
L = Logic Low = V
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are activ e and c ontrolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
IL
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to Figure 9 for the t imin g diagram. I
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
OUT
cludes programming data to the device and erasing
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the dev ice. OE# is the output control and gates arra y data to the output pins . WE# should
remain at V
. The BYTE# pin determines whether the
IH
device outputs array data in words or bytes.
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
. CE# is the power
IL
sectors of memory), the system must drive WE# and
CE# to V
, and OE# to VIH.
IL
For program operations, the BYTE # pin determines
whether the device accepts program data in bytes o r
words. Refer to “Word/Byte Configuration” for more information.
An erase operation can erase one sect or, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector address” consists of the address b its requ ired to uni quely
select a sector. The “Command D efinitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
on the device address input s produc e valid data on the
= Data Out, AIN = Address In
in the
CC1
Am29F400B 7
PRELIMINARY
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
in the DC Characteristics table represents the ac-
I
CC2
tive current specification for the w rite mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pin s are both held at V
(Note that this is a more restricted voltage range than
.) The device enters the TTL standby mode when
V
IH
CE# and RESET# pins are both held at V
requires standard access time (t
) for read access
CE
when the device is in either of these s tandby modes,
before it is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
± 0.5 V.
CC
. The device
IH
In the CMOS and TTL/NMOS-compatible DC Characteristics tables, I
represents the standby current
CC3
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t
RP,
the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
the TTL standby mode; if RESET# is held at V
, the device enters
IL
SS
±0.5
V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
rithms). The system can read data t
SET# pin returns to V
(not during Embe dded Algo-
after the RE-
.
IH
RH
Refer to the AC Characteristics tables for RESET# parameters and to Figure 10 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
8 Am29F400B
PRELIMINARY
Table 2. Am29F400BT Top Boot Block Sector Address Table
Sector Size
(Kbytes/
Sector A17 A16 A15 A14 A13 A12
SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA71110XX 32/16 70000h–77FFFh38000h–3BFFFh
SA8111100 8/4 78000h–79FFFh3C000h–3CFFFh
SA9111101 8/4 7A000h–7BFFFh3D000h–3DFFFh
SA1011111X 16/8 7C000h–7FFFFh3E000h–3FFFFh
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
Table 3. Am29F400BB Bottom Boot Block Sector Address Table
Sector Size
(Kbytes/
Sector A17 A16 A15 A14 A13 A12
SA000000X 16/8 00000h–03FFFh00000h–01FFFh
SA1000010 8/4 04000h–05FFFh02000h–02FFFh
SA2000011 8/4 06000h–07FFFh03000h–03FFFh
SA30001XX 32/16 08000h–0FFFFh04000h–07FFFh
SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh
Note:
Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration” section for more information.
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
(11.5 V to 12.5 V) on address pin
ID
Am29F400B 9
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t care .
When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require V
. See “Command Definitions” for
ID
details on using the autoselect mode.
Table 4. Am29F400B Autoselect Codes (High Voltage Method)
Description Mode CE# OE# WE#
PRELIMINARY
A17
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
Device ID:
Am29F400B
(Top Boot Block)
Device ID:
Am29F400B
(Bottom Boot Block)
Sector Protection Verification L L H SA X V
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Word L L H
XXV
Byte L L H X 23h
Word L L H
XXV
Byte L L H X ABh
XLXLL X 01h
ID
XLXLH
ID
XLXLH
ID
XLXHL
ID
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any se ctor. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
Details on this method are provided in a supplement,
publication number 20185. Contact an AMD representative to obtain a copy of this document.
The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unpr otection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to V
sectors can be programmed or erased by sele cting the
sector addresses. Once V
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 18 shows the timing diagrams, for this feature.
. During this mode, formerly protected
ID
) on address pin A9 and OE#.
ID
is removed from the RE-
ID
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadverten t writes (refer to Table 5 for command definitions). In addition, the following hardwar e
data protection mea sures prevent accidental erasure
or programming, which might otherwise be caused by
22h 23h
22h ABh
X
X
START
RESET# = V
(Note 1)
Perform Erase or
Program Operations
RESET# = V
Temporary Sector
Unprotect Completed
(Note 2)
ID
IH
01h
(protected)
00h
(unprotected)
21505C-5
10 Am29F400B
PRELIMINARY
spurious system level signals during V
power-up and
CC
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
Write Inhibit
CC
is less than V
CC
, the device does not ac-
LKO
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
. The system must provide the
LKO
CC
proper signals to the control pins to prevent unintentional writes when V
is greater than V
CC
LKO
.
COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device operations. Table 5 de fines the valid registe r command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information
on this mode.
must
The system
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parameters, and Figure 9 shows the timing diagram.
issue the reset command to re-ena-
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
, CE# = VIH or WE# = VIH. To initiate a write cycle,
V
IL
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = VIH during power up , the
IL
device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
howeve r, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (a lso applies during Erase Suspend).
Autoselect Command Sequence
The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
T ab le 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requi res V
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
ID
Am29F400B 11
PRELIMINARY
number of times, without initiating another command
sequence.
A read cycle at address XX00h or re trie ves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
not
system is
ings. The device automatically provides internally generated program pulses and verify the programmed cell
margin. Table 5 shows the address and data requirements for the byte prog ram command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
required to provide further controls or tim-
START
Write Program
Command Sequence
Data Poll
Embedded
Program
algorithm
in progress
Increment Address
Note:
See Table 5 for program command sequence.
No
from System
Verify Data?
Yes
Last Address?
Yes
Programming
Completed
No
21505C-6
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bu s-cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
not
algorithm. The device does
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any controls or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
require the system to
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.
12 Am29F400B
Loading...