AMD Advanced Micro Devices AM29F400AT-90FIB, AM29F400AT-90FI, AM29F400AT-90FCB, AM29F400AT-90FC, AM29F400AT-90EIB Datasheet

5.0 V-only Flash

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PRELIMINARY

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Am29F400AT/Am29F400AB

4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

Compatible with JEDEC-standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

Package options

— 44-pin SO
— 48-pin TSOP

Minimum 100,000 write/erase cycles guaranteed
High performance

— 60 ns maximum access time

Sector erase architecture

— One 16 Kbyte, two 8 Kbytes , one 32 Kbyte, and

seven 64 Kbytes

— Any combination of sectors can be erased. Also

supports full chip erase.

Sector protection

— Hardware method that disables any combination

of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.

Embedded Erase  Algorithms

— Automatically preprograms and erases the chip

or any sector

Embedded Program  Algorithms

— Automatically programs and verifies data at

specified address

Data

Polling and Tog gle Bit feature for detection

of program or erase cycle completion
Ready/Busy output (RY/BY)

— Hardware method for detection of program or

erase cycle completion

Erase Suspend/Resume

— Supports reading data from a sector not being

erased

Low power consumption

— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current

Enhanced power management for standby
mode

—1 µ A typical standby current

Boot Code Sector Architecture

— T = Top sector
— B = Bottom sector

Hardware RESET

— Resets internal state machine to the read mode

pin

GENERAL DESCRIPTION

The Am29F400A is a 4 Mbit, 5.0 V olt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system

5.0 Volt V
program or erase operations. The de vice can also be re­programmed in standard EPROM programmers .

This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.

supply. 12.0 Volt V

CC

is not required for

PP

The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa­rate chip enable (CE
enable (OE) controls.

The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con­tents serve as input to an internal state-machine
which controls the erase and programming circuitry.

), write enable (WE) and output

Publication# 20380 Rev: B Amendment/0
Issue Date: April 1997

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PRELIMINARY

Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.

The Am29F400A is programmed by executing the pro­gram command sequence. This will invoke the Embed­ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase , the de vice automat­ically times the erase pulse widths and verifies proper
cell margin.

This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re­programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F400A is erased when
shipped from the factory.

The Am29F400A device also features hardw are sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.

AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true backg round erase can be achieved.

The device features single 5.0 Volt power supply oper­ation for both read and write functions. Internally gen­erated and regulated voltages are provided for the
program and erase operations. A low V

detector au-

CC

tomatically inhibits write operations during power tran­sitions. The end of program or erase is detected by the

pin. Data Polling of DQ7, or by the Toggle Bit

RY/BY
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.

The Am29F400A also has a hardware RESET pin.
When this pin is driven low, execution of any Embed­ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto­matically reset to the read mode and will have errone­ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys­tem’s microprocessor to read the boot-up firmware
from the Flash memory.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective­ness. The Am29F400A memory electrically erases all
bits within a sector simultaneously via
Fowler-Nordhiem tunneling. The bytes/words are pro­grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.

Flexible Sector-Erase Architecture

One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbyte sectors

Individual-sector or multiple-sector erase capability
Sector protection is user definable

(x8) (x16)

7FFFFh 3FFFFh
7BFFFh 3DFFFh
79FFFh 3CFFFh
77FFFh 3BFFFh
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h 00000h

20380B-1

(x8) (x16)

7FFFFh 3FFFFh
6BFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
05FFFh 02FFFh
03FFFh 01FFFh
00000h 00000h

20380B-2

SA10

SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

SA10

SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

16 Kbyte

8 Kbyte

8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte

Am29F400AT Sector Architecture

64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte

8 Kbyte

8 Kbyte
16 Kbyte

Am29F400AB Sector Architecture

2 Am29F400AT/Am29F400AB

5.0 V-only Flash

%

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part No: Am29F400A

Ordering Part No:V

Max Access Time (ns) 60 70 90 120 150
CE

(E) Access (ns) 60 70 90 120 150

OE (G) Access (ns) 30 30 35 50 55

= 5.0 V ±

CC

V

= 5.0 V ± 10%

CC

5

-65

-70 -90 -120 -150

BLOCK DIAGRAM

DQ0–DQ15

V
V

WE

BYTE

RESET

A0-A17

A-1

CC
SS

CE
OE

RY/BY

Buffer

State

Control

Command

Register

V

Detector

CC

RY/BY

PGM V oltage

Generator

Timer

Erase V oltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

Address Latch

STB

Input/Output

Buffers

Data

Latch

Y-Gating

Cell MatrixX-Decoder

20380B-3

Am29F400AT/Am29F400AB 3

CONNECTION DIAGRAMS

PRELIMINARY

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

NC

RY/BY

A17

A7
A6
A5
A4
A3
A2
A1
A0

CE

V

SS

OE
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

20380B-4

4 Am29F400AT/Am29F400AB

5.0 V-only Flash

CONNECTION DIAGRAMS

PRELIMINARY

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE

RESET

NC
NC

RY/BY

NC

A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16

BYTE

V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

OE

V

SS

CE

A0

20380B-5

A16

BYTE

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE

V

SS

CE

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC

WE
RESET

NC
NC
RY/BY
NC

A17
A7
A6
A5
A4
A3
A2
A1

20380B-6

Am29F400AT/Am29F400AB 5

PRELIMINARY

PIN CONFIGURATION

A1, A0–A17 = 18 Addresses
BYTE
CE = Chip Enable
DQ0–DQ15 = 16 Data Inputs/Outputs
NC = Pin Not Connected Internally
OE = Output Enable
RESET = Hardware Reset Pin, Active Low
RY/BY = Ready/Busy Output
V

SS

V

SS

WE

= Selects 8-bit or 16-bit mode

= +5.0 V olt Single-Power Supply

( ± 10% for -90, -120, -150) or ( ± 5% for -75)
= Device Ground
= Write Enable

LOGIC SYMBOL

A-1

18

A0–A17

CE

(E)

(G)

OE
WE

(W)

RESET
BYTE

16 or 8

DQ0–DQ15

RY/BY

20380B-7

6 Am29F400AT/Am29F400AB

5.0 V-only Flash

PRELIMINARY

ORDERING INFORMATION
Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi­nation) is formed by a combination of the following:

AM29F400A -65 E C

T

DEVICE NUMBER/DESCRIPTION

Am29F400A
4 Megabit (512K x 8-Bit/256K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

B

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

TEMPERATURE RANGE

C = Commercial (0
I = Industrial (-40

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and
Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

°C to +70°C)

°C to +85°C)

AM29F400AT/B-65 EC, EI, FC, FI, SC, SI
AM29F400AT/B-70
AM29F400AT/B-90
AM29F400AT/B-120
AM29F400AT/B-150

Valid Combinations

EC, EI, EE, EEB,

FC, FI, FE, FEB,
SC, SI, SE, SEB

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

Am29F400AT/Am29F400AB 7

PRELIMINARY

±

Table 1. Am29F400A User Bus Operations (BYTE = V

Operation CE

Autoselect, AMD Manuf. Code (Note 1) L L H L L L V
Autoselect Device Code (Note 1) L L H H L L V
Read L L H A0 A1 A6 A9 D
Standby H XXXXXXHIGH Z H
Output Disable L H H XXXXHIGH Z H
Write L H L A0 A1 A6 A9 D
Verify Sector Protect (Note 2) L LHLHLV
Temporary Sector Unprotect XXXXXXX X V
Hardware Reset XXXXXXXHIGH Z L

OE WE A0 A1 A6 A9 DQ0–DQ15 RESET

Table 2. Am29F400A User Bus Operations (BYTE

Operation CE

Autoselect, AMD Manuf. Code
(Note 1)

Autoselect Device Code (Note 1) L L H H L L V
Read L L H A0 A1 A6 A9 D
Standby H XXXXXXHIGH Z HIGH Z H
Output Disable L H H XXXXHIGH Z HIGH Z H
Write L H L A0 A1 A6 A9 DIN HIGH Z H
Verify Sector Protect (Note 2) L LHLHLVIDCode HIGH Z H
Temporary Sector Unprotect XXXXXXX X HIGH Z V
Hardware Reset XXXXXXXHIGH Z HIGH Z L

OE WE A0 A1 A6 A9 DQ0–DQ7 DQ8–DQ15 RESET

LLHLLLV

ID

ID

)

IH

ID

ID

ID

= V

)

IL

Code HIGH Z H

Code HIGH Z H

OUT

Code H
Code H

OUT

IN

Code H

HIGH Z H

H

H

ID

ID

Legend:

L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. Refer to the section on Sector Protection.

Read Mode

The Am29F400A has two control functions which must
be satisfied in order to obtain data at the outputs. CE
the power control and should be used for de vice selec­tion. OE is the output control and should be used to
gate data to the output pins if a device is selected.

Address access time (t

) is equal to the delay from

ACC

stable addresses to valid output data. The chip enable
access time (t
and stable CE

) is the delay from stable addresses

CE

to valid data at the output pins.
The output enable access time is the delay from the
falling edge of OE to valid data at the output pins (as-

is

suming the addresses have been stable for at least
t

-t

OE

time).

ACC

Standby Mode

There are two ways to implement the standb y mode on
the Am29F400A device, both using the CE

A CMOS standby mode is achieved with the CE input
held at V
typically reduced to less than 5 µ A. A TTL standby
mode is achieved with the CE
this condition the current is typically reduced to 1 mA.

In the standby mode the outputs are in the high imped­ance state, independent of the OE

0.5 V. Under this condition the current is

CC

pin held at V

input.

8 Am29F400AT/Am29F400AB

pin.

IH

. Under

PRELIMINARY

5.0 V-only Flash

Output Disable

With the OE input at a logic high level (VIH), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.

Autoselect

The autoselect mode allows the reading of a binary
code from the device and will identify its manufacturer
and type. This mode is intended for use by program­ming equipment for the purpose of automatically
matching the device to be programmed with its corre­sponding programming algorithm. This mode is func­tional over the entire temperature range of the device.

To activate this mode, the programming equipment
must force V
Two identifier bytes may then be sequenced from the
device outputs by toggling address A0 from VIL to VIH.
All addresses are don’t cares except A0, A1, and A6
(see T ab le 3).

The manufacturer and device codes may also be read
via the command register, for instances when the

(11.5 V to 12.5 V) on address pin A9.

ID

Table 3. Am29F400A Sector Protection Verify Autoselect Codes

Am29F400A is erased or programmed in a system
without access to high voltage on the A9 pin. The com­mand sequence is illustrated in Table 4 (see Autoselect
Command Sequence).

Byte 0 (A0 = V

) represents the manufacturer’s code

IL

(AMD=01H) and byte 1 (A0 = VIH) the device identifier
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode). These two bytes/words are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as
the parity bit. In order to read the proper device codes
when executing the Autoselect, A1 must be V
(see Tables 3 and 4).

The autoselect mode also facilitates the determination
of sector protection in the system. By perf orming a read
operation at the address location XX02H with the
higher order address bits A12–A17 set to the desired
sector address, the device will return 01H for a pro­tected sector and 00H for a non-protected sector.

IL

Type A12-A17 A6 A1 A0 Code (HEX)

Manufacturer Code-AMD X V

Am29F400AT

Am29F400A Device

Am29F400AB

Sector Protection

*Outputs 01H at protected sector addresses

Byte

XVILV

Word 2223H

Byte

XVILV

Word 22ABH

Sector

Address

IL

V

IL

V

IL

IL

IL

V

IH

V

IL

V

IH

V

IH

V

IL

01H
23H

ABH

01H*

Table 4. Expanded Autoselect Code Table

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

23H

A-10HI-Z0HI-Z1HI-Z0HI-Z0HI-Z0HI-Z1HI-Z0000011000000111

A-10HI-Z0HI-Z1HI-Z0HI-Z0HI-Z0HI-Z1HI-Z0110011001100111

ABH

0

1

1

(W)

(W)

Code

2223H

22ABH

Type

Manufacturer Code-AMD 01H 0000000000000001

Am29F400AT(B)

Am29F400A
Device

Sector Protection 01H 0000000000000001

Am29F400AB(B)

B) - Byte mode
(W) - Word mode

Am29F400AT/Am29F400AB 9

PRELIMINARY

Table 5. Sector Address Tables (Am29F400AT)

(x8) Address

A17 A16 A15 A14 A13 A12

SA0 0 0 0 X X X 00000h-0FFFFh 00000h-07FFFh
SA1 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA2 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA3 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA4 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA5 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA6 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh
SA71110XX70000h-77FFFh 38000h-3BFFFh
SA811110078000h-79FFFh 3C000h-3CFFFh
SA91111017A000h-7BFFFh 3D000h-3DFFFh

SA10 11111X7C000h-7FFFFh 3E000h-3FFFFh

Range

(x16) Address

Range

Table 6. Sector Address Tables (Am29F400AB)

(x8) Address

A17 A16 A15 A14 A13 A12

SA000000X00000h-03FFFh 00000h-01FFFh
SA100001004000h-05FFFh 02000h-02FFFh
SA200001106000h-07FFFh 03000h-03FFFh
SA30001XX08000h-0FFFFh 04000h-07FFFh
SA4 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh
SA5 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh
SA6 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh
SA7 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh
SA8 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh
SA9 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh

SA10 1 1 1 X X X 70000h-7FFFFh 38000h-3FFFFh

Range

(x16) Address

Range

Write

Device erasure and programming are accomplished via
the command register. The contents of the register serve
as inputs to the internal state machine. The state ma­chine outputs dictate the function of the device.

The command register itself does not occupy any ad­dressable memory location. The register is a latch used
to store the commands, along with the address and data
information needed to execute the command. The com­mand register is written to by bringing WE

to VIL, while
CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later;
while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write
timings are used.

10 Am29F400AT/Am29F400AB

Refer to AC Write Characteristics and the Erase/Pro­gramming Waveforms for specific timing parameters.

Sector Protection

The Am29F400A features hardware sector protection.
This feature will disable both program and erase opera­tions in any combination of ten sectors of memory. The
sector protect feature is enabled using programming
equipment at the user’s site. The device is shipped with
all sectors unprotected. Alternatively , AMD ma y program
and protect sectors in the factory prior to shipping the
device (AMD’ s ExpressFlash  Service).

PRELIMINARY

5.0 V-only Flash

It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where
the higher order address bits A12–A17 is the desired
sector address, will produce a logical “1” at DQ0 for a
protected sector. See Table 3 for Autoselect codes.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors of the Am29F400A device in
order to change data in-system. The Sector Unprotect
mode is activated by setting the RESET pin to high v olt­age (12 V). During this mode, formerly protected sec­tors can be programmed or erased by selecting the
sector addresses. Once the 12 V is taken away from

the RESET pin, all the previously protected sectors will
be protected again. Refer to Figures 16 and 17.

Command Definitions

Device operations are selected by writing specific ad­dress and data sequences into the command register.

Writing incorrect address and data values
or writing them in the improper sequence will reset
the device to the read mode. Table 7 defines the valid

register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) com­mands are valid only while the Sector Erase operation
is in progress. Moreover, both Reset/Read commands
are functionally equivalent, resetting the device to the
read mode.

Am29F400AT/Am29F400AB 11