AMD Advanced Micro Devices AM29F200AT-55SCB, AM29F200AT-55SC, AM29F200AT-55FIB, AM29F200AT-55FI, AM29F200AT-55FEB Datasheet
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PRELIMINARY
Publication# 20637 Rev: B Amendment/+3
Issue Date: March 1998
Am29F200A
2 Megabit (256 K x 8-Bit/128 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
■ High performance
— Access times as fast as 55 ns
■ Low power consumption
— 20 mA typical active read current (byte mode)
— 28 mA typical active read current for
(word mode)
— 30 mA typical program/erase current
—1 µA typical standby current
■ Sector erase architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
three 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
T emporary Sector Unprotect feat ure allows code
changes in previously locked sectors
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 100,000 write/ erase cyc les guaranteed
■ Package options
— 44-pin SO
— 48-pin TSOP
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■ Data# Polling and Toggle Bit
— Detects program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Hardware method for detection of program or
erase cycle completion
■ Erase Suspend/Erase Resume
— Supports reading data from a sector not being
erased
■ Hardware RESET# pin
— Resets internal state machine to the reading
array data
2 Am29F200A
PRELIMINARY
GENERAL DESCRIPTION
The Am29F200A is a 2 Mbit, 5.0 Volt-only Flash memory organized as 262,144 byte s or 131,072 words. The
8 bits of data a ppear on DQ0–DQ7; the 16 bits on DQ0–
DQ15. The Am29F200A is offered in 44-pin SO and
48-pin TSOP packages. This device is designed to be
programmed in-system with the standard system 5.0
volt V
CC
supply. A 12.0 volt VPP is not required for
program or erase operation s. The device can also be
reprogrammed in standard EPROM programmers.
The standard device offers access times of 55, 70,
90, 120, and 150 ns, allowing operation of
high-speed microp ro cess ors withou t w ai t stat es. To
eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co ntrols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase co mmand sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle) status bits. After a program or eras e
cycle has been completed, the device is ready to read
array data or accept another command.
The sector erase archite cture allo ws m emory sect ors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically in hibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory . This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pi n terminates any operation
in progress and resets the internal state machine to
reading array dat a. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the devi ce into the standb y mode.
Pow er cons umption is g reatly r educed in this mode .
AMD’s Flash technology combines years of Flas h memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
program me d using hot electron in je ct i on.
Am29F200A 3
PRELIMINARY
PRODUCT SELECTOR GUIDE
BLOCK DIAGRAM
Family Part Number Am29F200A
Speed Option
V
CC
= 5.0 V ± 5% -55
V
CC
= 5.0 V ± 10% -70 -90 -120 -150
Max access time, ns (t
ACC
) 55 70 90 120 150
Max CE# access time, ns (tCE) 55 70 90 120 150
Max OE# access time, ns (tOE) 3030355055
Erase Voltage
Generator
Input/Output
Buffers
Data
Latch
Y-Gating
Cell MatrixX-Decoder
Y-Decoder
Address Latch
Chip Enable
Output Enable
Logic
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
WE#
CE#
OE#
A0–A16
STB
STB
DQ0–DQ15
RY/BY#
Buffer
RY/BY#
BYTE#
RESET#
A-1
V
CC
V
SS
20637B-1
4 Am29F200A
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
RY/BY#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
20637B-2
Am29F200A 5
PRELIMINARY
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
NC
A7
A6
A5
A4
A3
A2
20637B-3
Standard TSOP
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
A15
NC
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A1
NC
A7
A6
A5
A4
A3
A2
20637B-4
Reverse TSOP
6 Am29F200A
PRELIMINARY
PIN CONFIGURATION
A0–A16 = 17 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
V
CC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
= Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20637B-5
17
16 or 8
DQ0–DQ15
(A-1)
A0–A16
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
Am29F200A 7
PRELIMINARY
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29F200A
2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
CE-55Am29F200A T
Valid Combinations
AM29F200AT-55,
AM29F200AB-55
EC, EI, FC, FI, SC, SI
AM29F200AT-70,
AM29F200AB-70
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
AM29F200AT-90,
AM29F200AB-90
AM29F200AT-120,
AM29F200AB-120,
AM29F200AT-150,
AM29F200AB-150,
8 Am29F200A
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory loc ation.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F200A Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
OUT
= Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the by te or word configur ation. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at V
IH
. On x16 (word-wide) devices, the BYTE# pin
determines whether the device outputs array data in
words or bytes.
The internal state machin e is set for reading array
data upon device power-up, or after a ha rdware reset. This ensures that no spurious alteration of the
memory content occ urs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to VIH.
On x16 (word-wide) devices, for program op erations,
the BYTE# pin dete rmines whether the device a ccepts program data in bytes or words. Refer to
“Word/Byte Configuration” for more information.
Operation CE# OE# WE# RESET# A0–A16 DQ0–DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
High-Z
Write L H L H A
IN
D
IN
D
IN
High-Z
CMOS Standby V
CC
± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
(See Note)
XXX V
ID
A
IN
D
IN
D
IN
X
Am29F200A 9
PRELIMINARY
An erase operation can erase one sect or, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet f or t iming
diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standb y mode when CE#
and RESET# pins are both held at V
CC
± 0.5 V. (Note
that this is a more restrict ed voltage range than V
IH
.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
IH
. The device re-
quires standard access time (t
CE
) for read access
when the device is in either of these s tandby modes,
before it is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, I
CC3
represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardw are method of resetting the device to readin g arr ay data. When the system
drives the RESET# pin low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
IL
, the device enters
the TTL standby mode; if RESET# is held at V
SS
±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embe dded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high impedance state.
10 Am29F200A
PRELIMINARY
Table 2. Am29F200T Top Boot Block Sector Address Tabl e
Table 3. Am29F200B Bottom Boot Block Sector Address Table
Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See “Word/Byte Configuration”
section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Com mand Definitions ta ble shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V
ID
. See “Autoselect Command Sequence” for details on using the
autoselect mode.
Sector A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 1 1 0 X X 32/16 30000h–37FFFh 18000h–1BFFFh
SA4 1 1 1 0 0 8/4 38000h–39FFFh 1C000h–1CFFFh
SA5 1 1 1 0 1 8/4 3A000h–3BFFFh 1D000h–1DFFFh
SA6 1 1 1 1 X 16/8 3C000h–3FFFFh 1E000h–1FFFFh
Sector A16 A15 A14 A13 A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecim al )
(x8)
Address Range
(x16)
Address Range
SA0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh
SA1 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh
SA2 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh
SA3 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh
SA4 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
Am29F200A 11
PRELIMINARY
Table 4. Am29F200A Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 20551. Contact an
AMD representative to obtain a cop y of the appropriate
document.
The device is shipped with all s ectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
The Sector Unprotect mode is acti v ated b y setti ng the
RESET# pin to V
ID
. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are protec ted again. Figure 1 shows the algorithm, and the Temporar y Sector Unprotect diagram
(Figure 18 ) shows the tim ing waveforms, for this feature.
Figure 1. Temporary Sector Unprotect Operati on
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro-
Description Mode CE# OE# WE#
A16
to
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X V
ID
XLXLL X 01h
Device ID:
Am29F200A
(Top Boot Block)
Word L L H
XXVIDXLXLH
22h 51h
Byte L L H X 51h
Device ID:
Am29F200A
(Bottom Boot Block)
Word L L H
XXVIDXLXLH
22h 57h
Byte L L H X 57h
Sector Protection V erification L L H SA X V
ID
XLXHL
X
01h
(protected)
X
00h
(unprotected)
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20637B-6
12 Am29F200A
PRELIMINARY
gramming, which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
IL
, CE# = VIH or WE# = VIH. To initiate a writ e cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = VIH during powe r
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.
COMMAND DEFINITIONS
Writing specific addre ss and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Embedded Erase algorithm.
After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The system
must
issue the reset command to re-enable the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the devi ce resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
howeve r, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (a lso applies during Erase Suspend).
Autoselect Command Sequence
The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table show s the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
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