AMD Advanced Micro Devices AM29F100T-90FC, AM29F100T-90EIB, AM29F100T-90EI, AM29F100T-90EEB, AM29F100T-90EE Datasheet

FINAL

Am29F100

1 Megabit (128 K x 8-bit/64 K x 16-bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

—5.0 V ± 10% for read, erase, and program

operations

— Simplifies system-level power requirements

■ High performance

— 70 ns maximum access time

■ Low power consumption

— 20 mA typical active read current for byte mode
— 28 mA typical active read current for word mode
— 30 mA typical program/erase current
— 25 µA typical standby current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

one 32 Kword sectors (word mode)
— Any combination of sectors can be erased
— Supports full chip erase

■ Top or bottom boot block configurations

available

■ Sector protection

— Hardware-based feature that disables/re-

enables program and erase operations in any

combination of sectors
— Sector protection/unprotection can be

implemented using standard PROM

programming equipment
— Temporary Sector Unprote ct feature allows in-

system code changes in protected sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

pre-programs and erases the chip or any
combination of designated sector

— Embedded Program algorithm automatically

programs and verifies data at specified address

■ Minimum 100,000 program/erase cycles

guaranteed

■ Package options

— 44-pin SO
— 48-pin TSOP

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

■ Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

■ Ready/Busy pin (R Y/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data fr om,

or program data to, a sector that is not being
erased, then resumes the erase operation

■ Hardware RESET# pin

— Hardware method of resetting the device to

reading array data

Publication# 18926 Rev: C Amendment/+2
Issue Date: March 1998

GENERAL DESCRIPTION

The Am29F100 is a 1 Mbit, 5.0 V olt-only Flash memory
organized as 131,072 bytes or 65,536 words. The
Am29F100 is offered in 44-pin SO and 48-pin TSOP
packages. Word-wide data appears on DQ0-DQ15;
byte-wide data on DQ0-DQ7. The device is designed to
be programmed in-system with the standard system

5.0 Volt V
program or erase operations. The device can also be
programmed or erased in standard EPROM program­mers.

The standard device offers access times of 70, 90,
120, and 150 ns, allowing high-speed microproces­sors to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.

supply. A 12.0 volt VPP is not required for

CC

device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by re ading the DQ7 (D ata# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.

The Erase Suspend feature enables the sys tem to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.

The sec tor erase arc hitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.

The device requires only a single 5.0 volt power sup­ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal stat e machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for t he pro­gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This invokes the Embedded

Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically pre­programs the array (if it is not already programmed) be­fore executing the erase operation. During erase, the

The hardware data protection measures include a
low V

detector automatically inhibits write operat ions

CC

during power transitions. The hardware sector pro­tection feature disables both program and erase oper-

ations in any combination of the sectors of memory,
and is implemented using standard EPROM program­mers. The temporary sector unprotect feature allows
in-system changes to protected sectors.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode.
Power consumption is greatly reduced in t his mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.

2 Am29F100

PRODUCT SELECTOR GUIDE

Family Part Number Am29F100
Speed Option (V
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 30 35 50 55

= 5.0 V ± 10%) -70 -90 -120 -150

CC

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ15

Input/Output

Buffers

Data

Latch

V

CC

V

SS

WE#

BYTE#

RESET#

CE#
OE#

RY/BY#

Buffer

State

Control

Command

Register

RY/BY#

PGM Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A15

A-1

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

18926C-1

Am29F100 3

CONNECTION DIAGRAMS

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

NC
NC

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6

DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

18926C-2

NC

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1

4 Am29F100

18926C-3

CONNECTION DIAGRAMS

RY/BY#

PIN CONFIGURATION

A0–A15 = 16 Addresses

NC
NC

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

18926C-4

LOGIC SYMBOL

DQ0–DQ14= 15 Data Inputs/Outputs
DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
BYTE# = Selects 8-bit or 16-bit mode
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
V

CC

= +5.0 Volt Single Power Supply

(See Product Selector Guide for speed

options and voltage supply tolerances)
V

SS

= Device Ground

NC = Pin Not Connected Internally

16

A0–A15

CE#
OE#

WE#
RESET#

BYTE#

16 or 8

DQ0–DQ15

(A-1)

RY/BY#

18926C-5

Am29F100 5

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the elements below.

Am29F100 -70 E C

T

B

OPTIONAL PROCESSING

Blank = Sta ndard Pro ces sin g

B = Burn-In

(Contact an AMD representative for more infor­mation.)

TEMPERATURE RANGE

C = Commercial (0
I=Industrial (–40

E = Extended (–55

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TS R0 48)

S = 44-Pin Small Outline Package

(SO 044)

SPEED OPTION

See Product Selector Guide and
Valid Combinations

°C to +70°C)

°C to +85°C)

°C to +125°C)

AM29F100T-70,
AM29F100B-70

AM29F100T-90,
AM29F100B-90

AM29F100T-120,
AM29F100B-120

AM29F100T-150,
AM29F100B-150

DEVICE NUMBER/DESCRIPTION

Am29F100
1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

EC, EI, EE,

FC, FI, FE,
SC, SI, SE

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

Valid Combinations

6 Am29F100

DEVICE BUS OPERATIONS

This section describes the re quirements and us e of the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any ad dressable memory locatio n.
The register is composed of latches that store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Am29F100 Device Bus Operations

register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re­sulting output. The following subsections describe
each of these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A
Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector

Unprotect

Legend:

L = Logic Low = V

Notes:

1. Addresses are A15:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D

IL

XXXV

ID

), A15:A-1 in byte mode (BYTE# = VIL).

IH

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–D Q0 are active and con­trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 ar e ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

. The BYTE# pin determines whether the de-

IH

vice outputs array data in words or bytes.
The internal state machine is set for reading array

data upon device power-up , or after a hardware re­set. This ensures that no spurious alteration of the

. CE# is the power

IL

(Note 1)

IN

IN

A

IN

memory content occurs during th e power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

For program operations, the BYTE# pin determines
whether the device accepts prog ram data in bytes
or words. Refer to “Word/Byte Configuration” for
more information.

DQ0–

DQ7

D

OUT

D

IN

D

IN

, and OE# to VIH.

IL

BYTE#

= V

IH

D

OUT

D

IN

D

IN

in the DC Characteristics

CC1

BYTE#

= V

IL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

= Data Out

OUT

Am29F100 7

An erase operation can erase one sector, multiple sec­tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.

A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, t he system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specificat ions apply. Refer to “Write Operation
Status” for more information, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mo de. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restricted voltage rang e than V
The device e nters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t

CE

when the device is in either of these standby modes ,
before it is ready to read data.

The device also enters the standby mode when th e
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.

± 0.5 V. (Note

CC

IH

. The device re-

IH

) for read access

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

CC3

standby current specification.

RESET#: HARDWARE RESET PIN

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any oper ation in
progress, tristates all data output pins, and ignores all
read/write atte mpts for the duration of the RESET#
pulse. The device a lso resets the internal sta te ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the devic e is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operation is complete, which re quires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is co mplete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset opera tion is completed
within a time of t

.)

rithms). The system can read data t
SET# pin returns to V

(not during Embedded Algo-

READY

.

IH

RH

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped­ance state.

represents the

RP

SS

after the RE -

,

±

8 Am29F100

Table 2. Sector Addresses Tables (Am29F100T)

A15 A14 A13 A12 (x8) Address Range (x16 ) Address Rang e

SA0 0 X X X 00000h-0FF FFh 00000h-07FFFh
SA1 1 0 X X 10000h-17FFFh 08000h-0BFFFh
SA2 1 1 0 0 18000 h-1 9F FFh 0C000h-0CFFFh
SA3 1 1 0 1 1A000h-1BFFFh 0D000h-0DFFFh
SA4 1 1 1 X 1C000h-1FFFFh 0E000h-0FFFFh

Table 3. Sector Addresses Tables (Am29F100B)

A15 A14 A13 A12 (x8) Address Range (x16 ) Address Rang e

SA0 0 0 0 X 00000h-03FFFh 00000h-01FFFh
SA1 0 0 1 0 04000 h-0 5F FFh 02000h-02F FF h
SA2 0 0 1 1 06000 h-0 7F FFh 03000h-03F FF h
SA3 0 1 X X 08000h-0FFFFh 04000h-07FFFh
SA4 1 X X X 10000h-1FF FFh 08000h-0FFFFh

Autoselect Mode

The autoselect mode provides manu facturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding progra mming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In ad­dition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Command Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini­tions table. This method does not require V
“Command Definitions” for details on using the autose­lect mode.

ID

. See

Table 4. Am29F100 Autoselect Codes (High Voltage Method)

A15

A11

to

to

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID:

Am29F100
(Top Boot Block)

Device ID:
Am29F100
(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Word L L H

Byte L L H X D9h

Word L L H

Byte L L H X DFh

A12

A10 A9

XXV

XXV

A8

to

A7 A6

XLXLL X 01h

ID

XLXLH

ID

XLXLH

ID

XLXHL

ID

Am29F100 9

A5

to

A2 A1 A0

DQ8

to

DQ15

22h D9h

22h DFh

X

X

DQ7

DQ0

(protected)

(unprotected)

to

01h

00h

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously pro­tected sectors.

Sector protection/unprotection must be implemented
using programming equipment. The procedure re­quires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 20373. Contact an
AMD representative to obtain a copy of the appropriate
document.

) on address pin A9 and the

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

ID

IH

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact a n
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system.
The Sector Unprotect mo de is activ ated by setti ng the
RESET# pin to V
tected sectors can be programmed or erased by se­lecting the sector addresses. Once V
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo­rithm, and the Temporary Sector Unprotect (Figure

17) diagram shows the t imin g wave fo rms, fo r thi s fea­ture.

. During this mode, formerly pro-

ID

is removed

ID

Temporary Sector

Unprotect

Completed (Note 2)

18926C-6

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

Figure 1. Temporary Sector Unprotect Operation

10 Am29F100

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to t he Comma nd Defi­nitions table). In addition, the following hardware data
protection measures prevent accidental era sure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

COMMAND DEFINITIONS

Writing specific address and data command s or se­quences into the command register initiates device op­erations. The Command Defini tions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is a utomatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Em bedded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

must

The system
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

issue the reset command to re-en-

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

, CE# = VIH or WE# = VIH. To initia te a write c y-

= V

IL

cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power

IL

up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.

See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Timings diagram shows the
timing diagram.

Reset Command

Writing the reset command to the device resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operat ion,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

Am29F100 11

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an al ternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program­mers and requires V

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h or retrieves the manu­facturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) re­turns 01h if that sector is protected, or 00h if it is un­protected. Refer to the Se ctor Add ress t ables f or valid
sector addresses.

on address bit A9.

ID

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program­ming operation. The program command sequence
should be reinitiated once the device has reset to read­ing array data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indic ate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

START

Write Program

Command Sequence

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Program­ming is a four-bus-cycle operation. The program com­mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program addre ss and data are writte n next, which in
turn initiate the Embedded Program algorithm. The

not

system is
ings. The device automatically provides internally gen­erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the ad­dress and data requirements for the byte program com­mand sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of th e program operation by usin g

DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.

required to provide further controls or ti m-

Data Poll

Embedded

Program

algorithm

in progress

Increment Address

Note: See the appropriate Command Definitions table for
program command sequence.

No

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

No

18926C-7

Figure 2. Program Operation

12 Am29F100

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is ini tiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con­trols or timings during these operati ons. The Command
Definitions table shows the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a har dware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int egrity.

The system can determine the s tatus of the erase
operation by using DQ7, DQ6, or RY/BY#. See

“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latc hed.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for ti ming waveforms.

require the system to

Sector Erase Command Sequence

Sector erase is a six bus c ycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad­ditional unlock write cycles are then followed b y the ad­dress of the sector to be erased, and the sector erase
command. The Command Definitions table shows the
address and data requireme nts for the sector erase
command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any c ontrols or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sect or er ase buf fer
may be done in any sequence, and the number of sec­tors may be from one sector to all s ectors. The time be­tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be

require the system to preprogram

accepted, and erasure may begin. It is recommended
that processor interrupts be disabled dur ing this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) Th e time-out begins from the ris­ing edge of the final WE# pulse in the command se­quence.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta­tus of the erase operation by using DQ7, DQ6, or RY/
BY#. Refer to “Write Operation Status” for information
on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in­terrupt a sector erase operatio n and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase com mand sequence. The
Erase Suspend com mand is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the er ase operation. H owever,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-

Am29F100 13

minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to

any sector not selected for erasure. (The device “erase
suspends” all sectors selec ted for erasure.) N ormal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7 to determine if a sector is acti vely erasing
or is erase-suspended. See “Write Operation Status”
for information on these status bits.

After an erase-suspended program operation is com­plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.

The system may also write the autoselect command
sequence when the devic e is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing secto rs, since the
codes are no t stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Auto select Command Sequence ”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

18926C-8

Figure 3. Erase Operation

14 Am29F100

Table 5. Am29F100 Command Definitions

Command

Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXXX F0

Manufacturer ID

Device ID,
Top Boot Block

(Note 7)

Device ID,
Bottom Boot Block

Autoselect

Sector Protect Verify
(Note 8)

Program

Chip Erase

Sector Erase
Erase Suspend (Note 9) 1 XXXX B0

Erase Resume (Note 10) 1 XXXX 30

Word

Byte AAAA 5555 AAAA

Word

Byte AAAA 5555 AAAA XX02 D9

Word

Byte AAAA 5555 AAAA XX02 DF

Word

Byte AAAA 5555 AAAA

Word

Byte AAAA 5555 AAAA

Word

Byte AAAA 5555 AAAA AAAA 5555 AAAA

Word

Byte AAAA 5555 AAAA AAAA 5555

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

5555

4

5555

4

5555

4

5555

4

5555

4

5555

6

5555

6

AA

AA

AA

AA

AA

AA

AA

2AAA

2AAA

2AAA

2AAA

2AAA

2AAA

2AAA

55

55

55

55

55

55

55

Bus Cycles (Notes 2–4)

5555

5555

5555

5555

5555

5555

5555

90 XX00 01

XX01 22D9

90

XX01 22DF

90

(SA)

X02

90

(SA)

X04

A0 PA PD

5555

80

5555

80

XX00
XX01

00
01

AA

AA

2AAA

2AAA

5555

55

55 SA 30

10

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory l ocation to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles
are write operations.

4. Data bits DQ15–DQ8 are don’t c a res for unlock and
command cycles.

5. No unlock or command cycles required when reading array
data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A15–A12 uniquely select any sector.

7. The fourth cycle of the autoselect command sequence is a
read operation.

8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.

9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

10. The Erase Resume command is valid only during the Erase
Suspend mode.

Am29F100 15

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ3, DQ5, DQ6, DQ7, and
RY/BY#. Table 6 and the following subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ 7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the ris­ing edge of the final W E# pulse in the program or
erase command sequence.

During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector , Data# Polling on DQ7 is active for ap­proximately 2 µs, then the device returns to reading
array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true da tum output
described for the Embedded Program algorithm: the
erase function changes al l the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

No

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

After an erase command sequence is written, if all sec­tors selected for erasing are p rotected, Data# Polling
on DQ7 is active for approximately 100 µs, the n the de-

Notes:

1. VA = Valid address for programming. During a sector

vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

2. DQ7 should be rechecked even if DQ5 = “1” because

When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll­ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.

16 Am29F100

erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

DQ7 may change simultaneously with DQ5.

18926C-9

Figure 4. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid af ter
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy), the device is actively erasing
or programming. (T his includes programmin g in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia­grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

CC

.

DQ6: Toggle Bit I

Tog gle Bit I on DQ6 indicates whether an Embedde d
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op­eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog­gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protec ted,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the se lected sectors that
are protected.

If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggl es during the e rase-suspend-pro gram
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

The Write Operation Status table shows t he outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 5 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is togg ling . Typically, a

system would note and store the value of the toggle
bit after th e fi rs t r ead . After the s ec on d re a d, the sys­tem would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol­lowing read cycle.

However, if af ter the initial two read cycles, the system
determines that the toggle bit i s still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase op eration. If it is still toggling, th e
device did not complete the operation successfully , and
the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to mo nitor the
toggle bit and DQ5 through successive read cycles, de­termining the status as described in the previous para­graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase op eration can

change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue

the reset command to return the device to reading
array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine wh ether o r not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selected for er asure, the ent ire time­out also applies after each additional sector eras e
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee tha t the time b etween ad­ditional sector erase commands will always be less

Am29F100 17

than 50 µs. See also the “Sector Erase Command Se-
quence” section.

After the sector erase command sequ ence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored until the erase ope ration is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command h as been
accepted, the system software should check the s tatus
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last co mmand might not hav e been ac­cepted. Table 6 shows the outputs for DQ3.

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

1

No

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

(Notes
1, 2)

No

Program/Erase

Operation Complete

18926C-10

18 Am29F100

Figure 5. Toggle Bit Algorithm

Table 6. Write Operation Status

Standard
Mode

Erase
Suspend
Mode

DQ7

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A 0
Embedded Erase Algorithm 0 Toggle 0 1 0
Reading within Erase

Suspended Sector
Reading within Non-Erase Suspended

Sector
Erase-Suspend-Program DQ7# T oggle 0 N/A 0

(Note 1) DQ6

1 No tog gle 0 N/A 1

Data Data Data Data 1

DQ5

(Note 2) DQ3 RY/BY#

Notes:

1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Am29F100 19

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

V

CC

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.5 V

All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pin is – 0.5 V. Dur ing
voltage transitions, inputs may overshoot V

for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on input and I/O pins is V

age transitions, inp ut and I/O pins may overs hoot to V
+ 2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 pins may overshoot VSS to –2.0 V

for periods of up to 20 ns. See Figure 6. Maximum DC in­put voltage on A9 is +12.5 V which may overshoot to 13.5
V for periods up to 20 ns.

3. No more tha n one output short ed at a time. Durat ion of
the short circuit should not be greater than one second.

Stresses above those listed under “Abso lute Maximum Rat­ings” may cause per mane nt dam age to the device. This is a
stress rating only; fun ctio nal ope ration of t he d evice at these
or any other condition s above those indicated in the opera­tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex­tended periods may affect device reliability.

+ 0.5 V. During volt-

CC

to –2.0 V

SS

CC

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 6. Maximum Negative Overshoot

Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

Figure 7. Maximum Positive Overshoot

Waveform

18926C-11

18926C-12

OPERATING RANGES

Commercial (C) Devices

Case Temperature (T

Industrial (I) Devices

Case Temperature (T

Extended (E) Devices

Case Temperature (T

Supply Voltages

V

CC

for all devices . . . . . . . . . . . . .+4.50 V to +5.50 V

V

CC

Operating rang es define those limits between which the
functionality of the device is guaranteed.

20 Am29F100

) . . . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . . . –55°C to +125°C

A

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Max Unit

I

I
I

V
V

V

I

LI

I

LIT

I

LO

CC1

CC2

CC3

V

V

V

OL

OH

LKO

Input Load Current VIN = V
A9 Input Load Current V
Output Leakage Curren t V

V

Active Current (Note 1)

CC

V

Active Current (Notes 2, 3) V

CC

V

Standby Current V

CC

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2.0 V

IH

Voltage for Autoselect and

ID

Temporary Sector Unprotect

CC

OUT

V

CC = VCC

OE# = V

CC = VCC

CC = VCC

V

CC

Output Low Voltage IOL = 5.8 mA, V
Output High Voltage IOH = –2.5 mA, V
Low VCC Lock-out Voltage 3.2 4.2 V

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

SS

CC

to VCC, V

Max, CE# = V

IH

Max, CE# = V
Max, CE# = VIH, OE# = V

= 5.0 V 11.5 12.5 V

= V

CC

= V

CC

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

CC

active while Embedded Program or Embedded Erase Algorithm is in progress.

CC

3. Not 100% tested.

= V

Max ±1.0 µA

CC

= V

CC

Max ±1.0 µA

CC

IL,

Byte 40 mA

Word 50 mA

OE# = V

IL,

Min 0.45 V

CC

Min 2.4 V

CC

IH

IH

60 mA

1.0 mA

+ 0.5 V

CC

Am29F100 21

DC CHARACTERISTICS (continued)
CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Max Unit

I

I

I

V
V
V
V

I

I

LIT

I

LO

CC1

CC2

CC3

V

V

V

OH1

OH2

LKO

Input Load Current VIN = V

LI

A9 Input Load Current V
Output Leakage Current V

V

Active Current (Note 1)

CC

V

Active Current (Notes 2, 3) V

CC

V

Standby Current

CC

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 0.7 x V

IH

Voltage for Autoselect and

ID

Temporary Sector Unprotect
Output Low Voltage IOL = 5.8 mA, V

OL

Output High Voltage

CC

OUT

V

CC = VCC

CE# = V

CC = VCC

V

CC = VCC

CE# and RESET# = V

V

CC

I

OH

IOH = –100 µA, V

Low V

Lock-out Voltage 3.2 4.2 V

CC

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

Max,

OE# = V

IL,

= V

CC

CC

IH

Max, CE# = V
Max, OE# = V

CC

= 5.0 V 11.5 12.5 V

= V

CC

CC

= –2.5 mA, V

CC

CC

= V
= V

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

CC

active while Embedded Program or Embedded Erase Algorithm is in progress.

CC

3. Not 100% tested.

Max ±1.0 µA

CC

= V

Max ±1.0 µA

CC

Byte 40

Word 50

OE# = V

IL,

IH,

IH

60 mA

± 0.5 V 100 µA

CC VCC

+ 0.5 V

Min 0.45 V

Min 0.85 V

CC

Min VCC –0.4 V

CC

CC

mA

V

22 Am29F100

TEST CONDITIONS

5.0 V

Table 7. Test Specifications

Test Condition -70 All others Unit

Device

Under

Test

C

L

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

2.7 kΩ

18926C-13

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

L

30 100 pF

1.5 0.8 V

1.5 2.0 V

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

KS000010-PAL

Am29F100 23

AC CHARACTERISTICS
Read-only Operations Characteristics

Parameter

Symbol

Parameter Description Test Setup -70 -90 -120 -150 UnitJEDEC Std.

t

t

AVAV

t

AVQVtACC

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

Read Cycle Time (Note 1) Min 70 90 120 150 ns

RC

Address to Output Delay

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 30 35 50 55 ns

OE

t

Chip Enable to Output High Z (Notes 1, 2) Max 20 20 30 35 ns

DF

Output Enable to Output High Z

t

DF

(Notes 1, 2)

Output Enable Hold Time (Note 1)

t

OEH

CE# = V
OE# = V

IL
IL

IL

Max 70 90 120 150 ns

Max 70 90 120 150 ns

Max 20 20 30 35 ns

Read Min 0 ns
Toggle and Data

Polling

Min 10 ns

Output Hold Time From Addresses CE# or

t

AXQX

t

OH

OE#, Whichever Occurs First

Notes:

1. Not 100% tested.

2. Output Driver Disable Time.

3. See Figure 8 and Table 7 for test specifications.

Addresses

CE#

OE#

t

OEH

WE#

HIGH Z

Outputs

RESET#

t

RC

Addresses Stable

t

ACC

t

OE

t

CE

Min 0 ns

t

DF

t

OH

HIGH Z

Output Valid

RY/BY#

0 V

Figure 9. Read Operations Timings

24 Am29F100

18926C-14

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

RESET# Pulse Width Min 500 ns

t

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

Max 20 µs

Max 500 ns

t

RH

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

RY/BY#

CE#, OE#

RESET#

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 10. RESET# Timings

t

RB

18926C-15

Am29F100 25

AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)

Parameter

-70 -90 -120 -150JEDEC Std. Description Unit

t

ELFL/tELFH

t

FLQZ

t

FHQV

BYTE#

Switching

from word

to byte

mode

CE# to BYTE# Switching Low or High Max 5 ns
BYTE# Switching Low to Output HIGH Z Max 20 20 30 35 ns
BYTE# Switching High to Output Active Min 70 90 120 150 ns

CE#

OE#

BYTE#

t

DQ0–DQ14

DQ15/A-1

ELFL

t

ELFH

Data Output

(DQ0–DQ14)

DQ15

Output

t

FLQZ

Data Output

(DQ0–DQ7)

Address

Input

BYTE#

BYTE#

Switching

from byte

DQ0–DQ14

to word

mode

DQ15/A-1

Figure 11. BYTE# Timings for Read Operations

CE#

WE#

BYTE#

Note:

Refer to the Erase/Program Operations table for t

Figure 12. BYTE# Timings for Write Operations

Data Output
(DQ0–DQ7)

Address

The falling edge of the last WE# signal

t

SET

(tAS)

and tAH specifications.

AS

Input

t

FHQV

t

HOLD

Data Output

(DQ0–DQ14)

DQ15

Output

18926C-16

(tAH)

18926C-17

26 Am29F100

AC CHARACTERISTICS
Erase and Program Operations

Parameter Symbol

Parameter Description -70 -90 -120 -150 UnitJEDEC Standard

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

WHWH1

t

WHWH2

t

VCS

t

RB

t

BUSY

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 50 ns
Data Setup Time Min 30 45 50 50 ns
Data Hold Time Min 0 ns
Read Recover Time Before Write

(OE# High to WE# Low)
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 35 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 14 µs
Chip/Sector Erase Operation (Note 2) Typ 1.5 sec
VCC Set Up Time (Note 1) Min 50 µs
Recovery Time from RY/BY# Min 0 ns
Program/Erase Valid to RY/BY# Delay Min 30 35 50 55 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Min 0 ns

Am29F100 27

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Addresses

555h

t

WC

t

AS

PA PA

t

AH

PA

Read Status Data (last two cycles)

CE#

t

GHWL

OE#

t

WP

WE#

t

CS

t

DS

t

Data

A0h

RY/BY#

t

VCS

V

CC

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Figure 13. Program Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

t

WC

Addresses

CE#

OE#

WE#

Data

2AAh SA

t

GHWL

t

CH

t

WP

t

CS

t

DS

t

DH

55h

t

CH

t

WPH

DH

PD

t

BUSY

is the true data at the program address.

OUT

t

AS

555h for chip erase

t

WPH

t

AH

30h

10 for Chip Erase

t

BUSY

t

WHWH1

Status

t

WHWH2

VA

D

OUT

In

Progress

t

RB

VA

Complete

t

RB

18926C-13

RY/BY#

t

VCS

V

CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

28 Am29F100

18926C-13

AC CHARACTERISTICS

Addresses

t

ACC

CE#

t

CH

OE#

t

OEH

WE#

DQ7

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

18926C-18

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note: V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.

18926C-19

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

Am29F100 29

AC CHARACTERISTICS
Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std. Description Unit

t

VIDR

t

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

CE#

WE#

RY/BY#

VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

Unprotect

Min 4 µs

0 or 5 V

t

VIDR

t

VIDR

Program or Erase Command Sequence

t

RSP

18926C-20

Figure 17. Temporary Sector Unprotect Timing Diagram

30 Am29F100

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbol

Parameter Description -70 -90 -120 -150 UnitJEDEC Standard

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 45 45 50 50 ns
Data Setup Time Min 30 45 50 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recover Time Before Write Min 0 ns
WE# Setup Time Min 0 ns
WE# Hold Time Min 0 ns
CE# Pulse Width Min 35 45 50 50 ns
CE# Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 14 µs
Chip/Sector Erase Operation (Note 2) Typ 1.5 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29F100 31

AC CHARACTERISTICS

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 18. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

18926C-21

32 Am29F100

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Chip/Sector Erase Time 1.5 15 sec

Byte Programming Time 14 1000 µs
Word Programming Time 28 2000 µs
Chip Programming Time (Note 3) 1.8 12.5 sec

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

CommentsTyp (Note 1) Max (Note 2) Unit

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 5.0 V VCC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V, 100,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1
for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTIC

Parameter Description Min Max

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on I/O pins –1.0 V VCC + 1.0 V

SS

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Typ Max Unit

C

C

OUT

C

IN2

Input Capacitance VIN = 0 6 7.5 pF

IN

Output Capacitance V
Control Pin Capacitance VIN = 0 8 10 pF

= 0 8.5 12 pF

OUT

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Description Test Conditions Min Unit

°C 10 Years

Minimum Pattern Data Retention Time

150

125°C

20 Years

Am29F100 33

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

2.17

2.45

44

23

13.10

13.50

1

1.27 NOM.

TOP VIEW

28.00

28.40

0.35

0.50

SIDE VIEW

22

0.10

0.35

2.80

MAX.

15.70

16.30

SEATING
PLANE

0°
8°

0.10

0.21

0.60

1.00

END VIEW

16-038-SO44-2
SO 044
DF83
8-8-96 lv

34 Am29F100

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

48

11.90

12.10

0.50 BSC

25

0.05

0.15

16-038-TS48-2
TS 048
DT95
8-8-96 lv

1.20
MAX

0.25MM (0.0098") BSC

0.08

0.20

0.10

0°

0.21

5°

0.50

0.70

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

24

18.30

18.50

19.80

20.20

48

11.90

12.10

0.50 BSC

25

0.05

0.15

SEATING PLANE

1.20

MAX

0.25MM (0.0098") BSC

16-038-TS48

0.08

0.20

TSR048
DT95
8-8-96 lv

0.10

0°

0.21

5°

0.50

0.70

Am29F100 35

REVISION SUMMARY FOR AM29F100
Revision B+1

Product Selector Guide

Replaced the -75 column (70 ns, ±5%) with the -70 col­umn (70 ns, ±10%).

Ordering Information, Standard Products

The -70 designation is now listed in the part number ex­ample.

Valid Combinations:

with -70. The 70 ns speed grade is now available in the
same combinations as the other speed grades.

Replaced the -75 combin ations

chip/sector erase times (t

WHWH1

and t

WHWH2

, respec-

tively).

Erase and Programming Performance

Combined sector and chip erase times, added word
programming time s and erase/program cycle tim es.
Updated specifications.

Revision C

Global

Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.

Operating Ranges

VCC Supply Voltages:

Changed the -75 designation

to -70.

AC Characteristics

Read Only Operations:

Changed the -75 column head

to -70. All parameters remain the same.

Figure 7, Test Conditions:

Changed CL in Note 1 from -

75 to -70.

Write/Erase/Program Operations:

Changed the -75
column head to -70. Changed byte programming and
chip/sector erase times (t

WHWH1

and t

WHWH2

, respec-

tively).

Switching Waveforms

Temporary Sector Unprotect Timing Diagram, Figure

Corrected the top waveform. RESET# begins at 0

18:

V, then rises to 12 V in t

VIDR

.

AC Characteristics

Alternate CE# Controlled Writes:

Changed the -75 col-

umn head to -70. Changed byte pro gramming and

Revision C+1

Table 5, Command Definitions

Address bits A0–A14 are required for unlock cycles.
Therefore, addresses for second and fifth write cycles
are 2AAAh in word mode and 5555h in by te mode. Ad­dresses for first, third, fourth, and sixth cycles are
5555h in word mode and AAAAh in byte mode. Read
cycles are not affected. Deleted Note 5 to reflect the
correction.

Revision C+2

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

notes reference for t

WHWH1

and t

WHWH2

eters are 100% tested. Corrected the note reference
for t

. This parameter is not 100% tested.

VCS

Temporary Sector Unprotect Table

Added note reference for t

. This parameter is not

VIDR

100% tested.

Corrected the

. These param-

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

36 Am29F100