AMD Am29F100 Service Manual

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FINAL

Am29F100

1 Megabit (128 K x 8-bit/64 K x 16-bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

—5.0 V ± 10% for read, erase, and program

operations

— Simplifies system-level power requirements

■ High performance

— 70 ns maximum access time

■ Low power consumption

— 20 mA typical active read current for byte mode
— 28 mA typical active read current for word mode
— 30 mA typical program/erase current
— 25 µA typical standby current

■ Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

one 32 Kword sectors (word mode)
— Any combination of sectors can be erased
— Supports full chip erase

■ Top or bottom boot block configurations

available

■ Sector protection

— Hardware-based feature that disables/re-

enables program and erase operations in any

combination of sectors
— Sector protection/unprotection can be

implemented using standard PROM

programming equipment
— Temporary Sector Unprote ct feature allows in-

system code changes in protected sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

— Embedded Program algorithm automatically

■ Minimum 100,000 program/erase cycles

guaranteed

■ Package options

— 44-pin SO
— 48-pin TSOP

■ Compatible with JEDEC standards

— Pinout and software compatible with

— Superior inadvertent write protection

■ Data# Polling and Toggle Bits

— Provides a software method of detecting

■ Ready/Busy pin (R Y/BY#)

— Provides a hardware method for detecting

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data fr om,

■ Hardware RESET# pin

— Hardware method of resetting the device to

pre-programs and erases the chip or any
combination of designated sector

programs and verifies data at specified address

single-power-supply flash

program or erase cycle completion

program or erase cycle completion

or program data to, a sector that is not being
erased, then resumes the erase operation

reading array data

Publication# 18926 Rev: C Amendment/+2
Issue Date: March 1998

GENERAL DESCRIPTION

The Am29F100 is a 1 Mbit, 5.0 V olt-only Flash memory
organized as 131,072 bytes or 65,536 words. The
Am29F100 is offered in 44-pin SO and 48-pin TSOP
packages. Word-wide data appears on DQ0-DQ15;
byte-wide data on DQ0-DQ7. The device is designed to
be programmed in-system with the standard system

5.0 Volt V
program or erase operations. The device can also be
programmed or erased in standard EPROM program­mers.

The standard device offers access times of 70, 90,
120, and 150 ns, allowing high-speed microproces­sors to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.

supply. A 12.0 volt VPP is not required for

CC

device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by re ading the DQ7 (D ata# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.

The Erase Suspend feature enables the sys tem to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.

The sec tor erase arc hitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.

The device requires only a single 5.0 volt power sup­ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal stat e machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for t he pro­gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This invokes the Embedded

Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically pre­programs the array (if it is not already programmed) be­fore executing the erase operation. During erase, the

The hardware data protection measures include a
low V

detector automatically inhibits write operat ions

CC

during power transitions. The hardware sector pro­tection feature disables both program and erase oper-

ations in any combination of the sectors of memory,
and is implemented using standard EPROM program­mers. The temporary sector unprotect feature allows
in-system changes to protected sectors.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode.
Power consumption is greatly reduced in t his mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.

2 Am29F100

PRODUCT SELECTOR GUIDE

Family Part Number Am29F100
Speed Option (V
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 30 35 50 55

= 5.0 V ± 10%) -70 -90 -120 -150

CC

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ15

Input/Output

Buffers

Data

Latch

V

CC

V

SS

WE#

BYTE#

RESET#

CE#
OE#

RY/BY#

Buffer

State

Control

Command

Register

RY/BY#

PGM Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

A0–A15

A-1

VCC Detector

Timer

STB

Address Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

18926C-1

Am29F100 3

CONNECTION DIAGRAMS

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

NC
NC

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6

DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

18926C-2

NC

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A4
A3
A2
A1

4 Am29F100

18926C-3

CONNECTION DIAGRAMS

RY/BY#

PIN CONFIGURATION

A0–A15 = 16 Addresses

NC
NC

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

18926C-4

LOGIC SYMBOL

DQ0–DQ14= 15 Data Inputs/Outputs
DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
BYTE# = Selects 8-bit or 16-bit mode
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
V

CC

= +5.0 Volt Single Power Supply

(See Product Selector Guide for speed

options and voltage supply tolerances)
V

SS

= Device Ground

NC = Pin Not Connected Internally

16

A0–A15

CE#
OE#

WE#
RESET#

BYTE#

16 or 8

DQ0–DQ15

(A-1)

RY/BY#

18926C-5

Am29F100 5

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the elements below.

Am29F100 -70 E C

T

B

OPTIONAL PROCESSING

Blank = Sta ndard Pro ces sin g

B = Burn-In

(Contact an AMD representative for more infor­mation.)

TEMPERATURE RANGE

C = Commercial (0
I=Industrial (–40

E = Extended (–55

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TS R0 48)

S = 44-Pin Small Outline Package

(SO 044)

SPEED OPTION

See Product Selector Guide and
Valid Combinations

°C to +70°C)

°C to +85°C)

°C to +125°C)

AM29F100T-70,
AM29F100B-70

AM29F100T-90,
AM29F100B-90

AM29F100T-120,
AM29F100B-120

AM29F100T-150,
AM29F100B-150

DEVICE NUMBER/DESCRIPTION

Am29F100
1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

EC, EI, EE,

FC, FI, FE,
SC, SI, SE

BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector

Valid Combinations

6 Am29F100

DEVICE BUS OPERATIONS

This section describes the re quirements and us e of the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any ad dressable memory locatio n.
The register is composed of latches that store the com­mands, along with the address and data information
needed to execute the command. The contents of the

Table 1. Am29F100 Device Bus Operations

register serve as inputs to the internal state machine.
The state machine outputs d ictate the function of the
device. The appropriate device bus operations table
lists the inputs and control levels required, and the re­sulting output. The following subsections describe
each of these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET#

Read L L H H A

Write L H L H A
Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector

Unprotect

Legend:

L = Logic Low = V

Notes:

1. Addresses are A15:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V , X = Don’t Care, AIN = Addresses In, DIN = Data In, D

IL

XXXV

ID

), A15:A-1 in byte mode (BYTE# = VIL).

IH

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura­tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–D Q0 are active and con­trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 ar e ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

. The BYTE# pin determines whether the de-

IH

vice outputs array data in words or bytes.
The internal state machine is set for reading array

data upon device power-up , or after a hardware re­set. This ensures that no spurious alteration of the

. CE# is the power

IL

(Note 1)

IN

IN

A

IN

memory content occurs during th e power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

For program operations, the BYTE# pin determines
whether the device accepts prog ram data in bytes
or words. Refer to “Word/Byte Configuration” for
more information.

DQ0–

DQ7

D

OUT

D

IN

D

IN

, and OE# to VIH.

IL

BYTE#

= V

IH

D

OUT

D

IN

D

IN

in the DC Characteristics

CC1

BYTE#

= V

IL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-Z

= Data Out

OUT

Am29F100 7

An erase operation can erase one sector, multiple sec­tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.

A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, t he system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specificat ions apply. Refer to “Write Operation
Status” for more information, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mo de. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restricted voltage rang e than V
The device e nters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t

CE

when the device is in either of these standby modes ,
before it is ready to read data.

The device also enters the standby mode when th e
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.

± 0.5 V. (Note

CC

IH

. The device re-

IH

) for read access

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

CC3

standby current specification.

RESET#: HARDWARE RESET PIN

The RESET# pin provides a hardware method of reset­ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any oper ation in
progress, tristates all data output pins, and ignores all
read/write atte mpts for the duration of the RESET#
pulse. The device a lso resets the internal sta te ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the devic e is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operation is complete, which re quires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether
the reset operation is co mplete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset opera tion is completed
within a time of t

.)

rithms). The system can read data t
SET# pin returns to V

(not during Embedded Algo-

READY

.

IH

RH

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped­ance state.

represents the

RP

SS

after the RE -

,

±

8 Am29F100

Table 2. Sector Addresses Tables (Am29F100T)

A15 A14 A13 A12 (x8) Address Range (x16 ) Address Rang e

SA0 0 X X X 00000h-0FF FFh 00000h-07FFFh
SA1 1 0 X X 10000h-17FFFh 08000h-0BFFFh
SA2 1 1 0 0 18000 h-1 9F FFh 0C000h-0CFFFh
SA3 1 1 0 1 1A000h-1BFFFh 0D000h-0DFFFh
SA4 1 1 1 X 1C000h-1FFFFh 0E000h-0FFFFh

Table 3. Sector Addresses Tables (Am29F100B)

A15 A14 A13 A12 (x8) Address Range (x16 ) Address Rang e

SA0 0 0 0 X 00000h-03FFFh 00000h-01FFFh
SA1 0 0 1 0 04000 h-0 5F FFh 02000h-02F FF h
SA2 0 0 1 1 06000 h-0 7F FFh 03000h-03F FF h
SA3 0 1 X X 08000h-0FFFFh 04000h-07FFFh
SA4 1 X X X 10000h-1FF FFh 08000h-0FFFFh

Autoselect Mode

The autoselect mode provides manu facturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding progra mming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

(11.5 V to 12.5 V) on address pin

ID

A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In ad­dition, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Command Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini­tions table. This method does not require V
“Command Definitions” for details on using the autose­lect mode.

ID

. See

Table 4. Am29F100 Autoselect Codes (High Voltage Method)

A15

A11

to

to

Description Mode CE# OE# WE#

Manufacturer ID: AMD L L H X X V
Device ID:

Am29F100
(Top Boot Block)

Device ID:
Am29F100
(Bottom Boot Block)

Sector Protection Verification L L H SA X V

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Word L L H

Byte L L H X D9h

Word L L H

Byte L L H X DFh

A12

A10 A9

XXV

XXV

A8

to

A7 A6

XLXLL X 01h

ID

XLXLH

ID

XLXLH

ID

XLXHL

ID

Am29F100 9

A5

to

A2 A1 A0

DQ8

to

DQ15

22h D9h

22h DFh

X

X

DQ7

DQ0

(protected)

(unprotected)

to

01h

00h

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables
both program and erase operations in previously pro­tected sectors.

Sector protection/unprotection must be implemented
using programming equipment. The procedure re­quires a high voltage (V
control pins. Details on this method are provided in a
supplement, publication number 20373. Contact an
AMD representative to obtain a copy of the appropriate
document.

) on address pin A9 and the

ID

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

ID

IH

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact a n
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system.
The Sector Unprotect mo de is activ ated by setti ng the
RESET# pin to V
tected sectors can be programmed or erased by se­lecting the sector addresses. Once V
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo­rithm, and the Temporary Sector Unprotect (Figure

17) diagram shows the t imin g wave fo rms, fo r thi s fea­ture.

. During this mode, formerly pro-

ID

is removed

ID

Temporary Sector

Unprotect

Completed (Note 2)

18926C-6

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

Figure 1. Temporary Sector Unprotect Operation

10 Am29F100

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to t he Comma nd Defi­nitions table). In addition, the following hardware data
protection measures prevent accidental era sure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V
cept any write cycles. This protects data during V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

CC

COMMAND DEFINITIONS

Writing specific address and data command s or se­quences into the command register initiates device op­erations. The Command Defini tions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is a utomatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Em bedded Program or Em­bedded Erase algorithm.

After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

must

The system
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

issue the reset command to re-en-

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

, CE# = VIH or WE# = VIH. To initia te a write c y-

= V

IL

cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power

IL

up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to reading array data on
power-up.

See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Timings diagram shows the
timing diagram.

Reset Command

Writing the reset command to the device resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operat ion,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

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