Datasheet AM29F040B-90PIB, AM29F040B-90PI, AM29F040B-90PEB, AM29F040B-90PCB, AM29F040B-90PC Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Am29F040B

4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Distinctive Characteristics

■ 5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F040 device

■ High performance

— Access times as fast as 55 ns

■ Low power consumption

— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector architecture

— 8 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Sector protection:

A hardware method of locking sector s to prev ent
any program or erase operat ions within that
sector

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 progr am/erase cycles per

sector guaranteed

■ Package options

— 32-pin PLCC, TSOP, or PDIP

■ Compatible with JEDEC standards

— Pinout and software c ompatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase oper ation to read da ta

from, or program data to, a non-erasing sector,
then resumes the erase operation

Publication# 21445 Rev: B Amendment/+2
Issue Date: April 1998

PRELIMINARY

GENERAL DESCRIPTION

The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem­ory organized as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are div ided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of

data appear on DQ0–DQ7. The Am29F040B is offered
in 32-pin PLCC, TSOP, and PDIP packages. This de­vice is designed to be programmed in-system with the
standard system 5.0 volt V
not required for write or erase operations. The device
can also be programmed i n standard EPROM pro­grammers.

This device is manufactured using AMD’s 0.35 µm
process technology, and off ers all the f eatures and ben­efits of the Am29F040, which was manufactured using

0.5 µm process technology. In addtion, the
Am29F040B has a second toggle bit, DQ2, and also
offers the ability to program in the Erase Suspend
mode.

The standard Am29F040B o ffers access times of 55,
70, 90, 120, and 150 ns, allowing high-s peed micropro­cessors to operate without w ait states . To eliminate b us
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5. 0 v o lt po wer sup-
ply for both read and wr ite functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microproc essor write timing s. Register contents
serve as input to an internal sta te-machine that co n­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-

supply. A 12.0 volt VPP is

CC

matically times the program pulse widths an d verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequenc e. This initiates the Embedded Erase
algorithm—an in ternal algorithm that auto matically
preprograms the arra y (if it is not already progr ammed)
before e xecuting the er ase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.

The sector erase ar chitecture allo ws memo ry secto rs
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically in hibits write opera-

V

CC

tions during power transitions. The hardware sector
protection feature disables both program and erase

operations in any combination of the sectors of mem­ory . This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any s ector that is not selected for
erasure. True background erase can thus be achie ved.

The system can place the device into the standby
mode. Power consum ption is greatly reduced in
this mode.

AMD’s Flash technology combines years of Flash
memory manufacturing exper ience to produce the
highest levels of quality, reliability and cost effective­ness. The device electrically erases all bi t s w i th i n a
sector simultaneously via Fowler-Nordheim t unnel­ing. The data is programmed using hot electron injec­tion.

2 Am29F040B

PRELIMINARY

PRODUCT SELECTOR GUIDE

Family Part Number Am29F040B

= 5.0 V ± 5% -55

V

Speed Option

Max access time, ns (t

CC

= 5.0 V ± 10% -70 -90 -120 -150

V

CC

) 55 70 90 120 150

ACC

Max CE# access time, ns (tCE) 55 70 90 120 150
Max OE# access time, ns (tOE) 2530355055

Note: See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

DQ0–DQ7

V

CC

V

SS

Erase Voltage

Generator

Input/Output

Buffers

WE#

CE#
OE#

A0–A18

State

Control

Command

Register

V

Detector

CC

PGM Voltage

Generator

Timer

Chip Enable

Output Enable

STB

Logic

Y-Decoder

Address Latch

STB

Data Latch

Y-Gating

Cell MatrixX-Decoder

21445B-1

Am29F040B 3

CONNECTION DIAGRAMS

PRELIMINARY

A18
A16
A15
A12

DQ0
DQ1
DQ2

V

A11

A9

A8
A13
A14
A17

WE#

V

CC

A18
A16
A15
A12

A7

A6

A5

A4

A7
A6
A5
A4
A3
A2
A1
A0

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PDIP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

CC

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

21445B-2

32-Pin Standard TSOP

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

5
6
7
8
9
10
11
12
13

A12

DQ1

A15

A16

A18

1313023432

PLCC

17 18 19 20161514

SS

V

DQ2

DQ3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VCCWE#

DQ4

DQ5

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

A17

29
28
27
26
25
24
23
22
21

DQ6

SS

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

21445B-3

OE#

A10

CE#
DQ7
DQ6
DQ5
DQ4
DQ3

V

SS

DQ2
DQ1
DQ0

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-Pin Reverse TSOP

4 Am29F040B

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A11
A9
A8
A13
A14
A17
WE#
V

CC

A18
A16
A15
A12
A7
A6
A5
A4

21445B-4

PRELIMINARY

PIN CONFIGURATION

LOGIC SYMBOL

A0–A18 = Address Inputs
DQ0–DQ7 = Data Input/Output
CE# = Chip Enable
WE# = Write Enable

19

A0–A18

8

DQ0–DQ7

OE# = Output Enable
V

SS

= Device Ground

VCC = +5.0 V single power supply

(see Product Selector Guide for

CE#
OE#

WE#

device speed ratings and voltage
supply tolerances)

21445B-5

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:

Am29F040B -55 E C

B

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

Am29F040B-55
Am29F040B-70
Am29F040B-90
Am29F040B-120
Am29F040B-150

DEVICE NUMBER/DES CR IPT IO N

Am29F040B
4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Valid Combinations

JC, JI, JE, EC, EI, EE, FC, FI, FE

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

TEMPERATURE RANGE

C = Commercial (0
I=Industrial (–40

E = Extended (–55

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations list configurations planned to be sup­ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.

°C to +70°C)

°C to +85°C)

°C to +125°C)

Valid Combinations

Am29F040B 5

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa-

tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Table 1. Am29F040B Device Bus Operations

Operation CE# OE# WE# A0–A20 DQ0–DQ7

Read L L H A
Write L H L A
CMOS Standby VCC ± 0.5 V X X X High-Z

TTL Standby H X X X High-Z
Output Disable L H H X High-Z

Legend:

L = Logic Low = V

Note: See the section on Sector Protection for more information.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

IL

IN

IN

= Data Out, AIN = Address In

OUT

D

OUT

D

IN

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

.

IH

The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

An erase operation can erase one sect or, multiple sec­tors, or the entire de vice. The Sector Address Tables in-

, and OE# to VIH.

IL

dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifica tions apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is gr eatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

6 Am29F040B

PRELIMINARY

The device enters the CMOS standby mode when the
CE# pin is held at V
restricted voltage rang e than V
the TTL standby mode when CE# is held at V
device requires the standard ac cess time (t

± 0.5 V. (Note that this is a more

CC

.) The device enters

IH

) before it

CE

IH

. The

is ready to read data.
If the device is deselected during erasure or program -

in the DC Characteristics tables represents the

I

CC3

standby current specification.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

ming, the device draws active current until the
operation is completed.

Table 2. Sector Addresses Table

Sector A18 A17 A16 Address Range

SA0 0 0 0 00000h–0FFFFh
SA1 0 0 1 10000h–1FFFFh
SA2 0 1 0 20000h–2FFFFh
SA3 0 1 1 30000h–3FFFFh
SA4 1 0 0 40000h–4FFFFh
SA5 1 0 1 50000h–5FFFFh
SA6 1 1 0 60000h–6FFFFh
SA7 1 1 1 70000h–7FFFFh

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addi­tion, when verifying sector protection, the sector ad-

(11.5 V to 12.5 V) on address pin

ID

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Defini­tions table. This method does not require V

. See

ID

“Command Definitions” for details on using the autose­lect mode.

Am29F040B 7

PRELIMINARY

Table 3. Am29F040B Autoselect Codes (High Voltage Method)

Description A18–A16 A15–A10 A9 A8–A7 A6 A5–A2 A1 A0

Identifier Code on

DQ7-DQ0

Manufacturer ID: AMD X X V
Device ID: Am29F040B X X V

Sector Protection
Ve r ific atio n

Sector

Address

XV

ID

ID

ID

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro­tected sectors.

Sector protection/unprotection must be implemented
using programming equipment. The procedure re­quires a high voltage (V

) on address pin A9 and the

ID

control pins. Details on this method are provided in a
supplement, publication number 19957. Contact an
AMD representative to obtain a cop y of the appropriate
document.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Servic e. Contact an
AMD representative for details.

It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent accidental eras ure or pro-

XVILXVILV
XVILXVILV

XVILXVIHV

IL

IH

IL

01h
A4h

01h (protected)

00h (unprotected)

gramming, which might otherwise be caused by spuri­ous system level signals during V

power-up and

CC

power-down transitions, or from system noise.

Low V

When V

Write Inhibit

CC

is less than V

CC

, the device does not ac-

LKO

cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent uninten­tional writes when V

is greater than V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up , the

IL

device does not accept commands on the rising edge
of WE#. The internal state mac hine is automatically
reset to reading array data on power-up.

CC

CC

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

8 Am29F040B

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em­bedded Erase algorithm.

After the device accepts an Era se Suspend command,
the device enters the Erase Suspend mode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a progr amming operation in the Erase
Suspend mode, the system may once again read array

PRELIMINARY

data with the same ex ception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

must

The system
able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Tim ings diagram shows the
timing diagram.

issue the reset command to re-en-

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand
be written to return to reading array data (als o applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

must

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes ,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage

Method) table, which is in tended for PROM program­mers and requires VID on address bit A9.

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h or retrieves the manu­facturer code. A read cycle at address XX 01h returns
the device code. A read cycle containing a sector ad­dress (SA) and the address 02h in returns 01h if that
sector is protect ed, o r 0 0h if it i s unp rotec te d. Refer to
the Sector Address tables for valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
command. The program address and data are wr itten
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the prog ram oper ation b y using DQ7
or DQ6. See “Wr ite Operation Status” for information
on these status bits.

Any commands written to the device dur ing the Em­bedded Program Algorithm are ignored.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indic ate the operation was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

required to provide further

Am29F040B 9

Embedded

algorithm

in progress

Increment Address

Program

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

No

Last Address?

PRELIMINARY

plete, the device returns to reading array data and
addresses are no longer latched.

Figure 2 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command . The Command Definitions table
shows the address and data requirement s for the sec-

No

Yes

tor erase command sequence.
The device does

the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

not

require the system to preprogram

Yes

Programming

Completed

21445B-6

Note: See the appropriate Command Definitions table for
program command sequence.

Figure 1. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and ve rifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table show s the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored.

The system can deter mine the status of the erase

operation by using DQ7, DQ6, or DQ2. See “Wr ite
Operation Status” for information on these status
bits. When the Embedded Erase algorithm is com-

require the system to

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sector s. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the s ector

erase timer has timed out. (See the “DQ3 : Sector Erase
Timer” section.) The tim e-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, on ly the
Erase Suspend command is valid. All other commands
are ignored.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the sta­tus of the erase operation b y using DQ7, DQ6, or DQ2.
Refer to “Write Operation Status” for information on
these status bits.

10 Am29F040B

PRELIMINARY

Figure 2 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section f or par amet ers , and to
the Sector Erase Operations Ti ming diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to in­terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately ter minates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure . (The devi ce “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system can once again read arra y data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more infor ma­tion.

The system may also write the autos elect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21445B-7

Figure 2. Erase Operation

Am29F040B 11

PRELIMINARY

Table 4. Am29F040B Command Definitions

Bus Cycles (Notes 2–4)

Command
Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Autoselect

(Note 7)

Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Device ID 4 555 AA 2AA 55 555 90 X01 A4

Sector Protect Verify
(Note 8)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

XX00

4 555 AA 2AA 55 555 90

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A16 select a unique sector.

SA

X02

XX01

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles
are write operations.

4. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading array
data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status da ta).

7. The fourth cycle of the autoselect command sequence is a
read cycle.

8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.

9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.

10. The Erase Resume command is valid only during the Erase
Suspend mode.

12 Am29F040B

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

rithms) figure in the “AC Characteristics” section illus­trates this.

Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.

START

Read DQ7–DQ0

Addr = VA

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 2 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algor ithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the

following

read cycles. This is be­cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-

DQ7 = Data?

No

No

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

21445B-8

Figure 3. Data# Polling Algorithm

Am29F040B 13

PRELIMINARY

DQ6: Toggle Bit I

Toggle Bit I on D Q6 indicates whether a n Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the s ector erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cyc les to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog­gles for appro xi mately 100 µ s , t hen returns to read ing

array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Er ase alg orithm is in pr og ress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.

DQ2 toggles when the syste m reads at addresses
within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for s ector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.

Figure 4 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 4 for the follow ing discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically , a
system would note a nd store th e val ue of the to ggle bit
after the first read. After the second read, the system
would compare the ne w v alue of the toggle bit with the
first. If the toggle bit is not to ggling, the device has
completed the program or erase operation. The sys­tem can read arra y data on DQ7–DQ0 on the f ollo wing
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and
the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successi ve read cycles , de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform other
system tasks . In this ca se, the sy ste m must sta rt at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 4).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the pro gram or er ase cycle w as
not successfully completed.

14 Am29F040B

PRELIMINARY

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

START

Under both these conditions, t he system must issue the
reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selec ted for er asure, th e entire time­out also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een ad­ditional sector erase commands will always be less
than 50 µs. Se e also th e “S ector Er ase Command Se­quence” section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent s ector
erase command. If DQ3 is high on the second status
check, the last command m ight not have been ac­cepted. Table 5 shows the outputs for DQ3.

No

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

Note 1

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21445B-9

Figure 4. Toggle Bit Algorithm

Am29F040B 15

PRELIMINARY

Table 5. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

(Note 1) DQ6

1 No toggle 0 N/A Toggle

Data Data Data Data Data

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

DQ5

(Note 2) DQ3

DQ2

(Note 1)

16 Am29F040B

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

V

CC

A9, OE# (Note 2). . . . . . . . . . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may unde rshoot V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is V
voltage transitions, input and I/O pins may overshoot to
V

+ 2.0 V for periods up to 20 ns. See Figure 6.

CC

2. Minimum DC input volt age on A9 pin is –0.5 V. During
voltage transitions, A9 and OE# may unders hoot V
–2.0 V for periods of up to 20 ns. See Figure 5. Maximum
DC input voltage on A9 and OE# is 12 .5 V which may
overshoot to 13.5 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.

Stresses above those listed under “Absolute Maximum
Ratings” may c ause perm anent dama ge to the device. T his
is a stress rating on ly; functional operation o f the device at
these or any other conditions above those indicated in the op­erational sections of this specification is no t implied. Expo­sure of the device to absolute maximu m ratin g con ditions for
extended periods may affect device reliability.

CC

to –2.0 V

SS

+ 0.5 V. During

to

SS

20 ns

+0.8 V

–0.5 V
–2.0 V

20 ns

20 ns

Figure 5. Maximum Negative Overshoot

Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V
20 ns

20 ns

Figure 6. Maximum Positive Overshoot

Waveform

21445B-10

21445B-11

OPERATING RANGES

Commer cial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

V

Supply Voltages

CC

VCC for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V

for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V

V

CC

Operating rang es define those limits between which the
functionality of the device is guaranteed.

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

Am29F040B 17

PRELIMINARY

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

V

I

I
I
I

V
V

V
V

I

LI

LIT

I

LO

CC1

CC2

CC3

V

IL

IH

ID

OL

OH

LKO

Input Load Current VIN = V

A9 Input Load Current V
Output Leakage Current V
V

Active Read Current (Note 1) CE# = V

CC

VCC Active Write (Program/Erase)
Current (Notes 2, 3)

CC
OUT

CE#

VCC Standby Current VCC = VCC Max, CE# = V
Input Low Level –0.5 0.8 V
Input High Level 2.0 VCC + 0.5 V
Voltage for Autoselect

and Sector Protect

V

CC

Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V
Output High Level IOH = –2.5 mA, VCC = VCC Min 2.4 V
Low VCC Lock-Out Voltage 3.2 4.2 V

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

= V

OE# = V

IL,

CC

IH

IH

= V

Max ±1.0 µA

CC

= V

CC

Max ±1.0 µA

CC

20 30 mA
30 40 mA

IH

0.4 1.0 mA

= 5.25 V 10.5 12.5 V

CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Un it

Input Load Current VIN = V
A9 Input Load Current V
Output Leakage Current V
V

Active Read Current

CC

(Note 1)
V

Active Program/Erase Current

CC

(Notes 2, 3)
V

Standby Current (Note 4) VCC = VCC Max, CE# = V

CC

Input Low Level –0.5 0.8 V

IL

Input High Level 0.7 x V

IH

Voltage for Autoselect and Sector

ID

Protect

CC
OUT

CE# = V

CE#

V

CC

Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V
Output High Voltage IOH = –2.5 mA, V

IOH = –100 µA, VCC = VCC Min VCC –0.4 V

Low V

Lock-out Voltage 3.2 4.2 V

CC

I

I
I

V
V
V

I

I

LIT

I

LO

CC1

CC2

CC3

V

V
V

V

OH1
OH2
LKO

LI

OL

Notes for DC Characteristics (both tables):

1. The I

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

CC

The frequency component typically is less than 2 mA/MHz, with OE# at V

active while Embedded Algorithm (program or erase) is in progress.

2. I

CC

3. Not 100% tested.

4. For CMOS mode only, I

= 20 µA max at extended temperatures (> +85°C).

CC3

to VCC, V

SS

= V

Max, A9 = 12.5 V 50 µA

CC

= V

to VCC, VCC = V

SS

OE# = V

IL,

OE#

= VIL,

= VIH

CC

IH

= V

Max ±1.0 µA

CC

Max ±1.0 µA

CC

20 30 mA

30 40 mA

± 0.5 V 1 5 µA

CC

CC

VCC + 0.3 V

= 5.25 V 10.5 12.5 V

= V

CC

Min 0.85 VCC V

CC

.

IH

18 Am29F040B

TEST CONDITIONS

p

Device

Under

Test

C

L

6.2 kΩ

PRELIMINARY

5.0 V

2.7 kΩ

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Table 6. Test Specifications

Test Condition -55 All others Unit

L

30 100 pF

Note: Diodes are IN3064 or equivalent

Figure 7. Test Setu

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21445B-12

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 0.8 V

1.5 2.0 V

KS000010-PAL

Am29F040B 19

AC CHARACTERISTICS
Read Only Operations

PRELIMINARY

Parameter Symbols

Description Test Setup

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

t

t

ACC

t
t

t

OEH

t

t

t

Read Cycle Time (Note 3) Min 55 70 90 120 150 ns

RC

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 55 70 90 120 150 ns

CE

Output Enable to Output Delay Max 30 30 35 50 55 ns

OE

Output Enable Hold
Time (Note 3)

Chip Enable to Output High Z

DF

(Notes 2, 3)
Output Enable to Output High Z

DF

(Notes 2, 3)
Output Hold Time from Addresses, CE#

OH

or OE#, Whichever Occurs First

Notes:

1. See Figure 7 and Table 6 for test conditions.

2. Output driver disable time.

3. Not 100% tested.

Speed Options (Note 1)

UnitJEDEC Standard -55 -70 -90 -120 -150

CE# = V

OE# = V

IL,

Max 55 70 90 120 150 ns

IL

Read Min00000ns
Toggle and

Data# Polling

Min1010101010ns

Max1820203035ns

18 20 20 30 35 ns

Min00000ns

Addresses

CE#

OE#

WE#

Outputs

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 8. Read Operation Timings

t

OH

t

DF

HIGH Z

21445B-13

20 Am29F040B

AC CHARACTERISTICS
Erase and Program Operations

PRELIMINARY

Parameter Symbols

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

OES

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

WHWH1

t

WHWH2

Speed Options

Description

UnitJEDEC Std. -55 -70 -90 -120 -150

Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 45 50 50 ns
Data Setup Time Min 25 30 45 50 50 ns
Data Hold Time Min 0 ns
Output Enable Setup Time Min 0 ns
Read Recover Time Before Write

(OE# high to WE# low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 30 35 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation

(Note 2)

Sector Erase Operation
(Note 2)

Typ 7 µs

Typ 1 sec

t

VCS

VCC Set Up Time (Note 1) Min 50 µs

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Am29F040B 21

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

GHWL

t

CH

OE#

t

WP

WE#

t

t

DH

Data

V

CC

t

VCS

t

CS

t

DS

A0h

Note: PA = program address, PD = program data, D

Figure 9. Program Operation Timings

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

t

WPH

PD

is the true data at the program address.

OUT

PA

WHWH1

Status

D

OUT

21445B-14

Erase Command Sequence (last two cycles) Read Status Data

t

AS

555h for chip erase

Addresses

t

WC

2AAh SA

CE#

t

GHWL

t

t

WP

t

DS

55h

CH

t

WPH

t

DH

10 for Chip Erase

OE#

WE#

Data

V

CC

t

VCS

t

CS

Note:

SA = Sector Address. VA = Valid Address for reading status data.

Figure 10. Chip/Sector Erase Operation Timings

VA

t

AH

t

WHWH2

30h

Progress

VA

In

Complete

21445B-15

22 Am29F040B

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

PRELIMINARY

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

Status Data

Status Data

True

Valid Data

High Z

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle .

21445B-16

Figure 11. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

t

CH

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note:

V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.

21445B-17

Figure 12. Toggle Bit Timings (During Embedded Algorithms)

Am29F040B 23

AC CHARACTERISTICS

PRELIMINARY

Enter

Embedded

Erasing

WE#

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

DQ6

DQ2

DQ2 and DQ6 toggle with OE# and CE#

Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the “Write Operation Status” section for more
information.

21445B-18

Figure 13. DQ2 vs. DQ6

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbols

Description

Speed Options

UnitJEDEC Standard -55 -70 -90 -120 -150

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

t

WHWH2

Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 45 50 50 ns
Data Setup Time Min 25 30 45 50 50 ns
Data Hold Time Min 0 ns
Read Recover Time Before Write Min 0 ns
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 30 35 45 50 50 ns
Write Pulse Width High Min 20 20 20 20 20 ns
Byte Programming Operation

(Note 2)

Sector Erase Operation
(Note 2)

Typ 7 µs

Typ 1 sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

24 Am29F040B

AC CHARACTERISTICS

555 for program
2AA for erase

PRELIMINARY

PA for program
SA for sector erase
555 for chip erase

Data# Polling

Addresses

t

t

WC

WH

t

AS

t

AH

PA

WE#

t

GHEL

OE#

t

t

BUSY

WHWH1 or 2

DQ7# D

OUT

CE#

Data

t

CP

t

WS

t

RH

t

CPH

t

DS

t

DH

A0 for program
55 for erase

PD for program
30 for sector erase
10 for chip erase

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

Figure 14. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

21445B-19

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 se c
Chip Erase Time 8 64 sec
Byte Programming Time 7 300 µs

Chip Programming Time (Note 3) 3.6 10.8 sec

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V (4.75 V for -55), 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

Am29F040B 25

LATCHUP CHARACTERISTICS

PRELIMINARY

Min Max

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on all I/O pins –1.0 V VCC + 1.0 V

SS

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF
Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VIN = 0 7.5 9 pF

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

PLCC AND PDIP PIN CAPACITANCE

Parameter Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 4 6 pF
Output Capacitance V

= 0 8 12 pF

OUT

Control Pin Capacitance VPP = 0 8 12 pF

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

26 Am29F040B

PRELIMINARY

PHYSICAL DIMENSIONS
PD 032

32-Pin Plastic DIP (measured in inches)

1.640

1.670

.120
.160

32

.140
.225

Pin 1 I.D.

.045
.065

.005 MIN

.090
.110

.016
.022

17

.530
.580

16

SEATING PLANE

.015
.060

PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches)

.600
.625

.009
.015

.630
.700

0°

10°

16-038-S_AG
PD 032
EC75
5-28-97 lv

.585
.595

.547
.553

.026
.032

.447
.453

Pin 1 I.D.

TOP VIEW

.485
.495

.050 REF.

SEATING

PLANE

.125
.140

.080
.095

.009
.015

.013
.021

.400

REF.

SIDE VIEW

.042
.056

.490
.530

16-038FPO-5
PL 032
DA79
6-28-94 ae

Am29F040B 27

PRELIMINARY

PHYSICAL DIMENSIONS (continued)
TS 032

32-Pin Standard Thin Small Package (measured in millimeters)

Pin 1 I.D.

1

0.95

1.05

7.90

8.10

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TS 032
DA95
3-25-97 lv

28 Am29F040B

PRELIMINARY

PHYSICAL DIMENSIONS (continued)
TSR032

32-Pin Reversed Thin Small Outline Package (measured in millimeters)

Pin 1 I.D.

1

7.90

8.10

0.95

1.05

0.50 BSC

1.20

MAX

18.30

18.50

19.80

20.20

0.05

0.15

0.08

0.20

0.10

0°
5°

0.50

0.70

0.21

16-038-TSOP-2
TSR032
DA95
3-25-97 lv

Am29F040B 29

PRELIMINARY

REVISION SUMMARY FOR AM29F040B

Global

Formatted for consistency with other 5.0 volt-only data
data sheets.

Revision B+1

AC Characteristics, Er ase and Program Operations

Added Note references to t
rameter symbol for V

WHWH1

Set-up Time to t

CC

ification is 50 µs minimum. Deleted the last row in t able.

. Corrected the pa-

; the spec-

VCS

Revision B+2

Distinctive Characteristics

Changed minimum 100K wr ite/erase cycles guaran­teed to 1,000,000.

Ordering Infomation

Added extended temperature a v ailabilit y to the -55 and

-70 speed options.

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

notes reference f or t

WHWH1

and t

WHWH2

eters are 100% tested. Corrected the note ref erence for

. This parameter is not 100% tested.

t

VCS

Erase and Programming Performance

Changed mini mum 100K program a nd erase cycles
guaranteed to 1,000,000.

Corrected the

. These param-

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

30 Am29F040B