AMD Am29F032B Service Manual

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Am29F032B

32 Megabit (4 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.32 µm process technology

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 30 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current (standard access

time to active mode)

■ Flexible sector arc hitecture

— 64 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
— A hardware method of locking sector groups to

prevent any program or erase operations within
that sector group

— Temporary Sector Group Unprotect allows code

changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 write/erase cycles

guaranteed

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— 40-pin TSOP
— 44-pin SO

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting program

or erase cycle completion

■ Ready/Busy output (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

■ Erase Suspend/Resume

— Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,
then resumes the erase operation

■ Hardware reset pin (RESET#)

— Resets internal state machine to the read mode

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.

Publication# 21610 Rev: D Amendment/+1
Issue Date: December 5, 2000

GENERAL DESCRIPTION

The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
memory or ganized as 4,19 4,304 bytes of 8 bits e ach.
The 4 Mbytes of data are divided into 64 sectors of 64
Kbytes each for flexible erase capability. The 8 bits of

data appear on DQ0–DQ7. The Am29F032B is offered
in 40-pin TSOP and 44-pin SO packages. The
Am29F032B is manufactured using AMD’s 0.32 µm
process technology. This device is designed to be pro­grammed in-system with the standard s ystem 5.0 volt

supply. A 12.0 volt VPP is not required for program

V

CC

or erase operations. The device can also be pro­grammed in standard EPROM programmers.

The standard device offers access tim es of 70, 90,
120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus con­tention, the device has separate chip enable (CE#),
write enable (WE#), and output enable (OE#) controls.

The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal state machine that con­trols the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed for
the programming and erase operations. Reading data
out of the device is similar to reading from 12.0 volt
Flash or EPROM devices.

The device is programmed by executing the program
command sequence. This invokes the Embedded Pro­gram algorithm—an internal algorithm that automati­cally times the program pulse widths and verifies
proper cell margin. The device is e rased by executing
the erase command sequence. This invokes the Em­bedded Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other s ectors. A sector is typically
erased and verified within one second. The device is
erased when shipped from the factory.

The hardware sector group protection feature disables
both program and erase operations in an y combination
of the eight sector groups of memory. A sector group
consists of four adjacent sectors.

The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
True background erase can thus be achieved.

The device requires only a s ingle 5.0 v olt p o wer supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. A low V

detector automati-

CC

cally inhibits write operations during power transitions.
The host system can detect whether a program or
erase cycle is complete by using the RY/BY# pin, the
DQ7 (Data# Polling) or DQ6 (toggle) status bits. After
a program or erase cycle has been completed, the de­vice automatically returns to the read mode.

A hardware RESET# pin terminates any operation in
progress. The internal state machine is reset to the
read mode. The RESET# pin may be tied to the sys­tem reset circuitry. Therefore, if a system reset occurs
during either an Embedded Program or Embedded
Erase algorithm, the device is au tom at ic al ly re se t t o t he
read mode. This enables the system’s microprocessor
to read the boot-up firmware from the Flash memory.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of qu ality, reliab ility, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at
a time using the programming mechanism of hot
electron injection.

2 Am29F032B

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29F032B Device Bus Operations.................................. 8

Requirements for Reading Array Data............. ........................ 8

Writing Commands/Command Sequences ....................... .. .. .. . 8

Program and Erase Operation Status ...................................... 9

Standby Mode ............................. ..................................... ........ 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode................................................................ 9

Table 2. Am29F032B Sector Address Table............................. ...... 10

Autoselect Mode..................................................................... 11

Table 3. Am29F032B Autoselect Codes......................................... 11

Sector Group Protection/Unprot ection................... ................. 12

Table 4. Sector Group Addresses ................................................... 12

Temporary Sector Group Unprotect ....................................... 12

Figure 1. Temporary Sector Group Unprotect Operation................ 12

Hardware Data Protection...................................................... 13

Low VCC Write Inhibit..................................................................... 13

Write Pulse “Glitch” Protection........................................................ 13

Logical Inhibit........... ...... ... ..... ......... ....... ....... .... ..... ....... ......... ....... .. 13

Power-Up Write Inhibit.................................................................... 13

Command Definitions . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data.............. .................................................. 13

Reset Command..................................................................... 13

Autoselect Command Sequence............................................ 14

Byte Program Command Sequence... .............................. ...... 14

Chip Erase Command Sequence........................................... 14

Figure 2. Program Operation.......................................................... 15

Sector Erase Command Sequence........................................ 15

Erase Suspend/Erase Resume Commands..... .. ................. .. . 15

Figure 3. Erase Operation............................................................... 16

Command Definitions ............................................................. 17

Table 5. Am29F032B Command Definitions................................... 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling................................................................. 18

Figure 4. Data# Polling Algorithm ................................................... 18

RY/BY#: Ready/Busy# ........................................................... 19

DQ6: Toggle Bit I.................................................................... 19

DQ2: Toggle Bit II ................................................................... 19

Reading Toggle Bits DQ6/DQ2 .............................................. 19

DQ5: Exceeded Timing Limits................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Figure 5. Toggle Bit Algorithm........................................................ 20

Table 6. Write Operation Status ..................................................... 21

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22

Figure 6. Maximum Negat ive Overshoot Wav eform...................... 22

Figure 7. Maximum Positive Overshoot Waveform........................ 22

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

TTL/NMOS Compatible .......................................................... 23

CMOS Compatible.................................................................. 23

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8. Test Setup...................................................................... 24

Table 7. Test Specifications........................................................... 24

Key To Switching Waveforms . . . . . . . . . . . . . . . 24

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25

Read-only Operations............................................................. 25

Figure 9. Read Operation Timings................................................. 25

Hardware Reset (RESET#) .................................................... 26

Figure 10. RESET# Timings.......................................................... 26

Write (Erase/Program) Operations......................................... 27

Figure 11. Program Operation Timings.......................................... 28

Figure 12. Chip/Sector Erase Operation Timings .......................... 29

Figure 13. Data# Polling Timings (During Embedded Algorithms). 30

Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 30

Figure 15. DQ2 vs. DQ6................................................................. 31

Temporary Sector Unprotect.................................................. 31

Figure 16. Temporary Sector Group Unprotect Timings................ 31

Write (Erase/Program) Operations—Alter nate CE#

Controlled Writes.................................................................... 32

Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33

Erase And Programming Performance . . . . . . . 34

Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34

TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35

SO 044–44-Pin Small Outline Package.................................. 35

TS 040–40-Pin Standard Thin Small Outline Package........... 36

TSR040–40-Pin Reversed Thin Small Outline Package........ 37

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision A (June 1998) .......................................................... 38

Revision B (July 1998)............................................................ 38

Revision C (January 1999)..................... ................................ 38

Revision C+1 (April 14, 1999)................................................. 38

Revision D (November 17, 1999) ........................................... 38

Revision D+1 (December 5, 2000)......................................... 38

Am29F032B 3

PRODUCT SELECTOR GUIDE

Family Part Number Am29F032B

= 5.0 V ± 5% -75

V

Speed Options

Max access time, ns (t

ACC

Max CE# access time, ns (t
Max OE# access time, ns (t

CC

= 5.0 V ± 10% -90 -120 -150

V

CC

) 70 90 120 150

) 70 90 120 150

CE

) 40405075

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

V

CC

V

SS

RY/BY#

RESET#

WE#

CE#

OE#

A0–A21

State

Control

Command

Register

VCC Detector

PGM Voltage

Generator

Timer

Sector Switches

Erase Voltage

Generator

STB

Chip Enable

Output Enable

Y-Decoder

X-Decoder

Address Latch

STB

Input/Output

Buffers

Data

Latch

Y-Gating

Cell Matrix

4 Am29F032B

CONNECTION DIAGRAMS

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

RESET#

A11
A10

A20

A21

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

V

V
DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

NC

CC
SS
SS

A9
A8
A7
A6
A5
A4

1
2
3
4
5
6
7
8
9

CC

10
11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40-Pin Standard TSOP

40-Pin Reverse TSOP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20
A21
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3

A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4

NC

RESET#

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

A3

A2

A1

A0

DQ0
DQ1
DQ2
DQ3

V
V

SS
SS

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

CC

CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
A21
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

Am29F032B 5

PIN CONFIGURATION

A0–A21 = 22 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output

= +5.0 V single power supply

V

CC

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

= Device Ground

LOGIC SYMBOL

22

A0–A21

CE#
OE#

WE#
RESET# RY/BY#

8

DQ0–DQ7

6 Am29F032B

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Am29F032B -75 E I

DEVICE NUMBER/DESCRIPTION

Am29F032B
32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40

E = Extended (–55

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)
S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

°C to +85°C)

°C to +125°C)

Valid Combinations

AM29F032B-75 EC, EI, FC, FI, SC, SI
AM29F032B-90
AM29F032B-120
AM29F032B-150

EC, EI, EE, FC, FI, FE,
SC, SI, SE

Valid Combinations

Valid Combinations list configurations planned to be support­ed in volume for this device. Cons ult the loc al AM D sale s of­fice to confirm availab ility of specific valid com binations and
to check on newly released combinations.

Am29F032B 7

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29F032B Device Bus Operations

Operation CE# OE # WE# RESET# A0–A21 DQ0–DQ7

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Read L L H H A
Write L H L H A
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect

(See Note)

Legend:

L = Logic Low = V

Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

IL

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

. CE# is the power

IL

control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE#
should remain at V

.

IH

The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com­mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

in the DC Characteristics

CC1

table represents the active current specifi cation for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

XXX V

ID

sectors of memory), the system must drive WE# and
CE# to V

, and OE# to VIH.

IL

An erase operation can erase one sect or, multiple sec­tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits re­quired to uniquely select a secto r. See the “Writing
specific address and data commands or sequences
into the command register initiates device operations.
The Command Defin itions table define s the valid reg­ister command sequences. Writing incorrect address
and data values or writing them in the improper se­quence resets the device to reading array data.” sec­tion for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.

After the system wr ites the autosele ct comman d se­quence, the device enters the autoselect m ode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” and “Au­toselect Command Sequence” sections for more infor­mation.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The “AC

OUT

IN

IN

A

IN

= Data Out, AIN = Address In

D

OUT

D

IN

D

IN

cludes programming data to the device and erasing

8 Am29F032B

Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “The Erase Resume
command is valid only dur ing the Erase Suspend
mode.” for more information, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restricted voltage rang e than V

± 0.5 V. (Note

CC

IH

The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t

CE

. The device re-

IH

) for read a ccess when
the device is in either of these standb y modes, bef ore it
is ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

In the DC Ch aracteristics tables, I

represents the

CC3

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system

drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

, the device enters

IL

the TTL standby mode; if RESET# is held at V

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a

.)

time of t

(during Embedded Algorithms). The sys-

READ Y

tem can thus monitor RY/BY# to determine whether the
reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a tim e of t
rithms). The system can read data t
SET# pin returns to V

(not during Embedded Algo-

READY

.

IH

RH

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the devi ce is
disabled. The output pins are placed in t he high imped­ance state.

RP

SS

after the RE-

,

±

Am29F032B 9

Table 2. Am29F032B Sector Address Table

Sector A21 A20 A19 A18 A17 A1 6 Sector Size Address Range

SA0 0 0 0 0 0 0 64K 000000h–00FFFFh
SA1 0 0 0 0 0 1 64K 010000h–01FFFFh
SA2 0 0 0 0 1 0 64K 020000h–02FFFFh
SA3 0 0 0 0 1 1 64K 030000h–03FFFFh
SA4 0 0 0 1 0 0 64K 040000h–04FFFFh
SA5 0 0 0 1 0 1 64K 050000h–05FFFFh
SA6 0 0 0 1 1 0 64K 060000h–06FFFFh
SA7 0 0 0 1 1 1 64K 070000h–07FFFFh
SA8 0 0 1 0 0 0 64K 080000h–08FFFFh

SA9 0 0 1 0 0 1 64K 090000h–09FFFFh
SA10 0 0 1 0 1 0 64K 0A0000h–0AFFFFh
SA11 0 0 1 0 1 1 64K 0B0000h–0BFFFFh
SA12 0 0 1 1 0 0 64K 0C0000h–0CFFFFh
SA13 0 0 1 1 0 1 64K 0D0000h–0DFFFFh
SA14 0 0 1 1 1 0 64K 0E0000h–0EFFFFh
SA15 0 0 1 1 1 1 64K 0F0000h–0FFFFFh
SA16 0 1 0 0 0 0 64K 100000h–10FFFFh
SA17 0 1 0 0 0 1 64K 110000h–11FFFFh
SA18 0 1 0 0 1 0 64K 120000h–12FFFFh
SA19 0 1 0 0 1 1 64K 130000h–13FFFFh
SA20 0 1 0 1 0 0 64K 140000h–14FFFFh
SA21 0 1 0 1 0 1 64K 150000h–15FFFFh
SA22 0 1 0 1 1 0 64K 160000h–16FFFFh
SA23 0 1 0 1 1 1 64K 170000h–17FFFFh
SA24 0 1 1 0 0 0 64K 180000h–18FFFFh
SA25 0 1 1 0 0 1 64K 190000h–19FFFFh
SA26 0 1 1 0 1 0 64K 1A0000h–1AFFFFh
SA27 0 1 1 0 1 1 64K 1B0000h–1BFFFFh
SA28 0 1 1 1 0 0 64K 1C0000h–1CFFFFh
SA29 0 1 1 1 0 1 64K 1D0000h–1DFFFFh
SA30 0 1 1 1 1 0 64K 1E0000h–1EFFFFh
SA31 0 1 1 1 1 1 64K 1F0000h–1FFFFFh
SA32 1 0 0 0 0 0 64K 200000h–20FFFFh
SA33 1 0 0 0 0 1 64K 210000h–21FFFFh
SA34 1 0 0 0 1 0 64K 220000h–22FFFFh
SA35 1 0 0 0 1 1 64K 230000h–23FFFFh
SA36 1 0 0 1 0 0 64K 240000h–24FFFFh
SA37 1 0 0 1 0 1 64K 250000h–25FFFFh
SA38 1 0 0 1 1 0 64K 260000h–26FFFFh
SA39 1 0 0 1 1 1 64K 270000h–27FFFFh
SA40 1 0 1 0 0 0 64K 280000h–28FFFFh
SA41 1 0 1 0 0 1 64K 290000h–29FFFFh
SA42 1 0 1 0 1 0 64K 2A0000h–2AFFFFh
SA43 1 0 1 0 1 1 64K 2B0000h–2BFFFFh

10 Am29F032B

Table 2. Am29F032B Sector Address Table (Continued)

Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range

SA44 1 0 1 1 0 0 64K 2C0000h–2CFFFFh
SA45 1 0 1 1 0 1 64K 2D0000h–2DFFFFh
SA46 1 0 1 1 1 0 64K 2E0000h–2EFFFFh
SA47 1 0 1 1 1 1 64K 2F0000h–2FFFFFh
SA48 1 1 0 0 0 0 64K 300000h–30FFFFh
SA49 1 1 0 0 0 1 64K 310000h–31FFFFh
SA50 1 1 0 0 1 0 64K 320000h–32FFFFh
SA51 1 1 0 0 1 1 64K 330000h–33FFFFh
SA52 1 1 0 1 0 0 64K 340000h–34FFFFh
SA53 1 1 0 1 0 1 64K 350000h–35FFFFh
SA54 1 1 0 1 1 0 64K 360000h–36FFFFh
SA55 1 1 0 1 1 1 64K 370000h–37FFFFh
SA56 1 1 1 0 0 0 64K 380000h–38FFFFh
SA57 1 1 1 0 0 1 64K 390000h–39FFFFh
SA58 1 1 1 0 1 0 64K 3A0000h–3AFFFFh
SA59 1 1 1 0 1 1 64K 3B0000h–3BFFFFh
SA60 1 1 1 1 0 0 64K 3C0000h–3CFFFFh
SA61 1 1 1 1 0 1 64K 3D0000h–3DFFFFh
SA62 1 1 1 1 1 0 64K 3E0000h–3EFFFFh
SA63 1 1 1 1 1 1 64K 3F0000h–3FFFFFh

Note: All sectors are 64 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector group protection v erifica-

tion, through ide ntifier codes output on DQ7–DQ0.
This mode is primar ily intended for programming
equipment to automatically match a device to be pro­grammed with its corresponding programming algo­rithm. However, the autoselect cod es can also be
accessed in-system through the command register .

When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector group pro-

Description A21-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0

Manufacturer ID: AMD X X V
Device ID: Am29F032B X X V

Sector Group Protection
Verification

(11.5 V to 12.5 V) on address pin

ID

Table 3. Am29F032B Autoselect Codes

Sector
Group

Address

XV

ID

ID

ID

tection, the sect or group a ddress mus t appear on the
appropriate highest order address bits (see Table 4).
Table 3 also shows the remaining address bits that are
don’t care. When all necessary bits have been set as
required, the programming equipment may then read
the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command re gister, as shown in Table 5. This meth od
does not require V

on an address line. Refer to the

ID

Autoselect Command Sequence section for more in­formation.

Identifier Code on

DQ7-DQ0

XVILXVILV
XVILXVILV

XVILXVIHV

IL

IH

IL

01h
41h

01h (protected)

00h (unprotected)

Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit.

Am29F032B 11

Sector Group Protection/Unprotection

The hardware sector group protection feature disables
both program and erase operations in any sector
group. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group con­tains. The hardware sector group unprotection feature
re-enables both program and erase operations in pre­viously protected sector groups.

Sector grou p pr otection/unprotection must be imple­mented using pr ogramming equipm ent. The proce­dure requires a high voltage (V
and the control pins. Details on this method are pro­vided in a supplement, publication number 22184.
Contact an AMD representative to obtain a copy of the
appropriate document.

The device is shipped with all sector groups unpro­tected. AMD offers t he optio n of prog r amming a nd pro­tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con­tact an AMD representative for details.

It is possible to determine whether a sector gr oup is
protected or unprotected. See “Autoselect Mode” for
details.

) on address pin A9

ID

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is activat ed by
setting the RESET# pin to V
ing this mode, f ormerly protected se ctor g roups c an be
programmed or erased by selecting the sector group
addresses. Once V

is removed from the RESET#

ID

pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
Figure 16 shows the timing diagrams, for this feature.

Perform Erase or

Program Operations

(11.5 V – 12.5 V). Dur-

ID

START

RESET# = V

(Note 1)

RESET# = V

ID

IH

Table 4. Sector Group Addresses

Sector
Group A21 A20 A19 A18 Sectors

–

SGA00000SA0
SGA10001SA4
SGA2 0 0 1 0 SA8
SGA3 0 0 1 1 SA12
SGA4 0 1 0 0 SA16
SGA5 0 1 0 1 SA20
SGA6 0 1 1 0 SA24
SGA7 0 1 1 1 SA28
SGA81000SA32–SA35

SGA9 1 0 0 1 SA36–SA39
SGA10 1 0 1 0 SA40–SA43
SGA11 1 0 1 1 SA44–SA47
SGA12 1 1 0 0 SA48–SA51
SGA13 1 1 0 1 SA52–SA55
SGA14 1 1 1 0 SA56–SA59
SGA15 1 1 1 1 SA60–SA63

SA3

–

SA7

–

SA11

–

SA15

–

SA19

–

SA23

–

SA27

–

SA31

Temporary Sector Group

Unprotect Completed

(Note 2)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected
once again.

Figure 1. Temporary Sector Group Unprotect

Operation

12 Am29F032B

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection.
In addition, the following hardware data protection
measures prevent accidental erasure or programming,
which might otherwise be c aused by spur ious system
level signals during V

power-up and power-down

CC

transitions, or from system noise.

Low V

When V

Write Inhibit

CC

is less than V

CC

(see DC Characteristics

LKO

for voltage levels), the device does not accept any
write cycles. This protects data during V

power-up

CC

and power-down. The command register and all inter­nal program/erase circu its are disabled. Unde r this
condition the device resets to the read mode. Subse­quent writes are ignored until the V

level is greater

CC

COMMAND DEFINITIONS

Writing specific address and data commands or se­quences into the command register initiates device op­erations. The Command Definitions table defines the
valid register command sequences. Wri ting incorrect

address and data values or wr iting them in th e im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend mod e. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor­mation on this mode.

must

The system
able the device for reading array data if DQ5 goes
high, or while in the au toselect mode. See the “R eset
Command” section, next.

issue the reset command to re-en-

than V

. The system must ensure that the control

LKO

pins are logically correct to prevent unintentional
writes when V

is above V

CC

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

, CE# = VIH or WE# = VIH. To initiate a write cycle,

V

IL

CE# and WE# must be at V

while OE# is at VIH.

IL

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up,

IL

the device does not accept commands on the rising
edge of WE#. The intern al state machi ne is automati­cally reset to the read mode on power-up.

See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more infor ma­tion. The Read Operations table provides the read pa­rameters, and Read Operation Timings diagram
shows the timing diagram.

Reset Command

Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). O nce programming beg ins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mod e, the reset command

must

be written to retur n to read ing array data (also

applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

Am29F032B 13

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program­mers and requires V

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

on address bit A9.

ID

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-

not

gorithm. The system is
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a

required to provide further

hardware reset immediately terminates the program­ming operation. The program command sequence
should be reinitiated once the d e vice has res et to read­ing array data, to ensure data integ rity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1”, or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.

Chip Erase Command Sequence

Chip erase is a six-bu s-cycle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase

not

algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table shows the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can deter mine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“The Erase Resume com mand is valid only during
the Erase Suspend mode.” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no long er latched.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.

require the system to

14 Am29F032B

Embedded

Program

algorithm

in progress

Increment Address

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

No

Last Address?

Yes

No

otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the s ector

erase timer has timed out. (See the “DQ3 : Sector Erase
Timer” section.) The tim e-out begins from the rising
edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, on ly the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op­eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

Yes

Programming

Completed

Note: See Table 5 for program command sequence.

Figure 2. Program Operation

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec­tor erase command sequence.

not

The device does
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begi ns. During the time-out per iod,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all secto rs. The time be­tween these additional cycl es must be less than 50 µs ,

require the system to preprogram

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addr esses are
no longer latched. The system can determine the sta­tus of the erase operation b y using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “The Erase Resume command is
valid only during the Erase Suspend mode.” for infor­mation on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows t he syste m to in­terrupt a sector erase ope ration and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase c ommand sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the er ase oper at ion. Ad­dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-

Am29F032B 15

minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to

any sector not selected for erasure . (The devi ce “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is active ly erasing or is erase-suspended.
See “The Erase Resume command is v alid only during
the Erase Suspend mode.” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system can once again read arra y data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “The Erase Resume command is valid only
during the Erase Suspend mode.” f or more inf ormation.

The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operat ion. Further
writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de­vice has resumed erasing.

START

Write Erase

Command Sequence

Data Poll

from System

No

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Data = FFh?

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

Figure 3. Erase Operation

16 Am29F032B

Command Definitions

Table 5. Am29F032B Command Definitions

Bus Cycles (Notes 2–4)

Command

Sequence

(Note 1)

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Autoselect

(Note 7)

Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Device ID 4 555 AA 2AA 55 555 90 X01

Sector Group Protect
Verify (Note 8)

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the f alling edge of the WE# or CE# pulse,
whichever happens later.

First Second Third Fourth Fifth Sixth

Cycles

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

41

XX00

4 555 AA 2AA 55 555 90

SGA

X02

XX01

PD = Data to be progr ammed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A21–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address
bits A21–A18 select a unique sec tor group.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A21–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading
array data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is
a read cycle.

8. The data is 00h for an unprotected sector group and 01h
for a protected sector group.See “Autoselect Command
Sequence

” for more information.

9. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.

10. The Erase Resume command is valid only during the
Erase Suspend mode.

Am29F032B 17

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

rithms) figure in the “AC Characteristics” section illus­trates this.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

START

Read DQ7–DQ0

Addr = VA

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-

µ

proximately 2

s, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling

µ

on DQ7 is active f or appro ximately 100

s, then the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read valid data at

DQ7–DQ0 on the

following

read cycles. This is be­cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-

DQ7 = Data?

No

No

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

No

FAIL

Yes

Yes

PASS

Figure 4. Data# Polling Algorithm

18 Am29F032B

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia­grams for read, reset, program, and erase shows the
relationship of RY /BY# to other signals.

CC

.

DQ6: Toggle Bit I

Toggle Bi t I on DQ6 indicates w hether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the sector erase time-out.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figu re in the

“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare output s
for DQ2 and DQ6.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-

µ

gles for appro xi mately 100
array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a pro tected sector,

DQ6 toggles for approximately 2

command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

s, then returns to reading

µ

s after the program

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note a nd store th e val ue of the to ggle bit
after the first read. After the second read, the system
would compare the ne w v alue of the toggle bit with the
first. If the toggle bit is not to ggling, the device has
completed the program or erase operation. The sys­tem can read arra y data on DQ7–DQ0 on the f ollo wing
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

Am29F032B 19

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perfor m other
system tasks . In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selec ted for er asure, th e entire time­out also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een ad­ditional sector erase commands will always be less
than 50 µs. See a lso the “Sector Eras e Command Se­quence” section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the comm and has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

START

Read DQ7–DQ0

Read DQ7–DQ0

Toggle Bit

= Toggle?

Yes

No

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

(Note 1)

No

(Notes
1, 2)

No

Program/Erase

Operation Complete

Figure 5. Toggle Bit Algorithm

20 Am29F032B

Table 6. Write Operation Status

DQ7

Standard
Mode

Erase
Suspend
Mode

Operation

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase

Suspended Sector
Reading within Non-Erase

Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

(Note 1) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

DQ5

(Note 2) DQ3

DQ2

(Note 1) RY/BY#

Am29F032B 21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1). . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

V

CC

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 13.0 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 2 00 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

+ 2.0 V

CC

SS

to

During voltage transitions, inputs may overshoot V
–2.0 V for periods of up to 20 ns. See Figure 6. Maximum
DC voltage on output and I/O pins is V

+ 0.5 V. During

CC

voltage transitions, outputs may overshoot to V
for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
may ov ershoot V

to –2.0 V for periods of up to 20 ns. See

SS

Figure 6. Maximum DC input voltage on A9, OE#, and
RESET# is 13.0 V which may o vershoot to 13.5 V for
periods up to 20 ns .

3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.

+0.8 V

–0.5 V
–2.0 V

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V

20 ns

20 ns

20 ns

Figure 6. Maximum Negative

Overshoot Waveform

20 ns

20 ns

20 ns

Stresses greater than those listed in this section may cause
permanent damag e to the device. This is a stress rating only;
functional operation of the d evice at these or any other co ndi­tions above those indica ted in the op erational sectio ns of this
specification is not implied. Exposure of the device to absolute
maximum rating conditions f or extended periods may affect de­vice reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

Industrial (I) Devices

Ambient Temperature (T

Extended (E) Devices

Ambient Temperature (T

Supply Voltages

V

CC

for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V

V

CC

for ± 10% devices . . . . . . . . . .+4.50 V to +5.50 V

V

CC

Operating rang es define those limits between which the
functionality of the device is guaranteed.

) . . . . . . . . . . . 0°C to +70°C

A

) . . . . . . . . . –40°C to +85°C

A

) . . . . . . . . –55°C to +125°C

A

Figure 7. Maximum Positive

Overshoot Waveform

22 Am29F032B

DC CHARACTERISTICS
TTL/NMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

V

I
I

I

CC1

I

CC2

I

CC3

I

CC4

V

V
V

V
V

I

LI

LIT

LO

IH

ID

OL

OH

LKO

Input Load Current VIN = V

A9 Input Load Current V
Output Leakage Current V

CC

OUT

VCC Read Current (Note 1) CE# = V
VCC Write Current (Notes 2, 3) CE# = V
V

Standby Current

CC

(CE# Controlled)
V

Standby Current

CC

(RESET# Controlled)
Input Low Level –0.5 0.8 V

IL

CE# = V

V

CC

Input High Level 2.0 V
Voltage for Autoselect and Sector

Protect

V

CC

Output Low Voltage IOL = 12 mA, V
Output High Level IOH = –2.5 mA V
Low VCC Lock-out Vo ltag e 3.2 4.2 V

to VCC, V

SS

= V

Max, A9 = 12.0 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

, RESET# = V

IH

= V

Max, RESET# = V

CC

= VCC Max

CC

= VCC Max

CC

IH

IH

IH

IL

1.0 µA

±

1.0 µA

±

30 40 mA
40 60 mA

0.4 1.0 mA

0.4 1.0 mA

+ 0.5 V

CC

= 5.0 V 11.5 12.5 V

= V

CC

Min 0.45 V

CC

= V

CC

Min 2.4 V

CC

CMOS Compatible

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

Input Load Current VIN = V

LI

A9 Input Load Current V
Output Leakage Current V
V

Read Current (Note 1) CE# = V

CC

V

Write Current (Notes 2, 3) CE# = V

CC

V

Standby Current

CC

(CE# Controlled)
V

Standby Current

CC

(RESET# Controlled)
Input Low Level –0.5 0.8 V

IL

Input High Level 0.7x V

IH

Voltage for Autoselect

ID

and Sector Protect
Output Low Voltage IOL = 12 mA, V

OL

Output High Voltage

Low V

Lock-out Voltage 3.2 4.2 V

CC

CC

OUT

CE# = V
RESET# = V

RESET# = V

V

CC

I

OH

IOH = –100 µA, V

V
V
V

I
I

I

CC1

I

CC2

I

CC3

I

CC4

V

V
V

V

I

LIT

LO

OH1
OH2

LKO

Notes for DC Characteristics (both tables):

1. The I

2. I

current is typically less than 1 mA/MHz, with OE# at VIH.

CC

active while Embedded Program or Embedded Erase algorithm is in progress.

CC

3. Not 100% tested.

to VCC, V

SS

= V

Max, A9 = 12.0 V 50 µA

CC

= V

to VCC, V

SS

OE# = V

IL,

OE# = V

IL,

0.5 V,

±

CC

CC

SS

= V

CC

= V

CC

Max

CC

Max

30 40 mA
30 40 mA

15µA

CC

CC

IH

IH

0.5 V

±

0.5 V 1 5 µA

±

1.0 µA

±

1.0 µA

±

V

+ 0.3 V

CC

= 5.0 V 11.5 12.5 V

= V

CC

= –2.5 mA, V

Min 0.45 V

CC

= V

CC
CC

Min 0.85 V

CC

= V

Min VCC – 0.4 V

CC

CC

V

Am29F032B 23

TEST CONDITIONS

Device

Under

Test

C

L

6.2 k

5.0 V

2.7 k

Ω

Ω

Output Load 1 TTL gate
Output Load Capacitance, C

(including jig capacitance)
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V

Table 7. Test Specifications

Test Condition -75 All others Unit

L

30 100 pF

Note: Diodes are IN3064 or equivalent

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 0.8 V

1.5 2.0 V

24 Am29F032B

AC CHARACTERISTICS
Read-only Operations

Parameter Symbol

Parameter Description

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

t

ACC

t
t

Read Cycle Time (Note 1) Min 70 90 120 150 ns

RC

Address to Output Delay

Chip Enable to Output Delay OE# = VILMax 70 90 120 150 ns

CE

Output Enable to Output Delay Max 40 40 50 55 ns

OE

Read Min 0 ns

t

OEH

Output Enable Hold
Time (Note 1)

Toggle and
Data# Polling

t

EHQZ

t

GHQZ

t

AXQX

t

t

t

t

Ready

Chip Enable to Output High Z

DF

(Note 1)
Output Enable to Output High Z

DF

(Note 1)
Output Hold Time From Addresses CE#

OH

or OE# Whichever Occurs First
RESET# Pin Low to Read Mode

(Note 1)

Notes:

1. Not 100% tested.

2. Refer to Figure 8 and Table 7 for test specifications.

CE# = V
OE# = V

Test

Setup

Speed Options

IL

Max 70 90 120 150 ns

IL

Min 10 ns

Max20203035ns

Max20203035ns

Min 0 ns

Max 20 µs

UnitJEDEC Std -75 -90 -120 -150

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

t

RC

Addresses Stable

t

ACC

t

OE

t

OEH

t

CE

HIGH Z

Output Valid

Figure 9. Read Operation Ti mi ng s

t

DF

t

OH

HIGH Z

Am29F032B 25

AC CHARACTERISTICS
Hardware Reset (RESET#)

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

t

RESET# Pin Low (During Embedded

READY

Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded

READY

Algorithms) to Read or Write (See Note)
RESET# Pulse Width Min 500 ns

t

RP

RESET# High Time Before Read (See Note) Min 50 ns

t

RH

RY/BY# Recovery Time Min 0 ns

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

RY/BY#

CE#, OE#

RESET#

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

t

RP

Figure 10. RESET# Timings

t

RB

26 Am29F032B

AC CHARACTERISTICS
Write (Erase/Program) Operations

Parameter

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHWL

t

WHWH1

t

WHWH2

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

WHWH1

t

WHWH2

t

VCS

t

BUSY

Speed Options

Parameter Description

UnitJEDEC Std -75 -90 -120 -150

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 45 50 50 ns
Data Hold Time Min 0 ns
Read Recover Time Before Write

(OE# high to WE# low)

Min 0 ns

CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 40 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

Sector Erase Operation (Note 2)

Max 8 sec
VCC Set Up Time (Note 1) Min 50 µs
WE# to RY/BY# Valid Min 40 40 50 60 ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Am29F032B 27

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

CH

OE#

t

WP

WE#

t

WPH

t

DH

Data

t

CS

t

DS

A0h

RY/BY#

t

VCS

V

CC

Note: PA = program address, PD = program data, D

Figure 11. Program Operation Timings

Read Status Data (last two cycles)

t

AS

PA PA

t

AH

t

PD

t

BUSY

is the true data at the program address.

OUT

PA

WHWH1

Status

D

OUT

t

RB

28 Am29F032B

AC CHARACTERISTICS

t

AS

555h for chip erase

t

AH

Addresses

t

WC

2AAh SA

CE#

t

t

WP

t

DS

55h

t

CH

DH

t

WPH

30h

10 for Chip Erase

OE#

WE#

Data

t

CS

RY/BY#

t

VCS

V

CC

Note: SA = Sector Address. VA = Valid Address for reading status data.

Figure 12. Chip/Sector Erase Operation Timings

t

BUSY

t

WHWH2

VA

In

Progress

VA

Complete

t

RB

Am29F032B 29

AC CHARACTERISTICS

Addresses

CE#

t

CH

OE#

t

WE#

DQ7

OEH

t

ACC

t

RC

VA

t

CE

t

OE

t

DF

t

OH

Complement

VA VA

Complement

True

Valid Data

High Z

DQ0–DQ6

t

BUSY

Status Data

Status Data

True

Valid Data

High Z

RY/BY#

Note:

V A = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 13. Data# Polling Timings (During Embedded Algorithms)

t

RC

Addresses

CE#

OE#

WE#

DQ6/DQ2

RY/BY#

t

CH

t

BUSY

t

OEH

High Z

t

ACC

VA

t

CE

t

OE

t

DF

t

OH

(first read) (second read) (stops toggling)

VA VA

Valid Status

VA

Valid DataValid StatusValid Status

Note:

V A = Valid address; not required f or DQ6. Illustration shows first two status cycle after command sequence, last status read cycl e,
and array data read cycle.

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

30 Am29F032B

AC CHARACTERISTICS

Enter

Embedded

Erasing

WE#

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

DQ6

DQ2

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.

Figure 15. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

t

VID Rise and Fall Time (See Note) Min 500 ns

VIDR

RESET# Setup Time for Temporary Sector

t

RSP

Unprotect

Min 4 µs

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

12 V

0 or 5 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Figure 16. Temporary Sector Group Unprotect Timings

t

VIDR

0 or 5 V

Am29F032B 31

AC CHARACTERISTICS

Write (Erase/Program) Operations—Alternate CE# Controlled Writes

Parameter Symbol

Parameter Description

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WHWH1

t

WC

t

AS

t

AH

t

DS

t

DH

t

GHEL

t

WS

t

WH

t

CP

t

CPH

t

WHWH1

Write Cycle Time (Note 1) Min 70 90 120 150 ns
Address Setup Time Min 0 ns
Address Hold Time Min 40 45 50 50 ns
Data Setup Time Min 40 45 50 50 ns
Address Hold Time Min 0 ns
Read Recover Time Before Write Min 0 ns
CE# Setup Time Min 0 ns
CE# Hold Time Min 0 ns
Write Pulse Width Min 40 45 50 50 ns
Write Pulse Width High Min 20 ns
Byte Programming Operation (Note 2) Typ 7 µs

Typ 1 sec

t

WHWH2

t

WHWH2

Sector Erase Operation (Note 2)

Max 8 sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Speed Options

UnitJEDEC Std -75 -90 -120 -150

32 Am29F032B

AC CHARACTERISTICS

555 for program
2AA for erase

PA for program
SA for sector erase
555 for chip erase

Data# Polling

Addresses

WE#

OE#

CE#

Data

RESET#

RY/BY#

PA

t

WC

t

WH

t

WS

t

RH

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

BUSY

PD for program
30 for sector erase
10 for chip erase

t

WHWH1 or 2

DQ7# D

OUT

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. Alternate CE# Controlled Write Operation Timings

= Array Data.

OUT

Am29F032B 33

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 se c
Chip Erase Time 64 sec
Byte Programming Time 7 300 µs

Chip Programming Time (Note 3) 28.8 86.4 sec

Excludes 00h programming prior to
erasure (Note 4)

Excludes system-level overhead
(Note 5)

Notes:

°

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 4.5 V, 1,000,000 cycles (4.75 V for -75).

CC

3. The typical chip programming time is considerably less than the maximum chi p prog r amming time list ed, si nce most b yt es
program faster than the maxi mum by te progr am time listed. If the maxim um byte program ti me giv en is e xceeded, only then does
the device set DQ5 = 1. See t he sect ion on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all b yt es are prog r ammed to 00h before erasure.

5. System-level over head is the t ime r equired to execute the four-bus-cycle se quence for programming. See Table 5 for further
information on command definitions .

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

Description Min Max

Input Voltage with respect to V

Current –100 mA +100 mA

V

CC

on I/O pins –1.0 V VCC + 1.0 V

SS

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

C

C

OUT

C

IN2

Input Capacitance VIN = 0 6 7.5 pF

IN

Output Capacitance V

= 0 8.5 12 pF

OUT

Control Pin Capacitance VIN = 0 7.5 9 pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

34 Am29F032B

PHYSICAL DIMENSIONS

SO 044–44-Pin Small Outline Package

Dwg rev AC; 10/99

Am29F032B 35

PHYSICAL DIMENSIONS
TS 040–40-Pin Standard Thin Small Outline Package

36 Am29F032B

Dwg rev AA; 10/99

PHYSICAL DIMENSIONS
TSR040–40-Pin Reversed Thin Small Outline Package

Dwg rev AA; 10/99

Am29F032B 37

REVISION SUMMARY
Revision A (June 1998)

Initial release.

Revision B (July 1998)

Distinctive Characteristics

Changed typical active read current to 30 mA to match
DC Characteristics table.

Operating Ranges

Corrected temperature range descriptions to “ambi­ent.”

Revision C (January 1999)

Distinctive Characteristics

Added 20-year data retention subbullet.

Revision C+1 (April 14, 1999)

Deleted duplicate sections in the full data sheet.

Data Retention

Added table.

Revision D (November 17, 1999)

AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations

Deleted t
high.

Physical Dimensions

Replaced figures with more detailed illustrations.

and changed OE# waveform to star t at

GHWL

Revision D+1 (December 5, 2000)

Added table of contents.

Ordering Information

Deleted burn-in option.

Trademarks

Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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