AMD Am29F032B Service Manual
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Am29F032B
32 Megabit (4 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
■ Manufactured on 0.32 µm process technology
■ High performance
— Access times as fast as 70 ns
■ Low power consumption
— 30 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current (standard access
time to active mode)
■ Flexible sector arc hitecture
— 64 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
— A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
— Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■ Minimum 1,000,000 write/erase cycles
guaranteed
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
— 40-pin TSOP
— 44-pin SO
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase cycle completion
■ Ready/Busy output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■ Erase Suspend/Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■ Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.
Publication# 21610 Rev: D Amendment/+1
Issue Date: December 5, 2000
GENERAL DESCRIPTION
The Am29F032B is a 32 Mbit, 5.0 volt-only Flash
memory or ganized as 4,19 4,304 bytes of 8 bits e ach.
The 4 Mbytes of data are divided into 64 sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F032B is offered
in 40-pin TSOP and 44-pin SO packages. The
Am29F032B is manufactured using AMD’s 0.32 µm
process technology. This device is designed to be programmed in-system with the standard s ystem 5.0 volt
supply. A 12.0 volt VPP is not required for program
V
CC
or erase operations. The device can also be programmed in standard EPROM programmers.
The standard device offers access tim es of 70, 90,
120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#),
write enable (WE#), and output enable (OE#) controls.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state machine that controls the erase and programming circuit ry. Write cycles
also internally latch addresses and data needed for
the programming and erase operations. Reading data
out of the device is similar to reading from 12.0 volt
Flash or EPROM devices.
The device is programmed by executing the program
command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The device is e rased by executing
the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that
automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other s ectors. A sector is typically
erased and verified within one second. The device is
erased when shipped from the factory.
The hardware sector group protection feature disables
both program and erase operations in an y combination
of the eight sector groups of memory. A sector group
consists of four adjacent sectors.
The Erase Suspend feature enables the system to put
erase on hold for any period of time to read data from,
or program data to, a sector that is not being erased.
True background erase can thus be achieved.
The device requires only a s ingle 5.0 v olt p o wer supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. A low V
detector automati-
CC
cally inhibits write operations during power transitions.
The host system can detect whether a program or
erase cycle is complete by using the RY/BY# pin, the
DQ7 (Data# Polling) or DQ6 (toggle) status bits. After
a program or erase cycle has been completed, the device automatically returns to the read mode.
A hardware RESET# pin terminates any operation in
progress. The internal state machine is reset to the
read mode. The RESET# pin may be tied to the system reset circuitry. Therefore, if a system reset occurs
during either an Embedded Program or Embedded
Erase algorithm, the device is au tom at ic al ly re se t t o t he
read mode. This enables the system’s microprocessor
to read the boot-up firmware from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of qu ality, reliab ility, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at
a time using the programming mechanism of hot
electron injection.
2 Am29F032B
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F032B Device Bus Operations.................................. 8
Requirements for Reading Array Data............. ........................ 8
Writing Commands/Command Sequences ....................... .. .. .. . 8
Program and Erase Operation Status ...................................... 9
Standby Mode ............................. ..................................... ........ 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode................................................................ 9
Table 2. Am29F032B Sector Address Table............................. ...... 10
Autoselect Mode..................................................................... 11
Table 3. Am29F032B Autoselect Codes......................................... 11
Sector Group Protection/Unprot ection................... ................. 12
Table 4. Sector Group Addresses ................................................... 12
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Temporary Sector Group Unprotect Operation................ 12
Hardware Data Protection...................................................... 13
Low VCC Write Inhibit..................................................................... 13
Write Pulse “Glitch” Protection........................................................ 13
Logical Inhibit........... ...... ... ..... ......... ....... ....... .... ..... ....... ......... ....... .. 13
Power-Up Write Inhibit.................................................................... 13
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data.............. .................................................. 13
Reset Command..................................................................... 13
Autoselect Command Sequence............................................ 14
Byte Program Command Sequence... .............................. ...... 14
Chip Erase Command Sequence........................................... 14
Figure 2. Program Operation.......................................................... 15
Sector Erase Command Sequence........................................ 15
Erase Suspend/Erase Resume Commands..... .. ................. .. . 15
Figure 3. Erase Operation............................................................... 16
Command Definitions ............................................................. 17
Table 5. Am29F032B Command Definitions................................... 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18
DQ7: Data# Polling................................................................. 18
Figure 4. Data# Polling Algorithm ................................................... 18
RY/BY#: Ready/Busy# ........................................................... 19
DQ6: Toggle Bit I.................................................................... 19
DQ2: Toggle Bit II ................................................................... 19
Reading Toggle Bits DQ6/DQ2 .............................................. 19
DQ5: Exceeded Timing Limits................................................ 20
DQ3: Sector Erase Timer ....................................................... 20
Figure 5. Toggle Bit Algorithm........................................................ 20
Table 6. Write Operation Status ..................................................... 21
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negat ive Overshoot Wav eform...................... 22
Figure 7. Maximum Positive Overshoot Waveform........................ 22
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
TTL/NMOS Compatible .......................................................... 23
CMOS Compatible.................................................................. 23
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup...................................................................... 24
Table 7. Test Specifications........................................................... 24
Key To Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Read-only Operations............................................................. 25
Figure 9. Read Operation Timings................................................. 25
Hardware Reset (RESET#) .................................................... 26
Figure 10. RESET# Timings.......................................................... 26
Write (Erase/Program) Operations......................................... 27
Figure 11. Program Operation Timings.......................................... 28
Figure 12. Chip/Sector Erase Operation Timings .......................... 29
Figure 13. Data# Polling Timings (During Embedded Algorithms). 30
Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 30
Figure 15. DQ2 vs. DQ6................................................................. 31
Temporary Sector Unprotect.................................................. 31
Figure 16. Temporary Sector Group Unprotect Timings................ 31
Write (Erase/Program) Operations—Alter nate CE#
Controlled Writes.................................................................... 32
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33
Erase And Programming Performance . . . . . . . 34
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34
TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35
SO 044–44-Pin Small Outline Package.................................. 35
TS 040–40-Pin Standard Thin Small Outline Package........... 36
TSR040–40-Pin Reversed Thin Small Outline Package........ 37
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision A (June 1998) .......................................................... 38
Revision B (July 1998)............................................................ 38
Revision C (January 1999)..................... ................................ 38
Revision C+1 (April 14, 1999)................................................. 38
Revision D (November 17, 1999) ........................................... 38
Revision D+1 (December 5, 2000)......................................... 38
Am29F032B 3
PRODUCT SELECTOR GUIDE
Family Part Number Am29F032B
= 5.0 V ± 5% -75
V
Speed Options
Max access time, ns (t
ACC
Max CE# access time, ns (t
Max OE# access time, ns (t
CC
= 5.0 V ± 10% -90 -120 -150
V
CC
) 70 90 120 150
) 70 90 120 150
CE
) 40405075
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0
–
DQ7
V
CC
V
SS
RY/BY#
RESET#
WE#
CE#
OE#
A0–A21
State
Control
Command
Register
VCC Detector
PGM Voltage
Generator
Timer
Sector Switches
Erase Voltage
Generator
STB
Chip Enable
Output Enable
Y-Decoder
X-Decoder
Address Latch
STB
Input/Output
Buffers
Data
Latch
Y-Gating
Cell Matrix
4 Am29F032B
CONNECTION DIAGRAMS
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
RESET#
A11
A10
A20
A21
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
V
V
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC
CC
SS
SS
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
CC
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
40-Pin Reverse TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
A21
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
V
SS
V
SS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V
CC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
V
V
SS
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
SO
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
CC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
A21
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V
CC
Am29F032B 5
PIN CONFIGURATION
A0–A21 = 22 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
= +5.0 V single power supply
V
CC
V
SS
NC = Pin Not Connected Internally
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
= Device Ground
LOGIC SYMBOL
22
A0–A21
CE#
OE#
WE#
RESET# RY/BY#
8
DQ0–DQ7
6 Am29F032B
ORDERING INFORMATION
Standard Pr od ucts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F032B -75 E I
DEVICE NUMBER/DESCRIPTION
Am29F032B
32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40
E = Extended (–55
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
°C to +85°C)
°C to +125°C)
Valid Combinations
AM29F032B-75 EC, EI, FC, FI, SC, SI
AM29F032B-90
AM29F032B-120
AM29F032B-150
EC, EI, EE, FC, FI, FE,
SC, SI, SE
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Cons ult the loc al AM D sale s office to confirm availab ility of specific valid com binations and
to check on newly released combinations.
Am29F032B 7
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register itself does not occupy any addressable memory location. The register is composed of l atches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1. Am29F032B Device Bus Operations
Operation CE# OE # WE# RESET# A0–A21 DQ0–DQ7
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.
Read L L H H A
Write L H L H A
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z
TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect
(See Note)
Legend:
L = Logic Low = V
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D
IL
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
. CE# is the power
IL
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at V
.
IH
The internal state machine is set for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specifi cation for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
XXX V
ID
sectors of memory), the system must drive WE# and
CE# to V
, and OE# to VIH.
IL
An erase operation can erase one sect or, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required to uniquely select a secto r. See the “Writing
specific address and data commands or sequences
into the command register initiates device operations.
The Command Defin itions table define s the valid register command sequences. Writing incorrect address
and data values or writing them in the improper sequence resets the device to reading array data.” section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system wr ites the autosele ct comman d sequence, the device enters the autoselect m ode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.
in the DC Characteristics table represents the ac-
I
CC2
tive current specification for the write mode. The “AC
OUT
IN
IN
A
IN
= Data Out, AIN = Address In
D
OUT
D
IN
D
IN
cludes programming data to the device and erasing
8 Am29F032B
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “The Erase Resume
command is valid only dur ing the Erase Suspend
mode.” for more information, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restricted voltage rang e than V
± 0.5 V. (Note
CC
IH
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t
CE
. The device re-
IH
) for read a ccess when
the device is in either of these standb y modes, bef ore it
is ready to read data.
The device also enters the standb y mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Ch aracteristics tables, I
represents the
CC3
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a har dware method of resetting the device to readi ng arr ay data. When the system
drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
, the device enters
IL
the TTL standby mode; if RESET# is held at V
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operatio n is complete, which requires a
.)
time of t
(during Embedded Algorithms). The sys-
READ Y
tem can thus monitor RY/BY# to determine whether the
reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a tim e of t
rithms). The system can read data t
SET# pin returns to V
(not during Embedded Algo-
READY
.
IH
RH
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the devi ce is
disabled. The output pins are placed in t he high impedance state.
RP
SS
after the RE-
,
±
Am29F032B 9
Table 2. Am29F032B Sector Address Table
Sector A21 A20 A19 A18 A17 A1 6 Sector Size Address Range
SA0 0 0 0 0 0 0 64K 000000h–00FFFFh
SA1 0 0 0 0 0 1 64K 010000h–01FFFFh
SA2 0 0 0 0 1 0 64K 020000h–02FFFFh
SA3 0 0 0 0 1 1 64K 030000h–03FFFFh
SA4 0 0 0 1 0 0 64K 040000h–04FFFFh
SA5 0 0 0 1 0 1 64K 050000h–05FFFFh
SA6 0 0 0 1 1 0 64K 060000h–06FFFFh
SA7 0 0 0 1 1 1 64K 070000h–07FFFFh
SA8 0 0 1 0 0 0 64K 080000h–08FFFFh
SA9 0 0 1 0 0 1 64K 090000h–09FFFFh
SA10 0 0 1 0 1 0 64K 0A0000h–0AFFFFh
SA11 0 0 1 0 1 1 64K 0B0000h–0BFFFFh
SA12 0 0 1 1 0 0 64K 0C0000h–0CFFFFh
SA13 0 0 1 1 0 1 64K 0D0000h–0DFFFFh
SA14 0 0 1 1 1 0 64K 0E0000h–0EFFFFh
SA15 0 0 1 1 1 1 64K 0F0000h–0FFFFFh
SA16 0 1 0 0 0 0 64K 100000h–10FFFFh
SA17 0 1 0 0 0 1 64K 110000h–11FFFFh
SA18 0 1 0 0 1 0 64K 120000h–12FFFFh
SA19 0 1 0 0 1 1 64K 130000h–13FFFFh
SA20 0 1 0 1 0 0 64K 140000h–14FFFFh
SA21 0 1 0 1 0 1 64K 150000h–15FFFFh
SA22 0 1 0 1 1 0 64K 160000h–16FFFFh
SA23 0 1 0 1 1 1 64K 170000h–17FFFFh
SA24 0 1 1 0 0 0 64K 180000h–18FFFFh
SA25 0 1 1 0 0 1 64K 190000h–19FFFFh
SA26 0 1 1 0 1 0 64K 1A0000h–1AFFFFh
SA27 0 1 1 0 1 1 64K 1B0000h–1BFFFFh
SA28 0 1 1 1 0 0 64K 1C0000h–1CFFFFh
SA29 0 1 1 1 0 1 64K 1D0000h–1DFFFFh
SA30 0 1 1 1 1 0 64K 1E0000h–1EFFFFh
SA31 0 1 1 1 1 1 64K 1F0000h–1FFFFFh
SA32 1 0 0 0 0 0 64K 200000h–20FFFFh
SA33 1 0 0 0 0 1 64K 210000h–21FFFFh
SA34 1 0 0 0 1 0 64K 220000h–22FFFFh
SA35 1 0 0 0 1 1 64K 230000h–23FFFFh
SA36 1 0 0 1 0 0 64K 240000h–24FFFFh
SA37 1 0 0 1 0 1 64K 250000h–25FFFFh
SA38 1 0 0 1 1 0 64K 260000h–26FFFFh
SA39 1 0 0 1 1 1 64K 270000h–27FFFFh
SA40 1 0 1 0 0 0 64K 280000h–28FFFFh
SA41 1 0 1 0 0 1 64K 290000h–29FFFFh
SA42 1 0 1 0 1 0 64K 2A0000h–2AFFFFh
SA43 1 0 1 0 1 1 64K 2B0000h–2BFFFFh
10 Am29F032B
Table 2. Am29F032B Sector Address Table (Continued)
Sector A21 A20 A19 A18 A17 A16 Sector Size Address Range
SA44 1 0 1 1 0 0 64K 2C0000h–2CFFFFh
SA45 1 0 1 1 0 1 64K 2D0000h–2DFFFFh
SA46 1 0 1 1 1 0 64K 2E0000h–2EFFFFh
SA47 1 0 1 1 1 1 64K 2F0000h–2FFFFFh
SA48 1 1 0 0 0 0 64K 300000h–30FFFFh
SA49 1 1 0 0 0 1 64K 310000h–31FFFFh
SA50 1 1 0 0 1 0 64K 320000h–32FFFFh
SA51 1 1 0 0 1 1 64K 330000h–33FFFFh
SA52 1 1 0 1 0 0 64K 340000h–34FFFFh
SA53 1 1 0 1 0 1 64K 350000h–35FFFFh
SA54 1 1 0 1 1 0 64K 360000h–36FFFFh
SA55 1 1 0 1 1 1 64K 370000h–37FFFFh
SA56 1 1 1 0 0 0 64K 380000h–38FFFFh
SA57 1 1 1 0 0 1 64K 390000h–39FFFFh
SA58 1 1 1 0 1 0 64K 3A0000h–3AFFFFh
SA59 1 1 1 0 1 1 64K 3B0000h–3BFFFFh
SA60 1 1 1 1 0 0 64K 3C0000h–3CFFFFh
SA61 1 1 1 1 0 1 64K 3D0000h–3DFFFFh
SA62 1 1 1 1 1 0 64K 3E0000h–3EFFFFh
SA63 1 1 1 1 1 1 64K 3F0000h–3FFFFFh
Note: All sectors are 64 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection v erifica-
tion, through ide ntifier codes output on DQ7–DQ0.
This mode is primar ily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect cod es can also be
accessed in-system through the command register .
When using programming equipment, the autoselect
mode requires V
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector group pro-
Description A21-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0
Manufacturer ID: AMD X X V
Device ID: Am29F032B X X V
Sector Group Protection
Verification
(11.5 V to 12.5 V) on address pin
ID
Table 3. Am29F032B Autoselect Codes
Sector
Group
Address
XV
ID
ID
ID
tection, the sect or group a ddress mus t appear on the
appropriate highest order address bits (see Table 4).
Table 3 also shows the remaining address bits that are
don’t care. When all necessary bits have been set as
required, the programming equipment may then read
the corresponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command re gister, as shown in Table 5. This meth od
does not require V
on an address line. Refer to the
ID
Autoselect Command Sequence section for more information.
Identifier Code on
DQ7-DQ0
XVILXVILV
XVILXVILV
XVILXVIHV
IL
IH
IL
01h
41h
01h (protected)
00h (unprotected)
Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit.
Am29F032B 11
Sector Group Protection/Unprotection
The hardware sector group protection feature disables
both program and erase operations in any sector
group. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group contains. The hardware sector group unprotection feature
re-enables both program and erase operations in previously protected sector groups.
Sector grou p pr otection/unprotection must be implemented using pr ogramming equipm ent. The procedure requires a high voltage (V
and the control pins. Details on this method are provided in a supplement, publication number 22184.
Contact an AMD representative to obtain a copy of the
appropriate document.
The device is shipped with all sector groups unprotected. AMD offers t he optio n of prog r amming a nd protecting sector groups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector gr oup is
protected or unprotected. See “Autoselect Mode” for
details.
) on address pin A9
ID
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activat ed by
setting the RESET# pin to V
ing this mode, f ormerly protected se ctor g roups c an be
programmed or erased by selecting the sector group
addresses. Once V
is removed from the RESET#
ID
pin, all the previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
Figure 16 shows the timing diagrams, for this feature.
Perform Erase or
Program Operations
(11.5 V – 12.5 V). Dur-
ID
START
RESET# = V
(Note 1)
RESET# = V
ID
IH
Table 4. Sector Group Addresses
Sector
Group A21 A20 A19 A18 Sectors
–
SGA00000SA0
SGA10001SA4
SGA2 0 0 1 0 SA8
SGA3 0 0 1 1 SA12
SGA4 0 1 0 0 SA16
SGA5 0 1 0 1 SA20
SGA6 0 1 1 0 SA24
SGA7 0 1 1 1 SA28
SGA81000SA32–SA35
SGA9 1 0 0 1 SA36–SA39
SGA10 1 0 1 0 SA40–SA43
SGA11 1 0 1 1 SA44–SA47
SGA12 1 1 0 0 SA48–SA51
SGA13 1 1 0 1 SA52–SA55
SGA14 1 1 1 0 SA56–SA59
SGA15 1 1 1 1 SA60–SA63
SA3
–
SA7
–
SA11
–
SA15
–
SA19
–
SA23
–
SA27
–
SA31
Temporary Sector Group
Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1. Temporary Sector Group Unprotect
Operation
12 Am29F032B
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