Datasheet AM29F016B-90SIB, AM29F016B-90SI, AM29F016B-90SEB, AM29F016B-90SE, AM29F016B-90SCB Datasheet (AMD Advanced Micro Devices)

PRELIMINARY

Publication# 21444 Rev: B Amendment/+2
Issue Date: April 1998

Am29F016B

16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F016 device

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector architecture

— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:

A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group

Temporary Sector Group Unprotect allows code
changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 progr am/erase cycles per

sector guaranteed

■ Package options

— 48-pin and 40-pin TSOP
— 44-pin SO

■ Compatible with JEDEC standards

— Pinout and software c ompatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

— Provides a hardware method f or detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase oper ation to read da ta

from, or program data to, a non-erasing sector,
then resumes the erase operation

■ Hardware reset p in (RESET#)

— Resets internal state machine to the read mode

2 Am29F016B

PRELIMINARY

GENERAL DESCRIPTION

The Am29F016B is a 16 Mbit, 5.0 v olt-only Flash mem­ory organized as 2,097,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F016B is offered in
48-pin and 40-pin TSOP, and 44-pin SO packages.
This device is designed to be programmed in-s ystem
with the standard system 5.0 volt V

CC

supply. A 12.0

volt V

PP

is not required for program or erase
operations. The device can also be programmed in
standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the f eatures and ben­efits of the Am29F016, which was m anufactured using

0.5 µm process technology.
The standard device of fers access t imes of 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to
operate without wait states. To elim inate bus conten ­tion, the device has separate c hip enable (CE#), write
enable (WE#), and output enable (OE#) controls.

The device requires only a si ngle 5.0 volt power sup-
ply for both read and w rite functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set c ompatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con­trols the erase and programming circuitry. Write cycles
also internally latch addresses and data n eeded f o r the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already progr ammed)

before e xecutin g the erase operatio n. During erase, t he
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de vice is ready to read array data
or accept another command.

The sector erase ar chitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

CC

detector that automatically inhibits write opera­tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any com bination of the sectors of mem­ory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin ma y be t ied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.

Am29F016B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

Family Part Number Am29F016B
Speed Options (V

CC

= 5.0 V ± 10%) -70 -90 -120 -150
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 40 40 50 75

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

Register

V

CC

V

SS

WE#

CE#
OE#

STB

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A20

21444B-1

4 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

NC

RESET#

A11
A10

A9
A8
A7
A6
A5
A4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3

40-Pin Standard TSOP

21444B-2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

40-Pin Reverse TSOP

Am29F016B 5

PRELIMINARY

CONNECTION DIAGRAMS (continued)

1

24

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

NC

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

NC

RESET#

A11
A10

A9
A8
A7
A6
A5
A4

NC

48

25

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

NC

NC

NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC

48-Pin Standard TSOP

21444B-4

1

24

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

NC

NC

NC

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

NC

48

25

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

NC

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC

48-Pin Reverse TSOP

21444B-5

6 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

PIN CONFIGURATION

A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
V

CC

= +5.0 V single power supply

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

V

SS

= Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

NC

RESET#

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

A3

A2

A1

A0

DQ0
DQ1
DQ2
DQ3

V

SS

V

SS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

CC

CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

SO

21444B-6

21

8

DQ0–DQ7

A0–A20

CE#
OE#

WE#
RESET# RY/BY#

21444B-7

Am29F016B 7

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be support­ed in volume for this device. Cons ult the loc al AM D sale s of­fice to confirm availab ility of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DE SCR IP TIO N

Am29F016B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sec tor Era se Flash Mem or y

5.0 V Read, Program, and Erase

Am29F016B -70 E I

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40 °C to +85 °C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)

E4 = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F4 = 40-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TS R0 40)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

Am29F016B-70

EC, EI, FC, FI,
E4C, E4I, F4C, F4I, SC, SI

Am29F016B-90

EC, EI, EE, FC, FI, FE
E4C, E4I, E4E, F4C, F4I,
F4E, SC, SI, SE

Am29F016B-120
Am29F016B-150

8 Am29F016B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Table 1. Am29F016B Device Bus Operations

Legend:

L = Logic Low = V

IL

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

OUT

= Data Out, AIN = Address In

Note:

See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

IL

. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

IH

.

The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

CC1

in the DC Characteristics

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

IL

, and OE# to VIH.

An erase operation can erase one sect or, multiple sec­tors, or the entire de vice. The Sector Address Tables in­dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

I

CC2

in the DC Characteristics table represents the ac­tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

Read L L H H A

IN

D

OUT

Write L H L H A

IN

D

IN

CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect

(See Note)

XXX V

ID

A

IN

D

IN

Am29F016B 9

PRELIMINARY

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V

CC

± 0.5 V. (Note

that this is a more restrict ed voltage range than V

IH

.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V

IH

. The device re­quires standard access time (tCE) for read access when
the device is in either of these standb y modes, bef ore it
is ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program ­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

CC3

represents the
standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system
drives the RESET# pin low for at least a period of t

RP

,

the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

IL

, the device enters

the TTL standby mode; if RESET# is held at V

SS

±

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a
time of t

READY

(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t

READY

(not during Embe dded Algo-

rithms). The system can read data t

RH

after the RE-

SET# pin returns to V

IH

.

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

10 Am29F016B

PRELIMINARY

Table 2. Sector Address Table

Note: All sectors are 64 Kbytes in size.

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh
SA1 0 0 0 0 1 010000h-01FFFFh
SA2 0 0 0 1 0 020000h-02FFFFh
SA3 0 0 0 1 1 030000h-03FFFFh
SA4 0 0 1 0 0 040000h-04FFFFh
SA5 0 0 1 0 1 050000h-05FFFFh
SA6 0 0 1 1 0 060000h-06FFFFh
SA7 0 0 1 1 1 070000h-07FFFFh
SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh
SA10 0 1 0 1 0 0A0000h-0AFFFFh
SA11 0 1 0 1 1 0B0000h-0BFFFFh
SA12 0 1 1 0 0 0C0000h-0CFFFFh
SA13 0 1 1 0 1 0D0000h-0DFFFFh
SA14 0 1 1 1 0 0E0000h-0EFFFFh
SA15 0 1 1 1 1 0F0000h-0FFFFFh
SA16 1 0 0 0 0 100000h-10FFFFh
SA17 1 0 0 0 1 110000h-11FFFFh
SA18 1 0 0 1 0 120000h-12FFFFh
SA19 1 0 0 1 1 130000h-13FFFFh
SA20 1 0 1 0 0 140000h-14FFFFh
SA21 1 0 1 0 1 150000h-15FFFFh
SA22 1 0 1 1 0 160000h-16FFFFh
SA23 1 0 1 1 1 170000h-17FFFFh
SA24 1 1 0 0 0 180000h-18FFFFh
SA25 1 1 0 0 1 190000h-19FFFFh
SA26 1 1 0 1 0 1A0000h-1AFFFFh
SA27 1 1 0 1 1 1B0000h-1BFFFFh
SA28 1 1 1 0 0 1C0000h-1CFFFFh
SA29 1 1 1 0 1 1D0000h-1DFFFFh
SA30 1 1 1 1 0 1E0000h-1EFFFFh
SA31 1 1 1 1 1 1F0000h-1FFFFFh

Am29F016B 11

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

ID

(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addi­tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Defini­tions table. This method does not require V

ID

. See
“Command Definitions” for details on using the autose­lect mode.

Table 3. Am29F016B Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Group Protection/Unprotection

The hardware sector group protection feature dis­ables both program and erase operations in any sec­tor gr o u p. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group con­tains. The hardware sector group unprotection fea­ture re-enables both program and erase operations in
previously protected sector groups.

Sector group protection/unprotection must be imple­mented using programming equipment. The procedure
requires a high voltage (V

ID

) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 19613. Contact an
AMD representative to obtain a cop y of the appropriate
document.

The device is shipped with all sector grou ps unpro­tected. AMD offers t he optio n of prog r amming a nd pro­tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con­tact an AMD representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.

Table 4. Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V

ID

. During this mode,
formerly protected sector g roups can be programmed
or erased by selecting the sector group addresses.
Once V

ID

is removed from the RESET# pin, all the
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig­ure 16) shows the timing waveforms, for this feature.

Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0

Manufacturer ID:
AMD

LLH X X V

ID

XVILXVILV

IL

01h

Device ID:
Am29F016B

LLH X X VIDXVILXVILV

IH

ADh

Sector Group
Protection
Ve r ific atio n

LLH

Sector
Group

Address

XVIDXVILXVIHV

IL

01h (protected)

00h (unprotected)

Sector
Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0

–

SA3

SGA1 0 0 1 SA4

–

SA7

SGA2 0 1 0 SA8

–

SA11

SGA3 0 1 1 SA12

–

SA15

SGA4 1 0 0 SA16

–

SA19

SGA5 1 0 1 SA20

–

SA23

SGA6 1 1 0 SA24

–

SA27

SGA7 1 1 1 SA28

–

SA31

12 Am29F016B

PRELIMINARY

Figure 1. Temporary Sector Group Unprotect

Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V

CC

power-up and

power-down transitions, or from system noise.

Low V

CC

Write Inhibit

When V

CC

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

CC

is greater than V

LKO

. The system must provide the
proper signals to the control pins to prevent uninten­tional writes when V

CC

is greater than V

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#
= V

IL

, CE# = VIH or WE# = VIH. To initiate a write cy­cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL

and OE# = VIH during powe r
up, the device does not accept commands on the
rising edge of WE#. The inter nal state machine is
automatically reset to reading array data on
power-up.

START

Perform Erase or

Program Operations

RESET# = V

IH

Temporary

Sector Group Unprotect

Completed (Note 2)

RESET# = V

ID

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected
once again.

21444B-8

Am29F016B 13

PRELIMINARY

COMMAND DEFINITIONS

Writing specific addre ss and data commands or se­quences into the command register initiates device op­erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect

address and data values or writing them in the im-
proper sequence resets the device to reading array

data.
All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after comp leting an Embe dded Program or Em­bedded Erase algorithm.

After the device accepts an Er ase Suspend command,
the device enters the Erase Suspend m ode. The sys­tem can read array data using the standard read tim­ings, except that if it reads at an address within erase­suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once agai n read arra y
data with the same ex ception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.

The system

must

issue the reset command to re-en­able the dev ice f or reading arra y data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com­mand” section, next.

See also “Requirements for Reading Arr a y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame­ters, and Read Operation Tim ings diagram shows the
timing diagram.

Reset Command

Writing the reset command to the devi ce resets the de­vice to reading array data. Address bits are don’t care
for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig­nores reset commands until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the device to
reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, t he reset c ommand

must

be written to return to reading array data (also applies
to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read­ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect c ommand sequenc e allows the host
system to access the manufacturer and devices codes ,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an a lternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is in tended for PROM program­mers and requires V

ID

on address bit A9.

The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then en ters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.

A read cycle at address XX00h retrieves the manufac­turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Ad dr e ss ta bles for valid sector addres s es.

The system must write the reset command to exit the
autoselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro­gram command sequence is initiated by writing two un­lock write cycles, followed by the program set-up
command. The program address and data are wr itten
next, which in turn initiate the Embedded Program al­gorithm. The system is

not

required to provide further
controls or timings. The device automatically provides
internally generated program pulses and v erify the pro­grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.

When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation b y using DQ7,

14 Am29F016B

PRELIMINARY

DQ6, or RY/BY#. See “Write Operation Status” for in­formation on these status bits.

Any commands written to the device dur ing the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program­ming operation. The program command sequenc e
should be reinitiated once the de vi ce has reset t o read­ing array data, to ensure data integrity.

Programming is allowed in any sequence an d across
sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the op eration was suc­cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.

Note: See the appropriate Command Definitions table for
program command sequence.

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does

not

require the system to
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and verifies the entire
memory for an all zero data patter n prior to electr ical
erase. The system is not required to provide any con­trols or timings during these operations. The Command
Definitions table show s the address and data require­ments for the chip erase command sequence.

Any commands written to the chip during the Embed­ded Erase algorithm are ignored. Note that a ha rd ware
reset during the chip erase operation immediately ter­minates the operation. The Chip Erase command se­quence should be reinitiated once the device has
returned to reading array data, to ensure data int eg rity.

The system can deter mine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no long er latched.

Figure 3 illustrates the algorithm for the erase opera­tion. See the Erase/Program Operations tables in “AC
Characteristics” for p arameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un­lock cycles, followed by a set-up command. Two addi­tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command . The Command Definitions table
shows the address and data requirement s for the sec­tor erase command sequence.

The device does

not

require the system to preprogram
the memory prior to erase. The Embedded Erase algo­rithm automatically programs and verifies the s ector for
an all zero data pattern prior to electrical erase. The
system is not required to provide a ny controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sector s. The time be­tween these additional cycl es must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

No

Yes

Last Address?

No

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21444B-9

Am29F016B 15

PRELIMINARY

written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence

and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sec tor Erase
Timer” section.) The time-out be gins from the rising
edge of the final WE# pulse in the command sequence .

Once the sector erase operation has begun, onl y the
Erase Suspend command is valid. All other commands
are ignored. Note th at a hardware reset during the
sector erase operation immediately ter m inates the op­eration. The Sector Erase command sequence s hould
be reinitiated once the device has returned to reading
array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the
device returns to reading arra y data and addresses are
no longer latched. The system can determine the sta­tus of the erase operation b y usi ng DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa­tion on these status bits.

Figure 3 illustrates the algorithm for the erase opera­tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section f or par amet ers , and to
the Sector Erase Operations Ti ming diagr am for timing
waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the s yst em to in­terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only dur ing the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend comm and is ignored if written dur ing
the chip erase operation or Embedded Program algo­rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately ter minates the
time-out period and suspends the er ase oper at ion. Ad-

dresses are “don’t-cares” when writing the Erase Sus­pend command.

When the Erase Suspend command is written during a
sector erase operation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter­minates the time-out period and suspends the erase
operation.

After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasu re. (The de vice “er ase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec­tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.

After an erase-suspended program operation is com­plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper­ation. See “Write Operation Status” for more informa­tion.

The system may also write the autos elect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.

The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de­vice has resumed erasing.

16 Am29F016B

PRELIMINARY

Notes:

1. See the appropriate Command Definitions table for erase
command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

No

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21444B-10

Am29F016B 17

PRELIMINARY

Table 5. Am29F016B Command Definitions

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens
first.

SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.

SGA = Address of the sector group to be verified. Address
bits A20–A18 select a unique sec tor group.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus
cycles are write operations.

4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.

5. No unlock or command cycles required when reading
array data.

6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).

7. The fourth cycle of the autoselect command sequence is
a read cycle.

8. The data is 00h for an unprotected sector group and 01h
for a protected sector group. See “Autoselect Command
Sequence” for more information.

9. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.

10. The Erase Resume command is valid only during the
Erase Suspend mode.

Command
Sequence

(Note 1)

Bus Cycles (Notes 2–4)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0

Autoselect

(Note 7)

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 AD

Sector Group Protect
Verify (Note 8)

4 555 AA 2AA 55 555 90

SGA

X02

XX00

XX01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30

Cycles

18 Am29F016B

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de­scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for deter mining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, in dicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# P olling is v alid after the rising
edge of the final WE# pulse in the program or erase
command sequence.

During the Em bedded Program algor ithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 2 µs, then the device returns to reading

array data.
During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al­gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algor ithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” o r
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in­formation on DQ7.

After an erase command sequence is written, if all s ec­tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de­vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected.

When the system detects DQ7 has changed from the
complement to true data, it can read va lid data at DQ7–
DQ0 on the

following

read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll­ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.

DQ7 = Data?

Yes

No

No

DQ5 = 1?

No

Yes

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21444B-11

Figure 4. Data# Polling Algorithm

Am29F016B 19

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V

CC

.

If the output is low (Busy ), the de vice is activ ely er asing
or programming. (T his includes programming in the
Erase Suspend mode.) If th e output is high (Ready) ,
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia­grams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on D Q6 indicates whether a n Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or eras e op­eration), and during the s ector erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cyc les to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog­gles for appro xi mately 100 µ s , t hen returns to read ing

array data. If not all selected sectors are pro tected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When the device is activ ely erasing (that is ,
the Embedded Erase algorithm is in progress), D Q6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a pro tected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure show s the differences be­tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi­cates whether a par ticular sect or is actively erasing
(that is, the Embedded Erase algo rithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of t he final WE# pulse in
the command sequence.

DQ2 toggles w hen the system reads at addresses
within those sector s that have been selected for era­sure. (The system may use either OE# or CE# to con­trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus­pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era­sure. Thus, both status bits are required for s ector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.

Figure 5 shows the toggle bit algorithm in flowchar t
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows t he dif­ferences between DQ2 and DQ6 in graphical f orm.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the follow ing discussion. When­ever the system initially begins reading toggle bit sta­tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically , a
system would note a nd store th e val ue of the to ggle bit
after the first read. After the second read, the system
would compare the ne w v alue of the toggle bit with the
first. If the toggle bit is not to ggling, the device has
completed the program or erase operation. The sys­tem can read arra y data on DQ7–DQ0 on the f ollo wing
read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggli ng, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog­gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully comp leted the
program or erase operation. If it is still toggling, the
device did not complete the oper ation successfully, and

20 Am29F016B

PRELIMINARY

the system must write the reset command to return to
reading array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through success ive read cycle s, de­termining the status as described in the previous para­graph. Alterna tively, it may choose to perform o ther
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle was
not successfully completed.

The DQ5 failure condition may appear if the system
tries to program a “1” to a location that i s previously pro­grammed to “0.” Only an era se operation can change

a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, t he system must issue the

reset command to return the device to reading array
data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to det ermine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi­tional sectors are selec ted for er asure, th e entire time­out also applies after each add itional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guar antee t hat the time betw een ad­ditional sector erase commands will always be less
than 50 µs. Se e also th e “S ector Er ase Command Se­quence” section.

After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll­ing) or DQ6 (Toggle Bit I) to ensure the device has ac­cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be­gun; all further commands (other than Erase Su spend)
are ignored u ntil the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should ch eck the s tatus
of DQ3 prior to and following each subsequent s ector

erase command. If DQ3 is high on the second status
check, the last command might not have been ac­cepted. Table 6 shows the outputs for DQ3.

START

No

Yes

Yes

DQ5 = 1?

No

Yes

Toggle Bit

= Toggle?

No

Program/Erase

Operation Not
Complete, Write
Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is
toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21444B-12

Figure 5. Toggle Bit Algorithm

(Notes
1, 2)

(Note 1)

Am29F016B 21

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation

DQ7

(Note 1) DQ6

DQ5

(Note 2) DQ3

DQ2

(Note 1) RY/BY#

Standard
Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase
Suspend
Mode

Reading within Erase
Suspended Sector

1 No toggle 0 N/A Toggle 1

Reading within Non-Erase
Suspended Sector

Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

22 Am29F016B

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

V

CC

(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE#, RESET# (Note 2). . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During
voltage transitions, inputs may overshoot V

SS

to –2.0 V
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is V

CC

+ 0.5 V. During

voltage transitions, outputs may overshoot to V

CC

+ 2.0 V

for periods up to 20 ns. See Figure 7.

2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V . During voltage transitions, A9, OE#, RESET# pins
may overshoot V

SS

to –2.0 V for periods of up to 20 ns.
See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.

3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.

Stresses greater than those listed in this section may cause
permanent da mage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.

Figure 6. Maximum Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Case Temperature (TC) . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Case Temperature (T

C

) . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T

A

) . . . . . . . . –55°C to +125°C

V

CC

Supply Voltages

VCC for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V

Operating rang es define those limits between which the
functionality of the device is guaranteed.

20 ns

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21444B-13

20 ns

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

20 ns

2.0 V

21444B-14

Am29F016B 23

PRELIMINARY

DC CHARACTERISTICS
TTL/NMOS Compatible

CMOS Compatible

Notes for DC Characteristics (both tables):

1. The I

CC

current is typically less than 1 mA/MHz, with OE# at VIH.

2. I

CC

active while Embedded Program or Embedded Erase algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

I

LI

Input Load Current VIN = V

SS

to VCC, V

CC

= VCC Max ±1.0 µA

I

LIT

A9 Input Load Current V

CC

= V

CC

Max, A9 = 12.5 V 50 µA

I

LO

Output Leakage Current V

OUT

= V

SS

to VCC, V

CC

= VCC Max ±1.0 µA

I

CC1

VCC Read Current (Note 1) CE# = V

IL,

OE# = V

IH

25 40 mA

I

CC2

VCC Write Current (Notes 2, 3) CE# = V

IL,

OE# = V

IH

40 60 mA

I

CC3

V

CC

Standby Current

(CE# Controlled)

VCC = VCC Max, CE# = VIH,
RESET#

= VIH

0.4 1.0 mA

I

CC4

V

CC

Standby Current

(RESET# Controlled)

V

CC

= V

CC

Max, RESET# = V

IL

0.4 1.0 mA

V

IL

Input Low Level –0.5 0.8 V

V

IH

Input High Level 2.0 V

CC

+ 0.5 V

V

ID

Voltage for Autoselect and Sector
Protect

V

CC

= 5.0 V 11.5 12.5 V

V

OL

Output Low Voltage IOL = 12 mA, V

CC

= V

CC

Min 0.45 V

V

OH

Output High Level IOH = –2.5 mA V

CC

= V

CC

Min 2.4 V

V

LKO

Low VCC Lock-out Voltage 3.2 4.2 V

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

I

LI

Input Load Current VIN = V

SS

to VCC, V

CC

= V

CC

Max ±1.0 µA

I

LIT

A9 Input Load Current V

CC

= V

CC

Max, A9 = 12.5 V 50 µA

I

LO

Output Leakage Current V

OUT

= V

SS

to VCC, V

CC

= V

CC

Max ±1.0 µA

I

CC1

V

CC

Read Current (Note 1) CE# = V

IL,

OE# = V

IH

25 40 mA

I

CC2

V

CC

Write Current (Notes 2, 3) CE# = V

IL,

OE# = V

IH

30 40 mA

I

CC3

V

CC

Standby Current

(CE# Controlled)

V

CC = VCC

Max, CE# = V

CC

± 0.5 V,

RESET# = V

CC

± 0.5 V

15µA

I

CC4

V

CC

Standby Current

(RESET# Controlled)

V

CC

= V

CC

Max,

RESET# = V

SS

± 0.5 V

15µA

V

IL

Input Low Level –0.5 0.8 V

V

IH

Input High Level 0.7x V

CC

V

CC

+ 0.3 V

V

ID

Voltage for Autoselect
and Sector Protect

V

CC

= 5.0 V 11.5 12.5 V

V

OL

Output Low Voltage IOL = 12 mA, V

CC

= V

CC

Min 0.45 V

V

OH1

Output High Voltage

I

OH

= –2.5 mA, V

CC

= V

CC

Min 0.85 V

CC

V

V

OH2

IOH = –100 µA, V

CC

= V

CC

Min VCC – 0.4 V

V

LKO

Low V

CC

Lock-out Voltage 3.2 4.2 V

24 Am29F016B

PRELIMINARY

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

C

L

6.2 kΩ

5.0 V

Device

Under

Test

21444B-15

Figure 8. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition

All speed

options Unit

Output Load 1 TTL gate
Output Load Capacitance, C

L

(including jig capacitance)

100 pF

Input Rise and Fall Times 20 ns
Input Pulse Levels 0.45–2.4 V

Input timing measurement
reference levels

0.8 V

Output timing measurement
reference levels

2.0 V

KS000010-PAL

WAVEFORM I NP UTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Am29F016B 25

PRELIMINARY

AC CHARACTERISTICS
Read-only Operations

Notes:

1. Not 100% tested.

2. Refer to Figure 1 and Table 6 for test specifications.

Parameter Symbol

Parameter Description

Test

Setup

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

t

AVAV

t

RC

Read Cycle Time (Note 1) Min 70 90 120 150 ns

t

AVQV

t

ACC

Address to Output Delay

CE# = V

IL

OE# = V

IL

Max 70 90 120 150 ns

t

ELQV

t

CE

Chip Enable to Output Delay OE# = VILMax 70 90 120 150 ns

t

GLQV

t

OE

Output Enable to Output Delay Max 40 40 50 55 ns

t

OEH

Output Enable Hold
Time (Note 1)

Read Min0000ns
Toggle and

Data# Polling

Min10101010ns

t

EHQZ

t

DF

Chip Enable to Output High Z (Note 1) Max 20 20 30 35 ns

t

GHQZ

t

DF

Output Enable to Output High Z (Note 1) Max 20 20 30 35 ns

t

AXQX

t

OH

Output Hold Time From Addresses CE#
or OE# Whichever Occurs First

Min0000ns

t

Ready

RESET# Pin Low to Read Mode
(Note 1)

Max20202020µs

t

CE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output Valid

HIGH Z

Addresses Stable

t

RC

t

ACC

t

OEH

t

OE

0 V

RY/BY#

RESET#

t

DF

t

OH

21444B-16

Figure 9. Read Operation Ti mi ng s

26 Am29F016B

PRELIMINARY

AC CHARACTERISTICS
Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

t

READY

RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)

Max 20 µs

t

READY

RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)

Max 500 ns

t

RP

RESET# Pulse Width Min 500 ns

t

RH

RESET# High Time Before Read (See Note) Min 50 ns

t

RB

RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

RY/BY#

t

RP

t

Ready

Reset Timings NOT during Embedded Algorithms

t

Ready

CE#, OE#

t

RH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

t

RP

t

RB

21444B-17

Figure 10. RESET# Timings

Am29F016B 27

PRELIMINARY

AC CHARACTERISTICS
Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter

Parameter Description

Speed Options

UnitJEDEC Std -70 -90 -120 -150

t

AVAV

t

WC

Write Cycle Time (Note 1) Min 70 90 120 150 ns

t

AVWL

t

AS

Address Setup Time Min 0 ns

t

WLAX

t

AH

Address Hold Time Min 40 45 50 50 ns

t

DVWH

t

DS

Data Setup Time Min 40 45 50 50 ns

t

WHDX

t

DH

Data Hold Time Min 0 ns

t

OES

Output Enable Setup Time Min 0 ns

t

GHWL

t

GHWL

Read Recover Time Before Write
(OE# high to WE# low)

Min 0 ns

t

ELWL

t

CS

CE# Setup Time Min 0 ns

t

WHEH

t

CH

CE# Hold Time Min 0 ns

t

WLWH

t

WP

Write Pulse Width Min 40 45 50 50 ns

t

WHWL

t

WPH

Write Pulse Width High Min 20 ns

t

WHWH1tWHWH1

Byte Programming Operation (Note 2) Typ 7 µs

t

WHWH2tWHWH2

Sector Erase Operation (Note 2)

Typ 1 sec

Max 8 sec

t

VCS

VCC Set Up Time (Note 1) Min 50 µs

t

BUSY

WE# to RY/BY# Valid Min 40 40 50 60 ns

28 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

V

CC

Data

Addresses

t

DS

t

AH

t

DH

t

WP

PD

t

WHWH1

t

WC

t

AS

t

WPH

t

VCS

555h

PA PA

Read Status Data (last two cycles)

A0h

t

GHWL

t

CS

Status

D

OUT

Program Command Sequence (last two cycles)

RY/BY#

t

RB

t

BUSY

t

CH

PA

Note: PA = program address, PD = program data, D

OUT

is the true data at the program address.

21444B-18

Figure 11. Program Operation Timings

Am29F016B 29

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

V

CC

WE#

Data

2AAh SA

t

GHWL

t

AH

t

WP

t

WC

t

AS

t

WPH

555h for chip erase

10 for Chip Erase

30h

t

DS

t

VCS

t

CS

t

DH

55h

t

CH

In

Progress

Complete

t

WHWH2

VA

VA

RY/BY#

t

RB

t

BUSY

Note:

SA = Sector Address. VA = Valid Address for reading status data.

21444B-19

Figure 12. Chip/Sector Erase Operation Timings

30 Am29F016B

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

t

OE

High Z

DQ7

DQ0–DQ6

RY/BY#

t

BUSY

Complement

True

Addresses

VA

t

OEH

t

CE

t

CH

t

OH

t

DF

VA VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

t

ACC

t

RC

Note:

V A = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21444B-20

Figure 13. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

t

OE

DQ6/DQ2

RY/BY#

t

BUSY

Addresses

VA

t

OEH

t

CE

t

CH

t

OH

t

DF

VA VA

t

ACC

t

RC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

VA

Note:

V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.

21444B-21

Figure 14. Toggle Bit Timings (During Embedded Algorithms)

Am29F016B 31

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

t

VIDR

VID Rise and Fall Time (See Note) Min 500 n s

t

RSP

RESET# Setup Time for Temporary Sector
Unprotect

Min 4 µs

Enter

Erase

Erase

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Suspend
Program

Resume

Embedded

Erasing

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.

21444B-22

Figure 15. DQ2 vs. DQ6

RESET#

t

VIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

t

VIDR

t

RSP

Program or Erase Command Sequence

0 or 5 V

21444B-23

Figure 16. Temporary Sector Group Unprotect Timings

32 Am29F016B

PRELIMINARY

AC CHARACTERISTICS
Erase and Program Operations

Alternate CE# Controlled Writes

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Symbol

Parameter Description

Speed Options

UnitJEDEC Standard -70 -90 -120 -150

t

AVAV

t

WC

Write Cycle Time (Note 1) Min 7 0 90 120 1 50 ns

t

AVEL

t

AS

Address Setup Time Min 0 ns

t

ELAX

t

AH

Address Hold Time Min 40 45 50 50 ns

t

DVEH

t

DS

Data Setup Time Min 40 45 50 50 ns

t

EHDX

t

DH

Address Hold Time Min 0 ns

t

GHEL

t

GHEL

Read Recover Time Before Write Min 0 ns

t

WLEL

t

WS

CE# Setup Time Min 0 ns

t

EHWH

t

WH

CE# Hold Time Min 0 ns

t

ELEH

t

CP

Write Pulse Width Min 4 0 45 50 50 ns

t

EHEL

t

CPH

Write Pulse Width High Min 20 ns

t

WHWH1

t

WHWH1

Byte Programming Operation (Note 2) Typ 7 µs

t

WHWH2

t

WHWH2

Sector Erase Operation (Note 2)

Typ 1 sec

Max 8 sec

Am29F016B 33

PRELIMINARY

AC CHARACTERISTICS

t

GHEL

t

WS

OE#

CE#

WE#

RESET#

t

DS

Data

t

AH

Addresses

t

DH

t

CP

DQ7# D

OUT

t

WC

t

AS

t

CPH

PA

Data# Polling

A0 for program
55 for erase

t

RH

t

WHWH1 or 2

RY/BY#

t

WH

PD for program
30 for sector erase
10 for chip erase

555 for program
2AA for erase

PA for program
SA for sector erase
555 for chip erase

t

BUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

OUT

= Array Data.

2. Figure indicates the last two bus cycles of the command sequence.

21444B-24

Figure 17. Alternate CE# Controlled Write Operation Timings

34 Am29F016B

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 5.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

CC

= 4.5 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTIC

S

Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

A

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 1 8 sec

Excludes 00h programming prior to
erasure (Note 4)

Chip Erase Time 32 256 sec
Byte Programming Time 7 300 µs

Excludes system-level overhead
(Note 5)

Chip Programming Time (Note 3) 14.4 43.2 sec

Min Max

Input Voltage with respect to V

SS

on I/O pins –1.0 V VCC + 1.0 V

V

CC

Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

C

IN

Input Capacitance VIN = 0 6 7.5 pF

C

OUT

Output Capacitance V

OUT

= 0 8.5 12 pF

C

IN2

Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time

150°C 10 Years
125°C 20 Years

Am29F016B 35

PRELIMINARY

PHYSICAL DIMENSIONS

TS 040—40-Pin Standard Thin Small Outline Package (measured in millimeters)

TSR040—40-Pin Reverse Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

40

20

Pin 1 I.D.

21

1

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0°
5°

16-038-TSOP-1_AE
TS 040
2-27-97 lv

0.10

0.21

0.08

0.20

18.30

18.50

19.80

20.20

40

20

Pin 1 I.D.

21

1

0.50 BSC

9.90

10.10

0.95

1.05

0.05

0.15

1.20

MAX

0.50

0.70

0°
5°

16-038-TSOP-1_AE
TSR040
2-27-97 lv

0.10

0.21

0.08

0.20

36 Am29F016B

PRELIMINARY

PHYSICAL DIMENSIONS (continued)

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

48

25

1

24

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2
TS 048
DT95
8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC

0°
5°

0.08

0.20

48

25

1

24

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48
TSR048
DT95
8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC

0°
5°

0.08

0.20

Am29F016B 37

PRELIMINARY

PHYSICAL DIMENSIONS (continued)

SO 044—44-Pin Small Outline Package (measured in millimeters)

44

23

1

22

13.10

13.50

15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50

0.10

0.35

2.80

MAX.

SEATING
PLANE

16-038-SO44-2
SO 044
DF83
8-8-96 lv

0.10

0.21

0.60

1.00

0°
8°

END VIEW

SIDE VIEW

TOP VIEW

38 Am29F016B

PRELIMINARY

REVISION SUMMARY FOR AM29F016B
Revision B

Global

Made formatting and layout consistent with other data
sheets. Used updated common tables and diagr ams.

Revision B+1

AC Characteristics—Read-only Operations

Deleted note referring to output driver disable time.

Figure 16—Temporary Sector Group Unprotect
Timings

Corrected title to indicate “sector group. ”

Revision B+2

Global

Added -70 speed option, deleted -75 speed option.

Distinctive Characteristics

Changed minimum 100K wr ite/erase cycles guaran­teed to 1,000,000.

Ordering Information

Added extended temperature availability to -90, -120,
and -150 speed options.

Operating Ranges

Added extended temperature range.

DC Characteristics, CMOS Compatible

Corrected the CE# and RESET# test conditions for
I

CC3

and I

CC4

to VCC ±0.5 V.

AC Characteristics

Erase/Program Operations; Erase and Program Oper­ations Alternate CE# Controlled Writes:

Corrected the

notes reference f or t

WHWH1

and t

WHWH2

. These param­eters are 100% tested. Corrected the note ref erence for
t

VCS

. This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for t

VIDR

. This parameter is not

100% tested.

Erase and Programming Performance

Changed mini mum 100K program a nd erase cycles
guaranteed to 1,000,000.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.