AMD Advanced Micro Devices AM29F016B-90SIB, AM29F016B-90SI, AM29F016B-90SEB, AM29F016B-90SE, AM29F016B-90SCB Datasheet

PRELIMINARY

Publication# 21444 Rev: B Amendment/+2
Issue Date: April 1998

Am29F016B

16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10%, single power supply operation

— Minimizes system level power requirements

■ Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29F016 device

■ High performance

— Access times as fast as 70 ns

■ Low power consumption

— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access

time to active mode)

■ Flexible sector architecture

— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Group sector protection:

A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group

Temporary Sector Group Unprotect allows code
changes in previously locked sectors

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any
combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ Minimum 1,000,000 progr am/erase cycles per

sector guaranteed

■ Package options

— 48-pin and 40-pin TSOP
— 44-pin SO

■ Compatible with JEDEC standards

— Pinout and software c ompatible with

single-power-supply Flash standard

— Superior inadvertent write protection

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

— Provides a hardware method f or detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase oper ation to read da ta

from, or program data to, a non-erasing sector,
then resumes the erase operation

■ Hardware reset p in (RESET#)

— Resets internal state machine to the read mode

2 Am29F016B

PRELIMINARY

GENERAL DESCRIPTION

The Am29F016B is a 16 Mbit, 5.0 v olt-only Flash mem­ory organized as 2,097,152 bytes. The 8 bits of data

appear on DQ0–DQ7. The Am29F016B is offered in
48-pin and 40-pin TSOP, and 44-pin SO packages.
This device is designed to be programmed in-s ystem
with the standard system 5.0 volt V

CC

supply. A 12.0

volt V

PP

is not required for program or erase
operations. The device can also be programmed in
standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the f eatures and ben­efits of the Am29F016, which was m anufactured using

0.5 µm process technology.
The standard device of fers access t imes of 70, 90, 120,

and 150 ns, allowing high-speed microprocessors to
operate without wait states. To elim inate bus conten ­tion, the device has separate c hip enable (CE#), write
enable (WE#), and output enable (OE#) controls.

The device requires only a si ngle 5.0 volt power sup-
ply for both read and w rite functions. Internally gener­ated and regulated voltages are provided for the
program and erase operations.

The device is entirely command set c ompatible with the
JEDEC single-power-supply Flash standard. Com­mands are written to the command register using stan­dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con­trols the erase and programming circuitry. Write cycles
also internally latch addresses and data n eeded f o r the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto­matically times the program pulse widths and verifies
proper cell margin.

Device erasure occurs by executing the erase com­mand sequence. This initiates the Embedded Erase
algorithm—an inter nal algorithm that automatically
preprograms the array (if it is not already progr ammed)

before e xecutin g the erase operatio n. During erase, t he
device automatically times the erase pulse widths and
verifies proper cell margin.

The host system can detect whether a program or
erase operation is complete by obser ving the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de vice is ready to read array data
or accept another command.

The sector erase ar chitecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low
V

CC

detector that automatically inhibits write opera­tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any com bination of the sectors of mem­ory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achie ved.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin ma y be t ied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.

The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.

AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost
effectiveness. The device electrically erases all
bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.

Am29F016B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: See the AC Characteristics section for more information.

BLOCK DIAGRAM

Family Part Number Am29F016B
Speed Options (V

CC

= 5.0 V ± 10%) -70 -90 -120 -150
Max Access Time (ns) 70 90 120 150
CE# Access (ns) 70 90 120 150
OE# Access (ns) 40 40 50 75

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

Register

V

CC

V

SS

WE#

CE#
OE#

STB

STB

DQ0

–

DQ7

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A20

21444B-1

4 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

NC

RESET#

A11
A10

A9
A8
A7
A6
A5
A4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3

40-Pin Standard TSOP

21444B-2

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

40-Pin Reverse TSOP

Am29F016B 5

PRELIMINARY

CONNECTION DIAGRAMS (continued)

1

24

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

NC

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12

CE#

V

CC

NC

RESET#

A11
A10

A9
A8
A7
A6
A5
A4

NC

48

25

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

NC

NC

NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
NC

48-Pin Standard TSOP

21444B-4

1

24

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

NC

NC

NC

A20

NC

WE#

OE#

RY/BY#

DQ7
DQ6
DQ5
DQ4

V

CC

V

SS

V

SS

DQ3
DQ2
DQ1
DQ0

A0
A1
A2
A3

NC

48

25

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

NC

NC

NC
A19
A18
A17
A16
A15
A14
A13
A12
CE#
V

CC

NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC

48-Pin Reverse TSOP

21444B-5

6 Am29F016B

PRELIMINARY

CONNECTION DIAGRAMS

PIN CONFIGURATION

A0–A20 = 21 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output
V

CC

= +5.0 V single power supply

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)

V

SS

= Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

NC

RESET#

A11
A10

A9
A8
A7
A6
A5

A4
NC
NC

A3

A2

A1

A0

DQ0
DQ1
DQ2
DQ3

V

SS

V

SS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

V

CC

CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
V

CC

SO

21444B-6

21

8

DQ0–DQ7

A0–A20

CE#
OE#

WE#
RESET# RY/BY#

21444B-7

Am29F016B 7

PRELIMINARY

ORDERING INFORMATION
Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be support­ed in volume for this device. Cons ult the loc al AM D sale s of­fice to confirm availab ility of specific valid combinations and
to check on newly released combinations.

DEVICE NUMBER/DE SCR IP TIO N

Am29F016B
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sec tor Era se Flash Mem or y

5.0 V Read, Program, and Erase

Am29F016B -70 E I

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)
I = Industrial (–40 °C to +85 °C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR048)

E4 = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F4 = 40-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TS R0 40)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

Am29F016B-70

EC, EI, FC, FI,
E4C, E4I, F4C, F4I, SC, SI

Am29F016B-90

EC, EI, EE, FC, FI, FE
E4C, E4I, E4E, F4C, F4I,
F4E, SC, SI, SE

Am29F016B-120
Am29F016B-150

8 Am29F016B

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal c ommand register. The command register it­self does not occupy any addressable memory loca­tion. The register is composed of l atches that store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels requ ired, and the
resulting output. The following subsections describe
each of these operations in further detail.

Table 1. Am29F016B Device Bus Operations

Legend:

L = Logic Low = V

IL

, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, D

OUT

= Data Out, AIN = Address In

Note:

See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V

IL

. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re­main at V

IH

.

The internal state machin e is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessar y in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enable d for read access until the
command register contents are altered.

See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica­tions and to the Read Operations Timings diagram for
the timing waveforms. I

CC1

in the DC Characteristics

table represents the active current specification for
reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V

IL

, and OE# to VIH.

An erase operation can erase one sect or, multiple sec­tors, or the entire de vice. The Sector Address Tables in­dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini­tions” section for details on erasing a sector or the en­tire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.

I

CC2

in the DC Characteristics table represents the ac­tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Operation CE# OE# WE# RESET# A0–A20 DQ0–DQ7

Read L L H H A

IN

D

OUT

Write L H L H A

IN

D

IN

CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z

TTL Standby H X X H X High-Z
Output Disable L H H H X High-Z
Hardware Reset X X X L X High-Z
Temporary Sector Unprotect

(See Note)

XXX V

ID

A

IN

D

IN

Am29F016B 9

PRELIMINARY

Program and Erase Operation Status

During an erase or program operation, the system ma y
check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

CC

read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Charac­teristics section for timing diagrams.

Standby Mode

When the system is not reading or writing to the device ,
it can place the device in the standby mode. In this
mode, current consumption is great ly reduc ed, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V

CC

± 0.5 V. (Note

that this is a more restrict ed voltage range than V

IH

.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V

IH

. The device re­quires standard access time (tCE) for read access when
the device is in either of these standb y modes, bef ore it
is ready to read data.

The device also enters the standb y mode when the RE­SET# pin is driven low. Refer to the next section, “RE­SET#: Hardware Reset Pin”.

If the device is deselected during erasure or program ­ming, the device draws active current until the
operation is completed.

In the DC Charac teristics tables, I

CC3

represents the
standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a har dware method of reset­ting the device to readi ng arr ay data. When the system
drives the RESET# pin low for at least a period of t

RP

,

the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration o f the RESET#
pulse. The device also resets the inter nal state ma­chine to reading array data. The operation that was in­terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V

IL

, the device enters

the TTL standby mode; if RESET# is held at V

SS

±

0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm­ware from the Flash memory.

If RESET# is asserted during a program or erase oper­ation, the RY/BY# pin remains a “0” (busy) until the in­ternal reset operatio n is complete, which requires a
time of t

READY

(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t

READY

(not during Embe dded Algo-

rithms). The system can read data t

RH

after the RE-

SET# pin returns to V

IH

.

Refer to the AC Characteristics tables for RESET# pa­rameters and timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in t he high imped­ance state.

10 Am29F016B

PRELIMINARY

Table 2. Sector Address Table

Note: All sectors are 64 Kbytes in size.

Sector A20 A19 A18 A17 A16 Address Range

SA0 0 0 0 0 0 000000h-00FFFFh
SA1 0 0 0 0 1 010000h-01FFFFh
SA2 0 0 0 1 0 020000h-02FFFFh
SA3 0 0 0 1 1 030000h-03FFFFh
SA4 0 0 1 0 0 040000h-04FFFFh
SA5 0 0 1 0 1 050000h-05FFFFh
SA6 0 0 1 1 0 060000h-06FFFFh
SA7 0 0 1 1 1 070000h-07FFFFh
SA8 0 1 0 0 0 080000h-08FFFFh

SA9 0 1 0 0 1 090000h-09FFFFh
SA10 0 1 0 1 0 0A0000h-0AFFFFh
SA11 0 1 0 1 1 0B0000h-0BFFFFh
SA12 0 1 1 0 0 0C0000h-0CFFFFh
SA13 0 1 1 0 1 0D0000h-0DFFFFh
SA14 0 1 1 1 0 0E0000h-0EFFFFh
SA15 0 1 1 1 1 0F0000h-0FFFFFh
SA16 1 0 0 0 0 100000h-10FFFFh
SA17 1 0 0 0 1 110000h-11FFFFh
SA18 1 0 0 1 0 120000h-12FFFFh
SA19 1 0 0 1 1 130000h-13FFFFh
SA20 1 0 1 0 0 140000h-14FFFFh
SA21 1 0 1 0 1 150000h-15FFFFh
SA22 1 0 1 1 0 160000h-16FFFFh
SA23 1 0 1 1 1 170000h-17FFFFh
SA24 1 1 0 0 0 180000h-18FFFFh
SA25 1 1 0 0 1 190000h-19FFFFh
SA26 1 1 0 1 0 1A0000h-1AFFFFh
SA27 1 1 0 1 1 1B0000h-1BFFFFh
SA28 1 1 1 0 0 1C0000h-1CFFFFh
SA29 1 1 1 0 1 1D0000h-1DFFFFh
SA30 1 1 1 1 0 1E0000h-1EFFFFh
SA31 1 1 1 1 1 1F0000h-1FFFFFh

Am29F016B 11

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This
mode is primarily intended for progr amming equipment
to automatically match a device to be progr ammed with
its correspondi ng programming al gorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires V

ID

(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. I n addi­tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad­dress Tables. The Comm and Definitions table shows
the remaining address bits that are don’t c are. When all
necessary bits have been set as required, the program­ming equipment may then read the corresponding
identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the C ommand Defini­tions table. This method does not require V

ID

. See
“Command Definitions” for details on using the autose­lect mode.

Table 3. Am29F016B Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Group Protection/Unprotection

The hardware sector group protection feature dis­ables both program and erase operations in any sec­tor gr o u p. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group con­tains. The hardware sector group unprotection fea­ture re-enables both program and erase operations in
previously protected sector groups.

Sector group protection/unprotection must be imple­mented using programming equipment. The procedure
requires a high voltage (V

ID

) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 19613. Contact an
AMD representative to obtain a cop y of the appropriate
document.

The device is shipped with all sector grou ps unpro­tected. AMD offers t he optio n of prog r amming a nd pro­tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con­tact an AMD representative for details.

It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.

Table 4. Sector Group Addresses

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ­ously protected sector groups to change data in-sys­tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to V

ID

. During this mode,
formerly protected sector g roups can be programmed
or erased by selecting the sector group addresses.
Once V

ID

is removed from the RESET# pin, all the
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig­ure 16) shows the timing waveforms, for this feature.

Description CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0 DQ7-DQ0

Manufacturer ID:
AMD

LLH X X V

ID

XVILXVILV

IL

01h

Device ID:
Am29F016B

LLH X X VIDXVILXVILV

IH

ADh

Sector Group
Protection
Ve r ific atio n

LLH

Sector
Group

Address

XVIDXVILXVIHV

IL

01h (protected)

00h (unprotected)

Sector
Group A20 A19 A18 Sectors

SGA0 0 0 0 SA0

–

SA3

SGA1 0 0 1 SA4

–

SA7

SGA2 0 1 0 SA8

–

SA11

SGA3 0 1 1 SA12

–

SA15

SGA4 1 0 0 SA16

–

SA19

SGA5 1 0 1 SA20

–

SA23

SGA6 1 1 0 SA24

–

SA27

SGA7 1 1 1 SA28

–

SA31

12 Am29F016B

PRELIMINARY

Figure 1. Temporary Sector Group Unprotect

Operation

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi­nitions table). In addition, the following hardware data
protection measures pre vent a ccidental eras ure or pro­gramming, which might otherwise be caused by spuri­ous system level signals during V

CC

power-up and

power-down transitions, or from system noise.

Low V

CC

Write Inhibit

When V

CC

is less than V

LKO

, the device does not ac-

cept any write cycles. This protects data during V

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V

CC

is greater than V

LKO

. The system must provide the
proper signals to the control pins to prevent uninten­tional writes when V

CC

is greater than V

LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#
= V

IL

, CE# = VIH or WE# = VIH. To initiate a write cy­cle, CE# and WE# must be a logical zero while OE#
is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL

and OE# = VIH during powe r
up, the device does not accept commands on the
rising edge of WE#. The inter nal state machine is
automatically reset to reading array data on
power-up.

START

Perform Erase or

Program Operations

RESET# = V

IH

Temporary

Sector Group Unprotect

Completed (Note 2)

RESET# = V

ID

(Note 1)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected
once again.

21444B-8