AMD Am29DS163D Service Manual

Am29DS163D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

Publication Number 22326 Revision A Amendment +1 Issue Date November 8, 2004

THIS PAGE LEFT INTENTIONALLY BLANK.

ADVANCE INFORMATION

Am29DS163D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■ Multiple bank architectures

— Two devices available with different bank sizes (refer

to Table 3)

■ Secured Silicon (SecSi) Sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data.

— Customer lockable: Can be read, programmed, or

erased just like other sectors. Once locked, data cannot be changed.

— 64 Kbyte sector size

■ Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly zero

■ Package options

— 48-ball FBGA

■ Top or bottom boot block

■ Manufactured on 0.23 µm process technology

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast 100 ns

— Program time: 13 µs/word typical utilizing Accelerate function

■ Ultra low power consumption (typical values)

— 1 mA active read current at 1 MHz

— 5 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■ Minimum 1 million write cycles guaranteed per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■ Data Management Software (DMS)

— AMD-supplied software manages data programming

and erasing, enabling EEPROM emulation

— Eases sector erase limitations

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

■ WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function provides accelerated

program times

■ Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to prevent any program or erase operation within that sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

Publication# 22326 Rev: A Amendment/1 Issue Date: November 8, 2004

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29DS163D family consists of 16 megabit, 1.8 volt-only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 1.8 volt VCC supply, and can also be programmed in standard EPROM programmers.

The device is available with an access time of 100 and 120 ns. The devices are offered in an 48-ball FBGA package. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus con tention issues.

The device requires only a single 1.8 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations.

Am29DS163D Features

The Secured Silicon (SecSi) Sector is an additional 64 Kbyte sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator

Bit (DQ7) is permanently set to a 1 if the part is fac- tory locked, and set to a 0 if customer lockable. This

way, customer lockable parts can never be used to re place a factory locked part.

Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there.

DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS also allows the system software to be simplified, as it performs all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di

rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set standard. Commands are written to the command

register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase operation is complete by using the device sta tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). is completed, the device automatically returns to reading array data.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem ory. This is achieved in-system or via programming equipment.

The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

After a program or erase cycle

4 Am29DS163D

ADVANCE INFORMATION

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29DS163D Device Bus Operations .............................10

Word/Byte Configuration ........................................................10

Requirements for Reading Array Data ...................................10

Writing Commands/Command Sequences ............................11

Accelerated Program Operation ......................................................11

Autoselect Function s ........................... ................ ................ ............11

Simultaneous Read/Write Operations with Zero Latency .......11

Standby Mode ........................................................................11

Automatic Sleep Mode .................................... .. .....................12

RESET#: Hardware Reset Pin ...............................................12

Output Disable Mode ..............................................................12

Table 2. Am29DS163D Device Bank Divisions ...............................12

Table 3. Top Boot Sector Addresses (Am29DS16xDT) ..................13

SecSi Sector Addresses for Top Boot Device s.............................. 13

Table 5. Bottom Boot Sector Addresses (Am29DS16xDB) ............14

SecSi Sector Addresses for Botto m Boot Device s................. ........ 14

Autoselect Mode ............................................ .. .......................15

Table 7. Am29DS163D Autoselect Codes (High Voltage Method) 15

Sector/Sector Block Protection and Unprotection ..................16

Table 8. Top Boot Sector/Sector Block Addresses

for Protection/Unpro tection ............................... ................ ..............16

Table 9. Bottom Boot Sector/Sector Block Addresses

for Protection/Unpro tection ............................... ................ ..............16

Write Protect (WP#) ................................................................17

Temporary Sector/Sector Block Unprotect .............................17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. In-System Sector/Sector Block Protect

and Unprotect Algorithms. ................ ................................ ............... 18

SecSi (Secured Silicon) Sector Flash Memory Region ..........19

Hardware Data Protection ......................................................19

Low VCC Write Inhibit .....................................................................20

Write Pulse “Glitch” Protection ................... ................................ .....20

Logical Inhibit ..................................................................................20

Power-Up Write Inhibit ............... ................................................ .....20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 10. CFI Query Identification String........................................ 20

System Interface String........................ ................ ........................... 21

Table 12. Device Geometry Definit ion.................... ........................ 21

Table 13. Primary Vendor-Specific Extended Query ...................... 22

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................23

Reset Command .....................................................................23

Autoselect Command Sequence ......................... ...................23

Enter SecSi Sector/Exit SecSi Sector Command Sequence ..24

Byte/Word Program Command Sequence .............................24

Unlock Bypass Command Sequence ..............................................24

Figure 3. Program Operat io n.................... ................................ ...... 25

Chip Erase Command Sequence ...........................................25

Sector Erase Command Sequence ...................... .. ................25

Erase Suspend/Erase Resume Commands ........................... 26

Figure 4. Erase Operation............. ................ ................................ . 26

Table 14. Am29DS163D Command Defin itions........................ ...... 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Po l lin g .......... ... .. .............. .. ... .............. .. ... ............28

Figure 5. Data# Polling Algorithm................................................. . 28

RY/BY#: Ready/Busy# ............................................................ 29

DQ6: Toggle Bit I ....................................................................29

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ...................................................................30

Reading Toggle Bits DQ6/DQ2 ...............................................30

DQ5: Exceeded Timing Limits ................................................30

DQ3: Sector Era s e Time r ............ ...........................................30

Table 15. Write Operation Sta tus ............. ................ ......................31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform...................... 32

Figure 8. Maximum Positive Overshoot Waveform....................... 32

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I

and Automatic Sleep Currents)...................................................... 34

Figure 10. Typical I

Current vs. Time (Showing Active

CC1

vs. Frequency.............. ................ .............. 34

CC1

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup..................... ................. ................ .............. 35

Table 16. Test Specifications ................... ................ ................ ......35

Figure 12. Input Waveforms and Measurement Levels ................. 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Read Operation Timings. ........ .............................. ........ 36

Figure 14. Reset Timings............................................................... 37

Word/Byte Configuration (BYTE#) ..........................................38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Erase and Program Operations .............................................. 39

Figure 17. Program Operation Timings.......................................... 40

Figure 18. Accelerated Program Timing Diagram.......................... 40

Figure 19. Chip/Sector Erase Operation Timings.......................... 41

Figure 20. Back-to-back Read/Write Cycle Timings ...................... 42

Figure 21. Data# Polling Timings (During Embedded Algorithms) . 42

Figure 22. Toggle Bit Timings (During Embedded Algorithms)...... 43

Figure 23. DQ2 vs. DQ6............................ ................................ ..... 43

Temporary Sector/Sector Block Unprotect .............................44

Figure 24. Temporary Sector/Sector Block

Unprotect Timing Diagr a m.............. ................. ................ .............. 44

Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram 45

Alternate CE# Controlled Erase and Program O perations .....46

Figure 26. Alternate CE# Controlled Write

(Erase/Program) Operati o n Timings............. ................................ . 47

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package ...................................................... ...........49

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50

Am29DS163D 5

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Part Number Am29DS163D

Speed Option Standard Voltage Range: VCC = 1.8–2.2 V 100 120

Max Access Time (ns) 100 120

CE# Access (ns) 100 120

OE# Access (ns) 35 50

BLOCK DIAGRAM

OE# BYTE#

A0–A19

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

A0–A19

RY/BY#

A0–A19A0–A19

STATE

CONTROL

& COMMAND REGISTER

Upper Bank Address

Lower Bank Address

Y-Decoder

Status

Control

Y-Decoder

Upper Bank

X-Decoder

Lower Bank

Latches and Control Logic

Latches and

Control Logic

OE# BYTE#

DQ0–DQ15

DQ0–DQ15 DQ0–DQ15

6 Am29DS163D

CONNECTION DIAGRAMS

A6 B6 C6 D6 E6 F6 G6 H6

A5 B5 C5 D5 E5 F5 G5 H5

A4 B4 C4 D4 E4 F4 G4 H4

A3 B3 C3 D3 E3 F3 G3 H3

A2 B2 C2 D2 E2 F2 G2 H2

ADVANCE INFORMATION

48-Ball FBGA

Top View, Balls Facing Down

BYTE#A16A15A14A12A13

DQ15/A-1

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

DQ4DQ12DQ5A19NCRESET#WE#

A1 B1 C1 D1 E1 F1 G1 H1

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

CE#A0A1A2A4A3

OE#

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Am29DS163D 7

ADVANCE INFORMATION

PIN DESCRIPTION

A0–A19 = 20 Addresses

DQ0–DQ14 = 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RESET# = Hardware Reset Pin, Active Low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy Output

VCC = 1.8 volt-only single power supply

(see Product Selector Guide for speed options and voltage supply tolerances)

NC = Pin Not Connected Internally

= Device Ground

LOGIC SYMBOL

A0–A19

CE#

OE#

WE#

WP#/ACC

RESET#

BYTE#

16 or 8

DQ0–DQ15

(A-1)

RY/BY#

8 Am29DS163D

ADVANCE INFORMATION

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:

Am29DS163D T 100 E I

OPTIONAL PROCESSING

Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information)

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) F = Industrial (-40oC to +85oC) with Pb-free Package K = Extended (-55oC to +125oC) with Pb-free Package

PACKAGE TYPE

WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations for FBGA Packages

Order Number Package Marking

Am29DS163DT100, Am29DS163DB100

Am29DS163DT120, Am29DS163DB120

BOOT CODE SECTOR ARCHITECTURE

T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29DS163D 16Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con

WAI, WAE, WAF, WAK

S163DT10V, S163DB10V

S163DT12V, S163DB12V

I, E,

F, K

firm availability of specific valid combinations and to check on newly released combinations.

Valid Combinations

Am29DS163D 9

ADVANCE INFORMATION

DEVICE BUS OPERATIONS

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data informa tion needed to execute the command. The contents of

Tab l e 1. Am29DS163D Device Bus Operations

the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tab l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

DQ8–DQ15

Addresses

Operation CE# OE# WE# RESET# WP#/ACC

(Note 2)

Read L L H H L/H A

Write L H L H (Note 3) A

Standby

VCC ±

0.3 V

X X

VCC ±

0.3 V

H X High-Z High-Z High-Z

DQ0–

DQ7

OUT

BYTE#

= V

OUT

BYTE#

= V

DQ8–DQ14 = High-Z,

DQ15 = A-1

Output Disable L H H H L/H X High-Z High-Z High-Z

Reset X X X L L/H X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect X X X V

L/H

(Note 3)

(Note 3) A

SA, A6 = L,

A1 = H, A0 = L

SA, A6 = H,

A1 = H, A0 = L

X X

High-Z

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9.0–11.0 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A

= Address In, DIN = Data In, D

= Data Out

OUT

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection” on page 16.

3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in

Protection and Unprotection” on page 16. If WP#/ACC = V

all sectors are unprotected.

HH,

“Sector/Sector Block

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid

10 Am29DS163D

ADVANCE INFORMATION

addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.

See “Requirements for Reading Array Data” on

page 10 for more information. Refer to the Ta bl e on page 36 for timing specifications and to Figure 13, on page 36 for the timing diagram. I

in the DC Charac-

CC1

teristics table represents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” on page 10 for more information.

The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Configuration” section contains details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 3 on page 13 to

Tab l e 6 on page 14 indicate the address space that

each sector occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector.

CC2

tive current specification for the write mode. The “AC

Characteristics” on page 36 section contains timing

specification tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.

If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system

, and OE# to VIH.

in the DC Characteristics table represents the ac-

would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V

from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the inter nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to

“Autoselect Mode” on page 15 and “Autoselect Command Sequence” on page 23 for

more information.

Simultaneous Read/Write Operations with Zero

Latency

This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 20, on page 42 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I

CC6

and I

in the DC

CC7

Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

in the DC Characteristics table represents the

CC3

standby current specification.

Am29DS163D 11

ADVANCE INFORMATION

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t

ACC

+ 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad

dress access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I

in the “DC Characteristics” on page 33 represents

CC4

the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en sure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V draws CMOS standby current (I

±0.3 V, the device

). If RESET# is held

CC4

at V

but not within VSS±0.3 V, the standby current is

greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t

(during Embedded Algorithms). The sys-

READY

tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t

(not during Embedded Algo-

READY

rithms). The system can read data tRH after the RESET# pin returns to VIH.

Refer to “AC Characteristics” on page 36 for RESET# parameters and to Figure 14, on page 37 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Device

Part Number

Am29DS163D 4 Mbit

Megabits Sector Sizes Megabits Sector Sizes

Table 2. Am29DS163D Device Bank Divisions

Bank 1 Bank 2

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

12 Mbit

Twenty-four

64 Kbyte/32 Kword

12 Am29DS163D

ADVANCE INFORMATION

Table 3. Top Boot Sector Addresses (Am29DS16xDT)

Sector

Am29DS163DT

Bank 2

Bank 1

Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19 and A18 for Am29DS163DT.

SA0 00000xxx 64/32 000000h-00FFFFh 00000h–07FFFh

SA1 00001xxx 64/32 010000h-01FFFFh 08000h–0FFFFh

SA2 00010xxx 64/32 020000h-02FFFFh 10000h–17FFFh

SA3 00011xxx 64/32 030000h-03FFFFh 18000h–1FFFFh

SA4 00100xxx 64/32 040000h-04FFFFh 20000h–27FFFh

SA5 00101xxx 64/32 050000h-05FFFFh 28000h–2FFFFh

SA6 00110xxx 64/32 060000h-06FFFFh 30000h–37FFFh

SA7 00111xxx 64/32 070000h-07FFFFh 38000h–3FFFFh

SA8 01000xxx 64/32 080000h-08FFFFh 40000h–47FFFh

SA9 01001xxx 64/32 090000h-09FFFFh 48000h–4FFFFh

SA10 01010xxx 64/32 0A0000h-0AFFFFh 50000h–57FFFh

SA11 01011xxx 64/32 0B0000h-0BFFFFh 58000h–5FFFFh

SA12 01100xxx 64/32 0C0000h-0CFFFFh 60000h–67FFFh

SA13 01101xxx 64/32 0D0000h-0DFFFFh 68000h–6FFFFh

SA14 01110xxx 64/32 0E0000h-0EFFFFh 70000h–77FFFh

SA15 01111 xxx 64/32 0F0000h-0FFFFFh 78000h–7FFFFh

SA16 10000xxx 64/32 100000h-10FFFFh 80000h–87FFFh

SA17 10001xxx 64/32 110000h-11FFFFh 88000h–8FFFFh

SA18 10010xxx 64/32 120000h-12FFFFh 90000h–97FFFh

SA19 10011xxx 64/32 130000h-13FFFFh 98000h–9FFFFh

SA20 10100xxx 64/32 140000h-14FFFFh A0000h–A7FFFh

SA21 10101xxx 64/32 150000h-15FFFFh A8000h–AFFFFh

SA22 10110xxx 64/32 160000h-16FFFFh B0000h–B7FFFh

SA23 10111xxx 64/32 170000h-17FFFFh B8000h–BFFFFh

SA24 11000xxx 64/32 180000h-18FFFFh C0000h–C7FFFh

SA25 11001xxx 64/32 190000h-19FFFFh C8000h–CFFFFh

SA26 11010xxx 64/32 1A0000h-1AFFFFh D0000h–D7FFFh

SA27 11011xxx 64/32 1B0000h-1BFFFFh D8000h–DFFFFh

SA28 11100xxx 64/32 1C0000h-1CFFFFh E0000h–E7FFFh

SA29 11101xxx 64/32 1D0000h-1DFFFFh E8000h–EFFFFh

SA30 11110 xxx 64/32 1E0000h-1EFFFFh F0000h–F7FFFh

SA31 11111000 8/4 1F0000h-1F1FFFh F8000h–F8FFFh

SA32 11111001 8/4 1F2000h-1F3FFFh F9000h–F9FFFh

SA33 11111010 8/4 1F4000h-1F5FFFh FA000h–FAFFFh

SA34 111110 11 8/4 1F6000h-1F7FFFh FB000h–FBFFFh

SA35 1111110 0 8/4 1F8000h-1F9FFFh FC000h–FCFFFh

SA36 1111110 1 8/4 1FA000h-1FBFFFh FD000h–FDFFFh

SA37 1111111 0 8/4 1FC000h-1FDFFFh FE000h–FEFFFh

SA38 11111111 8/4 1FE000h-1FFFFFh FF000h–FFFFFh

Sector Address

A19–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Ranges

Table 4. SecSi Sector Addresses for Top Boot Devices

SecSi Sector

Entire Sector

Factory Programmed ESN 11111xxx 16 bytes/8 words 1F0000h-1F000Fh F8000h–F8007h

Sector Address

A19–A12

11111xxx 64 Kbytes/32 Kwords 1F0000h-1FFFFFh F8000h–FFFFFh

Size

(x8)

Address Range

(x16)

Address Range

Am29DS163D 13

ADVANCE INFORMATION

Table 5. Bottom Boot Sector Addresses (Am29DS16xDB)

Sector

Am29DS163DB

Bank 1

Bank 2

Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19 and A18 for Am29DS163DB.

SA0 00000000 8/4 000000h-001FFFh 00000h-00FFFh

SA1 00000001 8/4 002000h-003FFFh 01000h-01FFFh

SA2 00000010 8/4 004000h-005FFFh 02000h-02FFFh

SA3 00000011 8/4 006000h-007FFFh 03000h-03FFFh

SA4 00000100 8/4 008000h-009FFFh 04000h-04FFFh

SA5 00000101 8/4 00A000h-00BFFFh 05000h-05FFFh

SA6 00000110 8/4 00C000h-00DFFFh 06000h-06FFFh

SA7 00000111 8/4 00E000h-00FFFFh 07000h-07FFFh

SA8 00001XXX 64/32 010000h-01FFFFh 08000h-0FFFFh

SA9 00010XXX 64/32 020000h-02FFFFh 10000h-17FFFh

SA10 00011XXX 64/32 030000h-03FFFFh 18000h-1FFFFh

SA11 00100XXX 64/32 040000h-04FFFFh 20000h-27FFFh

SA12 00101XXX 64/32 050000h-05FFFFh 28000h-2FFFFh

SA13 00110XXX 64/32 060000h-06FFFFh 30000h-37FFFh

SA14 00111XXX 64/32 070000h-07FFFFh 38000h-3FFFFh

SA15 01000XXX 64/32 080000h-08FFFFh 40000h-47FFFh

SA16 01001XXX 64/32 090000h-09FFFFh 48000h-4FFFFh

SA17 01010XXX 64/32 0A0000h-0AFFFFh 50000h-57FFFh

SA18 01011XXX 64/32 0B0000h-0BFFFFh 58000h-5FFFFh

SA19 01100XXX 64/32 0C0000h-0CFFFFh 60000h-67FFFh

SA20 01101XXX 64/32 0D0000h-0DFFFFh 68000h-6FFFFh

SA21 0 1110X XX 64/32 0E0000h-0EFFFFh 70000h-77FFFh

SA22 01111XXX 64/32 0F0000h-0FFFFFh 78000h-7FFFFh

SA23 10000XXX 64/32 100000h-10FFFFh 80000h-87FFFh

SA24 10001XXX 64/32 110000h-11FFFFh 88000h-8FFFFh

SA25 10010XXX 64/32 120000h-12FFFFh 90000h-97FFFh

SA26 10011XXX 64/32 130000h-13FFFFh 98000h-9FFFFh

SA27 10100XXX 64/32 140000h-14FFFFh A0000h-A7FFFh

SA28 10101XXX 64/32 150000h-15FFFFh A8000h-AFFFFh

SA29 10110XXX 64/32 160000h-16FFFFh B0000h-B7FFFh

SA30 10111XXX 64/32 170000h-17FFFFh B8000h-BFFFFh

SA31 11000XXX 64/32 180000h-18FFFFh C0000h-C7FFFh

SA32 11001XXX 64/32 190000h-19FFFFh C8000h-CFFFFh

SA33 11010XXX 64/32 1A0000h-1AFFFFh D0000h-D7FFFh

SA34 11011XXX 64/32 1B0000h-1BFFFFh D8000h-DFFFFh

SA35 111 00X XX 64/32 1C0000h-1CFFFFh E0000h-E7FFFh

SA36 111 01X XX 64/32 1D0000h-1DFFFFh E8000h-EFFFFh

SA37 11110 XX X 64/32 1E0000h-1EFFFFh F0000h-F7FFFh

SA38 11111 XXX 64/32 1F0000h-1FFFFFh F8000h-FFFFFh

Sector Address

A19–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Table 6. SecSi Sector Addresses for Bottom Boot Devices

SecSi Sector

Entire Sector 00000XXX 64 Kbytes/32 Kwords 000000h-00FFFFh 00000h-07FFFh

Factory Programmed ESN 00000XXX 16 bytes/8 words 000000h-00000Fh 00000h–00007h

Sector Address

A19–A12

Size

(x8)

Address Range

14 Am29DS163D

(x16)

Address Range

ADVANCE INFORMATION

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming al gorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires VID (9.0 V to 11.0 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in

Table 7. Am29DS163D Autoselect Codes (High Voltage Method)

A19

Description CE# OE# WE#

Manufacturer ID: AMD L L H BA X

Device ID: Am29DS163D L L H BA X

Sector Protection Verification

SecSi Sector Indicator Bit (DQ7)

L L H SA X

L L H BA X

A12

A11

A10 A9

Table 7. In addition, when verifying sector protection,

the sector address must appear on the appropriate highest order address bits (see Tables 3–6). Ta b l e 7 shows the remaining address bits that are don’t care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 14. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.

X L X L L X X 01h

X L X L H 22h X 95h (T), 96h (B)

X L X H L X X

X L X H H X X

A1 A0

DQ8 to DQ15

BYTE#

= V

BYTE#

= V

01h (protected),

00h (unprotected)

85h (factory locked),

05h (not factory

locked)

DQ7

DQ0

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Am29DS163D 15

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