AMD Advanced Micro Devices AM29DL400BT-90FI, AM29DL400BT-90FEB, AM29DL400BT-90FE, AM29DL400BT-90FCB, AM29DL400BT-90FC Datasheet

Publication# 21606 Rev: C Amendment/0
Issue Date: May 1998

PRELIMINARY

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

■

Simultaneous Read/Write operations

Ñ Host system can program or erase in one bank,

then immediately and simultaneously read from

the other bank
Ñ Zero latency between read and write operations
Ñ Read-while-erase
Ñ Read-while-program

■

Single power supply operation

Ñ 2.7 to 3.6 volt read and write operations for

battery-powered applications

■

Manufactured on 0.35 µm process technology

High performance

■

Ñ Access times as fast as 70 ns

■

Low current consumption (typical values
at 5 MHz)

Ñ 7 mA active read current
Ñ 21 mA active read-while-program or read-while-

erase current
Ñ 17 mA active program-while-erase-suspended

current
Ñ 200 nA in standby mode
Ñ 200 nA in automatic sleep mode
Ñ Standard t

to transition from automatic sleep mode to

active mode

■

Flexible sector architecture

Ñ Two 16 Kword, two 8 Kword, four 4 Kword, and

six 32 Kword sectors in word mode
Ñ Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

six 64 Kbyte sectors in byte mode
Ñ Any combination of sectors can be erased
Ñ Supports full chip erase

■

Unlock Bypass Program Command

Ñ Reduces overall programming time when

issuing multiple program command sequences

chip enable access time applies

CE

■

Sector protection

Ñ Hardware method of locking a sector to prevent

any program or erase operation within that
sector

Ñ Sectors can be locked in-system or via

programming equipment

Ñ Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■

Top or bottom boot block conÞgurations
available

■

Embedded Algorithms

Ñ Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

Ñ Embedded Program algorithm automatically

programs and veriÞes data at speciÞed address

■

Minimum 1 million program/erase cycles
guaranteed per sector

■

Package options

Ñ 44-pin SO
Ñ 48-pin TSOP

■

Compatible with JEDEC standards

Ñ Pinout and software compatible with

single-power-supply ßash standard

Ñ Superior inadvertent write protection

■

Data# Polling and Toggle Bits

Ñ Provides a software method of detecting

program or erase cycle completion

■

Ready/Busy# output (RY/BY#)

Ñ Hardware method for detecting program or

erase cycle completion

■

Erase Suspend/Erase Resume

Ñ Suspends or resumes erasing sectors to allow

reading and programming in other sectors

Ñ No need to suspend if sector is in the other bank

■

Hardware reset pin (RESET#)

Ñ Hardware method of resetting the device to

reading array data

PRELIMINARY

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only ßash
memory device, organized as 262,144 words or
524,288 bytes. The device is offered in 44-pin SO and
48-pin TSOP packages. The word-wide (x16) data ap­pears on DQ0ÐDQ15; the byte-wide (x8) data appears
on DQ0ÐDQ7. This device requires only a single 3.0
volt V
operations. A standard EPROM programmer can also
be used to program and erase the device.

The standard device offers access times of 70, 80, 90,
and 120 ns, allowing high-speed microprocessors to
operate without wait states. Standard control pinsÑ
chip enable (CE#), write enable (WE#), and output en­able (OE#)Ñcontrol read and write operations, and
avoid bus contention issues.

The device requires only a

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the
program and erase operations.

supply to perform read, program, and erase

CC

single 3.0 volt power sup-

Simultaneous Read/Write Operations with
Zero Latency

The Simultaneous Read/Write architecture provides si-

multaneous operation by dividing the memory space

into two banks. Bank 1 contains boot/parameter sec­tors, and Bank 2 consists of larger, code sectors of uni­form size. The device can improve overall system
performance by allowing a host system to program or
erase in one bank, then immediately and simultane­ously read from the other bank, with zero latency . This
releases the system from waiting for the completion of
program or erase operations.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set
standard . Commands are written to the command

register using standard microprocessor write timings.
Register contents serve as input to an internal state
machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase
operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.

Device programming occurs by executing the program
command sequence. This initiates the Embedded

Program algorithmÑan internal algorithm that auto-

matically times the program pulse widths and veriÞes
proper cell margin. The Unlock Bypass mode facili­tates faster programming times by requiring only two
write cycles to program data instead of four.

Device erasure occurs by executing the erase com­mand sequence. This initiates the
algorithmÑan internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
veriÞes proper cell margin.

The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
been completed, the device automatically returns to
reading array data.

The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.

Hardware data protection measures include a low

V
tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem­ory. This can be achieved in-system or via program­ming equipment.

The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector within that bank that is
not selected for erasure. True background erase can
thus be achieved. There is no need to suspend the
erase operation if the read data is in the other bank.

The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device to reading array data, enabling the sys­tem microprocessor to read the boot-up Þrmware from
the Flash memory.

The device offers two power-saving features. When ad­dresses have been stable for a speciÞed amount of
time, the device enters the automatic sleep mode .
The system can also place the device into the standby

mode . Power consumption is greatly reduced in both

these modes.

AMDÕs Flash technology combines years of Flash mem­ory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The
device electrically erases all bits within a sector simulta­neously via Fowler-Nordheim tunneling. The bytes are
programmed one byte or word at a time using hot elec­tron injection.

status bits . After a program or erase cycle has

detector that automatically inhibits write opera-

CC

Embedded Erase

2 Am29DL400B

PRODUCT SELECTOR GUIDE

PRELIMINARY

Family Part Number

Speed Options (Full Voltage Range: V

= 2.7 Ð 3.6 V)

CC

-70 -80 -90 -120

Am29DL400B

Max Access Time (ns) 70 80 90 120

CE# Access (ns) 70 80 90 120

OE# Access (ns) 30 30 35 50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

V

CC

V

SS

A0–A17

A0–A17

RESET#

WE#

CE#

BYTE#
DQ0–DQ15

RY/BY#

A0–A17A0–A17

STATE

CONTROL

&
COMMAND
REGISTER

Upper Bank Address

Upper Bank

Y-Decoder

X-Decoder

Status

Control

X-Decoder

OE# BYTE#

Latches and Control Logic

DQ0–DQ15

A0–A17

Lower Bank Address

Lower Bank

Y-Decoder

Latches and

Control Logic

OE# BYTE#

DQ0–DQ15 DQ0–DQ15

21606C-1

Am29DL400B 3

CONNECTION DIAGRAMS

PRELIMINARY

A15
A14
A13
A12
A11
A10

A9

A8
NC
NC

WE#

RESET#

NC
NC

RY/BY#

NC

A17

A7

A6

A5

A4

A3

A2

A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A16
BYTE#
V

SS

DQ15/A-1
DQ7
DQ14
DQ6

DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10

DQ2
DQ9
DQ1
DQ8
DQ0
OE#

V

SS

CE#
A0

A16

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V

CC

DQ11

DQ3

DQ10

DQ2
DQ9
DQ1
DQ8
DQ0

OE#

V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Reverse TSOP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A15
A14

A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1

21606C-2

4 Am29DL400B

CONNECTION DIAGRAMS

PRELIMINARY

RY/BY#

NC

A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

OE#
DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

SS

10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9

SO

44

RESET#

43

WE#

42

A8

41

A9

40

A10

39

A11

38

A12

37

A13

36

A14

35

A15

34

A16

33

BYTE#

32

V
DQ15/A-1

31

DQ7

30

DQ14

29

DQ6

28

DQ13

27

DQ5

26

DQ12

25

DQ4

24

V

23

SS

CC

21606C-3

Am29DL400B 5

21606C-4

18

16 or 8

DQ0ÐDQ15

(A-1)

A0ÐA17

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

PRELIMINARY

PIN DESCRIPTION

A0-A17 = 18 Addresses
DQ0-DQ14 = 15 Data Inputs/Outputs
DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
BYTE# = Selects 8-bit or 16-bit mode
RESET# = Hardware Reset Pin, Active Low
RY/BY# = Ready/Busy Output

= 3.0 volt-only single power supply

V

CC

V

SS

NC = Pin Not Connected Internally

(see Product Selector Guide for speed
options and voltage supply tolerances)

= Device Ground

LOGIC SYMBOL

6 Am29DL400B

PRELIMINARY

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:

AM29DL400B -70

T

E

C

OPTIONAL PROCESSING

Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0¡C to +70¡C)
I = Industrial (Ð40¡C to +85¡C)
E = Extended (Ð55¡C to +125¡C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

AM29DL400BT-70
AM29DL400BB-70

AM29DL400BT-80
AM29DL400BB-80

AM29DL400BT-90
AM29DL400BB-90

AM29DL400BT-120
AM29DL400BB-120

DEVICE NUMBER/DESCRIPTION

Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

EC, EI, FC, FI,

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

SC, SI

Valid Combinations

Valid Combinations list conÞgurations planned to be sup­ported in volume for this device. Consult the local AMD sales
ofÞce to conÞrm availability of speciÞc valid combinations to
check on newly released combinations.

Am29DL400B 7

±

±

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it­self does not occupy any addressable memory loca­tion. The register is a latch used to store the
commands, along with the address and data informa­tion needed to execute the command. The contents of

Table 1. Am29DL400B Device Bus Operations

Operation CE# OE# WE# RESET#

Read L L H H A
Write L H L H A

Standby

CC

0.3 V

XX

V

Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Unprotect (Note 2) L H L V

Temporary Sector Unprotect X X X V

Legend:

L = Logic Low = V

, H = Logic High = V

IL

, V

= 12.0

IH

ID

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

V

CC

0.3 V

0.5 V, X = Don’t Care, A

±

), A17:A-1 in byte mode (BYTE# = V

IH

the register serve as inputs to the internal state ma­chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.

DQ8ÐDQ15

Sector Address,

A6 = L, A1 = H,

ID

Sector Address,
A6 = H, A1 = H,

ID

ID

Addresses

(Note 1)

IN

IN

X High-Z High-Z High-Z

A0 = L

A0 = L

A

IN

DQ0Ð

DQ7

D

OUT

D

IN

D

IN

D

IN

D

IN

= Address In, D

IN

IL

BYTE#

= V

IH

D

DQ8ÐDQ14 = High-Z,

OUT

D

IN

DQ15 = A-1

XX

XX

D

IN

= Data In, D

IN

).

BYTE#

= V

IL

High-Z

= Data Out

OUT

Word/Byte ConÞguration

The BYTE# pin controls whether the device data I/O
pins operate in the byte or word conÞguration. If the
BYTE# pin is set at logic Ô1Õ, the device is in word con­Þguration, DQ0-15 are active and controlled by CE#
and OE# .

If the BYTE# pin is set at logic Ô0Õ, the device is in byte
conÞguration, and only data I/O pins DQ0ÐDQ7 are ac­tive and controlled by CE# and OE#. The data I/O pins
DQ8ÐDQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con­trol and gates array data to the output pins. WE# should
remain at V

. The BYTE# pin determines whether the

IH

device outputs array data in words or bytes.

. CE# is the power

IL

The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem­ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as­sert valid addresses on the device address inputs pro­duce valid data on the device data outputs. Each bank
remains enabled for read access until the command
register contents are altered.

See ÒReading Array DataÓ for more information. Refer
to the AC Read-Only Operations table for timing spec­ifications and to Figure 13 for the timing diagram. I

in the DC Characteristics table represents the active
current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in­cludes programming data to the device and erasing

8 Am29DL400B

CC1

PRELIMINARY

±

sectors of memory), the system must drive WE# and
CE# to V

, and OE# to V

IL

.

IH

For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to ÒWord/Byte ConÞgurationÓ for more in­formation.

The device features an Unlock Bypass mode to facili­tate faster programming. Once a bank enters the Unlock
Bypass mode, only two write cycles are required to pro­gram a word or byte, instead of four. The ÒByte/Word
Program Command SequenceÓ section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec­tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con­tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A Òbank ad­dressÓ is the address bits required to uniquely select a
bank. Similarly, a Òsector addressÓ is the address bits
required to uniquely select a sector.

If the system writes the autoselect command se­quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter­nal register (which is separate from the memory array)
on DQ7ÐDQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.

in the DC Characteristics table represents the ac-

I

CC2

tive current specification for the write mode. The AC
Characteristics section contains timing speciÞcation ta­bles and timing diagrams for write operations.

Simultaneous Read/Write Operations with
Zero Latency

This device is capable of reading data from one bank of
memory while programming or erasing in the other
bank of memory. An erase operation may also be sus­pended to read from or program to another location
within the same bank (except the sector being erased).

Figure 19 shows how read and write cycles may be in­itiated for simultaneous operation with zero latency.
I

CC6

and I

in the DC Characteristics table represent

CC7

the current speciÞcations for read-while-program and
read-while-erase, respectively.

Standby Mode

When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde­pendent of the OE# input.

The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V

CC

0.3 V.
(Note that this is a more restricted voltage range than
V

.) If CE# and RESET# are held at V

IH

V

±

0.3 V, the device will be in the standby mode, but

CC

, but not within

IH

the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.

The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
ÒRESET#: Hardware Reset PinÓ.

If the device is deselected during erasure or program­ming, the device draws active current until the
operation is completed.

I

in the DC Characteristics table represents the

CC3

standby current speciÞcation.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I

CC4

Characteristics table represents the automatic sleep
mode current speciÞcation.

+ 30

ACC

in the DC

Am29DL400B 9

PRELIMINARY

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re­setting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP,
the device
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma­chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en­sure data integrity.

Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at VIL but not within VSS±0.3 V, the standby current will
be greater.

The RESET# pin may be tied to the system reset cir­cuitry. A system reset would thus also reset the Flash

immediately terminates

SS

). If RESET# is held

CC4

any operation in

±0.3 V, the device

memory, enabling the system to read the boot-up
Þrmware from the Flash memory.

If RESET# is asserted during a program or erase op­eration, the RY/BY# pin remains a Ò0Ó (busy) until the
internal reset operation is complete, which requires a
time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex­ecuting (RY/BY# pin is Ò1Ó), the reset operation is
completed within a time of t

(not du ring Embed-

READY

ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa­rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped­ance state.

10 Am29DL400B

PRELIMINARY

Table 2. Am29DL400BT Top Boot Sector Architecture

Sector Address

Bank Sector

SA0 0 0 0 X X X 64/32 00000hÐ0FFFFh 00000hÐ07FFFh

SA1 0 0 1 X X X 64/32 10000hÐ1FFFFh 08000hÐ0FFFFh

SA2 0 1 0 X X X 64/32 20000hÐ2FFFFh 10000hÐ17FFFh

Bank 2

SA3 0 1 1 X X X 64/32 30000hÐ3FFFFh 18000hÐ1FFFFh

SA4 1 0 0 X X X 64/32 40000hÐ4FFFFh 20000hÐ27FFFh

SA5 1 0 1 X X X 64/32 50000hÐ5FFFFh 28000hÐ2FFFFh

SA6 11000X 16/8 60000hÐ63FFFh 30000hÐ31FFFh

SA7 1 1 0

SA8 110110 8/4 6C000hÐ6DFFFh 36000hÐ36FFFh

SA9 110111 8/4 6E000hÐ6FFFFh 37000hÐ37FFFh

Bank 1

SA10 111000 8/4 70000hÐ71FFFh 38000hÐ38FFFh

SA11 111001 8/4 72000hÐ73FFFh 39000hÐ39FFFh

SA12 1 1 1

Bank

Address

Sector Size

(Kbytes/

A15 A14 A13 A12A17 A16

01X

10X

01X

10X

Kwords)

32/16 64000hÐ6BFFFh 32000hÐ35FFFh

32/16 74000hÐ7BFFFh 3A000hÐ3DFFFh

(x8)

Address Range

(x16)

Address Range

SA13 11111X 16/8 7C000hÐ7FFFFh 3E000hÐ3FFFFh

Note: The address r ange is A17:A-1 if in b yte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).

Am29DL400B 11

Bank Sector

SA13 1 1 1 X X X 64/32 70000hÐ7FFFFh 38000hÐ3FFFFh

SA12 1 1 0 X X X 64/32 60000hÐ6FFFFh 30000hÐ37FFFh

Bank

Address

PRELIMINARY

Table 3. Am29DL400BB Bottom Boot Sector Architecture

Sector Address

Sector Size

A15 A14 A13 A12A17 A16

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Bank 2

Bank 1

Note: The address r ange is A17:A-1 if in b yte mode (BYTE# = VIL). The address range is A17:A0 if in word mode (BYTE# = VIH).

Autoselect Mode

The autoselect mode provides manufacturer and de­vice identiÞcation, and sector protection veriÞcation,
through identiÞer codes output on DQ7ÐDQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.

When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in

SA11 1 0 1 X X X 64/32 50000hÐ5FFFFh 28000hÐ2FFFFh

SA10 1 0 0 X X X 64/32 40000hÐ4FFFFh 20000hÐ27FFFh

SA9 0 1 1 X X X 64/32 30000hÐ3FFFFh 18000hÐ1FFFFh

SA8 0 1 0 X X X 64/32 20000hÐ2FFFFh 10000hÐ17FFFh

SA7 00111X 16/8 1C000hÐ1FFFFh 0E000hÐ0FFFFh

SA6 0 0 1

SA5 001001 8/4 12000hÐ13FFFh 09000hÐ09FFFh

SA4 001000 8/4 10000hÐ11FFFh 08000hÐ08FFFh

SA3 000111 8/4 0E000hÐ0FFFFh 07000hÐ07FFFh

SA2 000110 8/4 0C000hÐ0DFFFh 06000hÐ06FFFh

SA1 0 0 0

SA0 00000X 16/8 00000hÐ03FFFh 00000hÐ01FFFh

10X

32/16 14000hÐ1BFFFh 0A000hÐ0DFFFh

01X

10X

32/16 04000hÐ0BFFFh 02000hÐ05FFFh

01X

Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are donÕt care.
When all necessary bits have been set as required, the
programming equipment may then read the corre­sponding identiÞer code on DQ7-DQ0.

To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. Refer to the Autoselect Command
Sequence section for more information.

12 Am29DL400B

PRELIMINARY

START

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = V

ID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once
again.

21606C-5

Table 4. Am29DL400B Autoselect Codes (High Voltage Method)

Description Mode CE# OE# WE#

A17

to

A12

A11

to

A10 A9

A8

to

A7 A6

A5

to

A2 A1 A0

DQ8

to

DQ15

DQ7

to

DQ0

Manufacturer ID: AMD L L H BA X V

Device ID:
Am29DL400B
(Top Boot Block)

Device ID:
Am29DL400B
(Bottom Boot Block)

Sector Protection VeriÞcation L L H SA X V

Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Word L L H

BA X V

Byte L L H X 0C

Word L L H

BA X V

Byte L L H X 0F

Sector Protection/Unprotection

The hardware sector protection feature disables both
program and erase operations in any sector. The hard­ware sector unprotection feature re-enables both pro­gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple­mented via two methods.

XLXLL X 01h

ID

22h 0C

XLXLH

ID

22h 0F

XLXLH

ID

XLXHL

ID

RESET# pin to VID (11.5 V Ð 12.5 V). During this
mode, formerly protected sectors can be programmed
or erased by selecting the sector addresses. Once V
is removed from the RESET# pin, all the previously
protected sectors are protected again. Figure 1
shows the algorithm, and Figure 23 shows the timing
diagrams, for this feature.

The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo­rithms and Figure 24 shows the timing diagram. This
method uses standard microprocessor bus cycle tim­ing. For sector unprotect, all unprotected sectors must
Þrst be protected prior to the Þrst sector unprotect
write cycle.

X

X

01h

(protected)

00h

(unprotected)

ID

The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD ßash devices. Pub­lication number 22145 contains further details; contact
an AMD representative to request a copy.

The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMDÕs ExpressFlashª Service. Contact an
AMD representative for details.

It is possible to determine whether a sector is pro­tected or unprotected. See the Autoselect Mode sec­tion for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ­ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the

Figure 1. Temporary Sector Unprotect Operation

Am29DL400B 13

PRELIMINARY

Temporary Sector

Unprotect Mode

Increment

PLSCNT

No

PLSCNT

= 25?

Yes

Device failed

Sector Protect

Algorithm

START

PLSCNT = 1

RESET# = V

Wait 1 ms

No

First Write

Cycle = 60h?

Set up sector

address

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

No

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

Yes

No

START

Protect all sectors:

The indicated portion

of the sector protect

ID

Reset

PLSCNT = 1

Yes

ID

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Increment

PLSCNT

No

PLSCNT

= 1000?

Yes

Device failed

Sector Unprotect

PLSCNT = 1

RESET# = V

Wait 1 ms

First Write

Cycle = 60h?

No

All sectors

protected?

Set up first sector

address

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

No

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Yes

Yes

Yes

Yes

ID

No

Temporary Sector

Unprotect Mode

Set up

next sector

address

No

ID

Algorithm

Write reset

command

Figure 2. In-System Sector Protect/Unprotect Algorithms

14 Am29DL400B

Sector Unprotect

complete

21606C-6

PRELIMINARY

Hardware Data Protection

The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com­mand deÞnitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than V
any write cycles. This protects data during V

, the device does not accept

LKO

CC

power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets to reading array data. Subsequent writes
are ignored until VCC is greater than V

. The system

LKO

must provide the proper signals to the control pins to

COMMAND DEFINITIONS

Writing speciÞc address and data commands or se­quences into the command register initiates device op­erations. Table 5 deÞnes the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.

All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
Þrst. Refer to the appropriate timing diagrams in the AC
Characteristics section.

Reading Array Data

The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.

After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-suspend­read mode, after which the system can read data from
any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the Erase
Suspend/Erase Resume Commands section for more
information.

The system
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.

See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.

must

issue the reset command to return a

prevent unintentional writes when V
V

.

LKO

is greater than

CC

Write Pulse ÒGlitchÓ Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.

Power-Up Write Inhibit

If WE# = CE# = V

and OE# = VIH during power up, the

IL

device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.

The Read-Only Operations table provides the read pa­rameters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
donÕt cares for this command.

The reset command may be written between the se­quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys­tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.

The reset command may be written between the se­quence cycles in a program command sequence be­fore programming begins. This resets the bank to
which the system was writing to the reading array
data. If the program command sequence is written to
a bank that is in the Erase Suspend mode, writing the
reset command returns that bank to the erase-sus­pend-read mode. Once programming begins, how­ever, the device ignores reset commands until the
operation is complete.

The reset command may be written between the se­quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data. If a bank en­tered the autoselect mode while in the Erase Suspend
mode, writing the reset command returns that bank to
the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to reading
array data (or erase-suspend-read mode if that bank
was in Erase Suspend).

Am29DL400B 15

PRELIMINARY

Autoselect Command Sequence

The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
on address pin A9. The autoselect command sequence
may be written to an address within a bank that is either
in the read or erase-suspend-read mode. The autose­lect command may not be written while the device is
actively programming or erasing in the other bank.

The autoselect command sequence is initiated by Þrst
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au­toselect command. The addressed bank then enters
the autoselect mode. The system may read at any ad­dress within the same bank any number of times with­out initiating another autoselect command sequence:

■ A read cycle at address (BA)XX00h (where BA is

the bank address) returns the manufacturer code.

■ A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device
code.

■ A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address
02h on A7ÐA0 in word mode (or the address 04h on
A6ÐA-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. Refer to Tables
2 and 3 for valid sector addresses.

The system may continue to read array data from the
other bank while a bank is in the autoselect mode. To
exit the autoselect mode, the system must write the
reset command to return both banks to reading array
data. If a bank enters the autoselect mode while
erase suspended, a reset command returns that
bank to the erase-suspend-read mode. A subsequent
Erase Resume command returns the bank to the
erase operation.

ID

Byte/Word Program Command Sequence

The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program­ming is a four-bus-cycle operation. The program com­mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is
ings. The device automatically generates the program
pulses and veriÞes the programmed cell margin. Table

not

required to provide further controls or tim-

5 shows the address and data requirements for the
byte program command sequence.

When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad­dresses are no longer latched. The system can deter­mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. Note that while the Embedded Pro­gram operation is in progress, the system can read
data from the non-programming bank. Refer to the
Write Operation Status section for information on these
status bits.

Any commands written to the device during the Em­bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.

Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from Ò0Ó back to a Ò1.Ó Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was suc­cessful. However, a succeeding read will show that
the data is still Ò0.Ó Only erase operations can convert
a Ò0Ó to a Ò1.Ó

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro­gram bytes or words to a bank faster than using the
standard program command sequence. The unlock by­pass command sequence is initiated by Þrst writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The Þrst cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program­ming time. Table 5 shows the requirements for the com­mand sequence.

During the unlock bypass mode, only the Unlock By­pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com­mand sequence. The Þrst cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
reading array data.

16 Am29DL400B

PRELIMINARY

Figure 3 illustrates the algorithm for the program oper­ation. Refer to the Erase and Program Operations table
in the AC Characteristics section for parameters, and
Figure 17 for timing diagrams.

START

Write Program

Command Sequence

Data Poll

Embedded

Program

algorithm

in progress

from System

Verify Data?

Yes

No

status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.

Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im­mediately terminates the erase operation. If that oc­curs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera­tion. Refer to the Erase and Program Operations tables
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad­ditional unlock cycles are written, and are then fol­lowed by the address of the sector to be erased, and
the sector erase command. Table 5 shows the ad­dress and data requirements for the sector erase
command sequence.

Increment Address

Note: See Table 5 for program command sequence.

No

Last Address?

Yes

Programming

Completed

21606C-7

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
preprogram prior to erase. The Embedded Erase algo­rithm automatically preprograms and veriÞes the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con­trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.

When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the

not

require the system to

The device does

not

require the system to preprogram
prior to erase. The Embedded Erase algorithm auto­matically programs and veriÞes the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim­ings during these operations.

After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com­mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec­tors may be from one sector to all sectors. The time be­tween these additional cycles must be less than 50 µs,
otherwise the last address and command may not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets
that bank to reading array data. The system must re-

write the command sequence and any additional ad­dresses and commands.

The system can monitor DQ3 (in the erasing bank) to
determine if the sector erase timer has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out
begins from the rising edge of the Þnal WE# pulse in the
command sequence.

When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from

Am29DL400B 17

PRELIMINARY

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

No

Yes

Erasure Completed

Embedded
Erase
algorithm
in progress

21606C-8

the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing bank. Refer to the Write
Operation Status section for information on these sta­tus bits.

Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset im­mediately terminates the erase operation. If that oc­curs, the sector erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera­tion. Refer to the Erase and Program Operations tables
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the sys­tem to interrupt a sector erase operation and then
read data from, or program data to, any sector not se­lected for erasure. The bank address is required when
writing this command. This command is valid only dur­ing the sector erase operation, including the 50 µs
time-out period during the sector erase command se­quence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm.

program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation. Refer
to the Write Operation Status section for more infor­mation.

In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.

To resume the sector erase operation, the system must
write the Erase Resume command. The bank address
of the erase-suspended bank is required when writing
this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.

When the Erase Suspend command is written during
the sector erase operation, the device requires a max­imum of 20 µs to suspend the erase operation. How­ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi­ately terminates the time-out period and suspends the
erase operation.

After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys­tem can read data from or program data to any sector
not selected for erasure. (The device Òerase suspendsÓ
all sectors selected for erasure.) Reading at any ad­dress within erase-suspended sectors produces status
information on DQ7ÐDQ0. The system can use DQ7,
or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.

After an erase-suspended program operation is com­plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the

Notes:

1. See Table 5 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

18 Am29DL400B

PRELIMINARY

Table 5. Am29DL400B Command DeÞnitions

Command

Sequence

(Note 1)

Read (Note 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Manufacturer ID

Device ID,
Top Boot Block

Device ID,
Bottom Boot Block

Autoselect (Note 8)

Sector Protect
Verify (Note 9)

Program

Unlock Bypass

Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 BA 90 XXX 00

Chip Erase

Sector Erase

Erase Suspend (Note 12) 1 BA B0

Erase Resume (Note 13) 1 BA 30

Word

Byte AAA 555 (BA)AAA

Word

Byte AAA 555 (BA)AAA (BA)X02 0C

Word

Byte AAA 555 (BA)AAA (BA)X02 0F

Word

Byte AAA 555 (BA)AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555 AAA

Word

Byte AAA 555 AAA AAA 555

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Cycles

555

4

555

4

555

4

555

4

555

4

555

3

555

6

555

6

AA

AA

AA

AA

AA

AA

AA

AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

55

55

55

55

55

55

55

55

Bus Cycles (Notes 2Ð5)

(BA)555

(BA)555

(BA)555

(BA)555

555

555

555

555

90 (BA)X00 01

(BA)X01 220C

90

(BA)X01 220F

90

90

A0 PA PD

20

80

80

(SA)

X02

(SA)

X04

555

555

XX00

XX01

00

01

AA

AA

2AA

2AA

555

55

55 SA 30

10

Legend:

X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles
are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles in word mode.

5. Address bits A17–A11 are don’t cares for unlock and
command cycles, unless bank address (BA) is required.

6. No unlock or command cycles required when bank is in read
mode.

7. The Reset command is required to return to reading array
data (or to the erase-suspend-read mode if previously in
Erase Suspend) when a bank is in the autoselect mode, or if
DQ5 is goes high (while the bank is providing status
information).

PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.

BA = Address of the bank that is being switched to autoselect
mode, is in bypass mode, or is being erased. Address bits A17–
A16 select a bank.

8. The fourth cycle of the autoselect command sequence is a
read cycle. The system must provide the bank address to
obtain the manufacturer or device ID information.

9. The data is 00h for an unprotected sector and 01h for a
protected sector. See the Autoselect Command Sequence
section for more information.

10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.

11. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass
mode.

12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector
erase operation, and requires the bank address.

13. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.

Am29DL400B 19

PRELIMINARY

DQ7 = Data?

Yes

No

No

DQ5 = 1?

No

Yes

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

21606C-9

WRITE OPERATION STATUS

The device provides several bits to determine the sta­tus of a write operation in the bank where a program or
erase operation is in progress: DQ2, DQ3, DQ5, DQ6,
DQ7, and RY/BY#. Table 6 and the following subsec­tions describe the function of these bits. DQ7, RY/BY#,
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. These three bits are discussed Þrst.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys­tem whether an Embedded Program or Erase algo­rithm is in progress or completed, or whether a bank is
in Erase Suspend. Data# Polling is valid after the rising
edge of the Þnal WE# pulse in the command sequence.

During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro­grammed to DQ7. This DQ7 status also applies to pro­gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap­proximately 1 µs, then that bank returns to reading
array data.

invalid. Valid data on DQ0ÐDQ7 will appear on succes­sive read cycles.

Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics section shows the Data# Poll­ing timing diagram.

During the Embedded Erase algorithm, Data# Polling
produces a Ò0Ó on DQ7. When the Embedded Erase al­gorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a Ò1Ó on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor­mation on DQ7.

After an erase command sequence is written, if all sec­tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the
bank returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se­lected sectors that are protected. However, if the sys­tem reads DQ7 at an address within a protected sector,
the status may not be valid.

Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0ÐDQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing sta­tus information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com­pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0ÐDQ6 may be still

Notes:

1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase , a v alid
address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

20 Am29DL400B

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the Þnal WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev­eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.

If the output is low (Busy), the device is actively eras­ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data, is in
the standby mode, or one of the banks is in the erase­suspend-read mode.

Table 6 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address within
the programming or erasing bank, and is valid after the
rising edge of the Þnal WE# pulse in the command se­quence (prior to the program or erase operation), and
during the sector erase time-out.

During an Embedded Program or Erase algorithm op­eration, successive read cycles to any address within
the programming or erasing bank cause DQ6 to toggle.
The system may use either OE# or CE# to control the
read cycles. When the operation is complete, DQ6
stops toggling.

After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog­gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro­tected sectors, and ignores the selected sectors that
are protected.

The system can use DQ6 and DQ2 together to deter­mine whether a sector is actively erasing or is erase­suspended. When a bank is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When that bank enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.

DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro­gram algorithm is complete.

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig­ure 6 shows the toggle bit algorithm. Figure 21 in the
ÒAC CharacteristicsÓ section shows the toggle bit timing
diagrams. Figure 22 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec­tion on DQ2: Toggle Bit II.

DQ2: Toggle Bit II

The ÒToggle Bit IIÓ on DQ2, when used with DQ6, indi­cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the Þnal WE# pulse in
the command sequence.

DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras­ure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot dis­tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode infor­mation. Refer to Table 6 to compare outputs for DQ2
and DQ6.

Figure 6 shows the toggle bit algorithm in ßowchart
form, and the section ÒDQ2: Toggle Bit IIÓ explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7ÐDQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
Þrst read. After the second read, the system would com­pare the new value of the toggle bit with the Þrst. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7ÐDQ0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys­tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not

Am29DL400B 21

PRELIMINARY

completed the operation successfully, and the system
must write the reset command to return to reading
array data.

The remaining scenario is that the system initially de­termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de­termining the status as described in the previous para­graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).

START

Read DQ7–DQ0

Read DQ7–DQ0

No

No

No

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has
exceeded a speciÞed internal pulse count limit. Under
these conditions DQ5 produces a Ò1,Ó indicating that the
program or erase cycle was not successfully completed.

The device may output a Ò1Ó on DQ5 if the system tries
to program a Ò1Ó to a location that was previously pro­grammed to Ò0.Ó Only an erase operation can change
a Ò0Ó back to a Ò1.Ó Under this condition, the device
halts the operation, and when the timing limit has been
exceeded, DQ5 produces a Ò1Ó.

Under both these conditions, the system must write the
reset command to return to reading array data (or to the
erase-suspend-read mode if a bank was previously in
the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also ap­plies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a Ò0Ó to a Ò1Ó. If the system can guarantee the time
between additional sector erase commands to be less
than 50 µs, it need not monitor DQ3. See also the Sec­tor Erase Command Sequence section.

After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
Ò1Ó, the Embedded Erase algorithm has begun; all fur­ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is Ò0Ó, the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys­tem software should check the status of DQ3 prior to
and following each subsequent sector erase command.
If DQ3 is high on the second status check, the last com­mand might not have been accepted.

Table 6 shows the status of DQ3 relative to the other
status bits.

Yes

Program/Erase

Operation Not
Complete, Write
Reset Command

Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.

Program/Erase

Operation Complete

Figure 6. Toggle Bit Algorithm

22 Am29DL400B

PRELIMINARY

Table 6. Write Operation Status

Standard
Mode

Erase
Suspend
Mode

DQ7

Status

Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Erase-Suspend­Read

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Suspended Sector
Non-Erase

Suspended Sector

(Note 2) DQ6

1 No toggle 0 N/A Toggle 1

Data Data Data Data Data 1

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Ref er to the appropriate subsection for further details.

3. When reading write operation status bits, the system must alwa ys provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.

Am29DL400B 23

PRELIMINARY

20 ns

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

20 ns

2.0 V

21606C-12

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . Ð65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . Ð65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . . Ð0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . . Ð0.5 V to +12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . .Ð0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins ma y undershoot V
to –2.0 V f or periods of up to 20 ns. Maximum DC v oltage
on input or I/O pins is V
voltage transitions, input or I/O pins ma y overshoot to V
+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
to 20 ns. See Figure 7. Maximum DC input v oltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.

3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.

Stresses above those listed under “Absolute Maximum Rat­ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera­tional sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for ex­tended periods may affect device reliability.

+0.5 V. See Figure 7. During

CC

to –2.0 V f or periods of up

SS

SS

CC

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA). . . . . . . . . . . . 0ûC to +70ûC

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . . Ð40ûC to +85ûC

Extended (E) Devices

Ambient Temperature (TA). . . . . . . . . Ð55ûC to +125ûC

VCC Supply Voltages

VCC for all devices. . . . . . . . . . . . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

20 ns

21606C-11

+0.8 V

Ð0.5 V

Ð2.0 V

20 ns

20 ns

Figure 7. Maximum Negative

Overshoot Waveform

24 Am29DL400B

Figure 8. Maximum Positive

Overshoot WaveformOperating Ranges

PRELIMINARY

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

= VSS to VCC,

V

IN

V

= VCC

CC

CC max

= VSS to VCC,

V

OUT

V

= V

CC

CC max

CE# = V

IL,

Byte Mode

CE# = V

IL,

Word Mode

max

±1.0 µA

; A9 = 12.5 V 35 µA

±1.0 µA

OE# = VIH,

5 MHz 7 12

1 MHz 2 4

OE# = VIH,

5 MHz 7 12

1 MHz 2 4

I

I

I

CC1

I

LI

LIT

LO

Input Load Current

A9 Input Load Current VCC = V

Output Leakage Current

VCC Active Read Current
(Note 1)

mA

I

CC2

I

CC3

I

CC4

I

CC5

I

CC6

I

CC7

I

CC8

V

V

V

VCC Active Write Current
(Note 2)

VCC Standby Current
(CE# Controlled)

VCC Reset Current
(RESET# Controlled)

Automatic Sleep Mode (Note 3)

VCC Active Read-While­Program Current (Notes 1, 4)

VCC Active Read-While-Erase
Current (Notes 1, 4)

VCC Active Program-While­Erase-Suspended Current
(Note 4)

IL

IH

ID

Input Low Voltage Ð0.5 0.8 V

Input High Voltage 0.7 x V

Voltage for Autoselect and
Temporary Sector Unprotect

CE# = V

VCC = V
CE#, RESET# = V

VCC = V
RESET# = V

= V

V

IH

V

IL

CE# = V
OE# = V

CE# = V
OE# = V

CE# = V
OE# = V

V

CC

OE# = VIH, WE# = V

IL,

CC max

CC max

SS

± 0.3 V;

CC

= V

± 0.3 V

SS

IL,

IH

IL,

IH

IL,

IH

; OE# = VIL;

± 0.3 V

CC

;

± 0.3 V

IL

Byte 21 45

Word 21 45

Byte 21 45

Word 21 45

CC

15 30 mA

0.2 5 µA

0.2 5 µA

0.2 5 µA

17 35 mA

VCC + 0.3 V

= 3.0 V ± 10% 11.5 12.5 V

mA

mA

V

V

V

V

OH1

OH2

OL

LKO

Output Low Voltage IOL = 4.0 mA, VCC = V

IOH = Ð2.0 mA, VCC = V

Output High Voltage

IOH = Ð100 µA, VCC = V

Low VCC Lock-Out Voltage
(Note 4)

0.45 V

CC min

0.85 V

CC min

VCCÐ0.4

CC min

2.3 2.5 V

Notes:

1. The I

2. I

current listed is typically less than 2 mA/MHz, with OE# at VIH.

CC

active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t
current is 200 nA.

4. Not 100% tested.

Am29DL400B 25

CC

+ 30 ns. Typical sleep mode

ACC

V

DC CHARACTERISTICS

Zero-Power Flash

20

15

10

5

Supply Current in mA

0

0 500 1000 1500 2000 2500 3000 3500 4000

PRELIMINARY

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9. I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

6

4

Supply Current in mA

2

0

1 2345

21606C-13

3.6 V

2.7 V

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

26 Am29DL400B

21606C-14

TEST CONDITIONS

Device

Under

Test

C

L

6.2 kW

PRELIMINARY

3.3 V

Test Condition -70, -80

2.7 kW
Output Load 1 TTL gate

Output Load Capacitance, C
(including jig capacitance)

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0Ð3.0 V

Table 7. Test SpeciÞcations

others Unit

L

30 100 pF

All

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

DonÕt Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

21606C-15

Input timing measurement
reference levels

Output timing measurement
reference levels

Steady

Changing from H to L

Changing from L to H

1.5 V

1.5 V

3.0 V

0.0 V

1.5 V 1.5 V

Figure 12. Input Waveforms and Measurement Levels

Am29DL400B 27

KS000010-PAL

OutputMeasurement LevelInput

21606C-16

AC CHARACTERISTICS

Read-Only Operations

PRELIMINARY

Parameter

JEDEC Std -70 -80 -90 -120 Unit

t

AVAV

t

AVQVtACC

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

Description Test Setup

t

Read Cycle Time (Note 1) Min 70 80 80 120 ns

RC

Address to Output Delay CE#, OE# = VILMax 70 80 80 120 ns

t

Chip Enable to Output Delay OE# = V

CE

t

Output Enable to Output Delay Max 30 30 35 50 ns

OE

t

Chip Enable to Output High Z (Note 1) Max 25 25 30 30 ns

DF

t

Output Enable to Output High Z (Note 1) Max 25 25 30 30 ns

DF

Output Hold Time From Addresses, CE# or

t

OH

OE#, Whichever Occurs First

Max 70 80 80 120 ns

IL

Min 0 ns

Speed Options

Read Min 0 ns

Output Enable Hold

t

OEH

Time (Note 1)

Toggle and
Data# Polling

Min 10 ns

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t

RC

Addresses

CE#

OE#

WE#

Outputs

RESET#

RY/BY#

0 V

Addresses Stable

t

ACC

t

RH

t

RH

t

OEH

t

OE

t

CE

HIGH Z

Figure 13. Read Operation Timings

t

OH

Output Valid

t

DF

HIGH Z

21606C-17

28 Am29DL400B

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Description All Speed Options UnitJEDEC Std

PRELIMINARY

t

Ready

t

Ready

t

RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)

t

RESET# Pulse Width Min 500 ns

RP

t

Reset High Time Before Read (See Note) Min 50 ns

RH

RESET# Low to Standby Mode Min 20 µs

RPD

t

RY/BY# Recovery Time Min 0 ns

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t

RP

t

Ready

Max 20 µs

Max 500 ns

t

RH

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t

Ready

RY/BY#

t

RB

CE#, OE#

RESET#

t

RP

21606C-18

Figure 14. Reset Timings

Am29DL400B 29

PRELIMINARY

AC CHARACTERISTICS
Word/Byte ConÞguration (BYTE#)

Parameter

-70 -80 -90 -120JEDEC Std Description Unit

t

ELFL/tELFH

t

FLQZ

t

FHQV

BYTE#

Switching

from word

to byte

mode

CE# to BYTE# Switching Low or High Max ns

BYTE# Switching Low to Output HIGH Z Max 25 25 30 30 ns

BYTE# Switching High to Output Active Min 70 80 90 120 ns

CE#

OE#

BYTE#

t

DQ0ÐDQ14

DQ15/A-1

ELFL

t

ELFH

Data Output

(DQ0ÐDQ14)

DQ15

Output

t

FLQZ

Data Output

(DQ0ÐDQ7)

Address

Input

BYTE#

BYTE#

Switching

from byte

to word

DQ0ÐDQ14

Data Output
(DQ0ÐDQ7)

mode

DQ15/A-1

Address

Input

t

FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(tAS)

t

HOLD

(tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

Data Output

(DQ0ÐDQ14)

DQ15

Output

21606C-19

21606C-20

30 Am29DL400B

AC CHARACTERISTICS

Erase and Program Operations

Parameter

PRELIMINARY

-70 -80 -90 -120JEDEC Std Description Unit

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHDL

t

WHWH1tWHWH1

t

WC

t

AS

t

ASO

t

AH

t

AHT

t

DS

t

DH

t

OEPH

t

GHWL

t

CS

t

CH

t

WP

t

WPH

t

SR/W

Write Cycle Time (Note 1) Min 70 80 90 120 ns

Address Setup Time Min 0 ns

Address Setup Time to OE# low during toggle bit polling Min 45 45 45 50 ns

Address Hold Time Min 45 45 45 50 ns

Address Hold Time From CE# or OE# high
during toggle bit polling

Min 0 ns

Data Setup Time Min 35 35 45 50 ns

Data Hold Time Min 0 ns

Output Enable High during toggle bit polling Min 20 20 20 25 ns

Read Recovery Time Before Write
(OE# High to WE# Low)

Min 0 ns

CE# Setup Time Min 0 ns

CE# Hold Time Min 0 ns

Write Pulse Width Min 35 35 35 50 ns

Write Pulse Width High Min 30 ns

Zero Latency Between Read and Write Operations Min 0 ns

Byte Typ 9

Programming Operation (Note 2)

µs

Word Typ 11

t

WHWH2tWHWH2

t

VCS

t

t

BUSY

Sector Erase Operation (Note 2) Typ 0.7 sec

VCC Setup Time (Note 1) Min 50 µs

Write Recovery Time from RY/BY# Min 0 ns

RB

Program/Erase Valid to RY/BY# Delay Min 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29DL400B 31

AC CHARACTERISTICS

2

PRELIMINARY

Program Command Sequence (last two cycles)

t

WC

Addresses

CE#

555h

t

GHWL

t

CH

OE#

t

WP

WE#

t

CS

t

DS

t

DH

Data

A0h

RY/BY#

V

CC

t

VCS

Notes:

1. PA = program address, PD = program data, D

2. Illustration shows device in word mode.

Read Status Data (last two cycles)

t

AS

t

WHWH1

PA

Status

PA PA

t

AH

t

WPH

PD

t

BUSY

is the true data at the program address.

OUT

D

OUT

t

RB

Addresses

CE#

OE#

WE#

Data

RY/BY#

V

CC

t

VCS

Figure 17. Program Operation Timings

t

WC

2AAh SA

t

GHWL

t

CH

t

WP

t

CS

t

DS

t

DH

55h

t

AS

555h for chip erase

t

WPH

t

AH

30h

10 for Chip Erase

t

BUSY

t

WHWH2

VA

In

Progress

VA

Complete

t

RB

21606C-21

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
. Illustration shows device in word mode.

21606C-22

Figure 18. Chip/Sector Erase Operation Timings

32 Am29DL400B

AC CHARACTERISTICS

PRELIMINARY

Addresses

CE#

OE#

WE#

Data

t

WPH

t

WC

Valid PA

t

AH

t

WP

t

DS

Valid

In

t

RC

Valid RA

t

ACC

t

CE

t

OE

t

OEH

t

DH

t

GHWL

t

DF

t

OH

Valid

Out

t

SR/W

t

WC

Valid PA

Read Cycle

Figure 19. Back-to-Back Read/Write Cycle Timings

Valid

In

CE# Controlled Write CyclesWE# Controlled Write Cycle

t

CPH

t

WC

Valid PA

Valid

In

t

CP

21606C-23

t

RC

Addresses

CE#

t

CH

t

ACC

VA

t

CE

t

OE

VA VA

OE#

t

OEH

t

DF

WE#

t

DQ7

DQ0–DQ6

t

BUSY

OH

Complement

Status Data

Complement

Status Data

True

True

Valid Data

Valid Data

High Z

High Z

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.

21606C-24

Figure 20. Data# Polling Timings (During Embedded Algorithms)

Am29DL400B 33

AC CHARACTERISTICS

PRELIMINARY

t

AHT

Addresses

t

ASO

CE#

t

OEH

WE#

OE#

t

DH

DQ6/DQ2 Valid Data

RY/BY#

Valid Data

(first read) (second read) (stops toggling)

Valid

Status

t

OEPH

t

OE

Valid

Status

t

CEPH

t

t

AS

AHT

Valid

Status

Note: V A = V alid address; not required f or DQ6. Illustration shows first two status cycle after command sequence , last status read
cycle, and array data read cycle

21606C-25

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

WE#

Erase

Erase

Suspend

Erase Suspend

Suspend Program

Read

Enter Erase

Erase
Suspend
Program

Erase Suspend

Read

Erase

Resume

Erase

Erase

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an er ase-suspended sector. The system ma y use OE# or CE# to toggle
DQ2 and DQ6.

21606C-26

Figure 22. DQ2 vs. DQ6

34 Am29DL400B

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

PRELIMINARY

All Speed OptionsJEDEC Std Description Unit

t

VIDR VID

t

RSP

t

RRB

Note: Not 100% tested.

RESET#

CE#

WE#

RY/BY#

Rise and Fall Time (See Note) Min 500 ns

RESET# Setup Time for Temporary Sector
Unprotect

RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect

12 V

0 V or 3 V

t

VIDR

Program or Erase Command Sequence

t

RSP

Min 4 µs

Min 4 µs

0 V or 3 V

t

VIDR

t

RRB

Figure 23. Temporary Sector Unprotect Timing Diagram

21606C-27

Am29DL400B 35

AC CHARACTERISTICS

V

ID

V

RESET#

IH

PRELIMINARY

SA, A6,

A1, A0

Valid* Valid* Valid*

Sector Protect/Unprotect Verify

Data

60h 60h 40h

1 µs

Sector Protect: 100 µs

Sector Unprotect: 10 ms

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector Protect/Unprotect Timing Diagram

Status

21606C-28

36 Am29DL400B

PRELIMINARY

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

t

AVAV

t

AVWL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

t

t

t

t

t

GHEL

Write Cycle Time (Note 1) Min 70 80 90 120 ns

WC

Address Setup Time Min 0 ns

AS

Address Hold Time Min 45 45 45 50 ns

AH

Data Setup Time Min 35 35 45 50 ns

DS

Data Hold Time Min 0 ns

DH

Read Recovery Time Before Write
(OE# High to WE# Low)

-70 -80 -90 -120JEDEC Std Description Unit

Min 0 ns

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

WS

t

WH

t

CP

t

CPH

WE# Setup Time Min 0 ns

WE# Hold Time Min 0 ns

CE# Pulse Width Min 35 35 35 50 ns

CE# Pulse Width High Min 30 ns

Byte Typ 9

t

WHWH1tWHWH1

t

WHWH2tWHWH2

Programming Operation (Note 2)

Word Typ 11

Sector Erase Operation (Note 2) Typ 0.7 sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

µs

Am29DL400B 37

AC CHARACTERISTICS

PRELIMINARY

Addresses

WE#

OE#

CE#

Data

RESET#

555 for program
2AA for erase

t

WC

t

WH

t

WS

t

RH

PA for program
SA for sector erase
555 for chip erase

t

AS

t

GHEL

t

CP

t

CPH

t

DS

t

DH

A0 for program
55 for erase

t

AH

t

PD for program
30 for sector erase
10 for chip erase

BUSY

Data# Polling

t

WHWH1 or 2

PA

DQ7# D

OUT

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,
D

= data written to the device.

OUT

3. Waveforms are for the word mode.

21606C-29

Figure 25. Alternate CE# Controlled Erase/Program Operation Timings

38 Am29DL400B

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 sec

Chip Erase Time 10 sec

Byte Program Time 9 300 µs

Word Program Time 11 360 µs

Chip Program Time
(Note 3)

Byte Mode 4.5 13.5

sec

Word Mode 2.9 8.7

Excludes 00h programming

prior to erasure (Note 4)

Excludes system level

overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90˚C, V

= 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Min Max

Input voltage with respect to V
(including A9, OE#, and RESET#)

Input voltage with respect to V

VCC Current Ð100 mA +100 mA

on all pins except I/O pins

SS

on all I/O pins Ð1.0 V VCC + 1.0 V

SS

Ð1.0 V 12.5 V

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance VIN = 0 6 7.5 pF

Output Capacitance V

Control Pin Capacitance VIN = 0 7.5 9 pF

= 0 8.5 12 pF

OUT

C

C

C

IN

OUT

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25˚C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

150ûC 10 Years

125ûC 20 Years

Am29DL400B 39

PRELIMINARY

PHYSICAL DIMENSIONS

TS 048
48-Pin Standard TSOP (measured in millimeters)

Pin 1 I.D.

1

See Detail B

24

18.30

18.50

19.80

20.20

B

48

25

1.20

MAX

11.90

12.10

0.95

1.05

0.10

Seating
Plane

C

0.50 BSC

0.05

0.15

B

Parallel to Seating Plane

0.08MM (0.0031") C A–B

0.17

0.27

0.10

0.21

See Detail A

0¡
5¡

M

With Plating

0.10

0.16

0.10

0.08

0.21

0.20

0.50

0.70

Gage Line

0.25MM (0.0098") BSC

Detail A

S

0.25 BASIC

0.17

0.23

Base Metal

Section B-B

40 Am29DL400B

Detail B

X = A or B

16-038-TSOP-2_AB
TS 048
EC98
5-14-98 lv

PRELIMINARY

PHYSICAL DIMENSIONS (continued)

TSR048
48-Pin Reverse TSOP (measured in millimeters)

Pin 1 I.D.

1

See Detail B

24

18.30

18.50

19.80

20.20

B

48

25

1.20

MAX

11.90

12.10

0.95

1.05

0.10

Seating
Plane

C

0.50 BSC

0.05

0.15

B

Parallel to Seating Plane

0.08MM (0.0031") C A–B

0.17

0.27

0.10

0.21

See Detail A

0¡
5¡

M

With Plating

0.10

0.16

0.10

0.08

0.21

0.20

0.50

0.70

Gage Line

0.25MM (0.0098") BSC

Detail A

S

0.25 BASIC

0.17

0.23

Section B-B

Base Metal

X = A or B

Detail B

16-038-TSOP-2_AB
TSR048
EC98
5-14-98 lv

Am29DL400B 41

PRELIMINARY

PHYSICAL DIMENSIONS (continued)

SO 044
44-Pin Small Outline (measured in millimeters)

2.17

2.45

44

23

13.10

13.50

1

1.27 NOM.

TOP VIEW

28.00

28.40

0.35

0.50

SIDE VIEW

22

0.10

0.35

2.80

MAX.

15.70

16.30

SEATING
PLANE

0°
8°

0.10

0.21

0.60

1.00

END VIEW

16-038-SO44-2
SO 044
DF83
8-8-96 lv

42 Am29DL400B

REVISION SUMMARY

PRELIMINARY

Revision B

Expanded data sheet from Advance Information to Pre­liminary version.

Revision C

Global

Changed -70R speed option to -70.

Figure 1, In-system Sector Protect/Unprotect
Algorithm

Added ÒPSLSCNT=1Ó to sector protect algorithm.

Reset Command

Deleted last paragraph; applies only to hardware reset.

DQ6: Toggle Bit I

First and second para., clariÞed that the toggle bit may
be read Òat any address within the programming or
erasing bank,Ó not at Òany address.Ó Fourth para., clari­Þed ÒdeviceÓ to ÒbankÓ

Operating Ranges

Deleted reference to regulated voltage range

DC Characteristics

Added Note 4 reference to I

CC6

and I

CC7

.

Erase and Program Operations

Corrected note references for t
t

VCS

WHWH1

, t

WHWH2

, and

Temporary Sector Unprotect

Added note reference to t

VIDR

.

Figure 24, Sector Protect/Unprotect Timing
Diagram

Updated Þgure to correct address waveformÑvalid ad­dress not required in Þrst cycle.

Alternate CE# Controlled Erase/Program
Operations

Corrected note references for t

WHWH1

, t

WHWH2

Erase and Programming Performance

In Note 2, changed worst case endurance to 1 million
cycles.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identiÞcation purposes only and may be trademarks of their respective companies.

Am29DL400B 43